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-rw-r--r--gcc/ChangeLog25
-rw-r--r--gcc/config/mips/mips.c4
-rw-r--r--gcc/config/mips/mips.h25
-rw-r--r--gcc/config/mips/mips.md109
4 files changed, 141 insertions, 22 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c65ec1e..059fa77 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,28 @@
+2008-06-18 Maxim Kuvyrkov <maxim@codesourcery.com>
+
+ * config/mips/mips.h (ISA_HAS_CONDMOVE): Slice ISA_HAS_FP_CONDMOVE
+ from it.
+ (ISA_HAS_FP_CONDMOVE): New macro.
+ (ISA_HAS_FP_MADD4_MSUB4, ISA_HAS_FP_MADD3_MSUB3): New macros.
+ (ISA_HAS_NMADD_NMSUB): Rename to ISA_HAS_NMADD4_NMSUB4.
+ (ISA_HAS_NMADD3_NMSUB3): New macro.
+ * config/mips/mips.c (mips_rtx_costs): Update.
+ * config/mips/mips.md (MOVECC): Don't use FP conditional moves when
+ compiling for ST Loongson 2E/2F.
+ (madd<mode>): Rename to madd4<mode>. Update.
+ (madd3<mode>): New pattern.
+ (msub<mode>): Rename to msub4<mode>. Update.
+ (msub3<mode>): New pattern.
+ (nmadd<mode>): Rename to nmadd4<mode>. Update.
+ (nmadd3<mode>): New pattern.
+ (nmadd<mode>_fastmath): Rename to nmadd4<mode>_fastmath. Update.
+ (nmadd3<mode>_fastmath): New pattern.
+ (nmsub<mode>): Rename to nmsub4<mode>. Update.
+ (nmsub3<mode>): New pattern.
+ (nmsub<mode>_fastmath): Rename to nmsub4<mode>_fastmath. Update.
+ (nmsub3<mode>_fastmath): New pattern.
+ (mov<SCALARF:mode>_on_<MOVECC:mode>, mov<mode>cc): Update.
+
2008-06-18 Steven Bosscher <steven@gcc.gnu.org>
* df.h (struct df_ref): Replace 'insn' field with 'insn_info' field.
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 3ef0b33..5618005 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -3286,7 +3286,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
case MINUS:
if (float_mode_p
- && ISA_HAS_NMADD_NMSUB (mode)
+ && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
&& TARGET_FUSED_MADD
&& !HONOR_NANS (mode)
&& !HONOR_SIGNED_ZEROS (mode))
@@ -3337,7 +3337,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
case NEG:
if (float_mode_p
- && ISA_HAS_NMADD_NMSUB (mode)
+ && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
&& TARGET_FUSED_MADD
&& !HONOR_NANS (mode)
&& HONOR_SIGNED_ZEROS (mode))
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 5bcebd8..781528d 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -745,14 +745,19 @@ enum mips_code_readable_setting {
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
-/* ISA has the conditional move instructions introduced in mips4. */
-#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
+/* ISA has the floating-point conditional move instructions introduced
+ in mips4. */
+#define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \
&& !TARGET_MIPS5500 \
&& !TARGET_MIPS16)
+/* ISA has the integer conditional move instructions introduced in mips4 and
+ ST Loongson 2E/2F. */
+#define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
+
/* ISA has LDC1 and SDC1. */
#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
@@ -787,14 +792,26 @@ enum mips_code_readable_setting {
/* Integer multiply-accumulate instructions should be generated. */
#define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
-/* ISA has floating-point nmadd and nmsub instructions for mode MODE. */
-#define ISA_HAS_NMADD_NMSUB(MODE) \
+/* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
+#define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
+
+/* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
+#define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
+
+/* ISA has floating-point nmadd and nmsub instructions
+ 'd = -((a * b) [+-] c)'. */
+#define ISA_HAS_NMADD4_NMSUB4(MODE) \
((ISA_MIPS4 \
|| (ISA_MIPS32R2 && (MODE) == V2SFmode) \
|| ISA_MIPS64) \
&& (!TARGET_MIPS5400 || TARGET_MAD) \
&& !TARGET_MIPS16)
+/* ISA has floating-point nmadd and nmsub instructions
+ 'c = -((a * b) [+-] c)'. */
+#define ISA_HAS_NMADD3_NMSUB3(MODE) \
+ TARGET_LOONGSON_2EF
+
/* ISA has count leading zeroes/ones instruction (not implemented). */
#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
|| ISA_MIPS32R2 \
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index d75ea8c..842e582 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -526,7 +526,8 @@
;; This mode iterator allows :MOVECC to be used anywhere that a
;; conditional-move-type condition is needed.
-(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
+(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
+ (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
;; 64-bit modes for which we provide move patterns.
(define_mode_iterator MOVE64
@@ -1904,33 +1905,53 @@
;; Floating point multiply accumulate instructions.
-(define_insn "*madd<mode>"
+(define_insn "*madd4<mode>"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_FUSED_MADD"
+ "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
"madd.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
-(define_insn "*msub<mode>"
+(define_insn "*madd3<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "0")))]
+ "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
+ "madd.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*msub4<mode>"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_FUSED_MADD"
+ "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
"msub.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
-(define_insn "*nmadd<mode>"
+(define_insn "*msub3<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "0")))]
+ "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
+ "msub.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmadd4<mode>"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (plus:ANYF
(mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB (<MODE>mode)
+ "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
&& TARGET_FUSED_MADD
&& HONOR_SIGNED_ZEROS (<MODE>mode)
&& !HONOR_NANS (<MODE>mode)"
@@ -1938,13 +1959,27 @@
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
-(define_insn "*nmadd<mode>_fastmath"
+(define_insn "*nmadd3<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (neg:ANYF (plus:ANYF
+ (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "0"))))]
+ "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmadd.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmadd4<mode>_fastmath"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF
(mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f")))]
- "ISA_HAS_NMADD_NMSUB (<MODE>mode)
+ "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
&& TARGET_FUSED_MADD
&& !HONOR_SIGNED_ZEROS (<MODE>mode)
&& !HONOR_NANS (<MODE>mode)"
@@ -1952,13 +1987,27 @@
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
-(define_insn "*nmsub<mode>"
+(define_insn "*nmadd3<mode>_fastmath"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF
+ (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "0")))]
+ "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && !HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmadd.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmsub4<mode>"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (minus:ANYF
(mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
(match_operand:ANYF 3 "register_operand" "f"))
(match_operand:ANYF 1 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB (<MODE>mode)
+ "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
&& TARGET_FUSED_MADD
&& HONOR_SIGNED_ZEROS (<MODE>mode)
&& !HONOR_NANS (<MODE>mode)"
@@ -1966,20 +2015,48 @@
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
-(define_insn "*nmsub<mode>_fastmath"
+(define_insn "*nmsub3<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (neg:ANYF (minus:ANYF
+ (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
+ (match_operand:ANYF 3 "register_operand" "f"))
+ (match_operand:ANYF 1 "register_operand" "0"))))]
+ "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmsub.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmsub4<mode>_fastmath"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF
(match_operand:ANYF 1 "register_operand" "f")
(mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
(match_operand:ANYF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB (<MODE>mode)
+ "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
&& TARGET_FUSED_MADD
&& !HONOR_SIGNED_ZEROS (<MODE>mode)
&& !HONOR_NANS (<MODE>mode)"
"nmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
-
+
+(define_insn "*nmsub3<mode>_fastmath"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF
+ (match_operand:ANYF 1 "register_operand" "f")
+ (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
+ (match_operand:ANYF 3 "register_operand" "0"))))]
+ "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && !HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmsub.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
;;
;; ....................
;;
@@ -6339,7 +6416,7 @@
(const_int 0)])
(match_operand:SCALARF 2 "register_operand" "f,0")
(match_operand:SCALARF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_FP_CONDMOVE"
"@
mov%T4.<fmt>\t%0,%2,%1
mov%t4.<fmt>\t%0,%3,%1"
@@ -6366,7 +6443,7 @@
(if_then_else:SCALARF (match_dup 5)
(match_operand:SCALARF 2 "register_operand")
(match_operand:SCALARF 3 "register_operand")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_FP_CONDMOVE"
{
mips_expand_conditional_move (operands);
DONE;
generated by cgit v1.1 at 2024-11-01 22:46:03 +0000