diff options
Diffstat (limited to 'gcc')
10 files changed, 108 insertions, 13 deletions
diff --git a/gcc/common/config/aarch64/aarch64-common.cc b/gcc/common/config/aarch64/aarch64-common.cc index 5fb9e9d..20bc4e1 100644 --- a/gcc/common/config/aarch64/aarch64-common.cc +++ b/gcc/common/config/aarch64/aarch64-common.cc @@ -140,20 +140,28 @@ aarch64_handle_option (struct gcc_options *opts, /* An ISA extension in the co-processor and main instruction set space. */ struct aarch64_option_extension { + /* The extension name to pass on to the assembler. */ const char *name; + /* The smallest set of feature bits to toggle to enable this option. */ aarch64_feature_flags flag_canonical; + /* If this feature is turned on, these bits also need to be turned on. */ aarch64_feature_flags flags_on; + /* If this feature is turned off, these bits also need to be turned off. */ aarch64_feature_flags flags_off; + /* Indicates whether this feature is taken into account during native cpu + detection. */ + bool native_detect_p; }; /* ISA extensions in AArch64. */ static constexpr aarch64_option_extension all_extensions[] = { -#define AARCH64_OPT_EXTENSION(NAME, IDENT, C, D, E, F) \ +#define AARCH64_OPT_EXTENSION(NAME, IDENT, C, D, E, FEATURE_STRING) \ {NAME, AARCH64_FL_##IDENT, feature_deps::IDENT ().explicit_on, \ - feature_deps::get_flags_off (feature_deps::root_off_##IDENT)}, + feature_deps::get_flags_off (feature_deps::root_off_##IDENT), \ + FEATURE_STRING[0]}, #include "config/aarch64/aarch64-option-extensions.def" - {NULL, 0, 0, 0} + {NULL, 0, 0, 0, false} }; struct processor_name_to_arch @@ -326,9 +334,13 @@ aarch64_get_extension_string_for_isa_flags outstr += opt.name; } - /* Remove the features in current_flags & ~isa_flags. */ + /* Remove the features in current_flags & ~isa_flags. If the feature does + not have an HWCAPs then it shouldn't be taken into account for feature + detection because one way or another we can't tell if it's available + or not. */ for (auto &opt : all_extensions) - if (opt.flag_canonical & current_flags & ~isa_flags) + if (opt.native_detect_p + && (opt.flag_canonical & current_flags & ~isa_flags)) { current_flags &= ~opt.flags_off; outstr += "+no"; diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index acc0cfe..e6f47cb 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -2808,14 +2808,6 @@ static const struct attribute_spec aarch64_attribute_table[] = { NULL, 0, 0, false, false, false, false, NULL, NULL } }; -/* An ISA extension in the co-processor and main instruction set space. */ -struct aarch64_option_extension -{ - const char *const name; - const unsigned long flags_on; - const unsigned long flags_off; -}; - typedef enum aarch64_cond_code { AARCH64_EQ = 0, AARCH64_NE, AARCH64_CS, AARCH64_CC, AARCH64_MI, AARCH64_PL, diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_19 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_19 new file mode 100644 index 0000000..616d3b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_19 @@ -0,0 +1,9 @@ +processor : 0 +BogoMIPS : 100.00 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd49 +CPU revision : 2 + diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_20 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_20 new file mode 100644 index 0000000..45d45d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_20 @@ -0,0 +1,9 @@ +processor : 0 +BogoMIPS : 100.00 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti paca pacg +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd49 +CPU revision : 2 + diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_21 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_21 new file mode 100644 index 0000000..3c418a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_21 @@ -0,0 +1,9 @@ +processor : 0 +BogoMIPS : 100.00 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 + diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_22 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_22 new file mode 100644 index 0000000..3147eec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_22 @@ -0,0 +1,9 @@ +processor : 0 +BogoMIPS : 100.00 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti paca pacg +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 + diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_19.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_19.c new file mode 100644 index 0000000..980d3f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_19.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_19" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv9-a\+crc\+profile\+memtag\+sve2-sm4\+sve2-aes\+sve2-sha3\+sve2-bitperm\+i8mm\+bf16\+nopauth\n} } } */ + +/* Test one that if the kernel doesn't report the availability of a mandatory + feature that it has turned it off for whatever reason. As such compilers + should follow along. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_20.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_20.c new file mode 100644 index 0000000..117df2b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_20.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_20" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv9-a\+crc\+profile\+memtag\+sve2-sm4\+sve2-aes\+sve2-sha3\+sve2-bitperm\+i8mm\+bf16\n} } } */ + +/* Check whether features that don't have a midr name during detection are + correctly ignored. These features shouldn't affect the native detection. + This particular test checks that predres is not turned off during + detection. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c new file mode 100644 index 0000000..efbd02c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_21" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+crc\+lse\+rcpc\+rdma\+dotprod\+fp16fml\+sb\+ssbs\+sve2-sm4\+sve2-aes\+sve2-sha3\+sve2-bitperm\+i8mm\+bf16\+flagm\n} } } */ + +/* Check that an Armv8-A core doesn't fall apart on extensions without midr + values. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c new file mode 100644 index 0000000..d431d49 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_22" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+crc\+lse\+rcpc\+rdma\+dotprod\+fp16fml\+sb\+ssbs\+sve2-sm4\+sve2-aes\+sve2-sha3\+sve2-bitperm\+i8mm\+bf16\+flagm\+pauth\n} } } */ + +/* Check that an Armv8-A core doesn't fall apart on extensions without midr + values and that it enables optional features. */ |