diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/match.pd | 9 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/pr110280.c | 12 |
2 files changed, 20 insertions, 1 deletions
diff --git a/gcc/match.pd b/gcc/match.pd index 48b76e6..33ccda3 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -8672,7 +8672,14 @@ and, (simplify (vec_perm vec_same_elem_p@0 @0 @1) - @0) + (if (types_match (type, TREE_TYPE (@0))) + @0 + (with + { + tree elem = uniform_vector_p (@0); + } + (if (elem) + { build_vector_from_val (type, elem); })))) /* Push VEC_PERM earlier if that may help FMA perception (PR101895). */ (simplify diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c new file mode 100644 index 0000000..d3279f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -fdump-tree-optimized" } */ + +#include "arm_sve.h" + +svuint32_t l() +{ + _Alignas(16) const unsigned int lanes[4] = {0, 0, 0, 0}; + return svld1rq_u32(svptrue_b8(), lanes); +} + +/* { dg-final { scan-tree-dump-not "VEC_PERM_EXPR" "optimized" } } */ |