diff options
Diffstat (limited to 'gcc')
83 files changed, 445 insertions, 245 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 74afa64..9142a39 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,6 +1,102 @@ +2015-09-20 Oleg Endo <olegendo@gcc.gnu.org> + + * gcc.target/sh/sh.exp (check_effective_target_sh4a, + check_effective_target_big_endian, check_effective_target_little_endian, + check_effective_target_any_fpu, check_effective_target_double_fpu, + check_effective_target_use_single_only_fpu, + check_effective_target_default_single_fpu, + check_effective_target_no_fpu, check_effective_target_has_xf_regs, + check_effective_target_has_fsca, check_effective_target_has_fsrra, + check_effective_target_has_fpchg, check_effective_target_has_dyn_shift, + check_effective_target_fmovd_enabled, + check_effective_target_has_privileged, check_effective_target_has_pref, + check_effective_target_banked_r0r7_isr, + check_effective_target_stack_save_isr): New effective target checks. + * gcc.target/sh/pr51244-16.c: Merge into pr51244-15.c. + * gcc.target/sh/pr51244-20-sh2a.c: Merge into pr51244-20.c. + * gcc.target/sh/pr51244-3.c: Merge into pr51244-2.c + * gcc.target/sh/pr54089-5.c: Merge into pr54089-4.c. + * gcc.target/sh/20080410-1.c: Use new effective target checks. + * gcc.target/sh/attr-isr-nosave_low_regs.c: Likewise. + * gcc.target/sh/attr-isr.c: Likewise. + * gcc.target/sh/fpul-usage-1.c: Likewise. + * gcc.target/sh/hiconst.c: Likewise. + * gcc.target/sh/mfmovd.c: Likewise. + * gcc.target/sh/pr21255-3.c: Likewise. + * gcc.target/sh/pr33135-1.c: Likewise. + * gcc.target/sh/pr33135-2.c: Likewise. + * gcc.target/sh/pr33135-3.c: Likewise. + * gcc.target/sh/pr33135-4.c: Likewise. + * gcc.target/sh/pr39423-2.c: Likewise. + * gcc.target/sh/pr49880-4.c: Likewise. + * gcc.target/sh/pr49880-5.c: Likewise. + * gcc.target/sh/pr50749-sf-postinc-1.c: Likewise. + * gcc.target/sh/pr50749-sf-postinc-2.c: Likewise. + * gcc.target/sh/pr50749-sf-postinc-3.c: Likewise. + * gcc.target/sh/pr50749-sf-postinc-4.c: Likewise. + * gcc.target/sh/pr50749-sf-predec-1.c: Likewise. + * gcc.target/sh/pr50749-sf-predec-2.c: Likewise. + * gcc.target/sh/pr50749-sf-predec-3.c: Likewise. + * gcc.target/sh/pr50749-sf-predec-4.c: Likewise. + * gcc.target/sh/pr50751-2.c: Likewise. + * gcc.target/sh/pr50751-3.c: Likewise. + * gcc.target/sh/pr50751-5.c: Likewise. + * gcc.target/sh/pr50751-6.c: Likewise. + * gcc.target/sh/pr50751-8.c: Likewise. + * gcc.target/sh/pr51244-15.c: Likewise. + * gcc.target/sh/pr51244-2.c: Likewise. + * gcc.target/sh/pr51244-20.c: Likewise. + * gcc.target/sh/pr51244-6.c: Likewise. + * gcc.target/sh/pr52483-4.c: Likewise. + * gcc.target/sh/pr53511-1.c: Likewise. + * gcc.target/sh/pr53512-1.c: Likewise. + * gcc.target/sh/pr53512-2.c: Likewise. + * gcc.target/sh/pr53512-3.c: Likewise. + * gcc.target/sh/pr53512-4.c: Likewise. + * gcc.target/sh/pr53513-1.c: Likewise. + * gcc.target/sh/pr54089-2.c: Likewise. + * gcc.target/sh/pr54089-3.c: Likewise. + * gcc.target/sh/pr54089-4.c: Likewise. + * gcc.target/sh/pr54602-2.c: Likewise. + * gcc.target/sh/pr54602-3.c: Likewise. + * gcc.target/sh/pr54602-4.c: Likewise. + * gcc.target/sh/pr54680.c: Likewise. + * gcc.target/sh/pr55303-1.c: Likewise. + * gcc.target/sh/pr55303-2.c: Likewise. + * gcc.target/sh/pr55303-3.c: Likewise. + * gcc.target/sh/pr56547-1.c: Likewise. + * gcc.target/sh/pr56547-2.c: Likewise. + * gcc.target/sh/pr61195.c: Likewise. + * gcc.target/sh/pr61996.c: Likewise. + * gcc.target/sh/pr6526.c: Likewise. + * gcc.target/sh/pragma-isr-nosave_low_regs.c: Likewise. + * gcc.target/sh/pragma-isr-trapa2.c: Likewise. + * gcc.target/sh/prefetch.c: Likewise. + * gcc.target/sh/rte-delay-slot.c: Likewise. + * gcc.target/sh/sh2a-band.c: Likewise. + * gcc.target/sh/sh2a-bclr.c: Likewise. + * gcc.target/sh/sh2a-bclrmem.c: Likewise. + * gcc.target/sh/sh2a-bld.c: Likewise. + * gcc.target/sh/sh2a-bor.c: Likewise. + * gcc.target/sh/sh2a-bset.c: Likewise. + * gcc.target/sh/sh2a-bsetmem.c: Likewise. + * gcc.target/sh/sh2a-bxor.c: Likewise. + * gcc.target/sh/sh2a-jsrn.c: Likewise. + * gcc.target/sh/sh2a-movi20s.c: Likewise. + * gcc.target/sh/sh2a-movrt.c: Likewise. + * gcc.target/sh/sh2a-resbank.c: Likewise. + * gcc.target/sh/sh2a-rtsn.c: Likewise. + * gcc.target/sh/sh2a-tbr-jump.c: Likewise. + * gcc.target/sh/sh4a-bitmovua.c: Likewise. + * gcc.target/sh/sh4a-cosf.c: Likewise. + * gcc.target/sh/sh4a-fsrra.c: Likewise. + * gcc.target/sh/sh4a-memmovua.c: Likewise. + * gcc.target/sh/sh4a-sincosf.c: Likewise. + * gcc.target/sh/sh4a-sinf.c: Likewise. + 2015-09-20 Jeff Law <law@redhat.com> - PR tree-optimization/47679 + PR tree-optimization/47679 * g++.dg/warn/Wuninitialized-6.C: New test. 2015-09-18 Ville Voutilainen <ville.voutilainen@gmail.com> diff --git a/gcc/testsuite/gcc.target/sh/20080410-1.c b/gcc/testsuite/gcc.target/sh/20080410-1.c index c398674..6e9e9c1 100644 --- a/gcc/testsuite/gcc.target/sh/20080410-1.c +++ b/gcc/testsuite/gcc.target/sh/20080410-1.c @@ -1,6 +1,5 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { little_endian } } } */ /* { dg-options "-O0" } */ -/* { dg-skip-if "" { "sh*-*-*" } "-mb" "" } */ /* { dg-final { scan-assembler-not "add\tr0,r0" } } */ /* This test checks chain reloads conflicts. If they don't diff --git a/gcc/testsuite/gcc.target/sh/attr-isr-nosave_low_regs.c b/gcc/testsuite/gcc.target/sh/attr-isr-nosave_low_regs.c index f1ad4cd..5087a73 100644 --- a/gcc/testsuite/gcc.target/sh/attr-isr-nosave_low_regs.c +++ b/gcc/testsuite/gcc.target/sh/attr-isr-nosave_low_regs.c @@ -3,8 +3,7 @@ (On SH3* and SH4* r0..r7 are banked) Call-saved registers r8..r13 also don't need to be restored. To test that we look for register push insns such as 'mov.l r0,@-r15'. */ -/* { dg-do compile { target { { "sh*-*-*" } && nonpic } } } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1*" "-m2*" "-m5*" } { "" } } */ +/* { dg-do compile { target { { banked_r0r7_isr } && nonpic } } } */ /* { dg-options "-O" } */ /* { dg-final { scan-assembler-times "rte" 1 } } */ /* { dg-final { scan-assembler-not "mov.l\tr\[0-9\],@-r15" } } */ diff --git a/gcc/testsuite/gcc.target/sh/attr-isr.c b/gcc/testsuite/gcc.target/sh/attr-isr.c index 8e24aa2..c2efd76 100644 --- a/gcc/testsuite/gcc.target/sh/attr-isr.c +++ b/gcc/testsuite/gcc.target/sh/attr-isr.c @@ -1,8 +1,7 @@ /* The call will clobber r0..r7, which will need not be saved/restored, but not the call-saved registers r8..r14. Check this by counting the register push insns. */ -/* { dg-do compile { target { { { sh-*-* sh[1234ble]*-*-* } && { ! sh2a*-*-* } } && nonpic } } } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m2a*" } { "" } } */ +/* { dg-do compile { target { { ! sh2a } && nonpic } } } */ /* { dg-options "-O" } */ /* { dg-final { scan-assembler-times "rte" 1} } */ /* { dg-final { scan-assembler-times "mov.l\tr\[0-7\],@-r15" 8 } } */ diff --git a/gcc/testsuite/gcc.target/sh/fpul-usage-1.c b/gcc/testsuite/gcc.target/sh/fpul-usage-1.c index 5c3bb19..277f708 100644 --- a/gcc/testsuite/gcc.target/sh/fpul-usage-1.c +++ b/gcc/testsuite/gcc.target/sh/fpul-usage-1.c @@ -1,8 +1,7 @@ /* Check that the FPUL register is used when reading a float as an int and vice versa, as opposed to pushing and popping the values over the stack. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler "fpul" } } */ /* { dg-final { scan-assembler-not "r15" } } */ diff --git a/gcc/testsuite/gcc.target/sh/hiconst.c b/gcc/testsuite/gcc.target/sh/hiconst.c index 778bb8a..d8911a5 100644 --- a/gcc/testsuite/gcc.target/sh/hiconst.c +++ b/gcc/testsuite/gcc.target/sh/hiconst.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-do compile } */ /* { dg-options "-O1" } */ char a; diff --git a/gcc/testsuite/gcc.target/sh/mfmovd.c b/gcc/testsuite/gcc.target/sh/mfmovd.c index ce3e993..3fb1e8e 100644 --- a/gcc/testsuite/gcc.target/sh/mfmovd.c +++ b/gcc/testsuite/gcc.target/sh/mfmovd.c @@ -1,9 +1,7 @@ /* Verify that we generate fmov.d instructions to move doubles when -mfmovd option is enabled. */ -/* { dg-do compile } */ -/* { dg-require-effective-target hard_float } */ +/* { dg-do compile { target { double_fpu } } } */ /* { dg-options "-mfmovd" } */ -/* { dg-skip-if "" { *-*-* } { "*-single-only" } { "" } } */ /* { dg-final { scan-assembler "fmov.d" } } */ extern double g; diff --git a/gcc/testsuite/gcc.target/sh/pr21255-3.c b/gcc/testsuite/gcc.target/sh/pr21255-3.c index a672784..7dccf07 100644 --- a/gcc/testsuite/gcc.target/sh/pr21255-3.c +++ b/gcc/testsuite/gcc.target/sh/pr21255-3.c @@ -1,6 +1,5 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { double_fpu } } } */ /* { dg-options "-O2 -fomit-frame-pointer" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m2e" "-m3e" "*single-only" } { "" } } */ /* { dg-final { scan-assembler "mov #?0,r.*; mov #?20,r" } } */ /* { dg-final { scan-assembler "mov #?1077149696,r.*; mov #?0,r" } } */ double diff --git a/gcc/testsuite/gcc.target/sh/pr33135-1.c b/gcc/testsuite/gcc.target/sh/pr33135-1.c index cc6a3f9..a6e8838 100644 --- a/gcc/testsuite/gcc.target/sh/pr33135-1.c +++ b/gcc/testsuite/gcc.target/sh/pr33135-1.c @@ -1,8 +1,7 @@ /* Check that fcmp/eq and fcmp/gt instructions are generated by default (implicit -mieee). */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "fcmp/eq" 4 } } */ /* { dg-final { scan-assembler-times "fcmp/gt" 4 } } */ @@ -29,4 +28,3 @@ test_03 (double a, double b) { return a >= b; } - diff --git a/gcc/testsuite/gcc.target/sh/pr33135-2.c b/gcc/testsuite/gcc.target/sh/pr33135-2.c index b93ecb8..ec6452b 100644 --- a/gcc/testsuite/gcc.target/sh/pr33135-2.c +++ b/gcc/testsuite/gcc.target/sh/pr33135-2.c @@ -1,8 +1,7 @@ /* Check that only the fcmp/gt instruction is generated when specifying -ffinite-math-only (implicit -mno-ieee). */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O1 -ffinite-math-only" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-not "fcmp/eq" } } */ /* { dg-final { scan-assembler-times "fcmp/gt" 4 } } */ diff --git a/gcc/testsuite/gcc.target/sh/pr33135-3.c b/gcc/testsuite/gcc.target/sh/pr33135-3.c index f5f9a5b..c5b9274 100644 --- a/gcc/testsuite/gcc.target/sh/pr33135-3.c +++ b/gcc/testsuite/gcc.target/sh/pr33135-3.c @@ -1,8 +1,7 @@ /* Check that fcmp/eq and fcmp/gt instructions are generated when specifying -ffinite-math-only and -mieee. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O1 -ffinite-math-only -mieee" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "fcmp/eq" 4 } } */ /* { dg-final { scan-assembler-times "fcmp/gt" 4 } } */ @@ -29,4 +28,3 @@ test_03 (double a, double b) { return a >= b; } - diff --git a/gcc/testsuite/gcc.target/sh/pr33135-4.c b/gcc/testsuite/gcc.target/sh/pr33135-4.c index 20178d7..0c5ff1c 100644 --- a/gcc/testsuite/gcc.target/sh/pr33135-4.c +++ b/gcc/testsuite/gcc.target/sh/pr33135-4.c @@ -1,8 +1,7 @@ /* Check that only the fcmp/gt instruction is generated when specifying -fno-finite-math-only and -mno-ieee. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O1 -fno-finite-math-only -mno-ieee" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-not "fcmp/eq" } } */ /* { dg-final { scan-assembler-times "fcmp/gt" 4 } } */ @@ -29,4 +28,3 @@ test_03 (double a, double b) { return a >= b; } - diff --git a/gcc/testsuite/gcc.target/sh/pr39423-2.c b/gcc/testsuite/gcc.target/sh/pr39423-2.c index 702384d..962d982 100644 --- a/gcc/testsuite/gcc.target/sh/pr39423-2.c +++ b/gcc/testsuite/gcc.target/sh/pr39423-2.c @@ -1,9 +1,8 @@ /* Check that displacement addressing is used for indexed addresses with a small offset, instead of re-calculating the index and that the movu.w instruction is used on SH2A. */ -/* { dg-do compile } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */ /* { dg-final { scan-assembler-not "add\t#1" } } */ /* { dg-final { scan-assembler "movu.w" } } */ diff --git a/gcc/testsuite/gcc.target/sh/pr49880-4.c b/gcc/testsuite/gcc.target/sh/pr49880-4.c index 5b5af1e..8819be0 100644 --- a/gcc/testsuite/gcc.target/sh/pr49880-4.c +++ b/gcc/testsuite/gcc.target/sh/pr49880-4.c @@ -1,9 +1,8 @@ /* Check that the option -mdiv=call-fp does not produce calls to the library function that uses FPU to implement integer division if FPU insns are not supported or are disabled. */ -/* { dg-do compile } */ +/* { dg-do compile { target { no_fpu } } } */ /* { dg-options "-mdiv=call-fp" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" } } */ /* { dg-final { scan-assembler-not "sdivsi3_i4\n|udivsi3_i4\n" } } */ int diff --git a/gcc/testsuite/gcc.target/sh/pr49880-5.c b/gcc/testsuite/gcc.target/sh/pr49880-5.c index bff9f33..f83a35b 100644 --- a/gcc/testsuite/gcc.target/sh/pr49880-5.c +++ b/gcc/testsuite/gcc.target/sh/pr49880-5.c @@ -1,8 +1,7 @@ /* Check that the option -mdiv=call-fp results in the corresponding library function calls on targets that have a double precision FPU. */ -/* { dg-do compile } */ +/* { dg-do compile { target { double_fpu || use_single_only_fpu } } } */ /* { dg-options "-mdiv=call-fp" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m2a" "-m4" "-m4a" "*single-only" } } */ /* { dg-final { scan-assembler "sdivsi3_i4\n" } } */ /* { dg-final { scan-assembler "udivsi3_i4\n" } } */ diff --git a/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-1.c b/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-1.c index 41e3bdd..3da1cca 100644 --- a/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-1.c +++ b/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-1.c @@ -1,7 +1,6 @@ /* PR target/50749: Verify that post-increment addressing is generated. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 1 } } */ float* @@ -12,4 +11,3 @@ test_func_00 (float* p, float* x) *x = r; return p; } - diff --git a/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-2.c b/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-2.c index 304ed11..ec9eff4 100644 --- a/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-2.c +++ b/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-2.c @@ -1,8 +1,7 @@ /* PR target/50749: Verify that subsequent post-increment addressings are generated. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 5 { xfail *-*-*} } } */ float* diff --git a/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-3.c b/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-3.c index 7461bed..3ce81b6 100644 --- a/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-3.c +++ b/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-3.c @@ -1,8 +1,7 @@ /* PR target/50749: Verify that post-increment addressing is generated inside a loop. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 1 } } */ float diff --git a/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-4.c b/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-4.c index b6dce42..65f45a3 100644 --- a/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-4.c +++ b/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-4.c @@ -1,8 +1,7 @@ /* PR target/50749: Verify that post-increment addressing is generated inside a loop. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 3 { xfail *-*-*} } } */ float diff --git a/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-1.c b/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-1.c index d51aa9e..05e603d 100644 --- a/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-1.c +++ b/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-1.c @@ -1,7 +1,6 @@ /* PR target/50749: Verify that pre-decrement addressing is generated. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 1 } } */ float* diff --git a/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-2.c b/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-2.c index cd87ce9..22ec161 100644 --- a/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-2.c +++ b/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-2.c @@ -1,8 +1,7 @@ /* PR target/50749: Verify that subsequent pre-decrement addressings are generated. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 5 { xfail *-*-*} } } */ float* diff --git a/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-3.c b/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-3.c index a772b23..6ed3254 100644 --- a/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-3.c +++ b/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-3.c @@ -1,8 +1,7 @@ /* PR target/50749: Verify that pre-decrement addressing is generated inside a loop. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 1 } } */ float* diff --git a/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-4.c b/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-4.c index 9d08038..26bc3eb 100644 --- a/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-4.c +++ b/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-4.c @@ -1,8 +1,7 @@ /* PR target/50749: Verify that pre-decrement addressing is generated inside a loop. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 3 { xfail *-*-*} } } */ float* diff --git a/gcc/testsuite/gcc.target/sh/pr50751-2.c b/gcc/testsuite/gcc.target/sh/pr50751-2.c index cd71642..c8780f9 100644 --- a/gcc/testsuite/gcc.target/sh/pr50751-2.c +++ b/gcc/testsuite/gcc.target/sh/pr50751-2.c @@ -2,9 +2,8 @@ base address is adjusted only once. On SH2A this test is skipped because there is a 4 byte mov.b insn that can handle larger displacements. Thus on SH2A the base address will not be adjusted in this case. */ -/* { dg-do compile } */ +/* { dg-do compile { target { ! sh2a } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */ /* { dg-final { scan-assembler-times "add" 2 } } */ void diff --git a/gcc/testsuite/gcc.target/sh/pr50751-3.c b/gcc/testsuite/gcc.target/sh/pr50751-3.c index 5b8d351..caf8a87 100644 --- a/gcc/testsuite/gcc.target/sh/pr50751-3.c +++ b/gcc/testsuite/gcc.target/sh/pr50751-3.c @@ -1,9 +1,8 @@ /* Check that on SH2A the 4 byte mov.b displacement insn is generated to handle larger displacements. If it is generated correctly, there should be no base address adjustments outside the mov.b insns. */ -/* { dg-do compile } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */ /* { dg-final { scan-assembler-not "add|sub" } } */ void diff --git a/gcc/testsuite/gcc.target/sh/pr50751-5.c b/gcc/testsuite/gcc.target/sh/pr50751-5.c index 5da9ac2..89658c0 100644 --- a/gcc/testsuite/gcc.target/sh/pr50751-5.c +++ b/gcc/testsuite/gcc.target/sh/pr50751-5.c @@ -2,9 +2,8 @@ base address is adjusted only once. On SH2A this test is skipped because there is a 4 byte mov.w insn that can handle larger displacements. Thus on SH2A the base address will not be adjusted in this case. */ -/* { dg-do compile } */ +/* { dg-do compile { target { ! sh2a } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */ /* { dg-final { scan-assembler-times "add" 2 } } */ void diff --git a/gcc/testsuite/gcc.target/sh/pr50751-6.c b/gcc/testsuite/gcc.target/sh/pr50751-6.c index 1297290..e8f0e3e 100644 --- a/gcc/testsuite/gcc.target/sh/pr50751-6.c +++ b/gcc/testsuite/gcc.target/sh/pr50751-6.c @@ -1,9 +1,8 @@ /* Check that on SH2A the 4 byte mov.w displacement insn is generated to handle larger displacements. If it is generated correctly, there should be no base address adjustments outside the mov.w insns. */ -/* { dg-do compile } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */ /* { dg-final { scan-assembler-not "add|sub" } } */ void diff --git a/gcc/testsuite/gcc.target/sh/pr50751-8.c b/gcc/testsuite/gcc.target/sh/pr50751-8.c index d9eda44..07bbee4 100644 --- a/gcc/testsuite/gcc.target/sh/pr50751-8.c +++ b/gcc/testsuite/gcc.target/sh/pr50751-8.c @@ -1,9 +1,8 @@ /* Check that on SH2A the 4 byte movu.b and movu.w displacement insns are generated. This has to be checked with -O2 because some of the patterns rely on peepholes. */ -/* { dg-do compile } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */ /* { dg-final { scan-assembler-times "movu.b" 4 } } */ /* { dg-final { scan-assembler-times "movu.w" 3 } } */ diff --git a/gcc/testsuite/gcc.target/sh/pr51244-15.c b/gcc/testsuite/gcc.target/sh/pr51244-15.c index e99963f..8b9d57b 100644 --- a/gcc/testsuite/gcc.target/sh/pr51244-15.c +++ b/gcc/testsuite/gcc.target/sh/pr51244-15.c @@ -1,13 +1,16 @@ /* Check that the redundant test removal code in the *cbranch_t split works - as expected on non-SH2A targets. Because on SH2A the movrt instruction - is used, this test is re-used and checked differently in pr51244-16.c. */ + as expected. */ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */ -/* { dg-final { scan-assembler-times "tst" 6 } } */ -/* { dg-final { scan-assembler-times "movt" 6 } } */ -/* { dg-final { scan-assembler-times "xor" 3 } } */ + /* { dg-final { scan-assembler-not "extu|exts|negc" } } */ +/* { dg-final { scan-assembler-times "tst" 6 } } */ + +/* { dg-final { scan-assembler-times "movt" 6 { target { ! sh2a } } } } */ +/* { dg-final { scan-assembler-times "xor" 3 { target { ! sh2a } } } } */ + +/* { dg-final { scan-assembler-times "movt" 3 { target { sh2a } } } } */ +/* { dg-final { scan-assembler-times "movrt" 3 { target { sh2a } } } } */ typedef char bool; diff --git a/gcc/testsuite/gcc.target/sh/pr51244-16.c b/gcc/testsuite/gcc.target/sh/pr51244-16.c deleted file mode 100644 index 5132f74..0000000 --- a/gcc/testsuite/gcc.target/sh/pr51244-16.c +++ /dev/null @@ -1,11 +0,0 @@ -/* Check that the redundant test removal code in the *cbranch_t split works - as expected on SH2A targets. */ -/* { dg-do compile } */ -/* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */ -/* { dg-final { scan-assembler-times "tst" 6 } } */ -/* { dg-final { scan-assembler-times "movt" 3 } } */ -/* { dg-final { scan-assembler-times "movrt" 3 } } */ -/* { dg-final { scan-assembler-not "extu|exts|negc" } } */ - -#include "pr51244-15.c" diff --git a/gcc/testsuite/gcc.target/sh/pr51244-2.c b/gcc/testsuite/gcc.target/sh/pr51244-2.c index a81ee7e..c631838 100644 --- a/gcc/testsuite/gcc.target/sh/pr51244-2.c +++ b/gcc/testsuite/gcc.target/sh/pr51244-2.c @@ -1,11 +1,11 @@ /* Check that when taking the complement of the T bit using the negc - instruction pattern, the constant -1 is loaded only once. - On SH2A this test is skipped because the movrt instruction is used - to get the complement of the T bit. */ + instruction pattern, the constant -1 is loaded only once on non-SH2A and + that the movrt insn is generated on SH2A. /* { dg-do compile } */ /* { dg-options "-O1 -mbranch-cost=2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */ -/* { dg-final { scan-assembler-times "mov\t#-1" 1 } } */ + +/* { dg-final { scan-assembler-times "mov\t#-1" 1 { target { ! sh2a } } } } */ +/* { dg-final { scan-assembler-times "movrt" 4 { target { sh2a } } } } */ void testfunc_00 (int* a, int* b, int c, int d) diff --git a/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c b/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c deleted file mode 100644 index 2c6f365..0000000 --- a/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c +++ /dev/null @@ -1,14 +0,0 @@ -/* Check that the SH specific sh_treg_combine RTL optimization pass works as - expected. */ -/* { dg-do compile } */ -/* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */ -/* { dg-final { scan-assembler-times "tst" 6 } } */ -/* { dg-final { scan-assembler-not "movt" } } */ -/* { dg-final { scan-assembler-times "nott" 2 } } */ -/* { dg-final { scan-assembler-times "cmp/eq" 2 } } */ -/* { dg-final { scan-assembler-times "cmp/hi" 4 } } */ -/* { dg-final { scan-assembler-times "cmp/gt" 2 } } */ -/* { dg-final { scan-assembler-not "not\t" } } */ - -#include "pr51244-20.c" diff --git a/gcc/testsuite/gcc.target/sh/pr51244-20.c b/gcc/testsuite/gcc.target/sh/pr51244-20.c index aad6a2f..c342163 100644 --- a/gcc/testsuite/gcc.target/sh/pr51244-20.c +++ b/gcc/testsuite/gcc.target/sh/pr51244-20.c @@ -1,15 +1,19 @@ /* Check that the SH specific sh_treg_combine RTL optimization pass works as - expected. On SH2A the expected insns are slightly different, see - pr51244-20-sh2a.c. */ + expected. */ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */ -/* { dg-final { scan-assembler-times "tst" 7 } } */ -/* { dg-final { scan-assembler-times "movt" 2 } } */ + +/* { dg-final { scan-assembler-not "not\t" } } */ /* { dg-final { scan-assembler-times "cmp/eq" 2 } } */ /* { dg-final { scan-assembler-times "cmp/hi" 4 } } */ /* { dg-final { scan-assembler-times "cmp/gt" 2 } } */ -/* { dg-final { scan-assembler-not "not\t" } } */ + +/* { dg-final { scan-assembler-times "tst" 7 { target { ! sh2a } } } } */ +/* { dg-final { scan-assembler-times "movt" 2 { target { ! sh2a } } } } */ + +/* { dg-final { scan-assembler-times "tst" 6 { target { sh2a } } } } */ +/* { dg-final { scan-assembler-not "movt" { target { sh2a } } } } */ +/* { dg-final { scan-assembler-times "nott" 2 { target { sh2a } } } } */ /* non-SH2A: 2x tst, 1x movt, 2x cmp/eq, 1x cmp/hi diff --git a/gcc/testsuite/gcc.target/sh/pr51244-3.c b/gcc/testsuite/gcc.target/sh/pr51244-3.c deleted file mode 100644 index 92963c4..0000000 --- a/gcc/testsuite/gcc.target/sh/pr51244-3.c +++ /dev/null @@ -1,16 +0,0 @@ -/* Check that when taking the complement of the T bit on SH2A, - the movrt instruction is being generated. */ -/* { dg-do compile } */ -/* { dg-options "-O1 -mbranch-cost=2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */ -/* { dg-final { scan-assembler-times "movrt" 4 } } */ - -void -testfunc_00 (int* a, int* b, int c, int d) -{ - b[0] = a[0] != c; - b[1] = a[1] != d; - b[2] = a[2] != c; - b[3] = a[3] != d; -} - diff --git a/gcc/testsuite/gcc.target/sh/pr51244-6.c b/gcc/testsuite/gcc.target/sh/pr51244-6.c index 3f9aafb..57f1f31 100644 --- a/gcc/testsuite/gcc.target/sh/pr51244-6.c +++ b/gcc/testsuite/gcc.target/sh/pr51244-6.c @@ -1,8 +1,7 @@ /* Check that no unnecessary sign or zero extension insn is generated after a negc or movrt insn that stores the inverted T bit in a reg. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-not "extu|exts" } } */ float diff --git a/gcc/testsuite/gcc.target/sh/pr52483-4.c b/gcc/testsuite/gcc.target/sh/pr52483-4.c index 743e8dc..81a24d4 100644 --- a/gcc/testsuite/gcc.target/sh/pr52483-4.c +++ b/gcc/testsuite/gcc.target/sh/pr52483-4.c @@ -1,8 +1,7 @@ /* Check that loads/stores from/to volatile floating point mems utilize indexed addressing modes. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "@\\(r0," 2 } } */ float diff --git a/gcc/testsuite/gcc.target/sh/pr53511-1.c b/gcc/testsuite/gcc.target/sh/pr53511-1.c index d58a72c..bd6ac00 100644 --- a/gcc/testsuite/gcc.target/sh/pr53511-1.c +++ b/gcc/testsuite/gcc.target/sh/pr53511-1.c @@ -1,7 +1,6 @@ /* Verify that the fmac insn is used for the standard fmaf function. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler "fmac" } } */ #include <math.h> diff --git a/gcc/testsuite/gcc.target/sh/pr53512-1.c b/gcc/testsuite/gcc.target/sh/pr53512-1.c index c54671b..14106c0 100644 --- a/gcc/testsuite/gcc.target/sh/pr53512-1.c +++ b/gcc/testsuite/gcc.target/sh/pr53512-1.c @@ -1,8 +1,7 @@ /* Verify that the fsca insn is used when specifying -mfsca and -funsafe-math-optimizations. */ -/* { dg-do compile } */ +/* { dg-do compile { target { has_fsca } } } */ /* { dg-options "-O1 -mfsca -funsafe-math-optimizations" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m3*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "fsca" 3 } } */ #include <math.h> diff --git a/gcc/testsuite/gcc.target/sh/pr53512-2.c b/gcc/testsuite/gcc.target/sh/pr53512-2.c index ed41011..a79e58a 100644 --- a/gcc/testsuite/gcc.target/sh/pr53512-2.c +++ b/gcc/testsuite/gcc.target/sh/pr53512-2.c @@ -1,8 +1,7 @@ /* Verify that the fsca insn is not used when specifying -mno-fsca and -funsafe-math-optimizations. */ -/* { dg-do compile } */ +/* { dg-do compile { target { has_fsca } } } */ /* { dg-options "-O1 -mno-fsca -funsafe-math-optimizations" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-not "fsca" } } */ #include <math.h> diff --git a/gcc/testsuite/gcc.target/sh/pr53512-3.c b/gcc/testsuite/gcc.target/sh/pr53512-3.c index 71522c8..19e9ede 100644 --- a/gcc/testsuite/gcc.target/sh/pr53512-3.c +++ b/gcc/testsuite/gcc.target/sh/pr53512-3.c @@ -1,8 +1,7 @@ /* Verify that the fsrra insn is used when specifying -mfsrra and -funsafe-math-optimizations and -ffinite-math-only. */ -/* { dg-do compile } */ +/* { dg-do compile { target { has_fsrra } } } */ /* { dg-options "-O1 -mfsrra -funsafe-math-optimizations -ffinite-math-only" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m3*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler "fsrra" } } */ #include <math.h> diff --git a/gcc/testsuite/gcc.target/sh/pr53512-4.c b/gcc/testsuite/gcc.target/sh/pr53512-4.c index 1645eed..a1d3e81 100644 --- a/gcc/testsuite/gcc.target/sh/pr53512-4.c +++ b/gcc/testsuite/gcc.target/sh/pr53512-4.c @@ -1,8 +1,7 @@ /* Verify that the fsrra insn is not used when specifying -mno-fsrra and -funsafe-math-optimizations and -ffinite-math-only. */ -/* { dg-do compile } */ +/* { dg-do compile { target { has_fsrra } } } */ /* { dg-options "-O1 -mno-fsrra -funsafe-math-optimizations -ffinite-math-only" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-not "fsrra" } } */ #include <math.h> @@ -12,4 +11,3 @@ test_func_00 (float x) { return 1 / sqrtf (x); } - diff --git a/gcc/testsuite/gcc.target/sh/pr53513-1.c b/gcc/testsuite/gcc.target/sh/pr53513-1.c index 9e4b344..a110611 100644 --- a/gcc/testsuite/gcc.target/sh/pr53513-1.c +++ b/gcc/testsuite/gcc.target/sh/pr53513-1.c @@ -1,6 +1,6 @@ /* Check that fpchg is used to switch FPSCR.PR mode on SH4A. */ +/* { dg-do compile { target { has_fpchg } } } */ /* { dg-additional-options "-O" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" } } */ /* { dg-final { scan-assembler "fpchg" } } */ /* { dg-final { scan-assembler-not "fpscr" } } */ diff --git a/gcc/testsuite/gcc.target/sh/pr54089-2.c b/gcc/testsuite/gcc.target/sh/pr54089-2.c index 17466f3..e6d6a0e 100644 --- a/gcc/testsuite/gcc.target/sh/pr54089-2.c +++ b/gcc/testsuite/gcc.target/sh/pr54089-2.c @@ -9,9 +9,8 @@ mov r4,r0 rts rotcr r0 */ -/* { dg-do compile } */ +/* { dg-do compile { target { has_dyn_shift } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m3* -m2a* -m4*" } } */ /* { dg-final { scan-assembler-not "neg" } } */ unsigned int diff --git a/gcc/testsuite/gcc.target/sh/pr54089-3.c b/gcc/testsuite/gcc.target/sh/pr54089-3.c index abdb021..7370f18 100644 --- a/gcc/testsuite/gcc.target/sh/pr54089-3.c +++ b/gcc/testsuite/gcc.target/sh/pr54089-3.c @@ -1,9 +1,8 @@ /* The dynamic shift library functions truncate the shift count to 5 bits. Verify that this is taken into account and no extra shift count truncations are generated before the library call. */ -/* { dg-do compile } */ +/* { dg-do compile { target { ! has_dyn_shift } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m1*" "-m2" "-m2e*" } } */ /* { dg-final { scan-assembler-not "and" } } */ /* { dg-final { scan-assembler-not "#31" } } */ diff --git a/gcc/testsuite/gcc.target/sh/pr54089-4.c b/gcc/testsuite/gcc.target/sh/pr54089-4.c index e01e51c..421d7bf 100644 --- a/gcc/testsuite/gcc.target/sh/pr54089-4.c +++ b/gcc/testsuite/gcc.target/sh/pr54089-4.c @@ -1,11 +1,15 @@ /* Check that the rotcr instruction is generated when shifting the - negated T bit on non-SH2A. */ + negated T bit on non-SH2A. + On SH2A expect a movrt rotr sequence instead. */ /* { dg-do compile } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */ -/* { dg-final { scan-assembler-times "rotcr" 1 } } */ -/* { dg-final { scan-assembler-times "tst" 1 } } */ -/* { dg-final { scan-assembler-times "movt" 1 } } */ + +/* { dg-final { scan-assembler-times "rotcr" 1 { target { ! sh2a } } } } */ +/* { dg-final { scan-assembler-times "tst" 1 { target { ! sh2a } } } } */ +/* { dg-final { scan-assembler-times "movt" 1 { target { ! sh2a } } } } */ + +/* { dg-final { scan-assembler-times "movrt" 1 { target { sh2a } } } } */ +/* { dg-final { scan-assembler-times "rotr" 1 { target { sh2a } } } } */ int test_00 (int a, int b) diff --git a/gcc/testsuite/gcc.target/sh/pr54089-5.c b/gcc/testsuite/gcc.target/sh/pr54089-5.c deleted file mode 100644 index decb9db..0000000 --- a/gcc/testsuite/gcc.target/sh/pr54089-5.c +++ /dev/null @@ -1,14 +0,0 @@ -/* Check that the movrt rotr instruction sequence is generated when shifting - the negated T bit on SH2A. */ -/* { dg-do compile } */ -/* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */ -/* { dg-final { scan-assembler-times "movrt" 1 } } */ -/* { dg-final { scan-assembler-times "rotr" 1 } } */ - -int -test_00 (int a, int b) -{ - int r = a != b; - return r << 31; -} diff --git a/gcc/testsuite/gcc.target/sh/pr54602-2.c b/gcc/testsuite/gcc.target/sh/pr54602-2.c index 05592dd..f5d5c77 100644 --- a/gcc/testsuite/gcc.target/sh/pr54602-2.c +++ b/gcc/testsuite/gcc.target/sh/pr54602-2.c @@ -1,9 +1,8 @@ /* Verify that the delay slot is not stuffed with register pop insns for interrupt handler function returns on SH1* and SH2* targets, where the rte insn uses the stack pointer. */ -/* { dg-do compile } */ +/* { dg-do compile { target { stack_save_isr } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m1*" "-m2*" } } */ /* { dg-final { scan-assembler-times "nop" 1 } } */ int test00 (int a, int b); diff --git a/gcc/testsuite/gcc.target/sh/pr54602-3.c b/gcc/testsuite/gcc.target/sh/pr54602-3.c index 5d6a75a..37dc005 100644 --- a/gcc/testsuite/gcc.target/sh/pr54602-3.c +++ b/gcc/testsuite/gcc.target/sh/pr54602-3.c @@ -1,8 +1,7 @@ /* Verify that the rte delay slot is not stuffed with register pop insns which touch the banked registers r0..r7 on SH3* and SH4* targets. */ -/* { dg-do compile } */ +/* { dg-do compile { target { banked_r0r7_isr } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m3*" "-m4*" } } */ /* { dg-final { scan-assembler-times "nop" 1 } } */ int __attribute__ ((interrupt_handler)) diff --git a/gcc/testsuite/gcc.target/sh/pr54602-4.c b/gcc/testsuite/gcc.target/sh/pr54602-4.c index 6bda66b..8e044ed 100644 --- a/gcc/testsuite/gcc.target/sh/pr54602-4.c +++ b/gcc/testsuite/gcc.target/sh/pr54602-4.c @@ -1,9 +1,8 @@ /* Verify that the delay slot is stuffed with register pop insns on SH3* and SH4* targets, where the stack pointer is not used by the rte insn. If everything works out, we won't see a nop insn. */ -/* { dg-do compile } */ +/* { dg-do compile { target { banked_r0r7_isr } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m3*" "-m4*" } } */ /* { dg-final { scan-assembler-not "rte\n\tnop" } } */ int test00 (int a, int b); diff --git a/gcc/testsuite/gcc.target/sh/pr54680.c b/gcc/testsuite/gcc.target/sh/pr54680.c index 807a53a..7b02de3 100644 --- a/gcc/testsuite/gcc.target/sh/pr54680.c +++ b/gcc/testsuite/gcc.target/sh/pr54680.c @@ -1,9 +1,8 @@ /* Verify that the fsca input value is not converted to float and then back to int. Notice that we can't count just "lds" insns because mode switches use "lds.l". */ -/* { dg-do compile } */ +/* { dg-do compile { target { has_fsca } } } */ /* { dg-options "-O2 -mfsca -funsafe-math-optimizations -fno-ipa-icf" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m3*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "fsca" 7 } } */ /* { dg-final { scan-assembler-times "shad" 1 } } */ /* { dg-final { scan-assembler-times "lds\tr\[0-9\],fpul" 6 } } */ diff --git a/gcc/testsuite/gcc.target/sh/pr55303-1.c b/gcc/testsuite/gcc.target/sh/pr55303-1.c index b77c5e1..bbf6570 100644 --- a/gcc/testsuite/gcc.target/sh/pr55303-1.c +++ b/gcc/testsuite/gcc.target/sh/pr55303-1.c @@ -1,8 +1,7 @@ /* Verify that the SH2A clips and clipu instructions are generated as expected. */ -/* { dg-do compile } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */ /* { dg-final { scan-assembler-times "clips.b" 2 } } */ /* { dg-final { scan-assembler-times "clips.w" 2 } } */ /* { dg-final { scan-assembler-times "clipu.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/sh/pr55303-2.c b/gcc/testsuite/gcc.target/sh/pr55303-2.c index 34f7063..4525790 100644 --- a/gcc/testsuite/gcc.target/sh/pr55303-2.c +++ b/gcc/testsuite/gcc.target/sh/pr55303-2.c @@ -1,9 +1,8 @@ /* Verify that for SH2A smax/smin -> cbranch conversion is done properly if the clips insn is not used and the expected comparison insns are generated. */ -/* { dg-do compile } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */ /* { dg-final { scan-assembler-times "cmp/pl" 4 } } */ int diff --git a/gcc/testsuite/gcc.target/sh/pr55303-3.c b/gcc/testsuite/gcc.target/sh/pr55303-3.c index 57c2f40..f5c2373 100644 --- a/gcc/testsuite/gcc.target/sh/pr55303-3.c +++ b/gcc/testsuite/gcc.target/sh/pr55303-3.c @@ -1,8 +1,7 @@ /* Verify that the special case (umin (reg const_int 1)) results in the expected instruction sequence on SH2A. */ -/* { dg-do compile } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */ /* { dg-final { scan-assembler-times "tst" 1 } } */ /* { dg-final { scan-assembler-times "movrt" 1 } } */ diff --git a/gcc/testsuite/gcc.target/sh/pr56547-1.c b/gcc/testsuite/gcc.target/sh/pr56547-1.c index 0c7c97e..d9be9be 100644 --- a/gcc/testsuite/gcc.target/sh/pr56547-1.c +++ b/gcc/testsuite/gcc.target/sh/pr56547-1.c @@ -1,9 +1,8 @@ /* Verify that the fmac insn is used for the expression 'a * b + a' and 'a * a + a'. This assumes that the default compiler setting is -ffp-contract=fast. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "fmac" 2 } } */ float diff --git a/gcc/testsuite/gcc.target/sh/pr56547-2.c b/gcc/testsuite/gcc.target/sh/pr56547-2.c index 2d36fa9..e9f1df9 100644 --- a/gcc/testsuite/gcc.target/sh/pr56547-2.c +++ b/gcc/testsuite/gcc.target/sh/pr56547-2.c @@ -1,8 +1,7 @@ /* Verify that the fmac insn is used for the expression 'a * b + a' and 'a * a + a' when -ffast-math is specified. */ -/* { dg-do compile } */ +/* { dg-do compile { target { any_fpu } } } */ /* { dg-options "-O1 -ffast-math" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ /* { dg-final { scan-assembler-times "fmac" 2 } } */ float diff --git a/gcc/testsuite/gcc.target/sh/pr61195.c b/gcc/testsuite/gcc.target/sh/pr61195.c index f3fb10b..5c79254 100644 --- a/gcc/testsuite/gcc.target/sh/pr61195.c +++ b/gcc/testsuite/gcc.target/sh/pr61195.c @@ -1,8 +1,6 @@ /* Verify that we don't switch mode for single moves. */ -/* { dg-do compile } */ -/* { dg-require-effective-target hard_float } */ -/* { dg-skip-if "" { *-*-* } { "mfmovd" } { "" } } */ -/* { dg-final { scan-assembler-not "fpscr" } } */ +/* { dg-do compile { target { any_fpu && { ! fmovd_enabled } } } } */ +/* { dg-final { scan-assembler-not "fpscr|fpchg" } } */ float *g; diff --git a/gcc/testsuite/gcc.target/sh/pr61996.c b/gcc/testsuite/gcc.target/sh/pr61996.c index 51a5f92..e839cc3 100644 --- a/gcc/testsuite/gcc.target/sh/pr61996.c +++ b/gcc/testsuite/gcc.target/sh/pr61996.c @@ -1,9 +1,8 @@ /* Check that the option -musermode has no effect on targets that do not support user/privileged mode and that it does not interfere with option -matomic-model=soft-imask. */ -/* { dg-do compile } */ +/* { dg-do compile { target { ! has_privileged } } } */ /* { dg-options "-matomic-model=soft-imask" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m1*" "-m2*" } } */ int test (void) diff --git a/gcc/testsuite/gcc.target/sh/pr6526.c b/gcc/testsuite/gcc.target/sh/pr6526.c index a49b877..7443b4d 100644 --- a/gcc/testsuite/gcc.target/sh/pr6526.c +++ b/gcc/testsuite/gcc.target/sh/pr6526.c @@ -1,8 +1,8 @@ /* Check that the XF registers are not clobbered by an integer division that is done using double precision FPU division. */ -/* { dg-do run } */ + +/* { dg-do run { target { default_single_fpu && has_xf_regs } } } */ /* { dg-options "-O1 -mdiv=call-fp" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4*-single" "-m4*-single-only" } } */ #include <assert.h> #include <stdlib.h> diff --git a/gcc/testsuite/gcc.target/sh/pragma-isr-nosave_low_regs.c b/gcc/testsuite/gcc.target/sh/pragma-isr-nosave_low_regs.c index fffc425..8c91b37 100644 --- a/gcc/testsuite/gcc.target/sh/pragma-isr-nosave_low_regs.c +++ b/gcc/testsuite/gcc.target/sh/pragma-isr-nosave_low_regs.c @@ -3,8 +3,7 @@ (On SH3* and SH4* r0..r7 are banked) Call-saved registers r8..r14 also don't need to be restored. To test that we look for register push insns such as 'mov.l r0,@-r15'. */ -/* { dg-do compile { target { { "sh*-*-*" } && nonpic } } } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1*" "-m2*" "-m5*" } { "" } } */ +/* { dg-do compile { target { { banked_r0r7_isr } && nonpic } } } */ /* { dg-options "-O" } */ /* { dg-final { scan-assembler-times "rte" 1 } } */ /* { dg-final { scan-assembler-not "mov.l\tr\[0-9\],@-r15" } } */ diff --git a/gcc/testsuite/gcc.target/sh/pragma-isr-trapa2.c b/gcc/testsuite/gcc.target/sh/pragma-isr-trapa2.c index e2e6999..49a60df 100644 --- a/gcc/testsuite/gcc.target/sh/pragma-isr-trapa2.c +++ b/gcc/testsuite/gcc.target/sh/pragma-isr-trapa2.c @@ -2,8 +2,7 @@ The function call will require to load the address first into a register, then use that for a jsr or jmp. It will also need to load a constant address in order to load fpscr. */ -/* { dg-do compile { target { { "sh*-*-*" } && nonpic } } } */ -/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ +/* { dg-do compile { target { { any_fpu } && nonpic } } } */ /* { dg-options "-O" } */ /* { dg-final { scan-assembler-times "rte" 1 } } */ /* { dg-final { scan-assembler-not "mov.l\tr\[0-9\],@-r15" } } */ diff --git a/gcc/testsuite/gcc.target/sh/prefetch.c b/gcc/testsuite/gcc.target/sh/prefetch.c index fb580bd..24b7939 100644 --- a/gcc/testsuite/gcc.target/sh/prefetch.c +++ b/gcc/testsuite/gcc.target/sh/prefetch.c @@ -1,9 +1,8 @@ -/* Testcase to check generation of a SH4 and SH2A operand cache prefetch - instruction PREF @Rm. */ -/* { dg-do assemble } */ +/* Testcase to check generation of the operand cache prefetch instruction + PREF @Rm. */ +/* { dg-do compile { target { has_pref } } } */ /* { dg-options "-O0" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" "-m3*" "-m4*" } } */ -/* { dg-final { scan-assembler "pref"} } */ +/* { dg-final { scan-assembler "pref" } } */ void opt (void) diff --git a/gcc/testsuite/gcc.target/sh/rte-delay-slot.c b/gcc/testsuite/gcc.target/sh/rte-delay-slot.c index 48f1b13..ea55212 100644 --- a/gcc/testsuite/gcc.target/sh/rte-delay-slot.c +++ b/gcc/testsuite/gcc.target/sh/rte-delay-slot.c @@ -1,6 +1,5 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { stack_save_isr } } } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m1 -m2*" } */ /* { dg-final { scan-assembler-not "\trte\t\n\tmov.l\t@r15\\+" } } */ /* This test checks if the compiler generates a pop instruction diff --git a/gcc/testsuite/gcc.target/sh/sh.exp b/gcc/testsuite/gcc.target/sh/sh.exp index f00dbd5..3064bd0 100644 --- a/gcc/testsuite/gcc.target/sh/sh.exp +++ b/gcc/testsuite/gcc.target/sh/sh.exp @@ -42,6 +42,217 @@ proc check_effective_target_sh1 { } { } ""] } +# Return 1 if target is SH4A +proc check_effective_target_sh4a { } { + return [check_no_compiler_messages sh4a object { + #ifndef __SH4A__ + #error "" + #endif + } ""] +} + +# Return 1 if target is big endian +proc check_effective_target_big_endian { } { + return [check_no_compiler_messages big_endian object { + #if __BYTE_ORDER__ != __ORDER_BIG_ENDIAN__ + #error "" + #endif + } ""] +} + +# Return 1 if target is little endian +proc check_effective_target_little_endian { } { + return [check_no_compiler_messages little_endian object { + #if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__ + #error "" + #endif + } ""] +} + +# Return 1 if the target has any FPU (single or double precision) +proc check_effective_target_any_fpu { } { + return [check_no_compiler_messages any_fpu object { + #ifndef __SH_FPU_ANY__ + #error "" + #endif + } ""] +} + +# Return 1 if the target has a double precision FPU which is allowed to be +# used by the compiler as such. +proc check_effective_target_double_fpu { } { + return [check_no_compiler_messages double_fpu object { + #ifndef __SH_FPU_DOUBLE__ + #error "" + #endif + } ""] +} + +# Return 1 if the target has a double precision FPU but it is only being used +# in single precision mode by the compiler +proc check_effective_target_use_single_only_fpu { } { + return [check_no_compiler_messages use_single_only_fpu object { + #if !(defined (__SH2A_SINGLE_ONLY__) \ + || defined (__SH4_SINGLE_ONLY__)) + #error "" + #endif + } ""] +} + +# Return 1 if the target has an FPU and the default mode is single +proc check_effective_target_default_single_fpu { } { + return [check_no_compiler_messages default_single_fpu object { + #if !(defined (__SH2E__) || defined (__SH3E__) \ + || defined (__SH2A_SINGLE__) \ + || defined (__SH2A_SINGLE_ONLY__) \ + || defined (__SH4_SINGLE__) \ + || defined (__SH4_SINGLE_ONLY__)) + #error "" + #endif + } ""] +} + +# Return 1 if the target has no FPU +proc check_effective_target_no_fpu { } { + return [check_no_compiler_messages no_fpu object { + #ifdef __SH_FPU_ANY__ + #error "" + #endif + } ""] +} + + +# Return 1 if the target has XF regs +proc check_effective_target_has_xf_regs { } { + return [check_no_compiler_messages has_xf_regs object { + #if !(defined (__SH_FPU_ANY__) \ + && (defined (__SH4__) \ + || defined (__SH4_SINGLE__) \ + || defined (__SH4_SINGLE_ONLY__) \ + || defined (__SH4A__))) + #error "" + #endif + } ""] +} + + +# Return 1 if the target can do the fsca insn +proc check_effective_target_has_fsca { } { + return [check_no_compiler_messages has_fsca object { + #if !(defined (__SH_FPU_ANY__) \ + && (defined (__SH4__) \ + || defined (__SH4_SINGLE__) \ + || defined (__SH4_SINGLE_ONLY__) \ + || defined (__SH4A__))) + #error "" + #endif + } ""] +} + +# Return 1 if the target can do the fsrra insn +proc check_effective_target_has_fsrra { } { + return [check_no_compiler_messages has_fsrra object { + #if !(defined (__SH_FPU_ANY__) \ + && (defined (__SH4__) \ + || defined (__SH4_SINGLE__) \ + || defined (__SH4_SINGLE_ONLY__) \ + || defined (__SH4A__))) + #error "" + #endif + } ""] +} + +# Return 1 if the target can do the fpchg insn +proc check_effective_target_has_fpchg { } { + return [check_no_compiler_messages has_fpchg object { + #if !(defined (__SH4A__) && defined (__SH_FPU_ANY__) \ + && !defined (__SH4_SINGLE_ONLY__)) + #error "" + #endif + } ""] +} + +# Return 1 if the target can do dynamic shifts +proc check_effective_target_has_dyn_shift { } { + return [check_no_compiler_messages has_dyn_shift object { + #if !(defined (__SH3__) \ + || defined (__SH3E__) \ + || defined (__SH2A__) \ + || defined (__SH4__) \ + || defined (__SH4_NOFPU__) \ + || defined (__SH4_SINGLE__) \ + || defined (__SH4_SINGLE_ONLY__) \ + || defined (__SH4A__)) + #error "" + #endif + } ""] +} + +# Return 1 if the mfmovd option is enabled +proc check_effective_target_fmovd_enabled { } { + return [check_no_compiler_messages fmovd_enabled object { + #ifndef __FMOVD_ENABLED__ + #error "" + #endif + } ""] +} + +# Return 1 if the target supports privileged mode +proc check_effective_target_has_privileged { } { + return [check_no_compiler_messages has_privileged object { + #if !(defined (__SH3__) \ + || defined (__SH3E__) \ + || defined (__SH4__) \ + || defined (__SH4_NOFPU__) \ + || defined (__SH4_SINGLE__) \ + || defined (__SH4_SINGLE_ONLY__) \ + || defined (__SH4A__)) + #error "" + #endif + } ""] +} + +# Return 1 if the target supports the prefetch insn +proc check_effective_target_has_pref { } { + return [check_no_compiler_messages has_pref object { + #if !(defined (__SH3__) \ + || defined (__SH3E__) \ + || defined (__SH4__) \ + || defined (__SH4_NOFPU__) \ + || defined (__SH4_SINGLE__) \ + || defined (__SH4_SINGLE_ONLY__) \ + || defined (__SH4A__)) + #error "" + #endif + } ""] +} + +# Return 1 if target does banked r0..r7 regs type of ISRs +proc check_effective_target_banked_r0r7_isr { } { + return [check_no_compiler_messages banked_r0r7_isr object { + #if !(defined (__SH3__) || defined (__SH3E__) \ + || defined (__SH4__) \ + || defined (__SH4_SINGLE__) \ + || defined (__SH4_SINGLE_ONLY__) \ + || defined (__SH4_NOFPU__) \ + || defined (__SH4A__)) + #error "" + #endif + } ""] +} + +# Return 1 if target does stack only type of ISRs +proc check_effective_target_stack_save_isr { } { + return [check_no_compiler_messages stack_save_isr object { + #if !(defined (__SH1__) \ + || defined (__SH2__) \ + || defined (__SH2E__) \ + || defined (__SH2A__)) + #error "" + #endif + } ""] +} + # Return 1 if target supports atomic-model=soft-gusa proc check_effective_target_atomic_model_soft_gusa_available { } { return [check_no_compiler_messages atomic_model_soft_gusa_available object { diff --git a/gcc/testsuite/gcc.target/sh/sh2a-band.c b/gcc/testsuite/gcc.target/sh/sh2a-band.c index a509626..fd1fe01 100644 --- a/gcc/testsuite/gcc.target/sh/sh2a-band.c +++ b/gcc/testsuite/gcc.target/sh/sh2a-band.c @@ -1,8 +1,7 @@ /* Testcase to check generation of a SH2A specific instruction for "BAND.B #imm3, @(disp12, Rn)". */ -/* { dg-do assemble } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O1 -mbitops" } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ /* { dg-final { scan-assembler "band.b"} } */ volatile struct diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bclr.c b/gcc/testsuite/gcc.target/sh/sh2a-bclr.c index ab1e3dd..7465d5b 100644 --- a/gcc/testsuite/gcc.target/sh/sh2a-bclr.c +++ b/gcc/testsuite/gcc.target/sh/sh2a-bclr.c @@ -1,8 +1,7 @@ /* Testcase to check generation of a SH2A specific instruction 'BCLR #imm3,Rn'. */ -/* { dg-do assemble } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ /* { dg-final { scan-assembler "bclr"} } */ struct a diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c b/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c index 9c99c59..d039e6e 100644 --- a/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c +++ b/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c @@ -1,8 +1,7 @@ /* Testcase to check generation of a SH2A specific instruction "BCLR #imm3,@(disp12,Rn)". */ -/* { dg-do assemble } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O2 -mbitops" } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ /* { dg-final { scan-assembler "bclr"} } */ /* { dg-final { scan-assembler "bclr.b"} } */ diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bld.c b/gcc/testsuite/gcc.target/sh/sh2a-bld.c index d0c74c9..0d4ab27 100644 --- a/gcc/testsuite/gcc.target/sh/sh2a-bld.c +++ b/gcc/testsuite/gcc.target/sh/sh2a-bld.c @@ -4,9 +4,8 @@ BLD #imm3, Rn BLD.B #imm3, @(disp12, Rn) */ -/* { dg-do assemble } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-Os -mbitops" } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ /* { dg-final { scan-assembler "bld"} } */ /* { dg-final { scan-assembler "bld.b"} } */ diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bor.c b/gcc/testsuite/gcc.target/sh/sh2a-bor.c index 8db4377..648e766 100644 --- a/gcc/testsuite/gcc.target/sh/sh2a-bor.c +++ b/gcc/testsuite/gcc.target/sh/sh2a-bor.c @@ -1,8 +1,7 @@ /* Testcase to check generation of a SH2A specific instruction for "BOR.B #imm3, @(disp12, Rn)". */ -/* { dg-do assemble } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O1 -mbitops" } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ /* { dg-final { scan-assembler "bor.b"} } */ volatile struct diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bset.c b/gcc/testsuite/gcc.target/sh/sh2a-bset.c index 322821b5..27e04b46f 100644 --- a/gcc/testsuite/gcc.target/sh/sh2a-bset.c +++ b/gcc/testsuite/gcc.target/sh/sh2a-bset.c @@ -1,8 +1,7 @@ /* Testcase to check generation of a SH2A specific instruction 'BSET #imm3,Rn'. */ -/* { dg-do assemble } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ /* { dg-final { scan-assembler "bset"} } */ struct a diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c b/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c index cf35ed6..ba57932 100644 --- a/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c +++ b/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c @@ -1,8 +1,7 @@ /* Testcase to check generation of a SH2A specific instruction "BSET #imm3,@(disp12,Rn)". */ -/* { dg-do assemble } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O2 -mbitops" } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ /* { dg-final { scan-assembler "bset"} } */ /* { dg-final { scan-assembler "bset.b"} } */ diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bxor.c b/gcc/testsuite/gcc.target/sh/sh2a-bxor.c index 6cca825..9259981 100644 --- a/gcc/testsuite/gcc.target/sh/sh2a-bxor.c +++ b/gcc/testsuite/gcc.target/sh/sh2a-bxor.c @@ -1,8 +1,7 @@ /* Testcase to check generation of a SH2A specific instruction for "BXOR.B #imm3, @(disp12, Rn)". */ -/* { dg-do assemble } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O1 -mbitops" } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ /* { dg-final { scan-assembler "bxor.b"} } */ volatile struct diff --git a/gcc/testsuite/gcc.target/sh/sh2a-jsrn.c b/gcc/testsuite/gcc.target/sh/sh2a-jsrn.c index 3f55327..62e3128 100644 --- a/gcc/testsuite/gcc.target/sh/sh2a-jsrn.c +++ b/gcc/testsuite/gcc.target/sh/sh2a-jsrn.c @@ -1,8 +1,7 @@ /* Testcase to check generation of a SH2A specific instruction for 'JSR/N @Rm'. */ -/* { dg-do assemble } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O0" } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ /* { dg-final { scan-assembler "jsr/n"} } */ void foo(void) diff --git a/gcc/testsuite/gcc.target/sh/sh2a-movi20s.c b/gcc/testsuite/gcc.target/sh/sh2a-movi20s.c index fe3226e..91cf96e 100644 --- a/gcc/testsuite/gcc.target/sh/sh2a-movi20s.c +++ b/gcc/testsuite/gcc.target/sh/sh2a-movi20s.c @@ -1,7 +1,6 @@ /* Testcase to check generation of 'MOVI20S #imm20, Rn'. */ -/* { dg-do assemble } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O0" } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ /* { dg-final { scan-assembler "movi20s"} } */ volatile long la; diff --git a/gcc/testsuite/gcc.target/sh/sh2a-movrt.c b/gcc/testsuite/gcc.target/sh/sh2a-movrt.c index 3e72930..dd2abc2 100644 --- a/gcc/testsuite/gcc.target/sh/sh2a-movrt.c +++ b/gcc/testsuite/gcc.target/sh/sh2a-movrt.c @@ -1,9 +1,8 @@ /* Testcase to check generation of a SH2A specific instruction for 'MOVRT Rn'. */ -/* { dg-do assemble } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O1" } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ -/* { dg-final { scan-assembler "movrt"} } */ +/* { dg-final { scan-assembler "movrt" } } */ int foo (void) diff --git a/gcc/testsuite/gcc.target/sh/sh2a-resbank.c b/gcc/testsuite/gcc.target/sh/sh2a-resbank.c index a12a711..bb2fa07 100644 --- a/gcc/testsuite/gcc.target/sh/sh2a-resbank.c +++ b/gcc/testsuite/gcc.target/sh/sh2a-resbank.c @@ -1,6 +1,5 @@ /* Test for resbank attribute. */ -/* { dg-do assemble } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-final { scan-assembler "resbank" } } */ extern void bar(void); diff --git a/gcc/testsuite/gcc.target/sh/sh2a-rtsn.c b/gcc/testsuite/gcc.target/sh/sh2a-rtsn.c index 612c303..78782b8 100644 --- a/gcc/testsuite/gcc.target/sh/sh2a-rtsn.c +++ b/gcc/testsuite/gcc.target/sh/sh2a-rtsn.c @@ -1,8 +1,7 @@ /* Testcase to check generation of a SH2A specific instruction for 'RTS/N'. */ -/* { dg-do assemble } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "-O0" } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ /* { dg-final { scan-assembler "rts/n"} } */ void diff --git a/gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c b/gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c index 24b57fe..7e92bb9 100644 --- a/gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c +++ b/gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c @@ -1,8 +1,7 @@ /* Testcase to check generation of a SH2A specific, TBR relative jump instruction - 'JSR @@(disp8,TBR)'. */ -/* { dg-do assemble } */ +/* { dg-do compile { target { sh2a } } } */ /* { dg-options "" } */ -/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ /* { dg-final { scan-assembler-times "jsr/n\\t@@\\(40,tbr\\)" 1} } */ /* { dg-final { scan-assembler-times "jsr/n\\t@@\\(72,tbr\\)" 1} } */ diff --git a/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c b/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c index 35ebf5c..13c6206 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c @@ -1,7 +1,6 @@ /* Verify that we generate movua to load unaligned 32-bit values on SH4A. */ -/* { dg-do run } */ +/* { dg-do run { target { sh4a } } } */ /* { dg-options "-O1 -save-temps -fno-inline" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a*" } } */ /* { dg-final { scan-assembler-times "movua.l" 6 } } */ /* Aligned. */ diff --git a/gcc/testsuite/gcc.target/sh/sh4a-cosf.c b/gcc/testsuite/gcc.target/sh/sh4a-cosf.c index d6277da..70262f8 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-cosf.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-cosf.c @@ -1,11 +1,13 @@ /* Verify that we generate single-precision sine and cosine approximate (fsca) in fast math mode on SH4A with FPU. */ -/* { dg-do compile } */ +/* { dg-do compile { target { sh4a && any_fpu } } } */ /* { dg-options "-O -ffast-math" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } } */ /* { dg-final { scan-assembler "fsca" } } */ #include <math.h> -float test(float f) { return cosf(f); } - +float +test (float f) +{ + return cosf (f); +} diff --git a/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c b/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c index 0bd7d87..ebbb05a 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c @@ -1,11 +1,13 @@ /* Verify that we generate single-precision square root reciprocal approximate (fsrra) in fast math mode on SH4A with FPU. */ -/* { dg-do compile } */ +/* { dg-do compile { target { has_fsrra } } } */ /* { dg-options "-O -ffast-math" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } } */ /* { dg-final { scan-assembler "fsrra" } } */ #include <math.h> -float test(float f) { return 1 / sqrtf(f); } - +float +test (float f) +{ + return 1 / sqrtf (f); +} diff --git a/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c b/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c index 7e817c4..bb565df 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c @@ -1,14 +1,15 @@ /* Verify that we generate movua to copy unaligned memory regions to 32-bit-aligned addresses on SH4A. */ -/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-do compile { target { sh4a } } } */ /* { dg-options "-O" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" "-m4a-nofpu" } } */ /* { dg-final { scan-assembler-times "movua.l" 2 } } */ #include <string.h> struct s { int i; char a[10], b[10]; } x; -int f() { - memcpy(x.a, x.b, 10); -} +int +f (void) +{ + memcpy (x.a, x.b, 10); +} diff --git a/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c b/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c index b85fa86..533c83c 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c @@ -1,12 +1,14 @@ /* Verify that we generate a single single-precision sine and cosine approximate (fsca) in fast math mode when a function computes both sine and cosine. */ -/* { dg-do compile } */ +/* { dg-do compile { target { sh4a && any_fpu } } } */ /* { dg-options "-O -ffast-math" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } } */ /* { dg-final { scan-assembler-times "fsca" 1 } } */ #include <math.h> -float test(float f) { return sinf(f) + cosf(f); } - +float +test (float f) +{ + return sinf (f) + cosf (f); +} diff --git a/gcc/testsuite/gcc.target/sh/sh4a-sinf.c b/gcc/testsuite/gcc.target/sh/sh4a-sinf.c index 0ce1326..fbe9592 100644 --- a/gcc/testsuite/gcc.target/sh/sh4a-sinf.c +++ b/gcc/testsuite/gcc.target/sh/sh4a-sinf.c @@ -1,11 +1,13 @@ /* Verify that we generate single-precision sine and cosine approximate (fsca) in fast math mode on SH4A with FPU. */ -/* { dg-do compile } */ +/* { dg-do compile { target { sh4a && any_fpu } } } */ /* { dg-options "-O -ffast-math" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } } */ /* { dg-final { scan-assembler "fsca" } } */ #include <math.h> -float test(float f) { return sinf(f); } - +float +test (float f) +{ + return sinf (f); +} |