diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 20 | ||||
| -rw-r--r-- | gcc/config.gcc | 9 | ||||
| -rw-r--r-- | gcc/config/arm/arm-cores.def | 107 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 129 | ||||
| -rw-r--r-- | gcc/config/arm/arm.h | 226 |
5 files changed, 172 insertions, 319 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f8cea474..e33a060 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,23 @@ +2004-04-30 Paul Brook <paul@codesourcery.com> + + * configure.gcc: Default ep9312 to hard-float. + * config/arm/arm-cores.def: Add ARCH field. + * config/arm/arm.c (FL_FOR_ARCH*): Define. + (arm_arch_cirrus): New variable. + (all_cores): Set and use arch. + (all_architectures): Ditto. + (arm_arch_name): New variable. + (arm_override_options): Set it. Use [SUB]TARGET_CPU_DEFAULT. + Set and use arm_arch_cirrus. + * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Set arch defines. + (enum processor_type): Update ARM_CORE define. + (enum target_cpus): Add. Replaces TARGET_CPU_* defines. + (CPP_SPEC): Remove %(cpp_cpu_arch). + (CPP_ARCH_DEFAULT_SPEC): Remove. + (CPP_CPU_ARCH_SPEC): Remove. + (EXTRA_SPECS): Don't use CPP_*ARCH*_SPEC. + (FPUTYPE_DEFAULT): Don't define here. + 2004-04-30 Richard Kenner <kenner@vlsi1.ultra.nyu.edu> * expr.c (store_constructor): SIZE operand is now in bits; CLEARED diff --git a/gcc/config.gcc b/gcc/config.gcc index 314018e..a33511e 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -2173,6 +2173,15 @@ if test x$with_cpu = x ; then esac fi +# Similarly for --with-float +if test x$with_fpu = x; then + case ${target} in + ep9312-*-*) + with_float=hard + ;; + esac +fi + # Similarly for --with-schedule. if test x$with_schedule = x; then case ${target} in diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 774ba6f..eeb50aa 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -20,68 +20,71 @@ 02111-1307, USA. */ /* Before using #include to read this file, define a macro: - - ARM_CORE(CORE_NAME, FLAGS) + + ARM_CORE(CORE_NAME, ARCH, FLAGS, COSTS) The CORE_NAME is the name of the core, represented as an identifier - rather than a string constant. The FLAGS are the bitwise-or of the - traits that apply to that core. + rather than a string constant. + ARCH is the architecture revision implemeted by the chip. + FLAGS are the bitwise-or of the traits that apply to that core. + This need not include flags implied by the architecture. + COSTS is the name of the rtx_costs routine to use. If you update this table, you must update the "tune" attribute in arm.md. */ -ARM_CORE(arm2, FL_CO_PROC | FL_MODE26, slowmul) -ARM_CORE(arm250, FL_CO_PROC | FL_MODE26, slowmul) -ARM_CORE(arm3, FL_CO_PROC | FL_MODE26, slowmul) -ARM_CORE(arm6, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul) -ARM_CORE(arm60, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul) -ARM_CORE(arm600, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul) -ARM_CORE(arm610, FL_MODE26 | FL_MODE32, slowmul) -ARM_CORE(arm620, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul) -ARM_CORE(arm7, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul) +ARM_CORE(arm2, 2, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE(arm250, 2, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE(arm3, 2, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE(arm6, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE(arm60, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE(arm600, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE(arm610, 3, FL_MODE26, slowmul) +ARM_CORE(arm620, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE(arm7, 3, FL_CO_PROC | FL_MODE26, slowmul) /* arm7m doesn't exist on its own, but only with D, (and I), but those don't alter the code, so arm7m is sometimes used. */ -ARM_CORE(arm7m, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M, fastmul) -ARM_CORE(arm7d, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul) -ARM_CORE(arm7dm, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M, fastmul) -ARM_CORE(arm7di, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul) -ARM_CORE(arm7dmi, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M, fastmul) -ARM_CORE(arm70, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul) -ARM_CORE(arm700, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul) -ARM_CORE(arm700i, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul) -ARM_CORE(arm710, FL_MODE26 | FL_MODE32, slowmul) -ARM_CORE(arm720, FL_MODE26 | FL_MODE32, slowmul) -ARM_CORE(arm710c, FL_MODE26 | FL_MODE32, slowmul) -ARM_CORE(arm7100, FL_MODE26 | FL_MODE32, slowmul) -ARM_CORE(arm7500, FL_MODE26 | FL_MODE32, slowmul) +ARM_CORE(arm7m, 3M, FL_CO_PROC | FL_MODE26, fastmul) +ARM_CORE(arm7d, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE(arm7dm, 3M, FL_CO_PROC | FL_MODE26, fastmul) +ARM_CORE(arm7di, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE(arm7dmi, 3M, FL_CO_PROC | FL_MODE26, fastmul) +ARM_CORE(arm70, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE(arm700, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE(arm700i, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE(arm710, 3, FL_MODE26, slowmul) +ARM_CORE(arm720, 3, FL_MODE26, slowmul) +ARM_CORE(arm710c, 3, FL_MODE26, slowmul) +ARM_CORE(arm7100, 3, FL_MODE26, slowmul) +ARM_CORE(arm7500, 3, FL_MODE26, slowmul) /* Doesn't have an external co-proc, but does have embedded fpa. */ -ARM_CORE(arm7500fe, FL_CO_PROC | FL_MODE26 | FL_MODE32, slowmul) +ARM_CORE(arm7500fe, 3, FL_CO_PROC | FL_MODE26, slowmul) /* V4 Architecture Processors */ -ARM_CORE(arm7tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB, fastmul) -ARM_CORE(arm710t, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB, fastmul) -ARM_CORE(arm720t, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB, fastmul) -ARM_CORE(arm740t, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB, fastmul) -ARM_CORE(arm8, FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED, fastmul) -ARM_CORE(arm810, FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED, fastmul) -ARM_CORE(arm9, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED, fastmul) -ARM_CORE(arm920, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED, fastmul) -ARM_CORE(arm920t, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED, fastmul) -ARM_CORE(arm940t, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED, fastmul) -ARM_CORE(arm9tdmi, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED, fastmul) -ARM_CORE(arm9e, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED, 9e) +ARM_CORE(arm7tdmi, 4T, FL_CO_PROC , fastmul) +ARM_CORE(arm710t, 4T, 0 , fastmul) +ARM_CORE(arm720t, 4T, 0 , fastmul) +ARM_CORE(arm740t, 4T, 0 , fastmul) +ARM_CORE(arm8, 4, FL_MODE26 | FL_LDSCHED, fastmul) +ARM_CORE(arm810, 4, FL_MODE26 | FL_LDSCHED, fastmul) +ARM_CORE(arm9, 4T, FL_LDSCHED, fastmul) +ARM_CORE(arm920, 4, FL_LDSCHED, fastmul) +ARM_CORE(arm920t, 4T, FL_LDSCHED, fastmul) +ARM_CORE(arm940t, 4T, FL_LDSCHED, fastmul) +ARM_CORE(arm9tdmi, 4T, FL_LDSCHED, fastmul) +ARM_CORE(arm9e, 4, FL_LDSCHED, 9e) -ARM_CORE(ep9312, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS, fastmul) -ARM_CORE(strongarm, FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_STRONG, fastmul) -ARM_CORE(strongarm110, FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_STRONG, fastmul) -ARM_CORE(strongarm1100, FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_STRONG, fastmul) -ARM_CORE(strongarm1110, FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_STRONG, fastmul) +ARM_CORE(ep9312, 4T, FL_LDSCHED | FL_CIRRUS, fastmul) +ARM_CORE(strongarm, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) +ARM_CORE(strongarm110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) +ARM_CORE(strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) +ARM_CORE(strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) /* V5 Architecture Processors */ -ARM_CORE(arm10tdmi, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5, fastmul) -ARM_CORE(arm1020t, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5, fastmul) -ARM_CORE(arm926ejs, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E, 9e) -ARM_CORE(arm1026ejs, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E, 9e) -ARM_CORE(xscale, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE, xscale) -ARM_CORE(iwmmxt, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT, xscale) +ARM_CORE(arm10tdmi, 5T, FL_LDSCHED, fastmul) +ARM_CORE(arm1020t, 5T, FL_LDSCHED, fastmul) +ARM_CORE(arm926ejs, 5TEJ, 0, 9e) +ARM_CORE(arm1026ejs, 5TEJ, 0, 9e) +ARM_CORE(xscale, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE, xscale) +ARM_CORE(iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale) /* V6 Architecture Processors */ -ARM_CORE(arm1136js, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6, 9e) -ARM_CORE(arm1136jfs, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6 | FL_VFPV2, 9e) +ARM_CORE(arm1136js, 6J, 0, 9e) +ARM_CORE(arm1136jfs, 6J, FL_VFPV2, 9e) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index f4a7ca7..a8007c9 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -331,6 +331,19 @@ int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ +#define FL_FOR_ARCH2 0 +#define FL_FOR_ARCH3 FL_MODE32 +#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) +#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4) +#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB) +#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5) +#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB) +#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E) +#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB) +#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE +#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6) +#define FL_FOR_ARCH6J FL_FOR_ARCH6 + /* The bits in this mask specify which instructions we are allowed to generate. */ static unsigned long insn_flags = 0; @@ -363,6 +376,9 @@ int arm_ld_sched = 0; /* Nonzero if this chip is a StrongARM. */ int arm_is_strong = 0; +/* Nonzero if this chip is a Cirrus variant. */ +int arm_arch_cirrus = 0; + /* Nonzero if this chip supports Intel Wireless MMX technology. */ int arm_arch_iwmmxt = 0; @@ -419,6 +435,7 @@ struct processors { const char *const name; enum processor_type core; + const char *arch; const unsigned long flags; bool (* rtx_costs) (rtx, int, int, int *); }; @@ -428,11 +445,11 @@ struct processors static const struct processors all_cores[] = { /* ARM Cores */ -#define ARM_CORE(NAME, FLAGS, COSTS) \ - {#NAME, arm_none, FLAGS, arm_##COSTS##_rtx_costs}, +#define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \ + {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs}, #include "arm-cores.def" #undef ARM_CORE - {NULL, arm_none, 0, NULL} + {NULL, arm_none, NULL, 0, NULL} }; static const struct processors all_architectures[] = @@ -441,22 +458,23 @@ static const struct processors all_architectures[] = /* We don't specify rtx_costs here as it will be figured out from the core. */ - { "armv2", arm2, FL_CO_PROC | FL_MODE26 , NULL}, - { "armv2a", arm2, FL_CO_PROC | FL_MODE26 , NULL}, - { "armv3", arm6, FL_CO_PROC | FL_MODE26 | FL_MODE32 , NULL}, - { "armv3m", arm7m, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M , NULL}, - { "armv4", arm7tdmi, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 , NULL}, + {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, + {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, + {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL}, + {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL}, + {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL}, /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no implementations that support it, so we will leave it out for now. */ - { "armv4t", arm7tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB , NULL}, - { "armv5", arm10tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 , NULL}, - { "armv5t", arm10tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 , NULL}, - { "armv5te", arm1026ejs, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E , NULL}, - { "armv6", arm1136js, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6 , NULL}, - { "armv6j", arm1136js, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6 , NULL}, - { "ep9312", ep9312, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS , NULL}, - {"iwmmxt", iwmmxt, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT , NULL}, - { NULL, arm_none, 0 , NULL} + {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL}, + {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL}, + {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL}, + {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL}, + {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL}, + {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL}, + {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL}, + {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL}, + {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, + {NULL, arm_none, NULL, 0 , NULL} }; /* This is a magic structure. The 'string' field is magically filled in @@ -471,6 +489,11 @@ struct arm_cpu_select arm_select[] = { NULL, "-mtune=", all_cores } }; + +/* The name of the proprocessor macro to define for this architecture. */ + +char arm_arch_name[] = "__ARM_ARCH_0UNK__"; + struct fpu_desc { const char * name; @@ -573,6 +596,10 @@ arm_override_options (void) for (sel = ptr->processors; sel->name != NULL; sel++) if (streq (ptr->string, sel->name)) { + /* Set the architecture define. */ + if (i != 2) + sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); + /* Determine the processor core for which we should tune code-generation. */ if (/* -mcpu= is a sensible default. */ @@ -611,52 +638,21 @@ arm_override_options (void) { const struct processors * sel; unsigned int sought; - static const struct cpu_default - { - const int cpu; - const char *const name; - } - cpu_defaults[] = - { - { TARGET_CPU_arm2, "arm2" }, - { TARGET_CPU_arm6, "arm6" }, - { TARGET_CPU_arm610, "arm610" }, - { TARGET_CPU_arm710, "arm710" }, - { TARGET_CPU_arm7m, "arm7m" }, - { TARGET_CPU_arm7500fe, "arm7500fe" }, - { TARGET_CPU_arm7tdmi, "arm7tdmi" }, - { TARGET_CPU_arm8, "arm8" }, - { TARGET_CPU_arm810, "arm810" }, - { TARGET_CPU_arm9, "arm9" }, - { TARGET_CPU_strongarm, "strongarm" }, - { TARGET_CPU_xscale, "xscale" }, - { TARGET_CPU_ep9312, "ep9312" }, - { TARGET_CPU_iwmmxt, "iwmmxt" }, - { TARGET_CPU_arm926ejs, "arm926ejs" }, - { TARGET_CPU_arm1026ejs, "arm1026ejs" }, - { TARGET_CPU_arm1136js, "arm1136js" }, - { TARGET_CPU_arm1136jfs, "arm1136jfs" }, - { TARGET_CPU_generic, "arm" }, - { 0, 0 } - }; - const struct cpu_default * def; - - /* Find the default. */ - for (def = cpu_defaults; def->name; def++) - if (def->cpu == TARGET_CPU_DEFAULT) - break; + enum processor_type cpu; - /* Make sure we found the default CPU. */ - if (def->name == NULL) - abort (); - - /* Find the default CPU's flags. */ - for (sel = all_cores; sel->name != NULL; sel++) - if (streq (def->name, sel->name)) - break; - - if (sel->name == NULL) - abort (); + cpu = TARGET_CPU_DEFAULT; + if (cpu == arm_none) + { +#ifdef SUBTARGET_CPU_DEFAULT + /* Use the subtarget default CPU if none was specified by + configure. */ + cpu = SUBTARGET_CPU_DEFAULT; +#endif + /* Default to ARM6. */ + if (cpu == arm_none) + cpu = arm6; + } + sel = &all_cores[cpu]; insn_flags = sel->flags; @@ -729,6 +725,7 @@ arm_override_options (void) insn_flags = sel->flags; } + sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); if (arm_tune == arm_none) arm_tune = (enum processor_type) (sel - all_cores); } @@ -834,6 +831,7 @@ arm_override_options (void) arm_arch5e = (insn_flags & FL_ARCH5E) != 0; arm_arch6 = (insn_flags & FL_ARCH6) != 0; arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; + arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0; arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; arm_is_strong = (tune_flags & FL_STRONG) != 0; @@ -895,14 +893,17 @@ arm_override_options (void) else { #ifdef FPUTYPE_DEFAULT - /* Use the default is it is specified for this platform. */ + /* Use the default if it is specified for this platform. */ arm_fpu_arch = FPUTYPE_DEFAULT; arm_fpu_tune = FPUTYPE_DEFAULT; #else /* Pick one based on CPU type. */ + /* ??? Some targets assume FPA is the default. if ((insn_flags & FL_VFP) != 0) arm_fpu_arch = FPUTYPE_VFP; - else if (insn_flags & FL_CIRRUS) + else + */ + if (arm_arch_cirrus) arm_fpu_arch = FPUTYPE_MAVERICK; else arm_fpu_arch = FPUTYPE_FPA_EMU2; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 8af53df..f64d338 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -26,6 +26,9 @@ #ifndef GCC_ARM_H #define GCC_ARM_H +/* The archetecture define. */ +extern char arm_arch_name[]; + /* Target CPU builtins. */ #define TARGET_CPU_CPP_BUILTINS() \ do \ @@ -69,45 +72,20 @@ \ builtin_assert ("cpu=arm"); \ builtin_assert ("machine=arm"); \ + \ + builtin_define (arm_arch_name); \ + if (arm_arch_cirrus) \ + builtin_define ("__MAVERICK__"); \ + if (arm_arch_xscale) \ + builtin_define ("__XSCALE__"); \ + if (arm_arch_iwmmxt) \ + builtin_define ("__IWMMXT__"); \ } while (0) -#define TARGET_CPU_arm2 0x0000 -#define TARGET_CPU_arm250 0x0000 -#define TARGET_CPU_arm3 0x0000 -#define TARGET_CPU_arm6 0x0001 -#define TARGET_CPU_arm600 0x0001 -#define TARGET_CPU_arm610 0x0002 -#define TARGET_CPU_arm7 0x0001 -#define TARGET_CPU_arm7m 0x0004 -#define TARGET_CPU_arm7dm 0x0004 -#define TARGET_CPU_arm7dmi 0x0004 -#define TARGET_CPU_arm700 0x0001 -#define TARGET_CPU_arm710 0x0002 -#define TARGET_CPU_arm7100 0x0002 -#define TARGET_CPU_arm7500 0x0002 -#define TARGET_CPU_arm7500fe 0x1001 -#define TARGET_CPU_arm7tdmi 0x0008 -#define TARGET_CPU_arm8 0x0010 -#define TARGET_CPU_arm810 0x0020 -#define TARGET_CPU_strongarm 0x0040 -#define TARGET_CPU_strongarm110 0x0040 -#define TARGET_CPU_strongarm1100 0x0040 -#define TARGET_CPU_arm9 0x0080 -#define TARGET_CPU_arm9tdmi 0x0080 -#define TARGET_CPU_xscale 0x0100 -#define TARGET_CPU_ep9312 0x0200 -#define TARGET_CPU_iwmmxt 0x0400 -#define TARGET_CPU_arm926ejs 0x0800 -#define TARGET_CPU_arm1026ejs 0x1000 -#define TARGET_CPU_arm1136js 0x2000 -#define TARGET_CPU_arm1136jfs 0x4000 -/* Configure didn't specify. */ -#define TARGET_CPU_generic 0x8000 - /* The various ARM cores. */ enum processor_type { -#define ARM_CORE(NAME, FLAGS, COSTS) \ +#define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \ NAME, #include "arm-cores.def" #undef ARM_CORE @@ -115,6 +93,15 @@ enum processor_type arm_none }; +enum target_cpus +{ +#define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \ + TARGET_CPU_##NAME, +#include "arm-cores.def" +#undef ARM_CORE + TARGET_CPU_generic +}; + /* The processor for which instructions should be scheduled. */ extern enum processor_type arm_tune; @@ -159,69 +146,9 @@ extern GTY(()) rtx aof_pic_label; #define TARGET_CPU_DEFAULT TARGET_CPU_generic #endif -/* If the configuration file doesn't specify the cpu, the subtarget may - override it. If it doesn't, then default to an ARM6. */ -#if TARGET_CPU_DEFAULT == TARGET_CPU_generic -#undef TARGET_CPU_DEFAULT - -#ifdef SUBTARGET_CPU_DEFAULT -#define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT -#else -#define TARGET_CPU_DEFAULT TARGET_CPU_arm6 -#endif -#endif - -#if TARGET_CPU_DEFAULT == TARGET_CPU_arm2 -#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__" -#else -#if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe -#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__" -#else -#if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m -#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__" -#else -#if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi -#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__" -#else -#if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100 -#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__" -#else -#if TARGET_CPU_DEFAULT == TARGET_CPU_xscale -#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__" -#else -#if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312 -#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__ -D__MAVERICK__" -/* Set TARGET_DEFAULT to the default, but without soft-float. */ -#ifdef TARGET_DEFAULT -#undef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME) -#endif -#else -#if TARGET_CPU_DEFAULT == TARGET_CPU_iwmmxt -#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__ -D__IWMMXT__" -#else -#if (TARGET_CPU_DEFAULT == TARGET_CPU_arm926ejs || \ - TARGET_CPU_DEFAULT == TARGET_CPU_arm1026ejs) -#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TEJ__" -#else -#if (TARGET_CPU_DEFAULT == TARGET_CPU_arm1136js || \ - TARGET_CPU_DEFAULT == TARGET_CPU_arm1136jfs) -#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_6J__" -#else -#error Unrecognized value in TARGET_CPU_DEFAULT. -#endif -#endif -#endif -#endif -#endif -#endif -#endif -#endif -#endif -#endif #undef CPP_SPEC -#define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \ +#define CPP_SPEC "%(subtarget_cpp_spec) \ %{mapcs-32:%{mapcs-26: \ %e-mapcs-26 and -mapcs-32 may not be used together}} \ %{msoft-float:%{mhard-float: \ @@ -229,96 +156,6 @@ extern GTY(()) rtx aof_pic_label; %{mbig-endian:%{mlittle-endian: \ %e-mbig-endian and -mlittle-endian may not be used together}}" -/* Set the architecture define -- if -march= is set, then it overrides - the -mcpu= setting. */ -#define CPP_CPU_ARCH_SPEC "\ -%{march=arm2:-D__ARM_ARCH_2__} \ -%{march=arm250:-D__ARM_ARCH_2__} \ -%{march=arm3:-D__ARM_ARCH_2__} \ -%{march=arm6:-D__ARM_ARCH_3__} \ -%{march=arm600:-D__ARM_ARCH_3__} \ -%{march=arm610:-D__ARM_ARCH_3__} \ -%{march=arm7:-D__ARM_ARCH_3__} \ -%{march=arm700:-D__ARM_ARCH_3__} \ -%{march=arm710:-D__ARM_ARCH_3__} \ -%{march=arm720:-D__ARM_ARCH_3__} \ -%{march=arm7100:-D__ARM_ARCH_3__} \ -%{march=arm7500:-D__ARM_ARCH_3__} \ -%{march=arm7500fe:-D__ARM_ARCH_3__} \ -%{march=arm7m:-D__ARM_ARCH_3M__} \ -%{march=arm7dm:-D__ARM_ARCH_3M__} \ -%{march=arm7dmi:-D__ARM_ARCH_3M__} \ -%{march=arm7tdmi:-D__ARM_ARCH_4T__} \ -%{march=arm8:-D__ARM_ARCH_4__} \ -%{march=arm810:-D__ARM_ARCH_4__} \ -%{march=arm9:-D__ARM_ARCH_4T__} \ -%{march=arm920:-D__ARM_ARCH_4__} \ -%{march=arm920t:-D__ARM_ARCH_4T__} \ -%{march=arm926ejs:-D__ARM_ARCH_5TEJ__} \ -%{march=arm9tdmi:-D__ARM_ARCH_4T__} \ -%{march=arm1026ejs:-D__ARM_ARCH_5TEJ__} \ -%{march=arm1136js:-D__ARM_ARCH_6J__} \ -%{march=arm1136jfs:-D__ARM_ARCH_6J__} \ -%{march=strongarm:-D__ARM_ARCH_4__} \ -%{march=strongarm110:-D__ARM_ARCH_4__} \ -%{march=strongarm1100:-D__ARM_ARCH_4__} \ -%{march=xscale:-D__ARM_ARCH_5TE__} \ -%{march=xscale:-D__XSCALE__} \ -%{march=ep9312:-D__ARM_ARCH_4T__} \ -%{march=ep9312:-D__MAVERICK__} \ -%{march=armv2:-D__ARM_ARCH_2__} \ -%{march=armv2a:-D__ARM_ARCH_2__} \ -%{march=armv3:-D__ARM_ARCH_3__} \ -%{march=armv3m:-D__ARM_ARCH_3M__} \ -%{march=armv4:-D__ARM_ARCH_4__} \ -%{march=armv4t:-D__ARM_ARCH_4T__} \ -%{march=armv5:-D__ARM_ARCH_5__} \ -%{march=armv5t:-D__ARM_ARCH_5T__} \ -%{march=armv5e:-D__ARM_ARCH_5E__} \ -%{march=armv5te:-D__ARM_ARCH_5TE__} \ -%{march=armv6:-D__ARM_ARCH6__} \ -%{march=armv6j:-D__ARM_ARCH6J__} \ -%{!march=*: \ - %{mcpu=arm2:-D__ARM_ARCH_2__} \ - %{mcpu=arm250:-D__ARM_ARCH_2__} \ - %{mcpu=arm3:-D__ARM_ARCH_2__} \ - %{mcpu=arm6:-D__ARM_ARCH_3__} \ - %{mcpu=arm600:-D__ARM_ARCH_3__} \ - %{mcpu=arm610:-D__ARM_ARCH_3__} \ - %{mcpu=arm7:-D__ARM_ARCH_3__} \ - %{mcpu=arm700:-D__ARM_ARCH_3__} \ - %{mcpu=arm710:-D__ARM_ARCH_3__} \ - %{mcpu=arm720:-D__ARM_ARCH_3__} \ - %{mcpu=arm7100:-D__ARM_ARCH_3__} \ - %{mcpu=arm7500:-D__ARM_ARCH_3__} \ - %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \ - %{mcpu=arm7m:-D__ARM_ARCH_3M__} \ - %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \ - %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \ - %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \ - %{mcpu=arm8:-D__ARM_ARCH_4__} \ - %{mcpu=arm810:-D__ARM_ARCH_4__} \ - %{mcpu=arm9:-D__ARM_ARCH_4T__} \ - %{mcpu=arm920:-D__ARM_ARCH_4__} \ - %{mcpu=arm920t:-D__ARM_ARCH_4T__} \ - %{mcpu=arm926ejs:-D__ARM_ARCH_5TEJ__} \ - %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \ - %{mcpu=arm1026ejs:-D__ARM_ARCH_5TEJ__} \ - %{mcpu=arm1136js:-D__ARM_ARCH_6J__} \ - %{mcpu=arm1136jfs:-D__ARM_ARCH_6J__} \ - %{mcpu=strongarm:-D__ARM_ARCH_4__} \ - %{mcpu=strongarm110:-D__ARM_ARCH_4__} \ - %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \ - %{mcpu=xscale:-D__ARM_ARCH_5TE__} \ - %{mcpu=xscale:-D__XSCALE__} \ - %{mcpu=ep9312:-D__ARM_ARCH_4T__} \ - %{mcpu=ep9312:-D__MAVERICK__} \ - %{mcpu=iwmmxt:-D__ARM_ARCH_5TE__} \ - %{mcpu=iwmmxt:-D__XSCALE__} \ - %{mcpu=iwmmxt:-D__IWMMXT__} \ - %{!mcpu*:%(cpp_cpu_arch_default)}} \ -" - #ifndef CC1_SPEC #define CC1_SPEC "" #endif @@ -333,8 +170,6 @@ extern GTY(()) rtx aof_pic_label; Do not define this macro if it does not need to do anything. */ #define EXTRA_SPECS \ - { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \ - { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \ { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ SUBTARGET_EXTRA_SPECS @@ -669,21 +504,6 @@ enum float_abi_type extern enum float_abi_type arm_float_abi; -/* Default floating point architecture. Override in sub-target if - necessary. - FIXME: Is this still necessary/desirable? Do we want VFP chips to - default to VFP unless overridden by a subtarget? If so it would be best - to remove these definitions. It also assumes there is only one cpu model - with a Maverick fpu. */ -#ifndef FPUTYPE_DEFAULT -#define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU2 -#endif - -#if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312 -#undef FPUTYPE_DEFAULT -#define FPUTYPE_DEFAULT FPUTYPE_MAVERICK -#endif - /* Which ABI to use. */ enum arm_abi_type { @@ -724,7 +544,7 @@ extern int thumb_code; extern int arm_is_strong; /* Nonzero if this chip is a Cirrus variant. */ -extern int arm_is_cirrus; +extern int arm_arch_cirrus; /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ extern int arm_arch_iwmmxt; |