diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 12 | ||||
| -rw-r--r-- | gcc/config/i386/i386.h | 8 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 46 |
3 files changed, 45 insertions, 21 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6fa9959..9f2f87b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2015-07-24 Uros Bizjak <ubizjak@gmail.com> + + PR target/64003 + * config/i386/i386.h (ADJUST_INSN_LENGTH): New define. + * config/i386/i386.md (maybe_prefix_bnd): New attribute. + (*jcc_1, *jcc_2, jump, simple_return_internal) + (simple_return_pop_internal): Set attribute maybe_prefix_bnd. + Set length_nobnd attribute instead of length attribute. + (indirect_jump, *tablejump_1): Set attribute maybe_prefix_bnd. + (length_nobnd): Remove attribute. + (length): Remove length_nobnd processing. + 2015-07-24 Nathan Sidwell <nathan@codesourcery.com> * gimplify.c (omp_default_clause): New function. Reorganize flow diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index ab668fe..72ec74d 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2260,6 +2260,14 @@ do { \ /* Default threshold for putting data in large sections with x86-64 medium memory model */ #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 + +/* Adjust the length of the insn with the length of BND prefix. */ +#define ADJUST_INSN_LENGTH(INSN, LENGTH) \ +do { \ + if (recog_memoized (INSN) >= 0 \ + && get_attr_maybe_prefix_bnd (INSN)) \ + LENGTH += ix86_bnd_prefixed_insn_p (INSN); \ +} while (0) /* Which processor to tune code generation for. These must be in sync with processor_target_table in i386.c. */ diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 18d0503..6b924e7 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -568,6 +568,9 @@ ] (const_int 0))) +;; Set when BND opcode prefix may be used. +(define_attr "maybe_prefix_bnd" "" (const_int 0)) + ;; Prefix used: original, VEX or maybe VEX. (define_attr "prefix" "orig,vex,maybe_vex,evex,maybe_evex" (cond [(eq_attr "mode" "OI,V8SF,V4DF") @@ -635,19 +638,12 @@ ] (const_int 1))) -;; When this attribute is set, calculate total insn length from -;; length_nobnd attribute, prefixed with eventual bnd prefix byte -(define_attr "length_nobnd" "" (const_int 0)) - ;; The (bounding maximum) length of an instruction in bytes. ;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences. ;; Later we may want to split them and compute proper length as for ;; other insns. (define_attr "length" "" - (cond [(eq_attr "length_nobnd" "!0") - (plus (symbol_ref ("ix86_bnd_prefixed_insn_p (insn)")) - (attr "length_nobnd")) - (eq_attr "type" "other,multi,fistp,frndint") + (cond [(eq_attr "type" "other,multi,fistp,frndint") (const_int 16) (eq_attr "type" "fcmp") (const_int 4) @@ -11133,14 +11129,15 @@ "%!%+j%C1\t%l0" [(set_attr "type" "ibr") (set_attr "modrm" "0") - (set (attr "length_nobnd") + (set (attr "length") (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -126)) (lt (minus (match_dup 0) (pc)) (const_int 128))) (const_int 2) - (const_int 6)))]) + (const_int 6))) + (set_attr "maybe_prefix_bnd" "1")]) (define_insn "*jcc_2" [(set (pc) @@ -11152,14 +11149,15 @@ "%!%+j%c1\t%l0" [(set_attr "type" "ibr") (set_attr "modrm" "0") - (set (attr "length_nobnd") + (set (attr "length") (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -126)) (lt (minus (match_dup 0) (pc)) (const_int 128))) (const_int 2) - (const_int 6)))]) + (const_int 6))) + (set_attr "maybe_prefix_bnd" "1")]) ;; In general it is not safe to assume too much about CCmode registers, ;; so simplify-rtx stops when it sees a second one. Under certain @@ -11425,14 +11423,15 @@ "%!jmp\t%l0" [(set_attr "type" "ibr") (set_attr "modrm" "0") - (set (attr "length_nobnd") + (set (attr "length") (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -126)) (lt (minus (match_dup 0) (pc)) (const_int 128))) (const_int 2) - (const_int 5)))]) + (const_int 5))) + (set_attr "maybe_prefix_bnd" "1")]) (define_expand "indirect_jump" [(set (pc) (match_operand 0 "indirect_branch_operand"))] @@ -11447,7 +11446,8 @@ "" "%!jmp\t%A0" [(set_attr "type" "ibr") - (set_attr "length_immediate" "0")]) + (set_attr "length_immediate" "0") + (set_attr "maybe_prefix_bnd" "1")]) (define_expand "tablejump" [(parallel [(set (pc) (match_operand 0 "indirect_branch_operand")) @@ -11496,7 +11496,8 @@ "" "%!jmp\t%A0" [(set_attr "type" "ibr") - (set_attr "length_immediate" "0")]) + (set_attr "length_immediate" "0") + (set_attr "maybe_prefix_bnd" "1")]) ;; Convert setcc + movzbl to xor + setcc if operands don't overlap. @@ -12072,10 +12073,11 @@ [(simple_return)] "reload_completed" "%!ret" - [(set_attr "length_nobnd" "1") + [(set_attr "length" "1") (set_attr "atom_unit" "jeu") (set_attr "length_immediate" "0") - (set_attr "modrm" "0")]) + (set_attr "modrm" "0") + (set_attr "maybe_prefix_bnd" "1")]) ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET ;; instruction Athlon and K8 have. @@ -12101,10 +12103,11 @@ (use (match_operand:SI 0 "const_int_operand"))] "reload_completed" "%!ret\t%0" - [(set_attr "length_nobnd" "3") + [(set_attr "length" "3") (set_attr "atom_unit" "jeu") (set_attr "length_immediate" "2") - (set_attr "modrm" "0")]) + (set_attr "modrm" "0") + (set_attr "maybe_prefix_bnd" "1")]) (define_insn "simple_return_indirect_internal" [(simple_return) @@ -12112,7 +12115,8 @@ "reload_completed" "%!jmp\t%A0" [(set_attr "type" "ibr") - (set_attr "length_immediate" "0")]) + (set_attr "length_immediate" "0") + (set_attr "maybe_prefix_bnd" "1")]) (define_insn "nop" [(const_int 0)] |