diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 15 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 79 |
2 files changed, 63 insertions, 31 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5f4d7fd..6626ba4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2016-05-07 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (*addqi_1): Add preferred_for_speed attribute + to disparage alternatives 3 and 4 for TARGET_PARTIAL_REG_STALL targets. + (*andqi_1): Add preferred_for_speed attribute to disparage + alternative 2 for TARGET_PARTIAL_REG_STALL targets. + (*<code>qi_1): Ditto. + (*one_cmplqi2_1): Add preferred_for_speed attribute to disparage + alternative 1 for TARGET_PARTIAL_REG_STALL targets. + (*ashlqi3_1): Ditto. + (*swap<mode>): Merge from *swap<mode>_1 and *swap<mode>_2 patterns. + Add preferred_for_size attribute to disparage alternative 0 and + preferred_for_speed attribute to disparage alternative 1 for + TARGET_PARTIAL_REG_STALL targets. + 2016-05-07 Tom de Vries <tom@codesourcery.com> PR tree-optimization/70956 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 2b7ff31..52b0775 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2699,34 +2699,31 @@ (set_attr "amdfam10_decode" "double") (set_attr "bdver1_decode" "double")]) -(define_insn "*swap<mode>_1" - [(set (match_operand:SWI12 0 "register_operand" "+r") - (match_operand:SWI12 1 "register_operand" "+r")) +(define_insn "*swap<mode>" + [(set (match_operand:SWI12 0 "register_operand" "+<r>,r") + (match_operand:SWI12 1 "register_operand" "+<r>,r")) (set (match_dup 1) (match_dup 0))] - "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" - "xchg{l}\t%k1, %k0" + "" + "@ + xchg{<imodesuffix>}\t%1, %0 + xchg{l}\t%k1, %k0" [(set_attr "type" "imov") - (set_attr "mode" "SI") + (set_attr "mode" "<MODE>,SI") + (set (attr "preferred_for_size") + (cond [(eq_attr "alternative" "0") + (symbol_ref "false")] + (symbol_ref "true"))) + ;; Potential partial reg stall on alternative 1. + (set (attr "preferred_for_speed") + (cond [(eq_attr "alternative" "1") + (symbol_ref "!TARGET_PARTIAL_REG_STALL")] + (symbol_ref "true"))) (set_attr "pent_pair" "np") (set_attr "athlon_decode" "vector") (set_attr "amdfam10_decode" "double") (set_attr "bdver1_decode" "double")]) -;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL -;; is disabled for AMDFAM10 -(define_insn "*swap<mode>_2" - [(set (match_operand:SWI12 0 "register_operand" "+<r>") - (match_operand:SWI12 1 "register_operand" "+<r>")) - (set (match_dup 1) - (match_dup 0))] - "TARGET_PARTIAL_REG_STALL" - "xchg{<imodesuffix>}\t%1, %0" - [(set_attr "type" "imov") - (set_attr "mode" "<MODE>") - (set_attr "pent_pair" "np") - (set_attr "athlon_decode" "vector")]) - (define_expand "movstrict<mode>" [(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand")) (match_operand:SWI12 1 "general_operand"))] @@ -5607,7 +5604,6 @@ (const_string "*"))) (set_attr "mode" "HI,HI,HI,SI")]) -;; %%% Potential partial reg stall on alternatives 3 and 4. What to do? (define_insn "*addqi_1" [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,q,r,r,Yp") (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,q,0,r,Yp") @@ -5615,7 +5611,7 @@ (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (PLUS, QImode, operands)" { - bool widen = (which_alternative == 3 || which_alternative == 4); + bool widen = (get_attr_mode (insn) != MODE_QI); switch (get_attr_type (insn)) { @@ -5664,7 +5660,12 @@ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) - (set_attr "mode" "QI,QI,QI,SI,SI,SI")]) + (set_attr "mode" "QI,QI,QI,SI,SI,SI") + ;; Potential partial reg stall on alternatives 3 and 4. + (set (attr "preferred_for_speed") + (cond [(eq_attr "alternative" "3,4") + (symbol_ref "!TARGET_PARTIAL_REG_STALL")] + (symbol_ref "true")))]) (define_insn "*addqi_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) @@ -8215,7 +8216,6 @@ (const_string "*"))) (set_attr "mode" "HI,HI,SI,HI")]) -;; %%% Potential partial reg stall on alternative 2. What to do? (define_insn "*andqi_1" [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,!k") (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,k") @@ -8238,7 +8238,12 @@ } } [(set_attr "type" "alu,alu,alu,msklog") - (set_attr "mode" "QI,QI,SI,HI")]) + (set_attr "mode" "QI,QI,SI,HI") + ;; Potential partial reg stall on alternative 2. + (set (attr "preferred_for_speed") + (cond [(eq_attr "alternative" "2") + (symbol_ref "!TARGET_PARTIAL_REG_STALL")] + (symbol_ref "true")))]) (define_insn "*andqi_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) @@ -8723,7 +8728,6 @@ [(set_attr "type" "alu,alu,msklog") (set_attr "mode" "HI")]) -;; %%% Potential partial reg stall on alternative 2. What to do? (define_insn "*<code>qi_1" [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r,!k") (any_or:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,k") @@ -8736,7 +8740,12 @@ <logic>{l}\t{%k2, %k0|%k0, %k2} k<logic>w\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "alu,alu,alu,msklog") - (set_attr "mode" "QI,QI,SI,HI")]) + (set_attr "mode" "QI,QI,SI,HI") + ;; Potential partial reg stall on alternative 2. + (set (attr "preferred_for_speed") + (cond [(eq_attr "alternative" "2") + (symbol_ref "!TARGET_PARTIAL_REG_STALL")] + (symbol_ref "true")))]) ;; See comment for addsi_1_zext why we do use nonimmediate_operand (define_insn "*<code>si_1_zext" @@ -9513,7 +9522,6 @@ (set_attr "prefix" "*,vex") (set_attr "mode" "HI")]) -;; %%% Potential partial reg stall on alternative 1. What to do? (define_insn "*one_cmplqi2_1" [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,!k") (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,k")))] @@ -9536,7 +9544,12 @@ [(set_attr "isa" "*,*,avx512f") (set_attr "type" "negnot,negnot,msklog") (set_attr "prefix" "*,*,vex") - (set_attr "mode" "QI,SI,QI")]) + (set_attr "mode" "QI,SI,QI") + ;; Potential partial reg stall on alternative 1. + (set (attr "preferred_for_speed") + (cond [(eq_attr "alternative" "1") + (symbol_ref "!TARGET_PARTIAL_REG_STALL")] + (symbol_ref "true")))]) ;; ??? Currently never generated - xor is used instead. (define_insn "*one_cmplsi2_1_zext" @@ -9955,7 +9968,6 @@ (const_string "*"))) (set_attr "mode" "HI,SI")]) -;; %%% Potential partial reg stall on alternative 1. What to do? (define_insn "*ashlqi3_1" [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,Yp") (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,l") @@ -10011,7 +10023,12 @@ (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") (const_string "*"))) - (set_attr "mode" "QI,SI,SI")]) + (set_attr "mode" "QI,SI,SI") + ;; Potential partial reg stall on alternative 1. + (set (attr "preferred_for_speed") + (cond [(eq_attr "alternative" "1") + (symbol_ref "!TARGET_PARTIAL_REG_STALL")] + (symbol_ref "true")))]) (define_insn "*ashlqi3_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) |