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-rw-r--r--gcc/config/i386/sse.md2
-rw-r--r--gcc/testsuite/gcc.target/i386/pr53652-1.c16
2 files changed, 17 insertions, 1 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index d8f3035..0864748 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -16631,7 +16631,7 @@
(define_insn "*andnot<mode>3"
[(set (match_operand:VI 0 "register_operand" "=x,x,v")
(and:VI
- (not:VI (match_operand:VI 1 "register_operand" "0,x,v"))
+ (not:VI (match_operand:VI 1 "vector_operand" "0,x,v"))
(match_operand:VI 2 "bcst_vector_operand" "xBm,xm,vmBr")))]
"TARGET_SSE"
{
diff --git a/gcc/testsuite/gcc.target/i386/pr53652-1.c b/gcc/testsuite/gcc.target/i386/pr53652-1.c
new file mode 100644
index 0000000..bd07ee2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr53652-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-final { scan-assembler-times "pandn\[ \\t\]" 2 } } */
+/* { dg-final { scan-assembler-not "vpternlogq\[ \\t\]" } } */
+
+typedef unsigned long long vec __attribute__((vector_size (16)));
+vec g;
+vec f1 (vec a, vec b)
+{
+ return ~a&b;
+}
+vec f2 (vec a, vec b)
+{
+ return ~g&b;
+}
+