diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/pa/pa.h | 3 | ||||
| -rw-r--r-- | gcc/config/pa/pa.md | 100 |
2 files changed, 103 insertions, 0 deletions
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 7e45c35..6fcc2fa 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -480,6 +480,9 @@ extern rtx hppa_pic_save_rtx (void); #define INDEX_REG_CLASS GENERAL_REGS #define BASE_REG_CLASS GENERAL_REGS +/* True if register is a general register. */ +#define GENERAL_REGNO_P(N) ((N) >= 1 && (N) <= 31) + #define FP_REG_CLASS_P(CLASS) \ ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS) diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 1e781ef..f0520bb 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2280,6 +2280,58 @@ (set_attr "pa_combine_type" "addmove") (set_attr "length" "4")]) +; Rewrite RTL using a REG+D store. This will allow the insn that +; computes the address to be deleted if the register it sets is dead. +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "") + (plus:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" ""))) + (set (mem:SI (match_dup 0)) + (match_operand:SI 3 "register_operand" ""))] + "!TARGET_64BIT + && !INT14_OK_STRICT + && GENERAL_REGNO_P (REGNO (operands[0])) + && GENERAL_REGNO_P (REGNO (operands[3])) + && REGNO (operands[0]) != REGNO (operands[3]) + && base14_operand (operands[2], E_SImode)" + [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2))) (match_dup 3)) + (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] + "") + +; Rewrite RTL using a REG+D load. This will allow the insn that +; computes the address to be deleted if the register it sets is dead. +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "") + (plus:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" ""))) + (set (match_operand:SI 3 "register_operand" "") + (mem:SI (match_dup 0)))] + "!TARGET_64BIT + && !INT14_OK_STRICT + && GENERAL_REGNO_P (REGNO (operands[0])) + && GENERAL_REGNO_P (REGNO (operands[3])) + && REGNO (operands[0]) != REGNO (operands[3]) + && REGNO (operands[1]) != REGNO (operands[3]) + && base14_operand (operands[2], E_SImode)" + [(set (match_dup 3) (mem:SI (plus:SI (match_dup 1) (match_dup 2)))) + (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] + "") + +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "") + (plus:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" ""))) + (set (match_operand:SI 3 "register_operand" "") + (mem:SI (match_dup 0)))] + "!TARGET_64BIT + && !INT14_OK_STRICT + && GENERAL_REGNO_P (REGNO (operands[0])) + && GENERAL_REGNO_P (REGNO (operands[3])) + && REGNO (operands[0]) == REGNO (operands[3]) + && base14_operand (operands[2], E_SImode)" + [(set (match_dup 3) (mem:SI (plus:SI (match_dup 1) (match_dup 2))))] + "") + ; Rewrite RTL using an indexed store. This will allow the insn that ; computes the address to be deleted if the register it sets is dead. (define_peephole2 @@ -4509,6 +4561,54 @@ (define_peephole2 [(set (match_operand:SI 0 "register_operand" "") + (plus:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" ""))) + (set (mem:SF (match_dup 0)) + (match_operand:SF 3 "register_operand" ""))] + "!TARGET_64BIT + && !INT14_OK_STRICT + && GENERAL_REGNO_P (REGNO (operands[0])) + && GENERAL_REGNO_P (REGNO (operands[3])) + && REGNO (operands[0]) != REGNO (operands[3]) + && base14_operand (operands[2], E_SImode)" + [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2))) (match_dup 3)) + (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] + "") + +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "") + (plus:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" ""))) + (set (match_operand:SF 3 "register_operand" "") + (mem:SF (match_dup 0)))] + "!TARGET_64BIT + && !INT14_OK_STRICT + && GENERAL_REGNO_P (REGNO (operands[0])) + && GENERAL_REGNO_P (REGNO (operands[3])) + && REGNO (operands[0]) != REGNO (operands[3]) + && REGNO (operands[1]) != REGNO (operands[3]) + && base14_operand (operands[2], E_SImode)" + [(set (match_dup 3) (mem:SF (plus:DI (match_dup 1) (match_dup 2)))) + (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] + "") + +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "") + (plus:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" ""))) + (set (match_operand:SF 3 "register_operand" "") + (mem:SF (match_dup 0)))] + "!TARGET_64BIT + && !INT14_OK_STRICT + && GENERAL_REGNO_P (REGNO (operands[0])) + && GENERAL_REGNO_P (REGNO (operands[3])) + && REGNO (operands[0]) == REGNO (operands[3]) + && base14_operand (operands[2], E_SImode)" + [(set (match_dup 3) (mem:SF (plus:DI (match_dup 1) (match_dup 2))))] + "") + +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "") (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "") (const_int 2)) (match_operand:SI 2 "register_operand" ""))) |