diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 38 | ||||
| -rw-r--r-- | gcc/config/i386/i386-builtin.def | 46 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 18 | ||||
| -rw-r--r-- | gcc/config/i386/i386.h | 5 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 13 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 14 |
6 files changed, 65 insertions, 69 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 63e228e..b25afd5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,16 @@ 2017-08-19 Uros Bizjak <ubizjak@gmail.com> + * config/i386/i386.h (OPTION_MASK_ISA_ROUND): Remove. + (TARGET_ISA_ROUND): Ditto. + (TARGET_ROUND): Ditto. + * config/i386/i386.c: Substitute TARGET_ROUND with TARGET_SSE4_1. + * config/i386/i386.md: Ditto. + * config/i386/sse.md: Ditto. + * config/i386/i386-builtin.def: Substitute OPTION_MASK_ISA_ROUND + with OPTION_MASK_ISA_SSE4_1. + +2017-08-19 Uros Bizjak <ubizjak@gmail.com> + PR target/81894 * doc/extend.texi (x86 Built-in Functions): Correct the name of __builtin_ia32_lzcnt_u16. @@ -18,8 +29,8 @@ * stor-layout.c (do_type_align): Merge DECL_WARN_IF_NOT_ALIGN. (handle_warn_if_not_align): New. (place_union_field): Call handle_warn_if_not_align. - (place_field): Call handle_warn_if_not_align. Copy - TYPE_WARN_IF_NOT_ALIGN. + (place_field): Call handle_warn_if_not_align. + Copy TYPE_WARN_IF_NOT_ALIGN. (finish_builtin_struct): Copy TYPE_WARN_IF_NOT_ALIGN. (layout_type): Likewise. * tree-core.h (tree_type_common): Add warn_if_not_align. Set @@ -31,14 +42,12 @@ (DECL_WARN_IF_NOT_ALIGN): Likewise. (SET_DECL_WARN_IF_NOT_ALIGN): Likewise. * doc/extend.texi: Document warn_if_not_aligned attribute. - * doc/invoke.texi: Document -Wif-not-aligned and - -Wpacked-not-aligned. + * doc/invoke.texi: Document -Wif-not-aligned and -Wpacked-not-aligned. 2017-08-17 Martin Liska <mliska@suse.cz> PR bootstrap/81864 - * tree-loop-distribution.c (ddrs_table): Change type to pointer - type. + * tree-loop-distribution.c (ddrs_table): Change type to pointer type. (get_data_dependence): Use it as pointer type. (distribute_loop): Likewise. @@ -129,8 +138,7 @@ 2017-08-17 Richard Biener <rguenther@suse.de> PR tree-optimization/81827 - * tree-ssa-structalias.c (struct variable_info): Add is_reg_var - flag. + * tree-ssa-structalias.c (struct variable_info): Add is_reg_var flag. (new_var_info): Initialize it conservatively. (get_call_vi): Mark register vars. (new_scalar_tmp_constraint_exp): Likewise. @@ -143,14 +151,12 @@ 2017-08-17 Marek Polacek <polacek@redhat.com> - * gimplify.c (gimplify_adjust_omp_clauses): Compare with 0 instead of - 1. + * gimplify.c (gimplify_adjust_omp_clauses): Compare with 0 instead of 1. 2017-08-17 Richard Biener <rguenther@suse.de> * tree-vrp.c (vrp_int_const_binop): Do not set *overflow_p - to true when overflow is undefined and we saturated the - result. + to true when overflow is undefined and we saturated the result. 2017-08-17 Alan Modra <amodra@gmail.com> @@ -178,16 +184,10 @@ Likewise. * tree-streamer-out.c (write_ts_type_non_common_tree_pointers): Likewise. - - lto/ - * lto.c (mentions_vars_p_type): Use TYPE_LANG_SLOT_1. - (compare_tree_sccs_1): No need to compare TYPE_BINFO directly. - (lto_fixup_prevailing_decls): Use TYPE_LANG_SLOT_1. 2017-08-16 David Malcolm <dmalcolm@redhat.com> - * diagnostic-show-locus.c (colorizer::m_caret): Remove unused - field. + * diagnostic-show-locus.c (colorizer::m_caret): Remove unused field. 2017-08-16 Uros Bizjak <ubizjak@gmail.com> diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index e91468a..6ce9074 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -852,36 +852,36 @@ BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmu BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI) /* SSE4.1 */ -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST) -BDESC (OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST) +BDESC (OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST) /* SSE4.2 */ BDESC (OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 3720d275..a7bb7f9 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -39909,7 +39909,7 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, CASE_CFN_LFLOOR: CASE_CFN_LLFLOOR: /* The round insn does not trap on denormals. */ - if (flag_trapping_math || !TARGET_ROUND) + if (flag_trapping_math || !TARGET_SSE4_1) break; if (out_mode == SImode && in_mode == DFmode) @@ -39936,7 +39936,7 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, CASE_CFN_LCEIL: CASE_CFN_LLCEIL: /* The round insn does not trap on denormals. */ - if (flag_trapping_math || !TARGET_ROUND) + if (flag_trapping_math || !TARGET_SSE4_1) break; if (out_mode == SImode && in_mode == DFmode) @@ -39986,7 +39986,7 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, CASE_CFN_LROUND: CASE_CFN_LLROUND: /* The round insn does not trap on denormals. */ - if (flag_trapping_math || !TARGET_ROUND) + if (flag_trapping_math || !TARGET_SSE4_1) break; if (out_mode == SImode && in_mode == DFmode) @@ -40011,7 +40011,7 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, CASE_CFN_FLOOR: /* The round insn does not trap on denormals. */ - if (flag_trapping_math || !TARGET_ROUND) + if (flag_trapping_math || !TARGET_SSE4_1) break; if (out_mode == DFmode && in_mode == DFmode) @@ -40036,7 +40036,7 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, CASE_CFN_CEIL: /* The round insn does not trap on denormals. */ - if (flag_trapping_math || !TARGET_ROUND) + if (flag_trapping_math || !TARGET_SSE4_1) break; if (out_mode == DFmode && in_mode == DFmode) @@ -40061,7 +40061,7 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, CASE_CFN_TRUNC: /* The round insn does not trap on denormals. */ - if (flag_trapping_math || !TARGET_ROUND) + if (flag_trapping_math || !TARGET_SSE4_1) break; if (out_mode == DFmode && in_mode == DFmode) @@ -40086,7 +40086,7 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, CASE_CFN_RINT: /* The round insn does not trap on denormals. */ - if (flag_trapping_math || !TARGET_ROUND) + if (flag_trapping_math || !TARGET_SSE4_1) break; if (out_mode == DFmode && in_mode == DFmode) @@ -52281,7 +52281,7 @@ ix86_optab_supported_p (int op, machine_mode mode1, machine_mode, if (SSE_FLOAT_MODE_P (mode1) && TARGET_SSE_MATH && !flag_trapping_math - && !TARGET_ROUND) + && !TARGET_SSE4_1) return opt_type == OPTIMIZE_FOR_SPEED; return true; @@ -52291,7 +52291,7 @@ ix86_optab_supported_p (int op, machine_mode mode1, machine_mode, if (SSE_FLOAT_MODE_P (mode1) && TARGET_SSE_MATH && !flag_trapping_math - && TARGET_ROUND) + && TARGET_SSE4_1) return true; return opt_type == OPTIMIZE_FOR_SPEED; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index e8ae3e3..f4c96fc 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -97,7 +97,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x) #define TARGET_LWP TARGET_ISA_LWP #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x) -#define TARGET_ROUND TARGET_ISA_ROUND #define TARGET_ABM TARGET_ISA_ABM #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) #define TARGET_SGX TARGET_ISA_SGX @@ -176,10 +175,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_16BIT TARGET_CODE16 #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) -/* SSE4.1 defines round instructions */ -#define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1 -#define TARGET_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) - #include "config/vxworks-dummy.h" #include "config/i386/i386-opts.h" diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 14688a8..0d04bff 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -15563,7 +15563,7 @@ (unspec:MODEF [(match_operand:MODEF 1 "register_operand" "x,v") (match_operand:SI 2 "const_0_to_15_operand" "n,n")] UNSPEC_ROUND))] - "TARGET_ROUND" + "TARGET_SSE4_1" "@ %vround<ssemodesuffix>\t{%2, %1, %d0|%d0, %1, %2} vrndscale<ssemodesuffix>\t{%2, %1, %d0|%d0, %1, %2}" @@ -15604,7 +15604,7 @@ { if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) { - if (TARGET_ROUND) + if (TARGET_SSE4_1) emit_insn (gen_sse4_1_round<mode>2 (operands[0], operands[1], GEN_INT (ROUND_MXCSR))); else @@ -15628,7 +15628,7 @@ if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH && !flag_trapping_math && !flag_rounding_math) { - if (TARGET_ROUND) + if (TARGET_SSE4_1) { operands[1] = force_reg (<MODE>mode, operands[1]); ix86_expand_round_sse4 (operands[0], operands[1]); @@ -15890,12 +15890,13 @@ || TARGET_MIX_SSE_I387) && (flag_fp_int_builtin_inexact || !flag_trapping_math)) || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH - && (TARGET_ROUND || !flag_trapping_math || flag_fp_int_builtin_inexact))" + && (TARGET_SSE4_1 || !flag_trapping_math + || flag_fp_int_builtin_inexact))" { if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH - && (TARGET_ROUND || !flag_trapping_math || flag_fp_int_builtin_inexact)) + && (TARGET_SSE4_1 || !flag_trapping_math || flag_fp_int_builtin_inexact)) { - if (TARGET_ROUND) + if (TARGET_SSE4_1) emit_insn (gen_sse4_1_round<mode>2 (operands[0], operands[1], GEN_INT (ROUND_<ROUNDING> | ROUND_NO_EXC))); diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 253ff5d..4f2328f 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15605,7 +15605,7 @@ [(match_operand:VF_128_256 1 "vector_operand" "YrBm,*xBm,xm") (match_operand:SI 2 "const_0_to_15_operand" "n,n,n")] UNSPEC_ROUND))] - "TARGET_ROUND" + "TARGET_SSE4_1" "%vround<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "ssecvt") @@ -15619,7 +15619,7 @@ [(match_operand:<sseintvecmode> 0 "register_operand") (match_operand:VF1_128_256 1 "vector_operand") (match_operand:SI 2 "const_0_to_15_operand")] - "TARGET_ROUND" + "TARGET_SSE4_1" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -15658,7 +15658,7 @@ (match_operand:VF2 1 "vector_operand") (match_operand:VF2 2 "vector_operand") (match_operand:SI 3 "const_0_to_15_operand")] - "TARGET_ROUND" + "TARGET_SSE4_1" { rtx tmp0, tmp1; @@ -15700,7 +15700,7 @@ UNSPEC_ROUND) (match_operand:VF_128 1 "register_operand" "0,0,x,v") (const_int 1)))] - "TARGET_ROUND" + "TARGET_SSE4_1" "@ round<ssescalarmodesuffix>\t{%3, %2, %0|%0, %2, %3} round<ssescalarmodesuffix>\t{%3, %2, %0|%0, %2, %3} @@ -15723,7 +15723,7 @@ (unspec:VF [(match_dup 3) (match_dup 4)] UNSPEC_ROUND))] - "TARGET_ROUND && !flag_trapping_math" + "TARGET_SSE4_1 && !flag_trapping_math" { machine_mode scalar_mode; const struct real_format *fmt; @@ -15751,7 +15751,7 @@ (define_expand "round<mode>2_sfix" [(match_operand:<sseintvecmode> 0 "register_operand") (match_operand:VF1 1 "register_operand")] - "TARGET_ROUND && !flag_trapping_math" + "TARGET_SSE4_1 && !flag_trapping_math" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -15766,7 +15766,7 @@ [(match_operand:<ssepackfltmode> 0 "register_operand") (match_operand:VF2 1 "register_operand") (match_operand:VF2 2 "register_operand")] - "TARGET_ROUND && !flag_trapping_math" + "TARGET_SSE4_1 && !flag_trapping_math" { rtx tmp0, tmp1; |