diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 71 | ||||
| -rw-r--r-- | gcc/DATESTAMP | 2 | ||||
| -rw-r--r-- | gcc/ada/ChangeLog | 83 | ||||
| -rw-r--r-- | gcc/c-family/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/riscv/predicates.md | 4 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.md | 2 | ||||
| -rw-r--r-- | gcc/config/rs6000/vxworks.h | 15 | ||||
| -rw-r--r-- | gcc/config/sh/predicates.md | 4 | ||||
| -rw-r--r-- | gcc/config/sh/sh-protos.h | 1 | ||||
| -rw-r--r-- | gcc/config/sh/sh.cc | 17 | ||||
| -rw-r--r-- | gcc/cp/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/fortran/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/fortran/io.cc | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 99 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/pr118241-b.cc | 33 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/sh/pr54236-2.c | 14 |
16 files changed, 352 insertions, 15 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3d625ce..319b756 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,74 @@ +2025-07-05 Alexandre Oliva <oliva@adacore.com> + + * config/rs6000/vxworks.h (SUBTARGET_DRIVER_SELF_SPECS): + Redefine to select word size matching TARGET_VXWORKS64. + (TARGET_VXWORKS64): Redefine in terms of TARGET_64BIT. + +2025-07-04 Vineet Gupta <vineetg@rivosinc.com> + + PR target/118241 + * config/riscv/riscv.md (prefetch): Add alternative "r". + +2025-07-04 Vineet Gupta <vineetg@rivosinc.com> + + * config/riscv/predicates.md (prefetch_operand): mack 5 bits. + +2025-07-04 Raphael Moreira Zinsly <rzinsly@ventanamicro.com> + + * config/sh/predicates.md + (treg_set_expr_not_const01): call sh_recog_treg_set_expr_not_01 + * config/sh/sh-protos.h + (sh_recog_treg_set_expr_not_01): New function + * config/sh/sh.cc (sh_recog_treg_set_expr_not_01): Likewise + +2025-07-04 Andrew Pinski <quic_apinski@quicinc.com> + + PR c/118948 + * fold-const.cc (tree_expr_nonnegative_warnv_p): Use + error_operand_p instead of checking for error_mark_node directly. + +2025-07-04 Pan Li <pan2.li@intel.com> + + * config/riscv/riscv-v.cc (expand_vx_binary_vec_dup_vec): Add + new case SS_PLUS. + (expand_vx_binary_vec_vec_dup): Ditto. + * config/riscv/riscv.cc (riscv_rtx_costs): Ditto. + * config/riscv/vector-iterators.md: Add new op ss_plus. + +2025-07-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/120944 + * tree-ssa-sccvn.cc (vn_reference_lookup_3): Gate optimizations + invalid when volatile is involved. + +2025-07-04 Jan Hubicka <hubicka@ucw.cz> + + * common.opt: Add period. + * common.opt.urls: Regenerate. + +2025-07-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/120927 + * tree-vect-data-refs.cc (vect_compute_data_ref_alignment): + Do not force a DRs base alignment when analyzing an + epilog loop. Check whether the step preserves alignment + for all VFs possibly involved sofar. + +2025-07-04 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.md (crc_combine): Avoid nested + subreg. + +2025-07-04 Shreya Munnangi <smunnangi1@ventanamicro.com> + + * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Add basic + instrumentation to all cases where fusion is detected. Fix + minor formatting goofs found in the process. + +2025-07-04 panciyan <panciyan@eswincomputing.com> + + * match.pd: Add signed scalar SAT_ADD IMM form2 matching. + 2025-07-03 Juergen Christ <jchrist@linux.ibm.com> * config/s390/s390.cc (expand_perm_with_merge): Add size change cases. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index f38cdfd..0f0154f 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20250704 +20250706 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index e8cb92b..d88e73f 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,86 @@ +2025-07-04 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/Make-lang.in (ACATSDIR): Change to acats-4. + +2025-07-04 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/utils.cc (make_packable_type): Clear the TYPE_PACKED + flag in the case where the alignment is bumped. + +2025-07-04 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/trans.cc (Subprogram_Body_to_gnu): Do not generate + a block-copy out for a null initialization procedure when the _Init + parameter is not passed in. + +2025-07-04 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/decl.cc (gnat_to_gnu_subprog_type): Only apply the + transformation to integer types. + +2025-07-04 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/decl.cc (gnat_to_gnu_subprog_type): Add guards. + +2025-07-04 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/decl.cc (gnat_to_gnu_subprog_type): In the case of a + subprogram using the Copy-In/Copy-Out mechanism, deal specially with + the case of 2 parameters of differing sizes. + * gcc-interface/trans.cc (Subprogram_Body_to_gnu): In the case of a + subprogram using the Copy-In/Copy-Out mechanism, make sure the types + are consistent on the two sides for all the parameters. + +2025-07-04 Steve Baird <baird@adacore.com> + + * sem_res.adb (Resolve_Type_Conversion): Replace code for + detecting a similar case with a more comprehensive test. + +2025-07-04 Bob Duff <duff@adacore.com> + + * doc/gnat_rm/implementation_defined_pragmas.rst + (Short_Circuit_And_Or): Add more documentation. + * sem_ch8.adb (Analyze_Subprogram_Renaming): + Disallow renamings. + * gnat_rm.texi: Regenerate. + +2025-07-04 Ronan Desplanques <desplanques@adacore.com> + + * exp_ch7.adb (Make_Final_Call): Tweak search of Finalize primitive. + * exp_util.adb (Finalize_Address): Likewise. + +2025-07-04 Eric Botcazou <ebotcazou@adacore.com> + + * freeze.adb (Check_Compile_Time_Size): Try harder to see whether + the bounds of array types are known at compile time. + +2025-07-04 Piotr Trojanek <trojanek@adacore.com> + + * sem_aux.ads (First_Discriminant): Remove space before period. + +2025-07-04 Steve Baird <baird@adacore.com> + + * sem_ch13.adb (Analyze_Record_Representation_Clause): In deciding + whether to generate a warning about a missing component clause, in + addition to calling Is_Unchecked_Union also call a new local + function, Unchecked_Union_Pragma_Pending, which checks for the + case of a not-yet-analyzed Unchecked_Union pragma occurring later + in the declaration list. + +2025-07-04 Steve Baird <baird@adacore.com> + + * mutably_tagged.adb (Make_CW_Size_Compile_Check): Include the + value of the Size'Class limit in the message generated via a + Compile_Time_Error pragma. + +2025-07-04 Ronan Desplanques <desplanques@adacore.com> + + * sem_ch13.adb (Check_Aspect_At_Freeze_Point): Remove obsolete bits. + +2025-07-04 Ronan Desplanques <desplanques@adacore.com> + + * sem_ch13.adb (Analyze_Aspect_Specifications): Fix error emission. + 2025-07-03 Eric Botcazou <ebotcazou@adacore.com> * gcc-interface/Makefile.in (gnatlib-sjlj): Delete. diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index dd2ae5c..bef9a0e 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,11 @@ +2025-07-04 Jakub Jelinek <jakub@redhat.com> + + PR c/120837 + * c-common.cc (pointer_int_sum): Rewrite the intop PLUS_EXPR or + MINUS_EXPR optimization into extension of both intop operands, + their separate multiplication and then addition/subtraction followed + by rest of pointer_int_sum handling after the multiplication. + 2025-07-01 Qing Zhao <qing.zhao@oracle.com> * c-gimplify.cc (is_address_with_access_with_size): New function. diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 061904b..8baad2f 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -33,11 +33,11 @@ (define_predicate "prefetch_operand" (ior (match_operand 0 "register_operand") (and (match_test "const_arith_operand (op, VOIDmode)") - (match_test "(INTVAL (op) & 0xf) == 0")) + (match_test "(INTVAL (op) & 0x1f) == 0")) (and (match_code "plus") (match_test "register_operand (XEXP (op, 0), word_mode)") (match_test "const_arith_operand (XEXP (op, 1), VOIDmode)") - (match_test "(INTVAL (XEXP (op, 1)) & 0xf) == 0")))) + (match_test "(INTVAL (XEXP (op, 1)) & 0x1f) == 0")))) (define_predicate "lui_operand" (and (match_code "const_int") diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 893c925..f5ec0c5 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -4402,7 +4402,7 @@ ) (define_insn "prefetch" - [(prefetch (match_operand 0 "prefetch_operand" "Q") + [(prefetch (match_operand 0 "prefetch_operand" "Qr") (match_operand 1 "imm5_operand" "i") (match_operand 2 "const_int_operand" "n"))] "TARGET_ZICBOP" diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h index fa2c837b..e77247b 100644 --- a/gcc/config/rs6000/vxworks.h +++ b/gcc/config/rs6000/vxworks.h @@ -34,6 +34,21 @@ along with GCC; see the file COPYING3. If not see /* Common definitions first. */ /*-------------------------------------------------------------*/ +/* Default to 64 bits when the target is powerpc64*-wrs-vxworks*, + and to 32 bits otherwise. */ +#undef SUBTARGET_DRIVER_SELF_SPECS +#if TARGET_VXWORKS64 +#define SUBTARGET_DRIVER_SELF_SPECS "%{!m64:%{!m32:-m64}}" +#else +#define SUBTARGET_DRIVER_SELF_SPECS "%{!m32:%{!m64:-m32}}" +#endif + +/* Having used the build-time TARGET_VXWORKS64 to choose the default ABI above, + redefine it so that it matches whichever ABI is selected for each + compilation. */ +#undef TARGET_VXWORKS64 +#define TARGET_VXWORKS64 TARGET_64BIT + /* CPP predefined macros. */ #undef TARGET_OS_CPP_BUILTINS diff --git a/gcc/config/sh/predicates.md b/gcc/config/sh/predicates.md index 7349c97..e67ec8a 100644 --- a/gcc/config/sh/predicates.md +++ b/gcc/config/sh/predicates.md @@ -630,9 +630,7 @@ ;; Same as treg_set_expr but disallow constants 0 and 1 which can be loaded ;; into the T bit. (define_predicate "treg_set_expr_not_const01" - (and (match_test "op != const0_rtx") - (match_test "op != const1_rtx") - (match_operand 0 "treg_set_expr"))) + (match_test "sh_recog_treg_set_expr_not_01 (op, mode)")) ;; A predicate describing the T bit register in any form. (define_predicate "t_reg_operand" diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h index c8cc19f..e78b669 100644 --- a/gcc/config/sh/sh-protos.h +++ b/gcc/config/sh/sh-protos.h @@ -261,6 +261,7 @@ extern rtx_insn* sh_peephole_emit_move_insn (rtx dst, rtx src); extern bool sh_in_recog_treg_set_expr (void); extern bool sh_recog_treg_set_expr (rtx op, machine_mode mode); +extern bool sh_recog_treg_set_expr_not_01 (rtx op, machine_mode mode); /* Result value of sh_split_treg_set_expr. Contains the first insn emitted and the optional trailing nott insn. */ diff --git a/gcc/config/sh/sh.cc b/gcc/config/sh/sh.cc index 1bc34e0..09e4ff7 100644 --- a/gcc/config/sh/sh.cc +++ b/gcc/config/sh/sh.cc @@ -12348,6 +12348,23 @@ sh_recog_treg_set_expr (rtx op, machine_mode mode) return result >= 0; } +/* Return TRUE if OP is an expression for which there is a pattern to + set the T bit unless the expression is trivially loadable into + the T bit, FALSE otherwise. */ +bool +sh_recog_treg_set_expr_not_01 (rtx op, machine_mode mode) +{ + if (op == const0_rtx || op == const1_rtx) + return false; + + /* A right shift of 31 will return 0 or 1. */ + if ((GET_CODE (op) == LSHIFTRT || GET_CODE (op) == ASHIFTRT) + && INTVAL (XEXP (op, 1)) == 31) + return false; + + return sh_recog_treg_set_expr (op, mode); +} + /* Returns true when recog of a 'treg_set_expr' is currently in progress. This can be used as a condition for insn/split patterns to allow certain T bit setting patters only to be matched as sub expressions of other diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index b1b173c..23511a0 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,10 @@ +2025-07-04 Jason Merrill <jason@redhat.com> + + PR c++/120575 + PR c++/116064 + * parser.cc (cp_parser_abort_tentative_parse): Check seen_error + instead of errorcount. + 2025-07-03 Jason Merrill <jason@redhat.com> PR c++/120716 diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index d0537d4..ea366b1 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,8 @@ +2025-07-04 Martin Jambor <mjambor@suse.cz> + + * io.cc (format_asterisk): Add a brace around static initialization + location part of the field locus. + 2025-07-03 Andre Vehreschild <vehre@gcc.gnu.org> PR fortran/120843 diff --git a/gcc/fortran/io.cc b/gcc/fortran/io.cc index 7466d8f..4d28c2c 100644 --- a/gcc/fortran/io.cc +++ b/gcc/fortran/io.cc @@ -29,7 +29,7 @@ along with GCC; see the file COPYING3. If not see gfc_st_label format_asterisk = {0, NULL, NULL, -1, ST_LABEL_FORMAT, ST_LABEL_FORMAT, NULL, - 0, {NULL, NULL}, NULL, 0}; + 0, {NULL, {NULL}}, NULL, 0}; typedef struct { diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c70aee2..e234630 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,102 @@ +2025-07-04 Vineet Gupta <vineetg@rivosinc.com> + + PR target/118241 + * gcc.target/riscv/pr118241-b.cc: New test. + +2025-07-04 Raphael Moreira Zinsly <rzinsly@ventanamicro.com> + + * gcc.target/sh/pr54236-2.c: Fix comments and expected output + +2025-07-04 Andrew Pinski <quic_apinski@quicinc.com> + + PR c/118948 + * gcc.dg/pr118948-1.c: New test. + +2025-07-04 Jason Merrill <jason@redhat.com> + + PR c++/120575 + PR c++/116064 + * g++.dg/template/permissive-error3.C: New test. + +2025-07-04 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Add asm check. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto. + +2025-07-04 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test + helper macros. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test + data for run test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i16.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i32.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i64.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i8.c: New test. + +2025-07-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/120944 + * gcc.dg/torture/pr120944.c: New testcase. + +2025-07-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/120927 + * gcc.dg/vect/vect-pr120927.c: New testcase. + * gcc.dg/vect/vect-pr120927-2.c: Likewise. + +2025-07-04 Jakub Jelinek <jakub@redhat.com> + + PR c/120837 + * gcc.dg/ubsan/pr120837.c: New test. + +2025-07-04 Xi Ruoyao <xry111@xry111.site> + + PR target/120807 + * gcc.c-torture/compile/pr120708.c: Rename to ... + * gcc.c-torture/compile/pr120807.c: ... here. + +2025-07-04 Xi Ruoyao <xry111@xry111.site> + + * gcc.c-torture/compile/pr120708.c: New test. + +2025-07-04 panciyan <panciyan@eswincomputing.com> + + * gcc.target/riscv/sat/sat_arith.h: Add signed scalar SAT_ADD IMM form2. + * gcc.target/riscv/sat/sat_s_add_imm-2-i16.c: New test. + * gcc.target/riscv/sat/sat_s_add_imm-2-i32.c: New test. + * gcc.target/riscv/sat/sat_s_add_imm-2-i64.c: New test. + * gcc.target/riscv/sat/sat_s_add_imm-2-i8.c: New test. + * gcc.target/riscv/sat/sat_s_add_imm-run-2-i16.c: New test. + * gcc.target/riscv/sat/sat_s_add_imm-run-2-i32.c: New test. + * gcc.target/riscv/sat/sat_s_add_imm-run-2-i64.c: New test. + * gcc.target/riscv/sat/sat_s_add_imm-run-2-i8.c: New test. + * gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i16.c: New test. + * gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i32.c: New test. + * gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i8.c: New test. + 2025-07-03 Jason Merrill <jason@redhat.com> PR c++/120716 diff --git a/gcc/testsuite/gcc.target/riscv/pr118241-b.cc b/gcc/testsuite/gcc.target/riscv/pr118241-b.cc new file mode 100644 index 0000000..b2cc73f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr118241-b.cc @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64imafdc_zba_zbb_zbs_zicbom_zicbop -mabi=lp64d" } */ + +/* Reduced from libsanitizer::asan_allocator. */ + +enum a { c }; +class d; +struct e { + long count; + void *batch[]; +}; +template <typename> class f { +public: + void g() { + if (e *b = h->i()) + for (; b->count;) + if (6 < b->count) + __builtin_prefetch(b->batch[6]); + } + d *h; +}; +class d { +public: + e *i(); +}; +struct j { + f<int> k; + j(a); + void l() { k.g(); } +} a(c); +void m() { a.l(); } + +/* { dg-final { scan-assembler-times "prefetch.r\t0\\(\[a-x0-9\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/sh/pr54236-2.c b/gcc/testsuite/gcc.target/sh/pr54236-2.c index 1e2f3bb..78befe4 100644 --- a/gcc/testsuite/gcc.target/sh/pr54236-2.c +++ b/gcc/testsuite/gcc.target/sh/pr54236-2.c @@ -4,10 +4,10 @@ /* { dg-do compile } */ /* { dg-options "-O1" } */ -/* { dg-final { scan-assembler-times "addc" 36 } } */ +/* { dg-final { scan-assembler-times "addc" 32 } } */ /* { dg-final { scan-assembler-times "shll" 14 } } */ -/* { dg-final { scan-assembler-times "add\tr" 12 } } */ -/* { dg-final { scan-assembler-not "movt" } } */ +/* { dg-final { scan-assembler-times "add\tr" 16 } } */ +/* { dg-final { scan-assembler-times "movt" 4 } } */ /* { dg-final { scan-assembler-times "add\t#1" 1 } } */ @@ -184,28 +184,28 @@ test_022 (int a, int b, int c, int d) int test_023 (int a, int b, int c, int d) { - // 1x shll, 1x addc + // 1x shll, 1x add return a + ((b >> 31) & 1); } int test_024 (int a, int b, int c, int d) { - // 1x shll, 1x addc + // 1x shll, 1x add return ((b >> 31) & 1) + a; } int test_025 (int a, int b, int c, int d) { - // 1x shll, 1x addc + // 1x shll, 1x add return ((a >> 31) & 1) + a; } int test_026 (int a, int b, int c, int d) { - // 1x shll, 1x addc + // 1x shll, 1x add return a + ((a >> 31) & 1); } |