diff options
Diffstat (limited to 'gcc')
67 files changed, 2395 insertions, 141 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 00f62e1..9a0d334 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,109 @@ +2025-11-02 Jeff Law <jlaw@ventanamicro.com> + + * config/riscv/bitmanip.md (rotrsi3): Use the sign extended form + for 32 bit rotates on TARGET_64BIT, even for constant counts. + * config/riscv/thead.md (th_srrisi3_extended): New pattern. + (th_srri<mode>3): Adjust formatting. + +2025-11-02 Uros Bizjak <ubizjak@gmail.com> + + PR target/122518 + * config/i386/i386.cc (ix86_canonicalize_comparison): Convert + (compare (minus (a b)) a) to (compare (a b)) to + match *sub<mode>_3 pattern. + +2025-11-02 Georg-Johann Lay <avr@gjlay.de> + + PR target/122527 + * config/avr/avr.cc (avr_load_libgcc_p): Return false if + the address-space is not ADDR_SPACE_FLASH. + (avr_out_lpm_no_lpmx [addr=REG]): Handle sizes of 3 and 4 bytes. + +2025-11-02 Georg-Johann Lay <avr@gjlay.de> + + PR tree-optimization/118012 + PR tree-optimization/122505 + * config/avr/avr.md (mulpsi3): Also allow the insn condition + in the case where avropt_pr118012 && !AVR_TINY. + (*mulpsi3): Handle split for the !AVR_HAVE_MUL case. + (*mulpsi3-nomul.libgcc_split, *mulpsi3-nomul.libgcc): New insns. + +2025-11-02 Richard Biener <rguenther@suse.de> + + * doc/tree-ssa.texi: Remove outdated info on FOR_EACH_IMM_USE_STMT + iteration, clarify SSA operand parts. + * ssa-iterators.h: Update toplevel comment. + +2025-11-02 Sam James <sam@gentoo.org> + + * .simplify-rtx.cc.swo: Removed. + +2025-11-01 Shreya Munnangi <smunnangi1@ventanamicro.com> + + PR target/67731 + * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): + Handle IOR of single bit bitfields from the same object. + +2025-11-01 Jeff Law <jlaw@ventanamicro.com> + + * config/riscv/riscv-protos.h (has_vtype_op): Add prototype. + (mask_agnostic_p, get_avl, vsetvl_insn_p): Likewise. + * config/riscv/riscv-vsetvl.cc (has_vtype_op): No longer static. + (vsetvl_insn_p, get_avl_mask_agnostic_p): Likewise. + * config/riscv/riscv.cc (struct last_vcofnig): New structure. + (clear_vconfig): New function. + (compatible_with_last_vconfig, riscv_sched_init): Likewise. + (riscv_sched_reorder): Likewise. + (TARGET_SCHED_INIT, TARGET_SCHED_REORDER): Define. + * config/riscv/vector.md ("*mov<mode>"): Set has_vtype_op, has_vl_op + attributes. + * .simplify-rtx.cc.swo: New file. + +2025-11-01 Jeff Law <jlaw@ventanamicro.com> + + PR rtl-optimization/122321 + * lra-constraints.cc (update_equiv): Make sure REGNO is in + ira_reg_equiv before trying to update ira_reg_equiv. + +2025-11-01 Martin Uecker <uecker@tugraz.at> + + * doc/extend.texi: Document new extension. + +2025-11-01 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (negsf2): + Add another insn pattern that is valid when TARGET_DENSITY is + enabled and both the source and destination are address registers. + +2025-11-01 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md + (c_enum "unspec", int_iterator ANY_ROUND): Add UNSPEC_ROUND. + (int_attr m_round): Add a pair of UNSPEC_ROUND and "round". + (int_attr c_round): New integer iterator attribute, that expands + to "flag_unsafe_math_optimizations" in the case of UNSPEC_ROUND, + and to "1" otherwise. + (l<m_round>sfsi2, *l<m_round>sfsi2_2x, *l<m_round>sfsi2_scaled): + Append " && <c_round>" to the conditions. + +2025-11-01 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (*fix<s_fix>_truncsfsi2_scaled, + *float<s_float>sisf2_scaled, *l<m_round>sfsi2_scaled): + Remove 'F'-constraint. + +2025-11-01 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR ipa/122512 + * cgraph.h (enum toplevel_type): Add TOPLEVEL_MAX. Add comment + about keeping toplevel_type_names in sync. + * symtab.cc (symtab_type_names): Rename to ... + (toplevel_type_names): Add new types and add an assert about + the size. + (symtab_node::get_symtab_type_string): Use toplevel_type_names + instead of symtab_type_names. + (symtab_node::dump_base): Likewise. + 2025-10-31 Andrew Pinski <andrew.pinski@oss.qualcomm.com> PR tree-optimization/122437 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 38eec11..2bb6e40 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20251101 +20251103 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index f91fc31..86629f3 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,25 @@ +2025-11-02 Eric Botcazou <ebotcazou@adacore.com> + + * locales.c (is_iso_639_3): New static function. + (c_get_language_code): Use it to validate the ISO-639-3 code + before returning it. + +2025-11-02 Eric Botcazou <ebotcazou@adacore.com> + + PR ada/58881 + * sem_ch3.adb (Build_Derived_Private_Type): Build the underlying + full view when the derivation occurs in the public part of the + scope of the parent. + (Build_Derived_Record_Type): Propagate Has_Unknown_Discriminants + in the same circumstances. + (Constrain_Discriminated_Type): Give a specific error message for + any type with the Has_Unknown_Discriminants flag. + +2025-11-02 Eric Botcazou <ebotcazou@adacore.com> + + PR ada/52319 + * sem_ch8.adb (End_Use_Package): Use the scope of the operator. + 2025-10-30 Eric Botcazou <ebotcazou@adacore.com> PR ada/15610 diff --git a/gcc/ada/locales.c b/gcc/ada/locales.c index a3f884c..89c5b7b 100644 --- a/gcc/ada/locales.c +++ b/gcc/ada/locales.c @@ -646,7 +646,7 @@ str_get_last_byte (char *lc_all) { return last_byte; } -/* Utility function to search in the iso_639_1 table for an iso-639-1 code; +/* Utility function to search in the iso_639 table for an iso-639-1 code; returns the corresponding iso-639-3 code or NULL if not found. */ static char* @@ -670,7 +670,30 @@ iso_639_1_to_639_3(char* iso_639_1_code) { return NULL; } -/* Utility function to search in the iso_639_1 table for a language name; +/* Utility function to search in the iso_639 table for an iso-639-3 code; + returns 1 if found or 0 if not found. */ + +static int +is_iso_639_3(char* iso_639_3_code) { + int len = ARRAY_SIZE (iso_639); + char **p = iso_639; + int j; + + p = p + 1; + for (j=0; j < len/3; j++) { + char* s1 = iso_639_3_code; + char* s2 = *p; + + if (s1[0]==s2[0] && s1[1]==s2[1] && s1[2]==s2[2]) + return 1; + + p = p + 3; + } + + return 0; +} + +/* Utility function to search in the iso_639 table for a language name; returns the corresponding iso-639-3 code or NULL if not found. */ static char* @@ -772,7 +795,8 @@ c_get_language_code (char4 p) { /* Copy the ISO-639-3 code (adding a null terminator) */ } else if (lang_length == 3) { - str_copy(iso_639_3_code, lc_all, lang_length); + if (is_iso_639_3(lc_all)) + str_copy(iso_639_3_code, lc_all, lang_length); /* Handle conversion of language name to ISO-639-3 */ diff --git a/gcc/ada/sem_ch3.adb b/gcc/ada/sem_ch3.adb index aa15166..79986bb 100644 --- a/gcc/ada/sem_ch3.adb +++ b/gcc/ada/sem_ch3.adb @@ -8500,26 +8500,28 @@ package body Sem_Ch3 is Full_P := Full_View (Parent_Type); -- A type extension of a type with unknown discriminants is an - -- indefinite type that the back-end cannot handle directly. + -- indefinite type that the back end cannot handle directly. -- We treat it as a private type, and build a completion that is -- derived from the full view of the parent, and hopefully has - -- known discriminants. + -- known discriminants. Note that the type will nevertheless be + -- turned into a public type in Build_Derived_Record_Type as for + -- any other extension; the only difference is the completion. -- If the full view of the parent type has an underlying record view, - -- use it to generate the underlying record view of this derived type + -- use it to generate the underlying record view of the derived type -- (required for chains of derivations with unknown discriminants). - -- Minor optimization: we avoid the generation of useless underlying - -- record view entities if the private type declaration has unknown - -- discriminants but its corresponding full view has no - -- discriminants. + -- Minor optimization: we avoid creating useless underlying record + -- view entities when the private type has unknown discriminants but + -- its corresponding full view has no discriminants. if Has_Unknown_Discriminants (Parent_Type) and then Present (Full_P) and then (Has_Discriminants (Full_P) or else Present (Underlying_Record_View (Full_P))) - and then not In_Open_Scopes (Par_Scope) - and then Expander_Active + and then (not In_Open_Scopes (Par_Scope) + or else not (In_Package_Body (Par_Scope) + or else In_Private_Part (Par_Scope))) then declare Full_Der : constant Entity_Id := Make_Temporary (Loc, 'T'); @@ -8534,7 +8536,7 @@ package body Sem_Ch3 is -- Build anonymous completion, as a derivation from the full -- view of the parent. This is not a completion in the usual - -- sense, because the current type is not private. + -- sense, because the derived type is no longer private. Decl := Make_Full_Type_Declaration (Loc, @@ -8557,8 +8559,18 @@ package body Sem_Ch3 is Underlying_Record_View (Full_P)); end if; + -- If the extension is done in the public part of the scope of + -- the parent, its visible declarations have been installed, so + -- we first need to uninstall them before reinstalling both the + -- private and the visible declarations in this order. + + if In_Open_Scopes (Par_Scope) then + Uninstall_Declarations (Par_Scope); + end if; + Install_Private_Declarations (Par_Scope); Install_Visible_Declarations (Par_Scope); + Insert_Before (N, Decl); -- Mark entity as an underlying record view before analysis, @@ -8582,6 +8594,13 @@ package body Sem_Ch3 is Uninstall_Declarations (Par_Scope); + -- If the extension is done in the public part of the scope of + -- the parent, reinstall the visible declarations only. + + if In_Open_Scopes (Par_Scope) then + Install_Visible_Declarations (Par_Scope); + end if; + if Etype (Full_Der) = Any_Type then pragma Assert (Serious_Errors_Detected > 0); return; @@ -10007,13 +10026,15 @@ package body Sem_Ch3 is or else Unknown_Discriminants_Present (N)); -- The partial view of the parent may have unknown discriminants, - -- but if the full view has discriminants and the parent type is - -- in scope they must be inherited. + -- but when its full view has discriminants and is visible, then + -- these discriminants must be inherited. elsif Has_Unknown_Discriminants (Parent_Type) and then (not Has_Discriminants (Parent_Type) - or else not In_Open_Scopes (Scope (Parent_Base))) + or else not In_Open_Scopes (Scope (Parent_Base)) + or else not (In_Package_Body (Scope (Parent_Base)) + or else In_Private_Part (Scope (Parent_Base)))) then Set_Has_Unknown_Discriminants (Derived_Type); end if; @@ -15144,19 +15165,20 @@ package body Sem_Ch3 is Fixup_Bad_Constraint; return; - -- Check that the type has visible discriminants. The type may be - -- a private type with unknown discriminants whose full view has - -- discriminants which are invisible. + -- Check that the type has known discriminants - elsif not Has_Discriminants (T) - or else - (Has_Unknown_Discriminants (T) - and then Is_Private_Type (T)) - then + elsif Has_Unknown_Discriminants (T) then + Error_Msg_N ("invalid constraint: type has unknown discriminants", C); + Fixup_Bad_Constraint; + return; + + elsif not Has_Discriminants (T) then Error_Msg_N ("invalid constraint: type has no discriminant", C); Fixup_Bad_Constraint; return; + -- And is not already constrained + elsif Is_Constrained (E) or else (Ekind (E) = E_Class_Wide_Subtype and then Present (Discriminant_Constraint (E))) diff --git a/gcc/ada/sem_ch8.adb b/gcc/ada/sem_ch8.adb index e9d00d0..a83ac64 100644 --- a/gcc/ada/sem_ch8.adb +++ b/gcc/ada/sem_ch8.adb @@ -5330,11 +5330,6 @@ package body Sem_Ch8 is --------------------- procedure End_Use_Package (N : Node_Id) is - Pack : Entity_Id; - Pack_Name : Node_Id; - Id : Entity_Id; - Elmt : Elmt_Id; - function Type_In_Use (T : Entity_Id; P : Entity_Id) return Boolean; -- Check whether type T is declared in P and appears in an active -- use_type clause. @@ -5349,6 +5344,14 @@ package body Sem_Ch8 is return Scope (BT) = P and then (In_Use (T) or else In_Use (BT)); end Type_In_Use; + -- Local variables + + Elmt : Elmt_Id; + Id : Entity_Id; + Pack : Entity_Id; + Pack_Name : Node_Id; + Scop : Entity_Id; + -- Start of processing for End_Use_Package begin @@ -5373,17 +5376,20 @@ package body Sem_Ch8 is -- Preserve use-visibility of operators that are primitive -- operators of a type that is use-visible through an active - -- use_type_clause. + -- use_type_clause. Note that we compare with the scope of + -- the operator and not Pack itself, lest Pack be a renaming. + + Scop := Scope (Id); if Nkind (Id) = N_Defining_Operator_Symbol and then - (Type_In_Use (Etype (Id), Pack) - or else Type_In_Use (Etype (First_Formal (Id)), Pack) + (Type_In_Use (Etype (Id), Scop) + or else Type_In_Use (Etype (First_Formal (Id)), Scop) or else (Present (Next_Formal (First_Formal (Id))) and then Type_In_Use - (Etype (Next_Formal (First_Formal (Id))), Pack))) + (Etype (Next_Formal (First_Formal (Id))), Scop))) then null; else diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index 274e2a7..23cc53a 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,21 @@ +2025-11-01 Martin Uecker <uecker@tugraz.at> + + * c-decl.cc (build_compound_literal): Add error. + * c-parser.cc (c_parser_braced_init): Take bool argument for + variable size instead of DECL. + (c_parser_initializer,c_parser_initval): Adapt. + (c_parser_postfix_expression_after_paren_type): Change + error to pedwarn. + * c-typeck.cc (process_init_element): Add error for + variable-size compound literal with static or constexpr. + +2025-11-01 Martin Uecker <uecker@tugraz.at> + + PR c/97986 + * c-parser.cc (c_parser_postfix_expression): Adapt. + * c-tree.h (c_build_va_arg): Adapt prototype. + * c-typeck.cc (c_build_va_arg): Handle UB. + 2025-10-30 Qing Zhao <qing.zhao@oracle.com> * c-typeck.cc (build_access_with_size_for_counted_by): When the element diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index 227c12a..0bdba55 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -3272,7 +3272,8 @@ avr_load_libgcc_p (rtx op) return (n_bytes > 2 && !AVR_HAVE_LPMX - && avr_mem_flash_p (op)); + && avr_mem_flash_p (op) + && MEM_ADDR_SPACE (op) == ADDR_SPACE_FLASH); } @@ -3624,6 +3625,46 @@ avr_out_lpm_no_lpmx (rtx_insn *insn, rtx *xop, int *plen) avr_asm_len ("sbiw %2,1", xop, plen, 1); break; /* 2 */ + + /* cases 3 and 4 are only needed with ELPM but no ELPMx. */ + + case 3: + if (REGNO (dest) == REG_Z - 2 + && !reg_unused_after (insn, all_regs_rtx[REG_31])) + avr_asm_len ("push r31", xop, plen, 1); + + avr_asm_len ("%4lpm $ mov %A0,%3 $ adiw %2,1", xop, plen, 3); + avr_asm_len ("%4lpm $ mov %B0,%3 $ adiw %2,1", xop, plen, 3); + avr_asm_len ("%4lpm $ mov %C0,%3", xop, plen, 2); + + if (REGNO (dest) == REG_Z - 2) + { + if (!reg_unused_after (insn, all_regs_rtx[REG_31])) + avr_asm_len ("pop r31", xop, plen, 1); + } + else if (!reg_unused_after (insn, addr)) + avr_asm_len ("sbiw %2,2", xop, plen, 1); + + break; /* 3 */ + + case 4: + avr_asm_len ("%4lpm $ mov %A0,%3 $ adiw %2,1", xop, plen, 3); + avr_asm_len ("%4lpm $ mov %B0,%3 $ adiw %2,1", xop, plen, 3); + if (REGNO (dest) != REG_Z - 2) + { + avr_asm_len ("%4lpm $ mov %C0,%3 $ adiw %2,1", xop, plen, 3); + avr_asm_len ("%4lpm $ mov %D0,%3", xop, plen, 2); + if (!reg_unused_after (insn, addr)) + avr_asm_len ("sbiw %2,3", xop, plen, 1); + } + else + { + avr_asm_len ("%4lpm $ push %3 $ adiw %2,1", xop, plen, 3); + avr_asm_len ("%4lpm $ mov %D0,%3", xop, plen, 2); + avr_asm_len ("pop $C0", xop, plen, 1); + } + + break; /* 4 */ } break; /* REG */ diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 30a02a4..d73cf96 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -3947,9 +3947,17 @@ (match_operand:PSI 2 "nonmemory_operand" ""))) (clobber (reg:HI 26)) (clobber (reg:DI 18))])] - "AVR_HAVE_MUL" + "AVR_HAVE_MUL + || (avropt_pr118012 + /* AVR_TINY passes args on the stack, so we cannot work + around PR118012 like this. */ + && ! AVR_TINY)" { - if (s8_operand (operands[2], PSImode)) + if (!AVR_HAVE_MUL) + { + operands[2] = force_reg (PSImode, operands[2]); + } + else if (s8_operand (operands[2], PSImode)) { rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode)); emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1])); @@ -4038,7 +4046,9 @@ (match_operand:PSI 2 "pseudo_register_or_const_int_operand" "rn"))) (clobber (reg:HI 26)) (clobber (reg:DI 18))] - "AVR_HAVE_MUL && !reload_completed" + "!reload_completed + && (AVR_HAVE_MUL + || (avropt_pr118012 && !AVR_TINY))" { gcc_unreachable(); } "&& 1" [(set (reg:PSI 18) @@ -4048,13 +4058,30 @@ (parallel [(set (reg:PSI 22) (mult:PSI (reg:PSI 22) (reg:PSI 18))) - (clobber (reg:QI 21)) - (clobber (reg:QI 25)) - (clobber (reg:HI 26))]) + (clobber (match_dup 3)) + (clobber (match_dup 4)) + (clobber (match_dup 5))]) (set (match_dup 0) (reg:PSI 22))] { - if (s8_operand (operands[2], PSImode)) + if (AVR_HAVE_MUL) + { + operands[3] = gen_rtx_REG (QImode, REG_21); + operands[4] = gen_rtx_REG (QImode, REG_25); + operands[5] = gen_rtx_REG (HImode, REG_26); + } + else + { + operands[3] = gen_rtx_REG (SImode, REG_18); + operands[4] = gen_rtx_SCRATCH (QImode); + operands[5] = gen_rtx_SCRATCH (HImode); + } + + if (!AVR_HAVE_MUL) + { + operands[2] = force_reg (PSImode, operands[2]); + } + else if (s8_operand (operands[2], PSImode)) { rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode)); emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1])); @@ -4106,6 +4133,32 @@ "%~call __mulpsi3" [(set_attr "type" "xcall")]) +(define_insn_and_split "*mulpsi3-nomul.libgcc_split" + [(set (reg:PSI 22) + (mult:PSI (reg:PSI 22) + (reg:PSI 18))) + (clobber (reg:SI 18)) + (clobber (scratch:QI)) + (clobber (scratch:HI))] + "!AVR_HAVE_MUL && avropt_pr118012 && !AVR_TINY" + "#" + "&& reload_completed" + [(scratch)] + { DONE_ADD_CCC }) + +(define_insn "*mulpsi3-nomul.libgcc" + [(set (reg:PSI 22) + (mult:PSI (reg:PSI 22) + (reg:PSI 18))) + (clobber (reg:SI 18)) + (clobber (scratch:QI)) + (clobber (scratch:HI)) + (clobber (reg:CC REG_CC))] + "reload_completed + && !AVR_HAVE_MUL && avropt_pr118012 && !AVR_TINY" + "%~call __mulpsi3" + [(set_attr "type" "xcall")]) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; 24-bit signed/unsigned division and modulo. diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 587b2bd..6b6febc 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -598,6 +598,20 @@ ix86_canonicalize_comparison (int *code, rtx *op0, rtx *op1, } } + /* SUB (a, b) underflows precisely when a < b. Convert + (compare (minus (a b)) a) to (compare (a b)) + to match *sub<mode>_3 pattern. */ + if (!op0_preserve_value + && (*code == GTU || *code == LEU) + && GET_CODE (*op0) == MINUS + && rtx_equal_p (XEXP (*op0, 0), *op1)) + { + *op1 = XEXP (*op0, 1); + *op0 = XEXP (*op0, 0); + *code = (int) swap_condition ((enum rtx_code) *code); + return; + } + /* Swap operands of GTU comparison to canonicalize addcarry/subborrow comparison. */ if (!op0_preserve_value diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 7a91473..7704f8c 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -130,6 +130,7 @@ ;; Only used for splitting insert_d and copy_{u,s}.d. (define_mode_iterator LASX_WD [V4DI V4DF V8SI V8SF]) +(define_mode_iterator LASX_PART [V4DI V4DF V8SF]) ;; Only used for copy256_{u,s}.w. (define_mode_iterator LASX_W [V8SI V8SF]) @@ -672,6 +673,41 @@ [(set_attr "move_type" "fmove") (set_attr "mode" "<MODE>")]) +;; vr0 -> low xr0 +;; +(define_insn "vec_cast<mode>" + [(set (match_operand:LASX_PART 0 "register_operand" "=f") + (subreg:LASX_PART + (match_operand:<VHMODE256_ALL> 1 "register_operand" "0") 0))] + "ISA_HAS_LASX" + "" + [(set_attr "type" "simd_splat") + (set_attr "mode" "<MODE>")]) + +(define_insn "vec_insert_lo_<mode>" + [(set (match_operand:LASX_PART 0 "register_operand" "=f") + (vec_concat:LASX_PART + (match_operand:<VHMODE256_ALL> 2 "register_operand" "f") + (vec_select:<VHMODE256_ALL> + (match_operand:LASX_PART 1 "register_operand" "0") + (match_operand:LASX_PART 3 "vect_par_cnst_high_half"))))] + "ISA_HAS_LASX" + "xvpermi.q\t%u0,%u2,0x30" + [(set_attr "type" "simd_splat") + (set_attr "mode" "<MODE>")]) + +(define_insn "vec_insert_hi_<mode>" + [(set (match_operand:LASX_PART 0 "register_operand" "=f") + (vec_concat:LASX_PART + (vec_select:<VHMODE256_ALL> + (match_operand:LASX_PART 1 "register_operand" "0") + (match_operand:LASX_PART 3 "vect_par_cnst_low_half")) + (match_operand:<VHMODE256_ALL> 2 "register_operand" "f")))] + "ISA_HAS_LASX" + "xvpermi.q\t%u0,%u2,0x02" + [(set_attr "type" "simd_splat") + (set_attr "mode" "<MODE>")]) + (define_expand "vec_perm<mode>" [(match_operand:LASX 0 "register_operand") (match_operand:LASX 1 "register_operand") diff --git a/gcc/config/loongarch/lasxintrin.h b/gcc/config/loongarch/lasxintrin.h index 6bcffc2..6c34ede 100644 --- a/gcc/config/loongarch/lasxintrin.h +++ b/gcc/config/loongarch/lasxintrin.h @@ -23,6 +23,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see <http://www.gnu.org/licenses/>. */ +#include <lsxintrin.h> + #ifndef _GCC_LOONGSON_ASXINTRIN_H #define _GCC_LOONGSON_ASXINTRIN_H 1 @@ -5368,5 +5370,159 @@ __m256i __lasx_xvfcmp_sun_s (__m256 _1, __m256 _2) #define __lasx_xvrepli_w(/*si10*/ _1) \ ((__m256i)__builtin_lasx_xvrepli_w ((_1))) +#if defined (__loongarch_asx_sx_conv) +/* Add builtin interfaces for 128 and 256 vector conversions. + For the assembly instruction format of some functions of the following vector + conversion, it is not described exactly in accordance with the format of the + generated assembly instruction. + In the front end of the Rust language, different built-in functions are called + by analyzing the format of assembly instructions. The data types of instructions + are all defined based on the interfaces of the defined functions, in the + following order: output, input... . */ +/* Assembly instruction format: xd, vj. */ +/* Data types in instruction templates: V8SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_cast_128_s (__m128 _1) +{ + return (__m256)__builtin_lasx_cast_128_s ((v4f32)_1); +} + +/* Assembly instruction format: xd, vj. */ +/* Data types in instruction templates: V4DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_cast_128_d (__m128d _1) +{ + return (__m256d)__builtin_lasx_cast_128_d ((v2f64)_1); +} + +/* Assembly instruction format: xd, vj. */ +/* Data types in instruction templates: V4DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_cast_128 (__m128i _1) +{ + return (__m256i)__builtin_lasx_cast_128 ((v2i64)_1); +} + +/* Assembly instruction format: xd, vj, vk. */ +/* Data types in instruction templates: V8SF, V4SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_concat_128_s (__m128 _1, __m128 _2) +{ + return (__m256)__builtin_lasx_concat_128_s ((v4f32)_1, (v4f32)_2); +} + +/* Assembly instruction format: xd, vj, vk. */ +/* Data types in instruction templates: V4DF, V2DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_concat_128_d (__m128d _1, __m128d _2) +{ + return (__m256d)__builtin_lasx_concat_128_d ((v2f64)_1, (v2f64)_2); +} + +/* Assembly instruction format: xd, vj, vk. */ +/* Data types in instruction templates: V4DI, V2DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_concat_128 (__m128i _1, __m128i _2) +{ + return (__m256i)__builtin_lasx_concat_128 ((v2i64)_1, (v2i64)_2); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V4SF, V8SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128 __lasx_extract_128_lo_s (__m256 _1) +{ + return (__m128)__builtin_lasx_extract_128_lo_s ((v8f32)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V4SF, V8SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128 __lasx_extract_128_hi_s (__m256 _1) +{ + return (__m128)__builtin_lasx_extract_128_hi_s ((v8f32)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DF, V4DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128d __lasx_extract_128_lo_d (__m256d _1) +{ + return (__m128d)__builtin_lasx_extract_128_lo_d ((v4f64)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DF, V4DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128d __lasx_extract_128_hi_d (__m256d _1) +{ + return (__m128d)__builtin_lasx_extract_128_hi_d ((v4f64)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DI, V4DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128i __lasx_extract_128_lo (__m256i _1) +{ + return (__m128i)__builtin_lasx_extract_128_lo ((v4i64)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DI, V4DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128i __lasx_extract_128_hi (__m256i _1) +{ + return (__m128i)__builtin_lasx_extract_128_hi ((v4i64)_1); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V8SF, V8SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_insert_128_lo_s (__m256 _1, __m128 _2) +{ + return (__m256)__builtin_lasx_insert_128_lo_s ((v8f32)_1, (v4f32)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V8SF, V8SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_insert_128_hi_s (__m256 _1, __m128 _2) +{ + return (__m256)__builtin_lasx_insert_128_hi_s ((v8f32)_1, (v4f32)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DF, V4DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_insert_128_lo_d (__m256d _1, __m128d _2) +{ + return (__m256d)__builtin_lasx_insert_128_lo_d ((v4f64)_1, (v2f64)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DF, V4DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_insert_128_hi_d (__m256d _1, __m128d _2) +{ + return (__m256d)__builtin_lasx_insert_128_hi_d ((v4f64)_1, (v2f64)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DI, V4DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_insert_128_lo (__m256i _1, __m128i _2) +{ + return (__m256i)__builtin_lasx_insert_128_lo ((v4i64)_1, (v2i64)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DI, V4DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_insert_128_hi (__m256i _1, __m128i _2) +{ + return (__m256i)__builtin_lasx_insert_128_hi ((v4i64)_1, (v2i64)_2); +} + +#endif /* defined(__loongarch_asx_sx_conv). */ #endif /* defined(__loongarch_asx). */ #endif /* _GCC_LOONGSON_ASXINTRIN_H. */ diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc index 9493ded..312d876 100644 --- a/gcc/config/loongarch/loongarch-builtins.cc +++ b/gcc/config/loongarch/loongarch-builtins.cc @@ -865,6 +865,27 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE) #define CODE_FOR_lasx_xvmaddwod_q_du CODE_FOR_lasx_maddwod_q_du_punned #define CODE_FOR_lasx_xvmaddwod_q_du_d CODE_FOR_lasx_maddwod_q_du_d_punned + +/* Add mutual conversion between 128 and 256 vectors. */ +#define CODE_FOR_lasx_extract_128_lo_s CODE_FOR_vec_extract_lo_v8sf +#define CODE_FOR_lasx_extract_128_hi_s CODE_FOR_vec_extract_hi_v8sf +#define CODE_FOR_lasx_extract_128_lo_d CODE_FOR_vec_extract_lo_v4df +#define CODE_FOR_lasx_extract_128_hi_d CODE_FOR_vec_extract_hi_v4df +#define CODE_FOR_lasx_extract_128_lo CODE_FOR_vec_extract_lo_v4di +#define CODE_FOR_lasx_extract_128_hi CODE_FOR_vec_extract_hi_v4di +#define CODE_FOR_lasx_insert_128_lo_s CODE_FOR_vec_insert_lo_v8sf +#define CODE_FOR_lasx_insert_128_hi_s CODE_FOR_vec_insert_hi_v8sf +#define CODE_FOR_lasx_insert_128_lo_d CODE_FOR_vec_insert_lo_v4df +#define CODE_FOR_lasx_insert_128_hi_d CODE_FOR_vec_insert_hi_v4df +#define CODE_FOR_lasx_insert_128_lo CODE_FOR_vec_insert_lo_v4di +#define CODE_FOR_lasx_insert_128_hi CODE_FOR_vec_insert_hi_v4di +#define CODE_FOR_lasx_concat_128_s CODE_FOR_vec_concatv8sf +#define CODE_FOR_lasx_concat_128_d CODE_FOR_vec_concatv4df +#define CODE_FOR_lasx_concat_128 CODE_FOR_vec_concatv4di +#define CODE_FOR_lasx_cast_128_s CODE_FOR_vec_castv8sf +#define CODE_FOR_lasx_cast_128_d CODE_FOR_vec_castv4df +#define CODE_FOR_lasx_cast_128 CODE_FOR_vec_castv4di + static const struct loongarch_builtin_description loongarch_builtins[] = { #define LARCH_MOVFCSR2GR 0 DIRECT_BUILTIN (movfcsr2gr, LARCH_USI_FTYPE_UQI, hard_float), @@ -2407,7 +2428,25 @@ static const struct loongarch_builtin_description loongarch_builtins[] = { LASX_BUILTIN (xvssrarni_bu_h, LARCH_UV32QI_FTYPE_UV32QI_V32QI_USI), LASX_BUILTIN (xvssrarni_hu_w, LARCH_UV16HI_FTYPE_UV16HI_V16HI_USI), LASX_BUILTIN (xvssrarni_wu_d, LARCH_UV8SI_FTYPE_UV8SI_V8SI_USI), - LASX_BUILTIN (xvssrarni_du_q, LARCH_UV4DI_FTYPE_UV4DI_V4DI_USI) + LASX_BUILTIN (xvssrarni_du_q, LARCH_UV4DI_FTYPE_UV4DI_V4DI_USI), + LASX_BUILTIN (extract_128_lo_s, LARCH_V4SF_FTYPE_V8SF), + LASX_BUILTIN (extract_128_hi_s, LARCH_V4SF_FTYPE_V8SF), + LASX_BUILTIN (extract_128_lo_d, LARCH_V2DF_FTYPE_V4DF), + LASX_BUILTIN (extract_128_hi_d, LARCH_V2DF_FTYPE_V4DF), + LASX_BUILTIN (extract_128_lo, LARCH_V2DI_FTYPE_V4DI), + LASX_BUILTIN (extract_128_hi, LARCH_V2DI_FTYPE_V4DI), + LASX_BUILTIN (insert_128_lo_s, LARCH_V8SF_FTYPE_V8SF_V4SF), + LASX_BUILTIN (insert_128_hi_s, LARCH_V8SF_FTYPE_V8SF_V4SF), + LASX_BUILTIN (insert_128_lo_d, LARCH_V4DF_FTYPE_V4DF_V2DF), + LASX_BUILTIN (insert_128_hi_d, LARCH_V4DF_FTYPE_V4DF_V2DF), + LASX_BUILTIN (insert_128_lo, LARCH_V4DI_FTYPE_V4DI_V2DI), + LASX_BUILTIN (insert_128_hi, LARCH_V4DI_FTYPE_V4DI_V2DI), + LASX_BUILTIN (concat_128_s, LARCH_V8SF_FTYPE_V4SF_V4SF), + LASX_BUILTIN (concat_128_d, LARCH_V4DF_FTYPE_V2DF_V2DF), + LASX_BUILTIN (concat_128, LARCH_V4DI_FTYPE_V2DI_V2DI), + LASX_BUILTIN (cast_128_s, LARCH_V8SF_FTYPE_V4SF), + LASX_BUILTIN (cast_128_d, LARCH_V4DF_FTYPE_V2DF), + LASX_BUILTIN (cast_128, LARCH_V4DI_FTYPE_V2DI) }; /* Index I is the function declaration for loongarch_builtins[I], or null if @@ -3001,6 +3040,10 @@ loongarch_expand_builtin_direct (enum insn_code icode, rtx target, tree exp, { struct expand_operand ops[MAX_RECOG_OPERANDS]; int opno, argno; + /* For vector extraction/insertion operations, sel_high_p being true + indicates that the high of the data is selected/retained from the + vector register. */ + bool sel_high_p = true; /* Map any target to operand 0. */ opno = 0; @@ -3019,6 +3062,51 @@ loongarch_expand_builtin_direct (enum insn_code icode, rtx target, tree exp, create_input_operand (&ops[1], CONST1_RTX (ops[0].mode), ops[0].mode); return loongarch_expand_builtin_insn (icode, 3, ops, has_target_p); + case CODE_FOR_vec_extract_lo_v8sf: + case CODE_FOR_vec_extract_lo_v4df: + case CODE_FOR_vec_extract_lo_v4di: + sel_high_p = false; + /* Fall through. */ + case CODE_FOR_vec_extract_hi_v8sf: + case CODE_FOR_vec_extract_hi_v4df: + case CODE_FOR_vec_extract_hi_v4di: + { + /* The selection method for constructing the high/low half. */ + loongarch_prepare_builtin_arg (&ops[1], exp, 0); + int nelts = GET_MODE_NUNITS (GET_MODE (ops[1].value)); + int half_nelts = nelts / 2; + int base = sel_high_p ? half_nelts : 0; + + rtx pat_rtx + = loongarch_gen_stepped_int_parallel (half_nelts, base, 1); + create_input_operand (&ops[2], pat_rtx, ops[1].mode); + + return loongarch_expand_builtin_insn (icode, 3, ops, has_target_p); + } + + case CODE_FOR_vec_insert_hi_v8sf: + case CODE_FOR_vec_insert_hi_v4df: + case CODE_FOR_vec_insert_hi_v4di: + sel_high_p = false; + /* Fall through. */ + case CODE_FOR_vec_insert_lo_v8sf: + case CODE_FOR_vec_insert_lo_v4df: + case CODE_FOR_vec_insert_lo_v4di: + { + /* The selection method for constructing the high/low half. */ + loongarch_prepare_builtin_arg (&ops[1], exp, 0); + loongarch_prepare_builtin_arg (&ops[2], exp, 1); + int nelts = GET_MODE_NUNITS (GET_MODE (ops[1].value)); + int half_nelts = nelts / 2; + int base = sel_high_p ? half_nelts : 0; + + rtx pat_rtx + = loongarch_gen_stepped_int_parallel (half_nelts, base, 1); + create_input_operand (&ops[3], pat_rtx, ops[1].mode); + + return loongarch_expand_builtin_insn (icode, 4, ops, has_target_p); + } + default: break; } diff --git a/gcc/config/loongarch/loongarch-c.cc b/gcc/config/loongarch/loongarch-c.cc index effdcf0..fc031a6 100644 --- a/gcc/config/loongarch/loongarch-c.cc +++ b/gcc/config/loongarch/loongarch-c.cc @@ -132,6 +132,7 @@ loongarch_update_cpp_builtins (cpp_reader *pfile) loongarch_def_or_undef (ISA_HAS_LSX, "__loongarch_simd", pfile); loongarch_def_or_undef (ISA_HAS_LSX, "__loongarch_sx", pfile); loongarch_def_or_undef (ISA_HAS_LASX, "__loongarch_asx", pfile); + loongarch_def_or_undef (ISA_HAS_LASX, "__loongarch_asx_sx_conv", pfile); builtin_undef ("__loongarch_simd_width"); if (ISA_HAS_LSX) diff --git a/gcc/config/loongarch/loongarch-ftypes.def b/gcc/config/loongarch/loongarch-ftypes.def index 337f2c2..68b1b44 100644 --- a/gcc/config/loongarch/loongarch-ftypes.def +++ b/gcc/config/loongarch/loongarch-ftypes.def @@ -42,6 +42,12 @@ DEF_LARCH_FTYPE (1, (USI, USI)) DEF_LARCH_FTYPE (1, (UDI, USI)) DEF_LARCH_FTYPE (1, (USI, UQI)) DEF_LARCH_FTYPE (1, (VOID, USI)) +DEF_LARCH_FTYPE (1, (V4SF, V8SF)) +DEF_LARCH_FTYPE (1, (V2DF, V4DF)) +DEF_LARCH_FTYPE (1, (V2DI, V4DI)) +DEF_LARCH_FTYPE (1, (V8SF, V4SF)) +DEF_LARCH_FTYPE (1, (V4DF, V2DF)) +DEF_LARCH_FTYPE (1, (V4DI, V2DI)) DEF_LARCH_FTYPE (2, (VOID, UQI, USI)) DEF_LARCH_FTYPE (2, (VOID, UHI, USI)) @@ -58,6 +64,12 @@ DEF_LARCH_FTYPE (2, (SI, SI, SI)) DEF_LARCH_FTYPE (2, (SI, DI, SI)) DEF_LARCH_FTYPE (2, (USI, USI, USI)) DEF_LARCH_FTYPE (2, (UDI, UDI, USI)) +DEF_LARCH_FTYPE (2, (V8SF, V4SF, V4SF)) +DEF_LARCH_FTYPE (2, (V4DF, V2DF, V2DF)) +DEF_LARCH_FTYPE (2, (V4DI, V2DI, V2DI)) +DEF_LARCH_FTYPE (2, (V8SF, V8SF, V4SF)) +DEF_LARCH_FTYPE (2, (V4DF, V4DF, V2DF)) +DEF_LARCH_FTYPE (2, (V4DI, V4DI, V2DI)) DEF_LARCH_FTYPE (3, (VOID, USI, USI, SI)) DEF_LARCH_FTYPE (3, (VOID, USI, UDI, SI)) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index f7ce3aa..c725d02 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -3439,13 +3439,8 @@ loongarch_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value) x = GEN_INT (codes[0].value); for (i = 1; i < num_ops; i++) { - if (!can_create_pseudo_p ()) - { - emit_insn (gen_rtx_SET (temp, x)); - x = temp; - } - else - x = force_reg (mode, x); + emit_insn (gen_rtx_SET (temp, x)); + x = temp; set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (codes[i-1].curr_value)); @@ -4234,7 +4229,8 @@ loongarch_rtx_costs (rtx x, machine_mode mode, int outer_code, machine_mode loongarch_split_reduction (machine_mode mode) { - if (LSX_SUPPORTED_MODE_P (mode)) + if (!VECTOR_MODE_P (mode) + || LSX_SUPPORTED_MODE_P (mode)) return mode; return mode_for_vector (as_a <scalar_mode> (GET_MODE_INNER (mode)), diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 697198f..166ddd9 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -357,7 +357,7 @@ { if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode)) FAIL; - if (TARGET_64BIT && register_operand (operands[2], QImode)) + if (TARGET_64BIT) { rtx t = gen_reg_rtx (DImode); emit_insn (gen_rotrsi3_sext (t, operands[1], operands[2])); diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index cdb706a..570acb1 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -209,6 +209,11 @@ rtl_opt_pass * make_pass_insert_landing_pad (gcc::context *ctxt); rtl_opt_pass * make_pass_vector_permconst (gcc::context *ctxt); rtl_opt_pass * make_pass_bclr_lowest_set_bit (gcc::context *ctxt); +/* Routines implemented in riscv-vsetvl.cc. */ +extern bool has_vtype_op (rtx_insn *); +extern bool mask_agnostic_p (rtx_insn *); +extern rtx get_avl (rtx_insn *); +extern bool vsetvl_insn_p (rtx_insn *); /* Routines implemented in riscv-string.c. */ extern bool riscv_expand_block_compare (rtx, rtx, rtx, rtx); diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 3586d0c..580ac9c 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -258,7 +258,7 @@ policy_to_str (bool agnostic_p) /* Return true if it is an RVV instruction depends on VTYPE global status register. */ -static bool +bool has_vtype_op (rtx_insn *rinsn) { return recog_memoized (rinsn) >= 0 && get_attr_has_vtype_op (rinsn); @@ -306,7 +306,7 @@ vector_config_insn_p (rtx_insn *rinsn) } /* Return true if it is vsetvldi or vsetvlsi. */ -static bool +bool vsetvl_insn_p (rtx_insn *rinsn) { if (!rinsn || !vector_config_insn_p (rinsn)) @@ -386,7 +386,7 @@ get_vl (rtx_insn *rinsn) } /* Helper function to get AVL operand. */ -static rtx +rtx get_avl (rtx_insn *rinsn) { if (vsetvl_insn_p (rinsn) || vsetvl_discard_result_insn_p (rinsn)) @@ -411,7 +411,7 @@ get_default_ma () } /* Helper function to get MA operand. */ -static bool +bool mask_agnostic_p (rtx_insn *rinsn) { /* If it doesn't have MA, we return agnostic by default. */ diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 63404d3..e978f92 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -10576,6 +10576,71 @@ riscv_issue_rate (void) return tune_param->issue_rate; } +/* Structure for very basic vector configuration tracking in the scheduler. */ +struct last_vconfig +{ + bool valid; + bool ta; + bool ma; + uint8_t sew; + uint8_t vlmul; + rtx avl; +} last_vconfig; + +/* Clear LAST_VCONFIG so we have no known state. */ +static void +clear_vconfig (void) +{ + memset (&last_vconfig, 0, sizeof (last_vconfig)); +} + +/* Return TRUE if INSN is a vector insn needing a particular + vector configuration that is trivially equal to the last + vector insn issued. Return FALSE otherwise. */ +static bool +compatible_with_last_vconfig (rtx_insn *insn) +{ + /* We might be able to extract the data from a preexisting vsetvl. */ + if (vsetvl_insn_p (insn)) + return false; + + /* Nothing to do for these cases. */ + if (!NONDEBUG_INSN_P (insn) || !has_vtype_op (insn)) + return false; + + extract_insn_cached (insn); + + rtx avl = get_avl (insn); + if (avl != last_vconfig.avl) + return false; + + if (get_sew (insn) != last_vconfig.sew) + return false; + + if (get_vlmul (insn) != last_vconfig.vlmul) + return false; + + if (tail_agnostic_p (insn) != last_vconfig.ta) + return false; + + if (mask_agnostic_p (insn) != last_vconfig.ma) + return false; + + /* No differences found, they're trivially compatible. */ + return true; +} + +/* Implement TARGET_SCHED_INIT, we use this to track the vector configuration + of the last issued vector instruction. We can then use that information + to potentially adjust the ready queue to issue instructions of a compatible + vector configuration instead of a conflicting configuration. That will + reduce the number of vsetvl instructions we ultimately emit. */ +static void +riscv_sched_init (FILE *, int, int) +{ + clear_vconfig (); +} + /* Implement TARGET_SCHED_VARIABLE_ISSUE. */ static int riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more) @@ -10600,9 +10665,88 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more) an assert so we can find and fix this problem. */ gcc_assert (insn_has_dfa_reservation_p (insn)); + /* If this is a vector insn with vl/vtype info, then record the last + vector configuration. */ + if (vsetvl_insn_p (insn)) + clear_vconfig (); + else if (NONDEBUG_INSN_P (insn) && has_vtype_op (insn)) + { + extract_insn_cached (insn); + + rtx avl = get_avl (insn); + if (avl == RVV_VLMAX) + avl = const0_rtx; + + if (!avl || !CONST_INT_P (avl)) + clear_vconfig (); + else + { + last_vconfig.valid = true; + last_vconfig.avl = avl; + last_vconfig.sew = get_sew (insn); + last_vconfig.vlmul = get_vlmul (insn); + last_vconfig.ta = tail_agnostic_p (insn); + last_vconfig.ma = mask_agnostic_p (insn); + } + } + return more - 1; } +/* Implement TARGET_SCHED_REORDER. The goal here is to look at the ready + queue and reorder it ever so slightly to encourage issing an insn with + the same vector configuration as the most recently issued vector + instruction. That will reduce vsetvl instructions. */ +static int +riscv_sched_reorder (FILE *, int, rtx_insn **ready, int *nreadyp, int) +{ + /* If we don't have a valid prior vector configuration, then there is + no point in reordering the ready queue, similarly if there is + just one entry in the queue. */ + if (!last_vconfig.valid || *nreadyp == 1) + return riscv_issue_rate (); + + return riscv_issue_rate (); + int nready = *nreadyp; + int priority = INSN_PRIORITY (ready[nready - 1]); + for (int i = nready - 1; i >= 0; i--) + { + rtx_insn *insn = ready[i]; + + /* On a high performance core, vsetvl instructions should be + inexpensive. Removing them is very much a secondary concern, so + be extremely conservative with reordering, essentially only + allowing reordering within the highest priority value. + + Lower end cores may benefit from more flexibility here. That + tuning is left to those who understand their core's behavior + and can thoroughly benchmark the result. Assuming such + designs appear, we can probably put an entry in the tuning + structure to indicate how much difference in priority to allow. */ + if (INSN_PRIORITY (insn) < priority) + break; + + if (compatible_with_last_vconfig (insn)) + { + /* This entry is compatible with the last vconfig and has + the same priority as the most important insn. So swap + it so that we keep the vector configuration as-is and + ultimately eliminate a vsetvl. + + Note no need to swap if this is the first entry in the + queue. */ + if (i == nready - 1) + break; + + std::swap (ready[i], ready[nready - 1]); + break; + } + } + + return riscv_issue_rate (); +} + + /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports instruction fusion of some sort. */ @@ -16011,9 +16155,15 @@ riscv_prefetch_offset_address_p (rtx x, machine_mode mode) #undef TARGET_SCHED_MACRO_FUSION_PAIR_P #define TARGET_SCHED_MACRO_FUSION_PAIR_P riscv_macro_fusion_pair_p +#undef TARGET_SCHED_INIT +#define TARGET_SCHED_INIT riscv_sched_init + #undef TARGET_SCHED_VARIABLE_ISSUE #define TARGET_SCHED_VARIABLE_ISSUE riscv_sched_variable_issue +#undef TARGET_SCHED_REORDER +#define TARGET_SCHED_REORDER riscv_sched_reorder + #undef TARGET_SCHED_ADJUST_COST #define TARGET_SCHED_ADJUST_COST riscv_sched_adjust_cost diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 20e82e6..42171a5 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -34,7 +34,7 @@ (define_insn "*th_srri<mode>3" [(set (match_operand:GPR 0 "register_operand" "=r") (rotatert:GPR (match_operand:GPR 1 "register_operand" "r") - (match_operand 2 "const_int_operand" "n")))] + (match_operand 2 "const_int_operand" "n")))] "TARGET_XTHEADBB && (TARGET_64BIT || <MODE>mode == SImode)" { bool wform = TARGET_64BIT && (<MODE>mode == SImode); @@ -45,6 +45,22 @@ [(set_attr "type" "bitmanip") (set_attr "mode" "<GPR:MODE>")]) +;; Version with explicit sign extension to facilitate sign extension +;; removal. +(define_insn "*th_srrisi3_extended" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (rotatert:SI (match_operand:SI 1 "register_operand" "r") + (match_operand 2 "const_int_operand" "n"))))] + "TARGET_XTHEADBB && TARGET_64BIT" + { + operands[2] = GEN_INT (INTVAL (operands[2]) + & (GET_MODE_BITSIZE (SImode) - 1)); + return "th.srriw\t%0,%1,%2"; + } + [(set_attr "type" "bitmanip") + (set_attr "mode" "SI")]) + (define_insn "*th_ext<mode>4" [(set (match_operand:GPR 0 "register_operand" "=r") (sign_extract:GPR (match_operand:GPR 1 "register_operand" "r") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 3cb87bf..9d34725 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1437,6 +1437,8 @@ [(set_attr "type" "vlde,vste,vmov") (set_attr "mode" "<MODE>") (set (attr "merge_op_idx") (const_int INVALID_ATTRIBUTE)) + (set (attr "has_vl_op") (const_string "false")) + (set (attr "has_vtype_op") (const_string "false")) (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE)) (set (attr "mode_idx") (const_int INVALID_ATTRIBUTE))] ) diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 73c2a03..08d1fa7 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,17 @@ +2025-11-02 Nathaniel Shead <nathanieloshead@gmail.com> + + PR c++/122421 + * module.cc (trees_in::read_var_def): Don't handle class-scope + variables anymore. + (trees_in::read_class_def): Handle them here instead. + +2025-11-01 Nathaniel Shead <nathanieloshead@gmail.com> + + PR c++/122381 + * module.cc (trees_out::core_vals): Write BASELINK_OPTYPE (aka + TREE_CHAIN). + (trees_in::core_vals): Read it. + 2025-10-30 Jakub Jelinek <jakub@redhat.com> * std-name-hint.gperf: Remove duplicate entries for ispanstream diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc index 31f5c81..e0b9efa 100644 --- a/gcc/cp/module.cc +++ b/gcc/cp/module.cc @@ -13048,12 +13048,11 @@ trees_in::read_var_def (tree decl, tree maybe_template) if (DECL_EXPLICIT_INSTANTIATION (decl) && !DECL_EXTERNAL (decl)) setup_explicit_instantiation_definition_linkage (decl); - if (DECL_IMPLICIT_INSTANTIATION (decl) - || (DECL_EXPLICIT_INSTANTIATION (decl) - && !DECL_EXTERNAL (decl)) - || (DECL_CLASS_SCOPE_P (decl) - && !DECL_VTABLE_OR_VTT_P (decl) - && !DECL_TEMPLATE_INFO (decl))) + /* Class static data members are handled in read_class_def. */ + if (!DECL_CLASS_SCOPE_P (decl) + && (DECL_IMPLICIT_INSTANTIATION (decl) + || (DECL_EXPLICIT_INSTANTIATION (decl) + && !DECL_EXTERNAL (decl)))) note_vague_linkage_variable (decl); } if (!dyn_init) @@ -13467,6 +13466,10 @@ trees_in::read_class_def (tree defn, tree maybe_template) DECL_ACCESS (d) = tree_cons (type, access, list); } } + + if (TREE_CODE (decl) == VAR_DECL + && TREE_CODE (maybe_template) != TEMPLATE_DECL) + note_vague_linkage_variable (decl); } } diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 30eae4b..00273c0 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -19701,7 +19701,16 @@ into the data cache. The instruction is issued in slot I1@. These built-in functions are available for LoongArch. -Data Type Description: +@menu +* Data Types:: +* Directly-mapped Builtin Functions:: +* Directly-mapped Division Builtin Functions:: +* Other Builtin Functions:: +@end menu + +@node Data Types +@subsubsection Data Types + @itemize @item @code{imm0_31}, a compile-time constant in range 0 to 31; @item @code{imm0_16383}, a compile-time constant in range 0 to 16383; @@ -19709,6 +19718,9 @@ Data Type Description: @item @code{imm_n2048_2047}, a compile-time constant in range -2048 to 2047; @end itemize +@node Directly-mapped Builtin Functions +@subsubsection Directly-mapped Builtin Functions + The intrinsics provided are listed below: @smallexample unsigned int __builtin_loongarch_movfcsr2gr (imm0_31) @@ -19832,6 +19844,9 @@ function you need to include @code{larchintrin.h}. void __break (imm0_32767) @end smallexample +@node Directly-mapped Division Builtin Functions +@subsubsection Directly-mapped Division Builtin Functions + These intrinsic functions are available by including @code{larchintrin.h} and using @option{-mfrecipe}. @smallexample @@ -19841,6 +19856,9 @@ using @option{-mfrecipe}. double __frsqrte_d (double); @end smallexample +@node Other Builtin Functions +@subsubsection Other Builtin Functions + Additional built-in functions are available for LoongArch family processors to efficiently use 128-bit floating-point (__float128) values. @@ -19867,6 +19885,15 @@ GCC provides intrinsics to access the LSX (Loongson SIMD Extension) instructions The interface is made available by including @code{<lsxintrin.h>} and using @option{-mlsx}. +@menu +* SX Data Types:: +* Directly-mapped SX Builtin Functions:: +* Directly-mapped SX Division Builtin Functions:: +@end menu + +@node SX Data Types +@subsubsection SX Data Types + The following vectors typedefs are included in @code{lsxintrin.h}: @itemize @@ -19894,6 +19921,9 @@ input/output values manipulated: @item @code{imm_n2048_2047}, an integer literal in range -2048 to 2047. @end itemize +@node Directly-mapped SX Builtin Functions +@subsubsection Directly-mapped SX Builtin Functions + For convenience, GCC defines functions @code{__lsx_vrepli_@{b/h/w/d@}} and @code{__lsx_b[n]z_@{v/b/h/w/d@}}, which are implemented as follows: @@ -20677,6 +20707,9 @@ __m128i __lsx_vxori_b (__m128i, imm0_255); __m128i __lsx_vxor_v (__m128i, __m128i); @end smallexample +@node Directly-mapped SX Division Builtin Functions +@subsubsection Directly-mapped SX Division Builtin Functions + These intrinsic functions are available by including @code{lsxintrin.h} and using @option{-mfrecipe} and @option{-mlsx}. @smallexample @@ -20693,6 +20726,16 @@ GCC provides intrinsics to access the LASX (Loongson Advanced SIMD Extension) instructions. The interface is made available by including @code{<lasxintrin.h>} and using @option{-mlasx}. +@menu +* ASX Data Types:: +* Directly-mapped ASX Builtin Functions:: +* Directly-mapped ASX Division Builtin Functions:: +* Directly-mapped SX and ASX Conversion Builtin Functions:: +@end menu + +@node ASX Data Types +@subsubsection ASX Data Types + The following vectors typedefs are included in @code{lasxintrin.h}: @itemize @@ -20721,6 +20764,9 @@ input/output values manipulated: @item @code{imm_n2048_2047}, an integer literal in range -2048 to 2047. @end itemize +@node Directly-mapped ASX Builtin Functions +@subsubsection Directly-mapped ASX Builtin Functions + For convenience, GCC defines functions @code{__lasx_xvrepli_@{b/h/w/d@}} and @code{__lasx_b[n]z_@{v/b/h/w/d@}}, which are implemented as follows: @@ -21525,6 +21571,9 @@ __m256i __lasx_xvxori_b (__m256i, imm0_255); __m256i __lasx_xvxor_v (__m256i, __m256i); @end smallexample +@node Directly-mapped ASX Division Builtin Functions +@subsubsection Directly-mapped ASX Division Builtin Functions + These intrinsic functions are available by including @code{lasxintrin.h} and using @option{-mfrecipe} and @option{-mlasx}. @smallexample @@ -21534,6 +21583,213 @@ __m256d __lasx_xvfrsqrte_d (__m256d); __m256 __lasx_xvfrsqrte_s (__m256); @end smallexample +@node Directly-mapped SX and ASX Conversion Builtin Functions +@subsubsection Directly-mapped SX and ASX Conversion Builtin Functions + +For convenience, the @code{lsxintrin.h} file was imported into @code{ +lasxintrin.h} and 18 new interface functions for 128 and 256 vector +conversions were added, using the @option{-mlasx} option. +@smallexample +__m256 __lasx_cast_128_s (__m128); +__m256d __lasx_cast_128_d (__m128d); +__m256i __lasx_cast_128 (__m128i); +__m256 __lasx_concat_128_s (__m128, __m128); +__m256d __lasx_concat_128_d (__m128d, __m128d); +__m256i __lasx_concat_128 (__m128i, __m128i); +__m128 __lasx_extract_128_lo_s (__m256); +__m128 __lasx_extract_128_hi_s (__m256); +__m128d __lasx_extract_128_lo_d (__m256d); +__m128d __lasx_extract_128_hi_d (__m256d); +__m128i __lasx_extract_128_lo (__m256i); +__m128i __lasx_extract_128_hi (__m256i); +__m256 __lasx_insert_128_lo_s (__m256, __m128); +__m256 __lasx_insert_128_hi_s (__m256, __m128); +__m256d __lasx_insert_128_lo_d (__m256d, __m128d); +__m256d __lasx_insert_128_hi_d (__m256d, __m128d); +__m256i __lasx_insert_128_lo (__m256i, __m128i); +__m256i __lasx_insert_128_hi (__m256i, __m128i); +@end smallexample + +When gcc does not support interfaces for 128 and 256 conversions, +use the following code for equivalent substitution. + +@smallexample + + #ifndef __loongarch_asx_sx_conv + + #include <lasxintrin.h> + #include <lsxintrin.h> + __m256 inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_cast_128_s (__m128 src) + @{ + __m256 dest; + asm ("" : "=f"(dest) : "0"(src)); + return dest; + @} + + __m256d inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_cast_128_d (__m128d src) + @{ + __m256d dest; + asm ("" : "=f"(dest) : "0"(src)); + return dest; + @} + + __m256i inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_cast_128 (__m128i src) + @{ + __m256i dest; + asm ("" : "=f"(dest) : "0"(src)); + return dest; + @} + + __m256 inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_concat_128_s (__m128 src1, __m128 src2) + @{ + __m256 dest; + asm ("xvpermi.q %u0,%u2,0x02\n" + : "=f"(dest) + : "0"(src1), "f"(src2)); + return dest; + @} + + __m256d inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_concat_128_d (__m128d src1, __m128d src2) + @{ + __m256d dest; + asm ("xvpermi.q %u0,%u2,0x02\n" + : "=f"(dest) + : "0"(src1), "f"(src2)); + return dest; + @} + + __m256i inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_concat_128 (__m128i src1, __m128i src2) + @{ + __m256i dest; + asm ("xvpermi.q %u0,%u2,0x02\n" + : "=f"(dest) + : "0"(src1), "f"(src2)); + return dest; + @} + + __m128 inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_extract_128_lo_s (__m256 src) + @{ + __m128 dest; + asm ("" : "=f"(dest) : "0"(src)); + return dest; + @} + + __m128d inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_extract_128_lo_d (__m256d src) + @{ + __m128d dest; + asm ("" : "=f"(dest) : "0"(src)); + return dest; + @} + + __m128i inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_extract_128_lo (__m256i src) + @{ + __m128i dest; + asm ("" : "=f"(dest) : "0"(src)); + return dest; + @} + + __m128 inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_extract_128_hi_s (__m256 src) + @{ + __m128 dest; + asm ("xvpermi.d %u0,%u1,0xe\n" + : "=f"(dest) + : "f"(src)); + return dest; + @} + + __m128d inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_extract_128_hi_d (__m256d src) + @{ + __m128d dest; + asm ("xvpermi.d %u0,%u1,0xe\n" + : "=f"(dest) + : "f"(src)); + return dest; + @} + + __m128i inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_extract_128_hi (__m256i src) + @{ + __m128i dest; + asm ("xvpermi.d %u0,%u1,0xe\n" + : "=f"(dest) + : "f"(src)); + return dest; + @} + + __m256 inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_insert_128_lo_s (__m256 src1, __m128 src2) + @{ + __m256 dest; + asm ("xvpermi.q %u0,%u2,0x30\n" + : "=f"(dest) + : "0"(src1), "f"(src2)); + return dest; + @} + + __m256d inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_insert_128_lo_d (__m256d a, __m128d b) + @{ + __m256d dest; + asm ("xvpermi.q %u0,%u2,0x30\n" + : "=f"(dest) + : "0"(src1), "f"(src2)); + return dest; + @} + + __m256i inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_insert_128_lo (__m256i src1, __m128i src2) + @{ + __m256i dest; + asm ("xvpermi.q %u0,%u2,0x30\n" + : "=f"(dest) + : "0"(src1), "f"(src2)); + return dest; + @} + + __m256 inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_insert_128_hi_s (__m256 src1, __m128 src2) + @{ + __m256 dest; + asm ("xvpermi.q %u0,%u2,0x02\n" + : "=f"(dest) + : "0"(src1), "f"(src2)); + return dest; + @} + + __m256d inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_insert_128_hi_d (__m256d src1, __m128d src2) + @{ + __m256d dest; + asm ("xvpermi.q %u0,%u2,0x02\n" + : "=f"(dest) + : "0"(src1), "f"(src2)); + return dest; + @} + + __m256i inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + __lasx_insert_128_hi (__m256i src1, __m128i src2) + @{ + __m256i dest; + asm ("xvpermi.q %u0,%u2,0x02\n" + : "=f"(dest) + : "0"(src1), "f"(src2)); + return dest; + @} + #endif + +@end smallexample + @node MIPS DSP Built-in Functions @subsection MIPS DSP Built-in Functions diff --git a/gcc/doc/tree-ssa.texi b/gcc/doc/tree-ssa.texi index dc6a111..25aa006 100644 --- a/gcc/doc/tree-ssa.texi +++ b/gcc/doc/tree-ssa.texi @@ -355,7 +355,7 @@ FOR_EACH_PHI_OR_STMT_DEF (def_operand_p, phi, iter, flags) Immediate use information is now always available. Using the immediate use iterators, you may examine every use of any @code{SSA_NAME}. For instance, -to change each use of @code{ssa_var} to @code{ssa_var2} and call fold_stmt on +to change each use of @code{ssa_var} to @code{val} and call fold_stmt on each stmt after that is done: @smallexample @@ -367,8 +367,9 @@ each stmt after that is done: FOR_EACH_IMM_USE_STMT (stmt, iterator, ssa_var) @{ FOR_EACH_IMM_USE_ON_STMT (imm_use_p, iterator) - SET_USE (imm_use_p, ssa_var_2); + SET_USE (imm_use_p, val); fold_stmt (stmt); + update_stmt (stmt); @} @end smallexample @@ -389,9 +390,7 @@ terminated early; a destructor takes care of that when leaving the @code{FOR_EACH_IMM_USE_STMT} scope. There are checks in @code{verify_ssa} which verify that the immediate use list -is up to date, as well as checking that an optimization didn't break from the -loop without using this macro. It is safe to simply 'break'; from a -@code{FOR_EACH_IMM_USE_FAST} traverse. +is up to date. Some useful functions and macros: @enumerate @@ -412,7 +411,9 @@ isn't located in a @code{PHI} node. @end enumerate Note that uses are not put into an immediate use list until their statement is -actually inserted into the instruction stream via a @code{bsi_*} routine. +actually inserted into the instruction stream via a @code{gsi_*} routine +which calls @code{update_stmt} to re-scan SSA operands and update the +immediate use lists. It is also still possible to utilize lazy updating of statements, but this should be used only when absolutely required. Both alias analysis and the diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 0d937eb..5501bca 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,9 @@ +2025-11-01 Harald Anlauf <anlauf@gmx.de> + + PR fortran/78640 + * resolve.cc (resolve_fl_procedure): Check function result of a + pure function against F2018:C1585. + 2025-10-31 Yuao Ma <c8ef@outlook.com> * intrinsic.texi: Fix typo. diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc index 48ce7578..1bbf21f 100644 --- a/gcc/lra-constraints.cc +++ b/gcc/lra-constraints.cc @@ -523,6 +523,11 @@ update_equiv (int regno) { rtx x; + /* If REGNO is beyond the length of the equivalence array structure, + then there's nothing to update. */ + if (regno >= ira_reg_equiv_len) + return; + if ((x = ira_reg_equiv[regno].memory) != NULL_RTX) ira_reg_equiv[regno].memory = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog index bb307bb..737ab12 100644 --- a/gcc/m2/ChangeLog +++ b/gcc/m2/ChangeLog @@ -1,3 +1,36 @@ +2025-11-02 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/122499 + * gm2-compiler/M2StackSpell.mod (PushName): Add comment. + (GetSpellHint): Rewrite. + (GetExportedSpellHint): New procedure function. + (GetScopeSpellHint): New procedure function. + * gm2-compiler/P1Build.bnf (IdentScope): Rewrite. + (PossiblyExportIdent): Ditto. + * gm2-compiler/P1SymBuild.mod (BuildImportInnerModule): Add + parameter to AddNameToImportList. + * gm2-compiler/SymbolTable.def (GetUnknownOnImport): New + procedure function. + (GetUnknownDeclScope): Ditto. + (AddNameToScope): Add tok parameter. + (AddNameToImportList): Ditto. + * gm2-compiler/SymbolTable.mod (SymUndefined): New field + declScope. + New field onImport. + (MakeObject): Add tok parameter. + (FillInUnknownFields): Initialize declScope. + Initialize onImport. + (GetUnknownOnImport): New procedure function. + (GetUnknownDeclScope): Ditto. + (AddNameToScope): Pass tok to MakeObject. + (AddNameToImportList): Add tok parameter. + Pass tok to MakeObject. + (GetDeclaredSym): Add parameters to FillInUnknownFields. + (RequestSym): Ditto. + (FetchUnknownFromModule): Ditto. + (FetchUnknownFromDefImp): Ditto. + (FetchUnknownFrom): Ditto. + 2025-10-30 Gaius Mulley <gaiusmod2@gmail.com> PR modula2/122485 diff --git a/gcc/m2/gm2-compiler/M2StackSpell.mod b/gcc/m2/gm2-compiler/M2StackSpell.mod index ac58c1c..06ce923 100644 --- a/gcc/m2/gm2-compiler/M2StackSpell.mod +++ b/gcc/m2/gm2-compiler/M2StackSpell.mod @@ -23,8 +23,10 @@ IMPLEMENTATION MODULE M2StackSpell ; FROM SymbolTable IMPORT NulSym, IsModule, IsDefImp, IsRecord, IsEnumeration, IsProcedure, GetNth, - GetSymName, GetSym, GetLocalSym, - UnknownReported, + GetSymName, GetSym, GetLocalSym, GetScope, + UnknownReported, IsUnknown, + GetUnknownOnImport, GetUnknownDeclScope, + ForeachExportedDo, ForeachProcedureDo, ForeachLocalSymDo, ForeachFieldEnumerationDo ; @@ -179,8 +181,9 @@ VAR PushCount : CARDINAL ; PushCandidate: Candidates ; + (* - PushName - + PushName - push a name to the candidate vec. *) PROCEDURE PushName (sym: CARDINAL) ; @@ -279,7 +282,7 @@ BEGIN cand := m2spellcheck.InitCandidates () ; IF PushCandidates (cand, sym) > 1 THEN - content := m2spellcheck.FindClosestCharStar (cand, string (misspelt)) ; + content := m2spellcheck.FindClosestCharStar (cand, string (misspelt)) ELSE content := NIL END ; @@ -310,6 +313,52 @@ END AddPunctuation ; *) PROCEDURE GetSpellHint (unknown: CARDINAL) : String ; +BEGIN + IF IsUnknown (unknown) AND + GetUnknownOnImport (unknown) AND + (GetUnknownDeclScope (unknown) # GetScope (unknown)) + THEN + (* It was created during an import statement. *) + RETURN GetExportedSpellHint (unknown, GetUnknownDeclScope (unknown)) + END ; + RETURN GetScopeSpellHint (unknown) +END GetSpellHint ; + + +(* + GetExportedSpellHint - return a string describing a spelling hint + using the module exported identifiers. +*) + +PROCEDURE GetExportedSpellHint (unknown, module: CARDINAL) : String ; +VAR + content : ConstCharStar ; + misspell, + HintStr : String ; +BEGIN + misspell := InitStringCharStar (KeyToCharStar (GetSymName (unknown))) ; + HintStr := NIL ; + PushCount := 0 ; + PushCandidate := m2spellcheck.InitCandidates () ; + ForeachExportedDo (module, PushName) ; + ForeachLocalSymDo (module, PushName) ; + IF PushCount > 0 + THEN + content := m2spellcheck.FindClosestCharStar (PushCandidate, + string (misspell)) ; + HintStr := BuildHintStr (HintStr, content) + END ; + m2spellcheck.KillCandidates (PushCandidate) ; + RETURN AddPunctuation (HintStr, '?') +END GetExportedSpellHint ; + + +(* + GetScopeSpellHint - return a string describing a spelling hint + using the visible scopes. +*) + +PROCEDURE GetScopeSpellHint (unknown: CARDINAL) : String ; VAR i, n : CARDINAL ; sym : CARDINAL ; @@ -331,7 +380,7 @@ BEGIN INC (i) END ; RETURN AddPunctuation (HintStr, '?') -END GetSpellHint ; +END GetScopeSpellHint ; (* diff --git a/gcc/m2/gm2-compiler/P1Build.bnf b/gcc/m2/gm2-compiler/P1Build.bnf index 4cbdf17..d56a286 100644 --- a/gcc/m2/gm2-compiler/P1Build.bnf +++ b/gcc/m2/gm2-compiler/P1Build.bnf @@ -358,9 +358,12 @@ END Ident ; *) PROCEDURE IdentScope (stopset0: SetOfStop0; stopset1: SetOfStop1; stopset2: SetOfStop2) ; +VAR + tokpos: CARDINAL ; BEGIN - Ident(stopset0, stopset1, stopset2) ; - AddNameToScope(LastIdent) + tokpos := GetTokenNo () ; + Ident (stopset0, stopset1, stopset2) ; + AddNameToScope (tokpos, LastIdent) END IdentScope ; @@ -374,14 +377,14 @@ PROCEDURE PossiblyExportIdent (stopset0: SetOfStop0; stopset1: SetOfStop1; stops VAR nothing: CARDINAL ; BEGIN - AddNameToScope(makekey(currentstring)) ; - PushTFtok(makekey(currentstring), identtok, GetTokenNo()) ; + AddNameToScope (GetTokenNo (), makekey (currentstring)) ; + PushTFtok (makekey (currentstring), identtok, GetTokenNo ()) ; CheckExplicitExported ; - IF NOT IsAutoPushOn() + IF NOT IsAutoPushOn () THEN - PopT(nothing) + PopT (nothing) END ; - Expect(identtok, stopset0, stopset1, stopset2) + Expect (identtok, stopset0, stopset1, stopset2) END PossiblyExportIdent ; diff --git a/gcc/m2/gm2-compiler/P1SymBuild.mod b/gcc/m2/gm2-compiler/P1SymBuild.mod index d6c0f2f..33d12bd 100644 --- a/gcc/m2/gm2-compiler/P1SymBuild.mod +++ b/gcc/m2/gm2-compiler/P1SymBuild.mod @@ -39,6 +39,7 @@ FROM M2Reserved IMPORT ImportTok, ExportTok, QualifiedTok, UnQualifiedTok, FROM FifoQueue IMPORT PutEnumerationIntoFifoQueue ; FROM P0SymBuild IMPORT EnterBlock, LeaveBlock ; +FROM libc IMPORT printf ; FROM SymbolTable IMPORT NulSym, ModeOfAddr, @@ -472,9 +473,6 @@ BEGIN OperandT(n+1)) ; i := 1 ; WHILE i<=n DO -(* - WriteString('Importing ') ; WriteKey(Operand(j)) ; WriteString(' from ') ; WriteKey(GetSymName(ModSym)) ; WriteLn ; -*) Sym := GetExported (OperandTok (n+1-i), ModSym, OperandT (n+1-i)) ; PutImported (Sym) ; @@ -619,7 +617,7 @@ BEGIN (* Ident List contains list of objects *) i := 1 ; WHILE i<=n DO - AddNameToImportList (OperandT (i)) ; + AddNameToImportList (OperandTok (i), OperandT (i)) ; INC (i) END ELSE diff --git a/gcc/m2/gm2-compiler/SymbolTable.def b/gcc/m2/gm2-compiler/SymbolTable.def index 09a5590..2a2f201 100644 --- a/gcc/m2/gm2-compiler/SymbolTable.def +++ b/gcc/m2/gm2-compiler/SymbolTable.def @@ -2136,6 +2136,20 @@ PROCEDURE UnknownReported (sym: CARDINAL) ; (* + GetUnknownOnImport - returns the onimport field of unknown sym. +*) + +PROCEDURE GetUnknownOnImport (sym: CARDINAL) : BOOLEAN ; + + +(* + GetUnknownDeclScope - returns the decl scope of unknown sym. +*) + +PROCEDURE GetUnknownDeclScope (sym: CARDINAL) : CARDINAL ; + + +(* IsReallyPointer - returns TRUE is sym is a pointer, address or a type declared as a pointer or address. *) @@ -2613,7 +2627,7 @@ PROCEDURE ResolveConstructorTypes ; current scope. *) -PROCEDURE AddNameToScope (n: Name) ; +PROCEDURE AddNameToScope (tok: CARDINAL; n: Name) ; (* @@ -2621,7 +2635,7 @@ PROCEDURE AddNameToScope (n: Name) ; module. *) -PROCEDURE AddNameToImportList (n: Name) ; +PROCEDURE AddNameToImportList (tok: CARDINAL; n: Name) ; (* diff --git a/gcc/m2/gm2-compiler/SymbolTable.mod b/gcc/m2/gm2-compiler/SymbolTable.mod index 023bd49..25170fb 100644 --- a/gcc/m2/gm2-compiler/SymbolTable.mod +++ b/gcc/m2/gm2-compiler/SymbolTable.mod @@ -230,6 +230,10 @@ TYPE SymUndefined = RECORD name : Name ; (* Index into name array, name *) (* of record. *) + declScope : CARDINAL ; (* Scope where unknown is *) + (* created. *) + onImport : BOOLEAN ; (* Was it created during an *) + (* import? *) oafamily : CARDINAL ; (* The oafamily for this sym *) errorScope: ErrorScope ; (* Title scope used if an *) (* error is emitted. *) @@ -1591,7 +1595,7 @@ END IsError ; MakeObject - creates an object node. *) -PROCEDURE MakeObject (name: Name) : CARDINAL ; +PROCEDURE MakeObject (tok: CARDINAL; name: Name) : CARDINAL ; VAR pSym: PtrToSymbol ; Sym : CARDINAL ; @@ -1601,8 +1605,8 @@ BEGIN WITH pSym^ DO SymbolType := ObjectSym ; Object.name := name ; - InitWhereDeclared(Object.At) ; - InitWhereFirstUsed(Object.At) + InitWhereDeclaredTok (tok, Object.At) ; + InitWhereFirstUsedTok (tok, Object.At) END ; RETURN( Sym ) END MakeObject ; @@ -8647,7 +8651,7 @@ BEGIN THEN (* Make unknown *) NewSym (Sym) ; - FillInUnknownFields (tok, Sym, SymName) ; + FillInUnknownFields (tok, Sym, SymName, NulSym, FALSE) ; (* Add to unknown tree *) AddSymToUnknownTree (ScopePtr, SymName, Sym) (* @@ -8684,7 +8688,7 @@ BEGIN THEN (* Make unknown. *) NewSym (Sym) ; - FillInUnknownFields (tok, Sym, SymName) ; + FillInUnknownFields (tok, Sym, SymName, NulSym, FALSE) ; (* Add to unknown tree *) AddSymToUnknownTree (ScopePtr, SymName, Sym) (* @@ -9252,7 +9256,7 @@ BEGIN IF Sym=NulSym THEN NewSym (Sym) ; - FillInUnknownFields (tok, Sym, SymName) ; + FillInUnknownFields (tok, Sym, SymName, ModSym, TRUE) ; PutSymKey (Unresolved, SymName, Sym) END END @@ -9283,7 +9287,7 @@ BEGIN IF Sym=NulSym THEN NewSym(Sym) ; - FillInUnknownFields (tok, Sym, SymName) ; + FillInUnknownFields (tok, Sym, SymName, ModSym, TRUE) ; PutSymKey (Unresolved, SymName, Sym) END END @@ -9310,7 +9314,7 @@ BEGIN IF Sym=NulSym THEN NewSym(Sym) ; - FillInUnknownFields (tok, Sym, SymName) ; + FillInUnknownFields (tok, Sym, SymName, scope, TRUE) ; PutSymKey(Unresolved, SymName, Sym) END END | @@ -9319,7 +9323,7 @@ BEGIN IF Sym=NulSym THEN NewSym(Sym) ; - FillInUnknownFields (tok, Sym, SymName) ; + FillInUnknownFields (tok, Sym, SymName, scope, TRUE) ; PutSymKey(Unresolved, SymName, Sym) END END | @@ -9328,7 +9332,7 @@ BEGIN IF Sym=NulSym THEN NewSym(Sym) ; - FillInUnknownFields (tok, Sym, SymName) ; + FillInUnknownFields (tok, Sym, SymName, NulSym, FALSE) ; PutSymKey(Unresolved, SymName, Sym) END END @@ -9599,7 +9603,8 @@ BEGIN CheckForUnknowns (tokno, name, ExportUnQualifiedTree, 'EXPORT UNQUALIFIED') ; CheckForSymbols (ExportRequest, - 'requested by another modules import (symbols have not been exported by the appropriate definition module)') ; + 'requested by another module import' + + ' and the symbol has not been exported by the appropriate definition module') ; CheckForUnknowns (tokno, name, Unresolved, 'unresolved') ; CheckForUnknowns (tokno, name, LocalSymbols, 'locally used') END | @@ -9752,12 +9757,12 @@ PROCEDURE CheckForSymbols (Tree: SymbolTree; a: ARRAY OF CHAR) ; VAR s: String ; BEGIN - IF NOT IsEmptyTree(Tree) + IF DoesTreeContainAny (Tree, IsUnreportedUnknown) THEN s := InitString ("the symbols are unknown at the end of module {%1Ea} when ") ; s := ConCat (s, Mark(InitString(a))) ; MetaErrorString1 (s, MainModule) ; - ForeachNodeDo(Tree, SymbolError) + ForeachNodeDo (Tree, SymbolError) END END CheckForSymbols ; @@ -11708,10 +11713,11 @@ END IsProcedureAnyNoReturn ; (* - FillInUnknownFields - + FillInUnknownFields - fills in all fields for the undefined sym. *) -PROCEDURE FillInUnknownFields (tok: CARDINAL; sym: CARDINAL; SymName: Name) ; +PROCEDURE FillInUnknownFields (tok: CARDINAL; sym: CARDINAL; SymName: Name; + descscope: CARDINAL; onimport: BOOLEAN) ; VAR pSym: PtrToSymbol ; BEGIN @@ -11722,6 +11728,8 @@ BEGIN name := SymName ; oafamily := NulSym ; errorScope := GetCurrentErrorScope () ; + declScope := descscope ; + onImport := onimport ; InitWhereFirstUsedTok (tok, At) END END @@ -11729,6 +11737,34 @@ END FillInUnknownFields ; (* + GetUnknownOnImport - returns the onimport field of unknown sym. +*) + +PROCEDURE GetUnknownOnImport (sym: CARDINAL) : BOOLEAN ; +VAR + pSym: PtrToSymbol ; +BEGIN + Assert (IsUnknown (sym)) ; + pSym := GetPsym (sym) ; + RETURN pSym^.Undefined.onImport +END GetUnknownOnImport ; + + +(* + GetUnknownDeclScope - returns the decl scope of unknown sym. +*) + +PROCEDURE GetUnknownDeclScope (sym: CARDINAL) : CARDINAL ; +VAR + pSym: PtrToSymbol ; +BEGIN + Assert (IsUnknown (sym)) ; + pSym := GetPsym (sym) ; + RETURN pSym^.Undefined.declScope +END GetUnknownDeclScope ; + + +(* FillInPointerFields - given a new symbol, sym, make it a pointer symbol and initialize its fields. *) @@ -12985,7 +13021,7 @@ END AddNameTo ; current scope. *) -PROCEDURE AddNameToScope (n: Name) ; +PROCEDURE AddNameToScope (tok: CARDINAL; n: Name) ; VAR pSym : PtrToSymbol ; scope: CARDINAL ; @@ -12995,9 +13031,9 @@ BEGIN WITH pSym^ DO CASE SymbolType OF - ProcedureSym: AddNameTo(Procedure.NamedObjects, MakeObject(n)) | - ModuleSym : AddNameTo(Module.NamedObjects, MakeObject(n)) | - DefImpSym : AddNameTo(DefImp.NamedObjects, MakeObject(n)) + ProcedureSym: AddNameTo(Procedure.NamedObjects, MakeObject (tok, n)) | + ModuleSym : AddNameTo(Module.NamedObjects, MakeObject (tok, n)) | + DefImpSym : AddNameTo(DefImp.NamedObjects, MakeObject (tok, n)) ELSE InternalError ('expecting - DefImp') @@ -13011,7 +13047,7 @@ END AddNameToScope ; module. *) -PROCEDURE AddNameToImportList (n: Name) ; +PROCEDURE AddNameToImportList (tok: CARDINAL; n: Name) ; VAR pSym : PtrToSymbol ; scope: CARDINAL ; @@ -13021,8 +13057,8 @@ BEGIN WITH pSym^ DO CASE SymbolType OF - ModuleSym: AddNameTo(Module.NamedImports, MakeObject(n)) | - DefImpSym: AddNameTo(DefImp.NamedImports, MakeObject(n)) + ModuleSym: AddNameTo (Module.NamedImports, MakeObject (tok, n)) | + DefImpSym: AddNameTo (DefImp.NamedImports, MakeObject (tok, n)) ELSE InternalError ('expecting - DefImp or Module symbol') diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index c4de035..989cf9c 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -3673,6 +3673,63 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, && GET_MODE_CLASS (mode) != MODE_CC) return CONSTM1_RTX (mode); + /* IOR of two single bit bitfields extracted from the same object. + Bitfields are represented as an AND based extraction */ + if (GET_CODE (op0) == AND + && GET_CODE (op1) == AND + /* Verify both AND operands are logical right shifts. */ + && GET_CODE (XEXP (op0, 0)) == LSHIFTRT + && GET_CODE (XEXP (op1, 0)) == LSHIFTRT + /* Verify both bitfields are extracted from the same object. */ + && XEXP (XEXP (op0, 0), 0) == XEXP (XEXP (op1, 0), 0) + /* Verify both fields are a single bit (could be generalized). */ + && XEXP (op0, 1) == CONST1_RTX (mode) + && XEXP (op1, 1) == CONST1_RTX (mode) + /* Verify bit positions (for cases with variable bit position). */ + && CONST_INT_P (XEXP (op0, 1)) + && CONST_INT_P (XEXP (op1, 1))) + { + unsigned HOST_WIDE_INT bitpos1 = INTVAL (XEXP (XEXP (op0, 0), 1)); + unsigned HOST_WIDE_INT bitpos2 = INTVAL (XEXP (XEXP (op1, 0), 1)); + unsigned HOST_WIDE_INT mask + = (HOST_WIDE_INT_1U << bitpos1) | (HOST_WIDE_INT_1U << bitpos2); + + rtx m = GEN_INT (mask); + rtx t = gen_rtx_AND (mode, XEXP (XEXP (op0, 0), 0), m); + t = gen_rtx_NE (mode, t, CONST0_RTX (mode)); + return t; + } + + /* IOR of multiple single bit bitfields extracted from the same object + (building on previous case). + First bitfield is represented as an AND based extraction, as done + above. Second represented as NE based extraction, from + output above. */ + if (GET_CODE (op0) == AND + && GET_CODE (op1) == NE + /* Verify AND operand is logical right shift. */ + && GET_CODE (XEXP (op0, 0)) == LSHIFTRT + /* Verify NE operand is an AND (based on output above). */ + && GET_CODE (XEXP (op1, 0)) == AND + /* Verify both bitfields are extracted from the same object. */ + && XEXP (XEXP (op0, 0), 0) == XEXP (XEXP (op1, 0), 0) + /* Verify masking is with a single bit and that we have a NE 0 + comparison for the other operand. */ + && XEXP (op0, 1) == CONST1_RTX (mode) + && XEXP (op1, 1) == CONST0_RTX (mode) + /* Verify bit position. */ + && CONST_INT_P (XEXP (op0, 1))) + { + unsigned HOST_WIDE_INT bitpos1 = INTVAL (XEXP (XEXP (op0, 0), 1)); + unsigned HOST_WIDE_INT mask + = (HOST_WIDE_INT_1U << bitpos1) | INTVAL (XEXP (XEXP (op1, 0), 1)); + + rtx m = GEN_INT (mask); + rtx t = gen_rtx_AND (mode, XEXP (XEXP (op0, 0), 0), m); + t = gen_rtx_NE (mode, t, CONST0_RTX (mode)); + return t; + } + /* Convert (ior (plus (A - 1)) (neg A)) to -1. */ if (match_plus_neg_pattern (op0, op1, mode)) return CONSTM1_RTX (mode); @@ -6394,6 +6451,21 @@ simplify_context::simplify_relational_operation_1 (rtx_code code, /* Canonicalize (LEU x 0) as (EQ x 0). */ if (code == LEU) return simplify_gen_relational (EQ, mode, cmp_mode, op0, op1); + + if ((code == NE || code == EQ) + /* Verify op0 is IOR */ + && GET_CODE (op0) == IOR + /* only enters if op1 is 0 */ + /* Verify IOR operand is NE */ + && GET_CODE (XEXP (op0, 0)) == NE + /* Verfiy second NE operand is 0 */ + && XEXP (XEXP (op0, 0), 1) == CONST0_RTX (mode)) + { + rtx t = gen_rtx_IOR (mode, XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)); + t = gen_rtx_fmt_ee (code, mode, t, CONST0_RTX (mode)); + return t; + } + } else if (op1 == const1_rtx) { diff --git a/gcc/ssa-iterators.h b/gcc/ssa-iterators.h index 03d701c..0822a98 100644 --- a/gcc/ssa-iterators.h +++ b/gcc/ssa-iterators.h @@ -36,25 +36,17 @@ along with GCC; see the file COPYING3. If not see base for a circular list, and initially this is the only node in the list. - Fast iteration allows each use to be examined, but does not allow - any modifications to the uses or stmts. - - Normal iteration allows insertion, deletion, and modification. the - iterator manages this by inserting a marker node into the list - immediately before the node currently being examined in the list. - this marker node is uniquely identified by having null stmt *and* a - null use pointer. - - When iterating to the next use, the iteration routines check to see - if the node after the marker has changed. if it has, then the node - following the marker is now the next one to be visited. if not, the - marker node is moved past that node in the list (visualize it as - bumping the marker node through the list). this continues until - the marker node is moved to the original anchor position. the - marker node is then removed from the list. - - If iteration is halted early, the marker node must be removed from - the list before continuing. */ + Fast iteration via FOR_EACH_IMM_USE_FAST allows each use to be + examined, but does not allow any modifications to the uses or stmts. + + Safe iteration via FOR_EACH_IMM_USE_STMT and FOR_EACH_IMM_USE_ON_STMT + allows insertion, deletion, and modification of SSA operands within + the current stmt iterated. The iterator manages this by re-sorting + the immediate uses to batch uses on a single stmt after each other + and inserts a marker node into the list immediately after the node + ending the current batch. This marker node is uniquely identified by + having null stmt *and* a null use pointer. */ + struct imm_use_iterator { /* This is the current use the iterator is processing. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 013121d..452c9c9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,89 @@ +2025-11-02 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/122499 + * gm2.dg/spell/iso/fail/badimport2.mod: New test. + * gm2.dg/spell/iso/fail/badimport3.mod: New test. + * gm2.dg/spell/iso/fail/badimport4.mod: New test. + +2025-11-02 Eric Botcazou <ebotcazou@adacore.com> + + * gcc.target/sparc/small-struct-1.c: Run only on Solaris. + +2025-11-02 Eric Botcazou <ebotcazou@adacore.com> + + * gcc.target/sparc/cbcond-1.c: Accept reverse branches. + * gcc.target/sparc/cbcond-2.c: Likewise. + * gcc.target/sparc/overflow-3.c: Likewise. + * gcc.target/sparc/overflow-4.c: Likewise. + * gcc.target/sparc/overflow-5.c: Likewise. + +2025-11-02 Uros Bizjak <ubizjak@gmail.com> + + PR target/122518 + * gcc.target/i386/pr122518.c: New test. + +2025-11-02 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/specs/unknown_discr1.ads: New test. + * gnat.dg/specs/unknown_discr1_pkg.ads: New helper. + * gnat.dg/specs/unknown_discr1_pkg-child.ads: Likewise. + * gnat.dg/specs/unknown_discr1_pkg-g.ads: Likewise. + * gnat.dg/specs/unknown_discr1_pkg-inst.ads: Likewise. + +2025-11-02 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/use_type4.adb: New test. + +2025-11-02 Georg-Johann Lay <avr@gjlay.de> + + * gcc.target/avr/torture/pr84211-fuse-move-1.c: Add -fno-lto. + +2025-11-02 Nathaniel Shead <nathanieloshead@gmail.com> + + PR c++/122421 + * g++.dg/modules/inst-6_a.C: New test. + * g++.dg/modules/inst-6_b.C: New test. + +2025-11-01 Shreya Munnangi <smunnangi1@ventanamicro.com> + + PR target/67731 + * gcc.target/riscv/pr67731.c: New test. + * gcc.target/sh/pr67731.c: New test. + +2025-11-01 Jeff Law <jlaw@ventanamicro.com> + + PR rtl-optimization/122321 + * gcc.target/riscv/rvv/autovec/pr122321.c: New test. + +2025-11-01 Harald Anlauf <anlauf@gmx.de> + + PR fortran/78640 + * gfortran.dg/pure_result.f90: New test. + +2025-11-01 Nathaniel Shead <nathanieloshead@gmail.com> + + PR c++/122381 + * g++.dg/modules/convop-2_a.H: New test. + * g++.dg/modules/convop-2_b.C: New test. + +2025-11-01 Martin Uecker <uecker@tugraz.at> + + * gcc.dg/gnu-compoundlit-1.c: New test. + * gcc.dg/gnu-compoundlit-2.c: New test. + * gcc.dg/pr68090.c: Adapt. + * gcc.dg/vla-init-4.c: Adapt. + * gcc.dg/vla-init-5.c: Adapt. + +2025-11-01 Martin Uecker <uecker@tugraz.at> + + PR c/97986 + * gcc.dg/pr97986-1.c: New test. + * gcc.dg/pr97986-2.c: New test. + +2025-11-01 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * gcc.dg/fold-vecperm-1.c: Test at forwprop3. + 2025-10-31 Tamar Christina <tamar.christina@arm.com> PR target/121853 diff --git a/gcc/testsuite/g++.dg/modules/inst-6_a.C b/gcc/testsuite/g++.dg/modules/inst-6_a.C new file mode 100644 index 0000000..7f35cc1 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/inst-6_a.C @@ -0,0 +1,14 @@ +// PR c++/122421 +// { dg-additional-options "-fmodules" } +// { dg-module-cmi M } + +export module M; + +export template <typename T> struct Type { + static const int arr[3]; +}; + +extern template const int Type<double>::arr[3]; +template <typename T> const int Type<T>::arr[] = { 42, 43, 44 }; + +export Type<int> ti; diff --git a/gcc/testsuite/g++.dg/modules/inst-6_b.C b/gcc/testsuite/g++.dg/modules/inst-6_b.C new file mode 100644 index 0000000..5a8092c --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/inst-6_b.C @@ -0,0 +1,12 @@ +// PR c++/122421 +// { dg-additional-options "-fmodules" } + +import M; + +int main() { + const int& a = Type<int>::arr[0]; + const int& b = Type<double>::arr[0]; +} + +// { dg-final { scan-assembler {_ZNW1M4TypeIiE3arrE:} } } +// { dg-final { scan-assembler-not {_ZNW1M4TypeIdE3arrE:} } } diff --git a/gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-1.c b/gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-1.c index 82ce227..4924e9d 100644 --- a/gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-1.c +++ b/gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-additional-options -std=gnu99 } */ +/* Disable LTO since it has problems with flobal asm. */ +/* { dg-additional-options { -std=gnu99 -fno-lto } } */ #define USE_VALUE 0 diff --git a/gcc/testsuite/gcc.target/i386/pr122518.c b/gcc/testsuite/gcc.target/i386/pr122518.c new file mode 100644 index 0000000..2791889 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr122518.c @@ -0,0 +1,15 @@ +/* PR target/122518 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +inline unsigned min (unsigned a, unsigned b) +{ + return (a < b) ? a : b; +} + +unsigned uminsub (unsigned a, unsigned b) +{ + return min (a - b, a); +} + +/* { dg-final { scan-assembler-not "cmp" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/imm-load.c b/gcc/testsuite/gcc.target/loongarch/imm-load.c index 33291fe..a125840 100644 --- a/gcc/testsuite/gcc.target/loongarch/imm-load.c +++ b/gcc/testsuite/gcc.target/loongarch/imm-load.c @@ -7,5 +7,5 @@ test (void) { return 0x1234567890abcdef; } -/* { dg-final { scan-rtl-dump-times "scanning new insn with uid" 6 "split1" } } */ +/* { dg-final { scan-rtl-dump-times "scanning new insn with uid" 4 "split1" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-concat-128-256-result.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-concat-128-256-result.c new file mode 100644 index 0000000..e876c4a --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-concat-128-256-result.c @@ -0,0 +1,68 @@ +/* { dg-options "-mabi=lp64d -O2 -mlasx -w -fno-strict-aliasing" } */ + +#include "../simd_correctness_check.h" +#include <lasxintrin.h> + +int +main () +{ + __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; + __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; + __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; + + __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; + __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; + __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; + + //__m128_op0={1,2,3,4},__m128_op1={5,6,7,8}; + *((int *)&__m128_op0[3]) = 0x40800000; + *((int *)&__m128_op0[2]) = 0x40400000; + *((int *)&__m128_op0[1]) = 0x40000000; + *((int *)&__m128_op0[0]) = 0x3f800000; + *((int *)&__m128_op1[3]) = 0x41000000; + *((int *)&__m128_op1[2]) = 0x40e00000; + *((int *)&__m128_op1[1]) = 0x40c00000; + *((int *)&__m128_op1[0]) = 0x40a00000; + *((int *)&__m256_result[7]) = 0x41000000; + *((int *)&__m256_result[6]) = 0x40e00000; + *((int *)&__m256_result[5]) = 0x40c00000; + *((int *)&__m256_result[4]) = 0x40a00000; + *((int *)&__m256_result[3]) = 0x40800000; + *((int *)&__m256_result[2]) = 0x40400000; + *((int *)&__m256_result[1]) = 0x40000000; + *((int *)&__m256_result[0]) = 0x3f800000; + __m256_out = __lasx_concat_128_s (__m128_op0, __m128_op1); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); + __m256_out = __lasx_cast_128_s (__m128_op0); + ASSERTEQ_32 (__LINE__, __m256_out, __m128_op0); + + //__m128i_op0={1,2},__m128i_op1={3,4}; + *((unsigned long *)&__m128i_op0[1]) = 0x2; + *((unsigned long *)&__m128i_op0[0]) = 0x1; + *((unsigned long *)&__m128i_op1[1]) = 0x4; + *((unsigned long *)&__m128i_op1[0]) = 0x3; + *((unsigned long *)&__m256i_result[3]) = 0x4; + *((unsigned long *)&__m256i_result[2]) = 0x3; + *((unsigned long *)&__m256i_result[1]) = 0x2; + *((unsigned long *)&__m256i_result[0]) = 0x1; + __m256i_out = __lasx_concat_128 (__m128i_op0, __m128i_op1); + ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); + __m256i_out = __lasx_cast_128 (__m128i_op0); + ASSERTEQ_64 (__LINE__, __m256i_out, __m128i_op0); + + //__m128d_op0={1,2},__m128i_op1={3,4}; + *((unsigned long *)&__m128d_op0[1]) = 0x4000000000000000; + *((unsigned long *)&__m128d_op0[0]) = 0x3ff0000000000000; + *((unsigned long *)&__m128d_op1[1]) = 0x4010000000000000; + *((unsigned long *)&__m128d_op1[0]) = 0x4008000000000000; + *((unsigned long *)&__m256d_result[3]) = 0x4010000000000000; + *((unsigned long *)&__m256d_result[2]) = 0x4008000000000000; + *((unsigned long *)&__m256d_result[1]) = 0x4000000000000000; + *((unsigned long *)&__m256d_result[0]) = 0x3ff0000000000000; + __m256d_out = __lasx_concat_128_d (__m128d_op0, __m128d_op1); + ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); + __m256d_out = __lasx_cast_128_d (__m128d_op0); + ASSERTEQ_64 (__LINE__, __m256d_out, __m128d_op0); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-concat-128-256.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-concat-128-256.c new file mode 100644 index 0000000..5d8cbb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-concat-128-256.c @@ -0,0 +1,92 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-mabi=lp64d -O2 -mlasx" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <lasxintrin.h> + +/* +**foo1: +** vinsgr2vr.d (\$vr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r6,1 +** vinsgr2vr.d (\$vr[0-9]+),\$r8,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x02 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256 +foo1 (__m128 x, __m128 y) +{ + return __builtin_lasx_concat_128_s (x, y); +} + +/* +**foo2: +** vinsgr2vr.d (\$vr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r6,1 +** vinsgr2vr.d (\$vr[0-9]+),\$r8,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x02 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256d +foo2 (__m128d x, __m128d y) +{ + return __builtin_lasx_concat_128_d (x, y); +} + +/* +**foo3: +** vinsgr2vr.d (\$vr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r6,1 +** vinsgr2vr.d (\$vr[0-9]+),\$r8,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x02 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256i +foo3 (__m128i x, __m128i y) +{ + return __builtin_lasx_concat_128 (x, y); +} + +/* +**foo4: +** vinsgr2vr.d (\$vr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r6,1 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256 +foo4 (__m128 x) +{ + return __builtin_lasx_cast_128_s (x); +} + +/* +**foo5: +** vinsgr2vr.d (\$vr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r6,1 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256d +foo5 (__m128d x) +{ + return __builtin_lasx_cast_128_d (x); +} + +/* +**foo6: +** vinsgr2vr.d (\$vr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r6,1 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256i +foo6 (__m128i x) +{ + return __builtin_lasx_cast_128 (x); +} diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-extract-256-128-result.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-extract-256-128-result.c new file mode 100644 index 0000000..61064d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-extract-256-128-result.c @@ -0,0 +1,69 @@ +/* { dg-options "-mabi=lp64d -O2 -mlasx -w -fno-strict-aliasing" } */ + +#include "../simd_correctness_check.h" +#include <lasxintrin.h> + +extern void abort (void); +int +main () +{ + __m128i __m128i_result0, __m128i_result1, __m128i_out, __m128i_result; + __m128 __m128_result0, __m128_result1, __m128_out, __m128_result; + __m128d __m128d_result0, __m128d_result1, __m128d_out, __m128d_result; + + __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; + __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; + __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; + + //__m256_op0 = {1,2,3,4,5,6,7,8}; + *((int *)&__m256_op0[7]) = 0x41000000; + *((int *)&__m256_op0[6]) = 0x40e00000; + *((int *)&__m256_op0[5]) = 0x40c00000; + *((int *)&__m256_op0[4]) = 0x40a00000; + *((int *)&__m256_op0[3]) = 0x40800000; + *((int *)&__m256_op0[2]) = 0x40400000; + *((int *)&__m256_op0[1]) = 0x40000000; + *((int *)&__m256_op0[0]) = 0x3f800000; + *((int *)&__m128_result1[3]) = 0x41000000; + *((int *)&__m128_result1[2]) = 0x40e00000; + *((int *)&__m128_result1[1]) = 0x40c00000; + *((int *)&__m128_result1[0]) = 0x40a00000; + *((int *)&__m128_result0[3]) = 0x40800000; + *((int *)&__m128_result0[2]) = 0x40400000; + *((int *)&__m128_result0[1]) = 0x40000000; + *((int *)&__m128_result0[0]) = 0x3f800000; + __m128_out = __lasx_extract_128_lo_s (__m256_op0); + ASSERTEQ_32 (__LINE__, __m128_result0, __m128_out); + __m128_out = __lasx_extract_128_hi_s (__m256_op0); + ASSERTEQ_32 (__LINE__, __m128_result1, __m128_out); + + //__m256i_op0 = {1,2,3,4}; + *((unsigned long *)&__m256i_op0[3]) = 0x4; + *((unsigned long *)&__m256i_op0[2]) = 0x3; + *((unsigned long *)&__m256i_op0[1]) = 0x2; + *((unsigned long *)&__m256i_op0[0]) = 0x1; + *((unsigned long *)&__m128i_result0[1]) = 0x2; + *((unsigned long *)&__m128i_result0[0]) = 0x1; + *((unsigned long *)&__m128i_result1[1]) = 0x4; + *((unsigned long *)&__m128i_result1[0]) = 0x3; + __m128i_out = __lasx_extract_128_lo (__m256i_op0); + ASSERTEQ_64 (__LINE__, __m128i_result0, __m128i_out); + __m128i_out = __lasx_extract_128_hi (__m256i_op0); + ASSERTEQ_64 (__LINE__, __m128i_result1, __m128i_out); + + //__m256d_op0 = {1,2,3,4}; + *((unsigned long *)&__m256d_op0[3]) = 0x4010000000000000; + *((unsigned long *)&__m256d_op0[2]) = 0x4008000000000000; + *((unsigned long *)&__m256d_op0[1]) = 0x4000000000000000; + *((unsigned long *)&__m256d_op0[0]) = 0x3ff0000000000000; + *((unsigned long *)&__m128d_result0[1]) = 0x4000000000000000; + *((unsigned long *)&__m128d_result0[0]) = 0x3ff0000000000000; + *((unsigned long *)&__m128d_result1[1]) = 0x4010000000000000; + *((unsigned long *)&__m128d_result1[0]) = 0x4008000000000000; + __m128d_out = __lasx_extract_128_lo_d (__m256d_op0); + ASSERTEQ_64 (__LINE__, __m128d_result0, __m128d_out); + __m128d_out = __lasx_extract_128_hi_d (__m256d_op0); + ASSERTEQ_64 (__LINE__, __m128d_result1, __m128d_out); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-extract-256-128.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-extract-256-128.c new file mode 100644 index 0000000..d2219ea --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-extract-256-128.c @@ -0,0 +1,86 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-mabi=lp64d -O2 -mlasx" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <lasxintrin.h> + +/* +**foo1_lo: +** vld (\$vr[0-9]+),\$r4,0 +** vpickve2gr.du \$r4,(\$vr[0-9]+),0 +** vpickve2gr.du \$r5,(\$vr[0-9]+),1 +** jr \$r1 +*/ +__m128 +foo1_lo (__m256 x) +{ + return __lasx_extract_128_lo_s (x); +} + +/* +**foo1_hi: +** xvld (\$xr[0-9]+),\$r4,0 +** xvpermi.d (\$xr[0-9]+),(\$xr[0-9]+),0xe +** vpickve2gr.du \$r4,(\$vr[0-9]+),0 +** vpickve2gr.du \$r5,(\$vr[0-9]+),1 +** jr \$r1 +*/ +__m128 +foo1_hi (__m256 x) +{ + return __lasx_extract_128_hi_s (x); +} + +/* +**foo2_lo: +** vld (\$vr[0-9]+),\$r4,0 +** vpickve2gr.du \$r4,(\$vr[0-9]+),0 +** vpickve2gr.du \$r5,(\$vr[0-9]+),1 +** jr \$r1 +*/ +__m128d +foo2_lo (__m256d x) +{ + return __lasx_extract_128_lo_d (x); +} + +/* +**foo2_hi: +** xvld (\$xr[0-9]+),\$r4,0 +** xvpermi.d (\$xr[0-9]+),(\$xr[0-9]+),0xe +** vpickve2gr.du \$r4,(\$vr[0-9]+),0 +** vpickve2gr.du \$r5,(\$vr[0-9]+),1 +** jr \$r1 +*/ +__m128d +foo2_hi (__m256d x) +{ + return __lasx_extract_128_hi_d (x); +} + +/* +**foo3_lo: +** vld (\$vr[0-9]+),\$r4,0 +** vpickve2gr.du \$r4,(\$vr[0-9]+),0 +** vpickve2gr.du \$r5,(\$vr[0-9]+),1 +** jr \$r1 +*/ +__m128i +foo3_lo (__m256i x) +{ + return __lasx_extract_128_lo (x); +} + +/* +**foo3_hi: +** xvld (\$xr[0-9]+),\$r4,0 +** xvpermi.d (\$xr[0-9]+),(\$xr[0-9]+),0xe +** vpickve2gr.du \$r4,(\$vr[0-9]+),0 +** vpickve2gr.du \$r5,(\$vr[0-9]+),1 +** jr \$r1 +*/ +__m128i +foo3_hi (__m256i x) +{ + return __lasx_extract_128_hi (x); +} diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-insert-128-256-result.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-insert-128-256-result.c new file mode 100644 index 0000000..ce5abf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-insert-128-256-result.c @@ -0,0 +1,97 @@ +/* { dg-options "-mabi=lp64d -O2 -mlasx -w -fno-strict-aliasing" } */ + +#include "../simd_correctness_check.h" +#include <lasxintrin.h> + +extern void abort (void); +int +main () +{ + __m128i __m128i_op0, __m128i_op1, __m128i_out; + __m128 __m128_op0, __m128_op1, __m128_out; + __m128d __m128d_op0, __m128d_op1, __m128d_out; + + __m256i __m256i_op0, __m256i_result0, __m256i_result1, __m256i_out; + __m256 __m256_op0, __m256_result0, __m256_result1, __m256_out; + __m256d __m256d_op0, __m256d_result0, __m256d_result1, __m256d_out; + + //__m256_op0 = {1,2,3,4,5,6,7,8}, __m128_op0 ={9,9,9,9}; + *((int *)&__m256_op0[7]) = 0x41000000; + *((int *)&__m256_op0[6]) = 0x40e00000; + *((int *)&__m256_op0[5]) = 0x40c00000; + *((int *)&__m256_op0[4]) = 0x40a00000; + *((int *)&__m256_op0[3]) = 0x40800000; + *((int *)&__m256_op0[2]) = 0x40400000; + *((int *)&__m256_op0[1]) = 0x40000000; + *((int *)&__m256_op0[0]) = 0x3f800000; + *((int *)&__m128_op0[3]) = 0x41100000; + *((int *)&__m128_op0[2]) = 0x41100000; + *((int *)&__m128_op0[1]) = 0x41100000; + *((int *)&__m128_op0[0]) = 0x41100000; + *((int *)&__m256_result0[7]) = 0x41000000; + *((int *)&__m256_result0[6]) = 0x40e00000; + *((int *)&__m256_result0[5]) = 0x40c00000; + *((int *)&__m256_result0[4]) = 0x40a00000; + *((int *)&__m256_result0[3]) = 0x41100000; + *((int *)&__m256_result0[2]) = 0x41100000; + *((int *)&__m256_result0[1]) = 0x41100000; + *((int *)&__m256_result0[0]) = 0x41100000; + *((int *)&__m256_result1[7]) = 0x41100000; + *((int *)&__m256_result1[6]) = 0x41100000; + *((int *)&__m256_result1[5]) = 0x41100000; + *((int *)&__m256_result1[4]) = 0x41100000; + *((int *)&__m256_result1[3]) = 0x40800000; + *((int *)&__m256_result1[2]) = 0x40400000; + *((int *)&__m256_result1[1]) = 0x40000000; + *((int *)&__m256_result1[0]) = 0x3f800000; + __m256_out = __lasx_insert_128_lo_s (__m256_op0, __m128_op0); + ASSERTEQ_32 (__LINE__, __m256_result0, __m256_out); + __m256_out = __lasx_insert_128_hi_s (__m256_op0, __m128_op0); + ASSERTEQ_32 (__LINE__, __m256_result1, __m256_out); + + //__m256i_op0 ={1,2,3,4},__m128i_op0={5,6},__m128i_op1={7,8}; + *((unsigned long *)&__m256i_op0[3]) = 0x4; + *((unsigned long *)&__m256i_op0[2]) = 0x3; + *((unsigned long *)&__m256i_op0[1]) = 0x2; + *((unsigned long *)&__m256i_op0[0]) = 0x1; + *((unsigned long *)&__m128i_op0[1]) = 0x6; + *((unsigned long *)&__m128i_op0[0]) = 0x5; + *((unsigned long *)&__m128i_op1[1]) = 0x8; + *((unsigned long *)&__m128i_op1[0]) = 0x7; + *((unsigned long *)&__m256i_result0[3]) = 0x4; + *((unsigned long *)&__m256i_result0[2]) = 0x3; + *((unsigned long *)&__m256i_result0[1]) = 0x6; + *((unsigned long *)&__m256i_result0[0]) = 0x5; + *((unsigned long *)&__m256i_result1[3]) = 0x8; + *((unsigned long *)&__m256i_result1[2]) = 0x7; + *((unsigned long *)&__m256i_result1[1]) = 0x2; + *((unsigned long *)&__m256i_result1[0]) = 0x1; + __m256i_out = __lasx_insert_128_lo (__m256i_op0, __m128i_op0); + ASSERTEQ_64 (__LINE__, __m256i_result0, __m256i_out); + __m256i_out = __lasx_insert_128_hi (__m256i_op0, __m128i_op1); + ASSERTEQ_64 (__LINE__, __m256i_result1, __m256i_out); + + //__m256d_op0 ={1,2,3,4},__m128d_op0={5,6},__m128d_op1={7,8}; + *((unsigned long *)&__m256d_op0[3]) = 0x4010000000000000; + *((unsigned long *)&__m256d_op0[2]) = 0x4008000000000000; + *((unsigned long *)&__m256d_op0[1]) = 0x4000000000000000; + *((unsigned long *)&__m256d_op0[0]) = 0x3ff0000000000000; + *((unsigned long *)&__m128d_op0[1]) = 0x4018000000000000; + *((unsigned long *)&__m128d_op0[0]) = 0x4014000000000000; + *((unsigned long *)&__m128d_op1[1]) = 0x4020000000000000; + *((unsigned long *)&__m128d_op1[0]) = 0x401c000000000000; + *((unsigned long *)&__m256d_result0[3]) = 0x4010000000000000; + *((unsigned long *)&__m256d_result0[2]) = 0x4008000000000000; + *((unsigned long *)&__m256d_result0[1]) = 0x4018000000000000; + *((unsigned long *)&__m256d_result0[0]) = 0x4014000000000000; + *((unsigned long *)&__m256d_result1[3]) = 0x4020000000000000; + *((unsigned long *)&__m256d_result1[2]) = 0x401c000000000000; + *((unsigned long *)&__m256d_result1[1]) = 0x4000000000000000; + *((unsigned long *)&__m256d_result1[0]) = 0x3ff0000000000000; + __m256d_out = __lasx_insert_128_lo_d (__m256d_op0, __m128d_op0); + ASSERTEQ_64 (__LINE__, __m256d_result0, __m256d_out); + __m256d_out = __lasx_insert_128_hi_d (__m256d_op0, __m128d_op1); + ASSERTEQ_64 (__LINE__, __m256d_result1, __m256d_out); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-insert-128-256.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-insert-128-256.c new file mode 100644 index 0000000..326c855 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-insert-128-256.c @@ -0,0 +1,95 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-mabi=lp64d -O2 -mlasx" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <lasxintrin.h> + +/* +**foo1: +** vinsgr2vr.d (\$vr[0-9]+),\$r6,0 +** xvld (\$xr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x30 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256 +foo1 (__m256 x, __m128 y) +{ + return __builtin_lasx_insert_128_lo_s (x, y); +} + +/* +**foo2: +** vinsgr2vr.d (\$vr[0-9]+),\$r6,0 +** xvld (\$xr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x02 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256 +foo2 (__m256 x, __m128 y) +{ + return __builtin_lasx_insert_128_hi_s (x, y); +} + +/* +**foo3: +** vinsgr2vr.d (\$vr[0-9]+),\$r6,0 +** xvld (\$xr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x30 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256d +foo3 (__m256d x, __m128d y) +{ + return __builtin_lasx_insert_128_lo_d (x, y); +} + +/* +**foo4: +** vinsgr2vr.d (\$vr[0-9]+),\$r6,0 +** xvld (\$xr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x02 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256d +foo4 (__m256d x, __m128d y) +{ + return __builtin_lasx_insert_128_hi_d (x, y); +} + +/* +**foo5: +** vinsgr2vr.d (\$vr[0-9]+),\$r6,0 +** xvld (\$xr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x30 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256i +foo5 (__m256i x, __m128i y) +{ + return __builtin_lasx_insert_128_lo (x, y); +} + +/* +**foo6: +** vinsgr2vr.d (\$vr[0-9]+),\$r6,0 +** xvld (\$xr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x02 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256i +foo6 (__m256i x, __m128i y) +{ + return __builtin_lasx_insert_128_hi (x, y); +} diff --git a/gcc/testsuite/gcc.target/riscv/pr52345.c b/gcc/testsuite/gcc.target/riscv/pr52345.c new file mode 100644 index 0000000..90feb91 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr52345.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gcbv_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-O2 -march=rv32gcbv_zicond -mabi=ilp32" { target { rv32 } } } */ + +int f(int a, int b) +{ + int c = a != 0; + int d = (c!=0|b!=0); + return d; +} + +int h (int a, int b) +{ + int c = (a!=0|b); + int d = c==0; + return d; +} + +/* { dg-final { scan-assembler-times {\tor} 2 } } */ +/* { dg-final { scan-assembler-times {\tsnez} 1 } } */ +/* { dg-final { scan-assembler-times {\tseqz} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr67731.c b/gcc/testsuite/gcc.target/riscv/pr67731.c new file mode 100644 index 0000000..6f254fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr67731.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gcbv -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-O2 -march=rv32gcbv -mabi=ilp32" { target { rv32 } } } */ + +typedef struct +{ + _Bool a : 1; + _Bool b : 1; + _Bool c : 1; + _Bool d : 1; + unsigned int e : 4; +} S; + +_Bool test_00 (S* s) +{ + return s->b | s->c; +} + +_Bool test_01 (S* s) +{ + return s->b | s->c | s->d; +} +/* { dg-final { scan-assembler-times {\tlw\ta0,0\(a0\).*?\n\tandi\ta0,a0,\d+.*?\n\tsnez\ta0,a0.*?\n\tret} 2 } } */ +/* { dg-final { scan-assembler-not {\tor} } } */ +/* { dg-final { scan-assembler-not {\tbexti} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c new file mode 100644 index 0000000..0e34bc1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c @@ -0,0 +1,150 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -w -O0" { target rv64 } } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -w -O0" { target rv32 } } */ + + +typedef int a; +typedef signed char b; +typedef char c; +typedef short d; +typedef unsigned short e; +typedef a f; +typedef unsigned g; +typedef long h; +h j, k, l, m, n, o; +int p, q, r, s; +short t; +volatile a u; +a v[]; +char w, x; +a *y, *z; +a **aa; +__attribute__((always_inline)) b __attribute__((vector_size(16))) +ab(f __attribute__((vector_size(8 * sizeof(f)))), d ac, + d __attribute__((vector_size(2 * sizeof(d)))), d) { + return __builtin_shufflevector( + (b __attribute__((vector_size(16)))) __builtin_convertvector( + (d __attribute__((vector_size(16 *sizeof(d))))){ + ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac}, + c __attribute__((vector_size(16)))) | + __builtin_convertvector( + (d __attribute__((vector_size(16 *sizeof(d))))){ + ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac}, + c __attribute__((vector_size(16)))), + __builtin_convertvector( + (d __attribute__((vector_size(16 *sizeof(d))))){ + ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac}, + b __attribute__((vector_size(16)))), + 3, 21, 0, 2, 2, 7, 1, 8, 4, 0, 8, 0, 8, 9, 5, 6); +} +__attribute__((always_inline)) g +ad(d ae, h __attribute__((vector_size(32 * sizeof(h))))) { + g f = 6318; + return (8 ? ae / 786856318u : 0) & ae; +} +a(af)(a, int); +void(ag)(long); +char(ah)(char, char); +char(ai)(char); +short(aj)(short, short); +int ak(long, int *, int *, char, int); +void al(signed, a *, int *, long); +char am(int *, short, short); +void an(int *, long, int); +void ao(int, int *, a *); +a ap() { + int *aq, *ar, *as; + short at; + char au, av, aw = 2; + long ax, ay, az = j; + int ba, i; + g __attribute__((vector_size(16 * sizeof(g)))) bb = {80}; + b __attribute__((vector_size(4))) bc = {6}; + int bd[1]; + char *be = &w; + int bf, bg = q; + a **bh[] = { + &y, &z, &z, &y, &y, &y, &y, &y, &z, &z, &y, &z, &y, &y, &y, &y, &z, &y, + &z, &y, &y, &y, &z, &z, &z, &y, &z, &z, &z, &y, &z, &z, &y, &z, &z, &y, + &z, &z, &z, &y, 0, &z, 0, &y, 0, &y, &y, &z, &z, &y, &y, 0, &z, 0, + &z, 0, &y, &z, &z, 0, &z, 0, &z, &z, &z, &y, &z, &z, &y, &z, &z, &y, + 0, &z, 0, &z, &z, &y, 0, &z, 0, &y, 0, &y, &y, &z, &z, &y, &y, 0, + &z, 0, &z, 0, &y, &z, &z, 0, &z, 0, &z, &z, &z, &y, &z, &z, &y, &z, + &z, &y, 0, &z, 0, &z, &z, &y, 0, &z, 0, &y, 0, &y, &y, &z, &z, &y, + &y, 0, &z, 0, &z, 0, &y, &z, &z, 0, &z, 0, &z, &z, &z, &y, &z, &z, + &y, &z, &z, &y, 0, &z, 0, &z, &z, &y, 0, &z, 0, &y, 0, &y, &y, &z, + &z, &y, &y, 0, &z, 0, &z, 0, &y, &z, &z, 0, 0, &z, 0, &z, &z, &z, + &y, &z, &z, &y, &z, &z, &y, 0, &z, 0, 0, &z, &z}; + for (; i; i++) + bd[i] = p; + h __attribute__((vector_size(32 * sizeof(h)))) + bi = {2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, + 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, + 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681}, + bj = __builtin_convertvector( + (c __attribute__((vector_size(32)))){ + aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, + aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw}, + h __attribute__((vector_size(32 * sizeof(h))))), + bk = __builtin_convertvector( + __builtin_shufflevector(bb, bb, 4, 8, 7, 9, 1, 10, 4, 7, 0, 4, 3, 5, 6, 7, + 6, 2, 2, 20, 6, 4, 7, 7, 9, 7, 4, 9, 8, 6, 1, 0, + 6, 9), + h __attribute__((vector_size(32 * sizeof(h))))); + bb = __builtin_convertvector( + ab(__builtin_shufflevector( + __builtin_shufflevector( + __builtin_convertvector( + __builtin_shufflevector(bb, bb, 1, 31, 8, 2, 3, 7, 4, 0, 7, + 3, 4, 6, 7, 1, 9, 3, 8, 7, 1, 8, 5, + 3, 9, 9, 0, 3, 2, 8, 5, 2, 5, 3), + f __attribute__((vector_size(32 * sizeof(f))))), + (f __attribute__((vector_size(32 * sizeof(f))))){ + 800761418310502961587690471176286910032020044212442466872080013589354162852207417903424527024812447907811618435019152886919380169872910001752451018659493155196043018716516518746289614523948734758456011127254301274351182132760058399143431214610613191313926994549901191890929084305862034120561651877003645}, + 32, 44), + (f __attribute__((vector_size(2 * sizeof(f))))){o}, 1, 0, 3, 0, 2, + 1, 3, 3), + ad(__builtin_clzg((g)aw, (f)bb[9]), + (h __attribute__((vector_size(32 * sizeof(h))))){ + bi[0] ?: bk[0], bi[1] ? 1 : bk[1], bi[2] ? 2 : bk[2], + bi[3] ? 3 : bk[3], bi[4] ? 4 : bk[4], bi[5] ? 5 : bk[5], + bi[6] ? 6 : bk[6], bi[7] ? 7 : bk[7], bi[8] ? 8 : bk[8], + bi[9] ? 9 : bk[9], bi[0] ? 10 : bk[0], bi[1] ? 1 : bk[1], + bi[2] ? 2 : bk[2], bi[3] ? 3 : bk[3], bi[4] ? 4 : bk[4], + bi[5] ? 5 : bk[5], bi[6] ? 6 : bk[6], bi[7] ? 7 : bk[7], + bi[8] ? 8 : bk[8], bi[9] ? 9 : bk[9], bi[0] ? 20 : bk[0], + bi[1] ? 1 : bk[1], bi[2] ? 2 : bk[2], bi[3] ? 3 : bk[3], + bi[4] ? bj[4] : 4, bi[5] ?: 5, bi[6] ?: 6, + bi[7] ? 0 : 7, bi[8] ?: 8, bi[9] ? 0 : 9, + bi[0] ? 0 : 30, bi[1] ?: 1}), + (d __attribute__((vector_size(2 * sizeof(d))))) + __builtin_shufflevector( + __builtin_convertvector( + __builtin_shufflevector(bb, bb, 2, 7, 21, 6), + e __attribute__((vector_size(4 * sizeof(e))))), + __builtin_convertvector( + (c __attribute__((vector_size(4)))){aw, aw}, + e __attribute__((vector_size(4 * sizeof(e))))), + 5, 1) + + (__builtin_convertvector( + __builtin_shufflevector(bb, bb, 4, 5), + e __attribute__((vector_size(2 * sizeof(e))))) <= + __builtin_convertvector( + (c __attribute__((vector_size(2)))){aw}, + e __attribute__((vector_size(2 * sizeof(e)))))), + n ? bb[5] << n : aw), + g __attribute__((vector_size(16 * sizeof(g))))); + ag(aw & t); + at = aj(aw, v[1]); + au = ah(at, aw); + ba = af((1 == ax != aw) <= aw <= au, aw); + ao(0, &bd[0], &r); + o = ay; + an(aq, aw, k); + av = am(ar, l, k); + *be = ai(*be); + al(x, as, &bd[0], aw); + bg = ak(u, &s, &bf, aw, aw); + as = *aa; + return m; +} diff --git a/gcc/testsuite/gcc.target/sh/pr67731.c b/gcc/testsuite/gcc.target/sh/pr67731.c new file mode 100644 index 0000000..43c1657 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr67731.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -m4 -ml" } */ + +typedef struct +{ + _Bool a : 1; + _Bool b : 1; + _Bool c : 1; + _Bool d : 1; + unsigned int e : 4; +} S; + +_Bool test_00 (S* s) +{ + return s->b | s->c; +} + +_Bool test_01 (S* s) +{ + return s->b | s->c | s->d; +} + +/* { dg-final { scan-assembler-times {\ttst} 2 } } */ +/* { dg-final { scan-assembler-times {\tnegc} 2 } } */ +/* { dg-final { scan-assembler-not {\tor} } } */ diff --git a/gcc/testsuite/gcc.target/sparc/cbcond-1.c b/gcc/testsuite/gcc.target/sparc/cbcond-1.c index 74fe475..742ab1d 100644 --- a/gcc/testsuite/gcc.target/sparc/cbcond-1.c +++ b/gcc/testsuite/gcc.target/sparc/cbcond-1.c @@ -34,5 +34,5 @@ void cbcondle (int a) /* { dg-final { scan-assembler "cwbe\t%" { target ilp32 } } } */ /* { dg-final { scan-assembler "cwbne\t%" { target ilp32 } } } */ -/* { dg-final { scan-assembler "cwbl\t%" } } */ -/* { dg-final { scan-assembler "cwble\t%" } } */ +/* { dg-final { scan-assembler "cwbl|cwbge\t%" } } */ +/* { dg-final { scan-assembler "cwble|cwbg\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/cbcond-2.c b/gcc/testsuite/gcc.target/sparc/cbcond-2.c index da6c617..c55f9e9 100644 --- a/gcc/testsuite/gcc.target/sparc/cbcond-2.c +++ b/gcc/testsuite/gcc.target/sparc/cbcond-2.c @@ -35,5 +35,5 @@ void cbcondle (long a) /* { dg-final { scan-assembler "cxbe\t%" } } */ /* { dg-final { scan-assembler "cxbne\t%" } } */ -/* { dg-final { scan-assembler "cxbl\t%" } } */ -/* { dg-final { scan-assembler "cxble\t%" } } */ +/* { dg-final { scan-assembler "cxbl|cxbge\t%" } } */ +/* { dg-final { scan-assembler "cxble|cxbg\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/overflow-3.c b/gcc/testsuite/gcc.target/sparc/overflow-3.c index 52d6ab2..ce52de0 100644 --- a/gcc/testsuite/gcc.target/sparc/overflow-3.c +++ b/gcc/testsuite/gcc.target/sparc/overflow-3.c @@ -38,6 +38,6 @@ bool my_neg_overflow (int32_t a, int32_t *res) /* { dg-final { scan-assembler-times "addcc\t%" 2 } } */ /* { dg-final { scan-assembler-times "subcc\t%" 4 } } */ /* { dg-final { scan-assembler-times "addx\t%" 3 } } */ -/* { dg-final { scan-assembler-times "bvs" 3 } } */ +/* { dg-final { scan-assembler-times "bvs|bvc" 3 } } */ /* { dg-final { scan-assembler-not "cmp\t%" } } */ /* { dg-final { scan-assembler-not "save\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/overflow-4.c b/gcc/testsuite/gcc.target/sparc/overflow-4.c index c6121b9..2b62edf 100644 --- a/gcc/testsuite/gcc.target/sparc/overflow-4.c +++ b/gcc/testsuite/gcc.target/sparc/overflow-4.c @@ -38,7 +38,7 @@ bool my_neg_overflow (int64_t a, int64_t *res) /* { dg-final { scan-assembler-times "addcc\t%" 2 } } */ /* { dg-final { scan-assembler-times "subcc\t%" 4 } } */ /* { dg-final { scan-assembler-times "movlu\t%" 1 } } */ -/* { dg-final { scan-assembler-times "blu" 2 } } */ -/* { dg-final { scan-assembler-times "bvs" 3 } } */ +/* { dg-final { scan-assembler-times "blu|bgeu" 2 } } */ +/* { dg-final { scan-assembler-times "bvs|bvc" 3 } } */ /* { dg-final { scan-assembler-not "cmp\t%" } } */ /* { dg-final { scan-assembler-not "save\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/overflow-5.c b/gcc/testsuite/gcc.target/sparc/overflow-5.c index f00283f..0459a65 100644 --- a/gcc/testsuite/gcc.target/sparc/overflow-5.c +++ b/gcc/testsuite/gcc.target/sparc/overflow-5.c @@ -38,6 +38,6 @@ bool my_neg_overflow (int64_t a, int64_t *res) /* { dg-final { scan-assembler-times "addcc\t%" 2 } } */ /* { dg-final { scan-assembler-times "subcc\t%" 4 } } */ /* { dg-final { scan-assembler-times "addxc\t%" 3 } } */ -/* { dg-final { scan-assembler-times "bvs" 3 } } */ +/* { dg-final { scan-assembler-times "bvs|bvc" 3 } } */ /* { dg-final { scan-assembler-not "cmp\t%" } } */ /* { dg-final { scan-assembler-not "save\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/small-struct-1.c b/gcc/testsuite/gcc.target/sparc/small-struct-1.c index 4897288..1ceccd5 100644 --- a/gcc/testsuite/gcc.target/sparc/small-struct-1.c +++ b/gcc/testsuite/gcc.target/sparc/small-struct-1.c @@ -42,5 +42,5 @@ double get2x (struct vec2x v) return v.x + v.y; } -/* { dg-final { scan-assembler-not "ldx" } } */ -/* { dg-final { scan-assembler-not "stx" } } */ +/* { dg-final { scan-assembler-not "ldx" { target *-*-solaris* } } } */ +/* { dg-final { scan-assembler-not "stx" { target *-*-solaris* } } } */ diff --git a/gcc/testsuite/gm2.dg/spell/iso/fail/badimport2.mod b/gcc/testsuite/gm2.dg/spell/iso/fail/badimport2.mod new file mode 100644 index 0000000..63fd338 --- /dev/null +++ b/gcc/testsuite/gm2.dg/spell/iso/fail/badimport2.mod @@ -0,0 +1,12 @@ + +(* { dg-do compile } *) +(* { dg-options "-g -c" } *) + +MODULE badimport2 ; + +FROM StrIO IMPORT Writestring ; + (* { dg-error "error: In program module 'badimport2': unknown symbol 'Writestring', did you mean WriteString?" "Writestring" { target *-*-* } 7 } *) + +BEGIN + +END badimport2. diff --git a/gcc/testsuite/gm2.dg/spell/iso/fail/badimport3.mod b/gcc/testsuite/gm2.dg/spell/iso/fail/badimport3.mod new file mode 100644 index 0000000..ab82cd5 --- /dev/null +++ b/gcc/testsuite/gm2.dg/spell/iso/fail/badimport3.mod @@ -0,0 +1,17 @@ + +(* { dg-do compile } *) +(* { dg-options "-g -c" } *) + +MODULE badimport3 ; + +CONST + Foo = 42 ; + +MODULE inner ; +IMPORT foo ; + (* { dg-error "error: In inner module 'inner': unknown symbol 'foo', did you mean Foo?" "foo" { target *-*-* } 11 } *) +END inner ; + + +BEGIN +END badimport3. diff --git a/gcc/testsuite/gm2.dg/spell/iso/fail/badimport4.mod b/gcc/testsuite/gm2.dg/spell/iso/fail/badimport4.mod new file mode 100644 index 0000000..1b310d7 --- /dev/null +++ b/gcc/testsuite/gm2.dg/spell/iso/fail/badimport4.mod @@ -0,0 +1,17 @@ + +(* { dg-do compile } *) +(* { dg-options "-g -c" } *) + +MODULE badimport4 ; + +CONST + Foo = 42 ; + +MODULE inner ; +IMPORT foo ; + (* { dg-error "error: In inner module 'inner': unknown symbol 'foo', did you mean Foo?" "foo" { target *-*-* } 11 } *) +END inner ; + + +BEGIN +END badimport4. diff --git a/gcc/testsuite/gnat.dg/specs/unknown_discr1.ads b/gcc/testsuite/gnat.dg/specs/unknown_discr1.ads new file mode 100644 index 0000000..d1c85e1 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/unknown_discr1.ads @@ -0,0 +1,23 @@ +-- { dg-do compile } + +with Unknown_Discr1_Pkg; use Unknown_Discr1_Pkg; +with Unknown_Discr1_Pkg.Child; +with Unknown_Discr1_Pkg.Inst; + +package Unknown_Discr1 is + + A : Tagged_Type (0); -- { dg-error "type has unknown discriminants" } + + B : Child.Derived_1 (1); -- { dg-error "type has unknown discriminants" } + + C : Child.Derived_2 (2); -- { dg-error "type has unknown discriminants" } + + D : Child.Nested.Derived_3 (3); -- { dg-error "type has unknown discriminants" } + + E : Inst.Derived_1 (1); -- { dg-error "type has unknown discriminants" } + + F : Inst.Derived_2 (2); -- { dg-error "type has unknown discriminants" } + + G : Inst.Nested.Derived_3 (3); -- { dg-error "type has unknown discriminants" } + +end Unknown_Discr1; diff --git a/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-child.ads b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-child.ads new file mode 100644 index 0000000..681efbc --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-child.ads @@ -0,0 +1,17 @@ +package Unknown_Discr1_Pkg.Child is + + type Derived_1 is new Tagged_Type with null record; + + type Derived_2 is new Derived_1 with null record; + + package Nested is + + type Derived_3 is new Tagged_Type with private; + + private + + type Derived_3 is new Tagged_Type with null record; + + end Nested; + +end Unknown_Discr1_Pkg.Child; diff --git a/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-g.ads b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-g.ads new file mode 100644 index 0000000..1570405 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-g.ads @@ -0,0 +1,21 @@ +generic + + type Base (<>) is new Tagged_Type with private; + +package Unknown_Discr1_Pkg.G is + + type Derived_1 is new Base with null record; + + type Derived_2 is new Derived_1 with null record; + + package Nested is + + type Derived_3 is new Tagged_Type with private; + + private + + type Derived_3 is new Tagged_Type with null record; + + end Nested; + +end Unknown_Discr1_Pkg.G; diff --git a/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-inst.ads b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-inst.ads new file mode 100644 index 0000000..5dfe119 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-inst.ads @@ -0,0 +1,3 @@ +with Unknown_Discr1_Pkg.G; + +package Unknown_Discr1_Pkg.Inst is new Unknown_Discr1_Pkg.G (Tagged_Type); diff --git a/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg.ads b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg.ads new file mode 100644 index 0000000..d769b4d --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg.ads @@ -0,0 +1,9 @@ +package Unknown_Discr1_Pkg is + + type Tagged_Type (<>) is tagged limited private; + +private + + type Tagged_Type (Kind : Integer) is tagged limited null record; + +end Unknown_Discr1_Pkg; diff --git a/gcc/testsuite/gnat.dg/use_type4.adb b/gcc/testsuite/gnat.dg/use_type4.adb new file mode 100644 index 0000000..5ceb288 --- /dev/null +++ b/gcc/testsuite/gnat.dg/use_type4.adb @@ -0,0 +1,29 @@ +-- { dg-do compile } + +procedure Use_Type4 is + + package P1 is + type T is new Integer; + function "and" (L, R : in Integer) return T; + end P1; + + package body P1 is + function "and" (L, R : in Integer) return T is + begin + return T (L * R); + end "and"; + end P1; + + use type P1.T; + + package Renaming renames P1; + + package P2 is + use Renaming; + end P2; + + G : P1.T := Integer'(1) and Integer'(2); + +begin + null; +end; |