diff options
Diffstat (limited to 'gcc')
135 files changed, 6340 insertions, 8693 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f7ffd4d..d597002 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,282 @@ +2025-05-13 Andrew MacLeod <amacleod@redhat.com> + + * tree-ssanames.cc (set_bitmask): Use int_range_max for temps. + * value-range.cc (irange::set_range_from_bitmask): Handle all + trailing zero values. + +2025-05-12 Pan Li <pan2.li@intel.com> + + * match.pd: Add form 7 matching pattern for unsigned integer + SAT_ADD. + +2025-05-12 Andrew Pinski <quic_apinski@quicinc.com> + + * config/aarch64/aarch64.md (cmov<mode>6): Remove. + +2025-05-12 Andrew Pinski <quic_apinski@quicinc.com> + + PR middle-end/120230 + * optabs.cc (can_compare_p): Remove support for ccp_cmov. + * optabs.def (cmov_optab): Remove. + * optabs.h (can_compare_purpose): Remove ccp_cmov. + +2025-05-12 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/120231 + * range-op-float.cc (operator_cast::fold_range): New variants. + (operator_cast::op1_range): Likewise. + * range-op-mixed.h (operator_cast::fold_range): Likewise. + (operator_cast::op1_range): Likewise + * range-op.cc (range_op_handler::fold_range): Add RO_FIF dispatch. + (range_op_handler::op1_range): Add RO_IFF and RO_FII patterns. + (range_operator::fold_range): Provide new variant default. + (range_operator::op1_range): Likewise. + * range-op.h (range_operator): Add new variant methods. + +2025-05-12 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/120188 + * doc/gm2.texi (Semantic checking): Add -fm2-plugin command line option. + +2025-05-12 Thomas Schwinge <tschwinge@baylibre.com> + + * config/nvptx/nvptx-sm.def: Add '61'. + * config/nvptx/nvptx-gen.h: Regenerate. + * config/nvptx/nvptx-gen.opt: Likewise. + * config/nvptx/nvptx.cc (first_ptx_version_supporting_sm): Adjust. + * config/nvptx/nvptx.opt (-march-map=sm_61, -march-map=sm_62): + Likewise. + * config.gcc: Likewise. + * doc/invoke.texi (Nvidia PTX Options): Document '-march=sm_61'. + * config/nvptx/gen-multilib-matches-tests: Extend. + +2025-05-12 Thomas Schwinge <tschwinge@baylibre.com> + + * config/nvptx/nvptx-opts.h (enum ptx_version): Add + 'PTX_VERSION_5_0'. + * config/nvptx/nvptx.cc (ptx_version_to_string) + (ptx_version_to_number): Adjust. + * config/nvptx/nvptx.h (TARGET_PTX_5_0): New. + * config/nvptx/nvptx.opt (Enum(ptx_version)): Add 'EnumValue' + '5.0' for 'PTX_VERSION_5_0'. + * doc/invoke.texi (Nvidia PTX Options): Document '-mptx=5.0'. + +2025-05-12 Dongyan Chen <chendongyan@isrc.iscas.ac.cn> + + * common/config/riscv/riscv-common.cc + (riscv_subset_list::check_conflict_ext): New extension. + * config/riscv/riscv.opt: Ditto. + +2025-05-12 Dongyan Chen <chendongyan@isrc.iscas.ac.cn> + + * common/config/riscv/riscv-common.cc + (riscv_subset_list::check_conflict_ext): New extension. + * config/riscv/riscv.opt: Ditto. + +2025-05-12 Richard Biener <rguenther@suse.de> + + * lto-streamer-out.cc (hash_tree): Hash TYPE_MODE_RAW. + When offloading hash modes as VOIDmode for aggregates + and vectors. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * doc/extend.texi: Remove the iwmmxt intrinsics. + * doc/md.texi: Remove the iwmmxt-related constraints. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/aout.h (REGISTER_NAMES): Remove iwmmxt registers. + * config/arm/arm.h (FIRST_IWMMXT_REGNUM): Delete. + (LAST_IWMMXT_REGNUM): Delete. + (FIRST_IWMMXT_GR_REGNUM): Delete. + (LAST_IWMMXT_GR_REGNUM): Delete. + (IS_IWMMXT_REGNUM): Delete. + (IS_IWMMXT_GR_REGNUM): Delete. + (FRAME_POINTER_REGNUM): Define relative to CC_REGNUM. + (ARG_POINTER_REGNUM): Define relative to FRAME_POINTER_REGNUM. + (FIRST_PSEUDO_REGISTER): Adjust. + (WREG): Delete. + (WGREG): Delete. + (REG_ALLOC_ORDER): Remove iWMMX registers. + (enum reg_class): Remove iWMMX register classes. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Remove iWMMX registers. + * config/arm/arm.md (CC_REGNUM): Adjust value. + (VFPCC_RENGUM): Likewise. + (APSRQ_REGNUM): Likewise. + (APSRGE_REGNUM): Likewise. + (VPR_REGNUM): Likewise. + (RA_AUTH_CODE): Likewise. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm-cpus.in (feature iwmmxt, feature iwmmxt2): Delete. + * config/arm/arm-protos.h (arm_output_iwmmxt_shift_immediate): Delete. + (arm_output_iwmmxt_tinsr): Delete. + (arm_arch_iwmmxt): Delete. + (arm_arch_iwmmxt2): Delete. + * config/arm/arm.h (TARGET_IWMMXT): Delete. + (TARGET_IWMMXT2): Delete. + (TARGET_REALLY_IWMMXT): Delete. + (TARGET_REALLY_IWMMXT2): Delete. + (VALID_IWMMXT_REG_MODE): Delete. + (ARM_HAVE_V8QI_ARITH): Remove iWMMXT. + (ARM_HAVE_V4HI_ARITH): Likewise. + (ARM_HAVE_V2SI_ARITH): Likewise. + (ARM_HAVE_V8QI_LDST): Likewise. + (ARM_HAVE_V4HI_LDST): Likewise. + (ARM_HAVE_V2SI_LDST): Likewise. + (SECONDARY_OUTPUT_RELOAD_CLASS): Remove iWMMXT cases. + (SECONDARY_INPUT_RELOAD_CLASS): Likewise. + * config/arm/arm.cc (arm_arch_iwmmxt): Delete. + (arm_arch_iwmmxt2): Delete. + (arm_option_reconfigure_globals): Don't initialize them. + (arm_register_move_cost): Remove costs for iwmmxt. + (struct minipool_node): Update comment. + (output_move_double): Likewise + (output_return_instruction): Likewise. + (arm_print_operand, cases 'U' and 'w'): Report an error if + used. + (arm_regno_class): Remove iWMMXT cases. + (arm_debugger_regno): Remove iWMMXT cases. + (arm_output_iwmmxt_shift_immediate): Delete. + (arm_output_iwmmxt_tinsr): Delete. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm-c.cc (arm_cpu_builtins): Remove predefines + for __IWWMXT__, __IWMMXT2__ and __ARM_WMMX. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/iterators.md (VMMX, VMMX2): Remove mode iterators. + (MMX_char): Remove mode iterator attribute. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm.md (core_cycles): Remove iwmmxt attributes. + * config/arm/types.md (autodetect_type): Likewise. + * config/arm/marvell-f-iwmmxt.md: Removed. + * config/arm/t-arm: Remove marvell-f-iwmmxt.md + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm.cc (arm_option_check_internal): Remove + IWMMXT check. + (arm_options_perform_arch_sanity_checks): Likewise. + (use_return_insn): Likewise. + (arm_init_cumulative_args): Likewise. + (arm_legitimate_index_p): Likewise. + (thumb2_legitimate_index_p): Likewise. + (arm_compute_save_core_reg_mask): Likewise. + (output_return_instruction): Likewise. + (arm_compute_frame_layout): Likewise. + (arm_save_coproc_regs): Likewise. + (arm_hard_regno_mode_ok): Likewise. + (arm_expand_epilogue_apcs_frame): Likewise. + (arm_expand_epilogue): Likewise. + (arm_vector_mode_supported_p): Likewise. + (arm_preferred_simd_mode): Likewise. + (arm_conditional_register_usage): Likewise. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config.gcc (arm, --with-abi): Remove iwmmxt abi option. + * config/arm/arm.opt (enum ARM_ABI_IWMMXT): Remove. + * config/arm/arm.h (TARGET_IWMMXT_ABI): Delete. + (enum arm_pcs): Remove ARM_PCS_AAPCS_IWMMXT. + (FUNCTION_ARG_REGNO_P): Remove IWMMXT ABI support. + (CUMULATIVE_ARGS): Remove iwmmxt_nregs. + * config/arm/arm.cc (arm_options_perform_arch_sanity_checks): + Remove IWMMXT ABI checks. + (arm_libcall_value_1): Likewise. + (arm_function_value_regno_p): Likewise. + (arm_apply_result_size): Remove adjustment for IWMMXT ABI. + (arm_function_arg): Remove IWMMXT ABI support. + (arm_arg_partial_bytes): Likewise. + (arm_function_arg_advance): Likewise. + (arm_init_cumulative_args): Don't initialize iwmmxt_nregs. + * doc/invoke.texi (arm -mabi): Remove mention of the iwmmxt + ABI option. + * config/arm/arm-opts.h (enum arm_abi_type): Remove ARM_ABI_IWMMXT. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm.md(attr arch): Remove iwmmxt and iwmmxt2. + Remove checks based on TARGET_REALLY_IWMMXT2 from all split + patterns. + (arm_movdi): Likewise. + (*arm_movt): Likewise. + (arch_enabled): Remove test for iwmmxt2. + * config/arm/constraints.md (y, z): Remove register constraints. + (Uy): Remove memory constraint. + * config/arm/thumb2.md (thumb2_pop_single): Remove check for + IWMMXT. + * config/arm/vec-common.md (mov<mode>): Remove check for IWMMXT. + (mul<mode>3): Likewise. + (xor<mode>3): Likewise. + (<absneg_str><mode>2): Likewise. + (@movmisalign<mode>): Likewise. + (@mve_<mve_insn>q_<supf><mode>): Likewise. + (vashl<mode>3): Likewise. + (vashr<mode>3): Likewise. + (vlshr<mode>3): Likewise. + (uavg<mode>3_ceil): Likewise. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm.md: Don't include iwmmxt.md. + * config/arm/t-arm (MD_INCLUDES): Remove iwmmxt*.md. + * config/arm/iwmmxt.md: Removed. + * config/arm/iwmmxt2.md: Removed. + * config/arm/unspecs.md: Remove comment referring to + iwmmxt2.md. + (enum unspec): Remove iWMMXt unspec values. + (enum unspecv): Likewise. + * config/arm/predicates.md (imm_or_reg_operand): Delete. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm-builtins.cc (enum arm_builtins): Delete iWMMX + builtin values. + (bdesc_2arg): Likewise. + (bdesc_1arg): Likewise. + (arm_init_iwmmxt_builtins): Delete. + (arm_init_builtins): Don't call arm_init_iwmmxt_builtins. + (safe_vector_operand): Use __builtin_unreachable instead of emitting + an iwmmxt builtin. + (arm_general_expand_builtin): Remove iWMMX builtins support. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm-cpus.in (arch iwmmxt): treat in the same + way as we would treat XScale. + (arch iwmmxt2): Likewise. + (cpu xscale): Add aliases for iwmmxt and iwmmxt2. + (cpu iwmmxt): Delete. + (cpu iwmmxt2): Delete. + * config/arm/arm-generic.md (load_ldsched_xscale): Remove references + to iwmmxt. + (load_ldsched): Likewise. + * config/arm/arm-tables.opt: Regenerated. + * config/arm/arm-tune.md: Regenerated. + * doc/sourcebuild.texi (arm_iwmmxt_ok): Delete. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm.h (SECONDARY_OUTPUT_RELOAD_CLASS): Add parentheis + and re-indent. + (SECONDARY_INPUT_RELOAD_CLASS): Likewise. + +2025-05-12 H.J. Lu <hjl.tools@gmail.com> + + PR target/120228 + * config/i386/i386-features.cc (ix86_place_single_vector_set): + Remove df_insn_rescan after emit_insn_*. + (remove_partial_avx_dependency): Likewise. + (replace_vector_const): Likewise. + 2025-05-11 Jan Hubicka <hubicka@ucw.cz> * config/i386/i386.cc (ix86_widen_mult_cost): Use sse_op to cost diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 823f45b..83f5cb2 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20250512 +20250513 diff --git a/gcc/Makefile.in b/gcc/Makefile.in index e3af923..72d1322 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -3703,7 +3703,7 @@ TEXI_GCC_FILES = gcc.texi gcc-common.texi gcc-vers.texi frontends.texi \ contribute.texi compat.texi funding.texi gnu.texi gpl_v3.texi \ fdl.texi contrib.texi cppenv.texi cppopts.texi avr-mmcu.texi \ implement-c.texi implement-cxx.texi gcov-tool.texi gcov-dump.texi \ - lto-dump.texi + lto-dump.texi riscv-ext.texi # we explicitly use $(srcdir)/doc/tm.texi here to avoid confusion with # the generated tm.texi; the latter might have a more recent timestamp, diff --git a/gcc/ada/Make-generated.in b/gcc/ada/Make-generated.in index 95c2a1d..5cb1b32 100644 --- a/gcc/ada/Make-generated.in +++ b/gcc/ada/Make-generated.in @@ -18,7 +18,7 @@ GEN_IL_FLAGS = -gnata -gnat2012 -gnatw.g -gnatyg -gnatU $(GEN_IL_INCLUDES) ada/seinfo_tables.ads ada/seinfo_tables.adb ada/sinfo.h ada/einfo.h ada/nmake.ads ada/nmake.adb ada/seinfo.ads ada/sinfo-nodes.ads ada/sinfo-nodes.adb ada/einfo-entities.ads ada/einfo-entities.adb: ada/stamp-gen_il ; @true ada/stamp-gen_il: $(fsrcdir)/ada/gen_il* $(MKDIR) ada/gen_il - cd ada/gen_il; gnatmake -q -g $(GEN_IL_FLAGS) gen_il-main + cd ada/gen_il; gnatmake -g $(GEN_IL_FLAGS) gen_il-main # Ignore errors to work around finalization issues in older compilers - cd ada/gen_il; ./gen_il-main $(fsrcdir)/../move-if-change ada/gen_il/seinfo_tables.ads ada/seinfo_tables.ads @@ -46,7 +46,7 @@ ada/stamp-snames : ada/snames.ads-tmpl ada/snames.adb-tmpl ada/snames.h-tmpl ada -$(MKDIR) ada/bldtools/snamest $(RM) $(addprefix ada/bldtools/snamest/,$(notdir $^)) $(CP) $^ ada/bldtools/snamest - cd ada/bldtools/snamest && gnatmake -q xsnamest && ./xsnamest + cd ada/bldtools/snamest && gnatmake xsnamest && ./xsnamest $(fsrcdir)/../move-if-change ada/bldtools/snamest/snames.ns ada/snames.ads $(fsrcdir)/../move-if-change ada/bldtools/snamest/snames.nb ada/snames.adb $(fsrcdir)/../move-if-change ada/bldtools/snamest/snames.nh ada/snames.h diff --git a/gcc/ada/gcc-interface/Makefile.in b/gcc/ada/gcc-interface/Makefile.in index 4ffdc1e..2c42cb1 100644 --- a/gcc/ada/gcc-interface/Makefile.in +++ b/gcc/ada/gcc-interface/Makefile.in @@ -634,7 +634,7 @@ OSCONS_EXTRACT=$(GCC_FOR_ADA_RTS) $(GNATLIBCFLAGS_FOR_C) -S s-oscons-tmplt.i -$(MKDIR) ./bldtools/oscons $(RM) $(addprefix ./bldtools/oscons/,$(notdir $^)) $(CP) $^ ./bldtools/oscons - (cd ./bldtools/oscons ; gnatmake -q xoscons) + (cd ./bldtools/oscons ; gnatmake xoscons) $(RTSDIR)/s-oscons.ads: ../stamp-gnatlib1-$(RTSDIR) s-oscons-tmplt.c gsocket.h ./bldtools/oscons/xoscons $(RM) $(RTSDIR)/s-oscons-tmplt.i $(RTSDIR)/s-oscons-tmplt.s diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index e06cd5f..3d3ca11 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -19,6 +19,7 @@ along with GCC; see the file COPYING3. If not see #include <sstream> #include <vector> +#include <unordered_map> #include <queue> #define INCLUDE_STRING @@ -41,229 +42,216 @@ along with GCC; see the file COPYING3. If not see #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN) #endif +/* Type for pointer to member of gcc_options and cl_target_option. */ +typedef int (gcc_options::*opt_var_ref_t); +typedef int (cl_target_option::*cl_opt_var_ref_t); + +/* Types for recording extension to internal flag. */ +struct riscv_extra_ext_flag_table_t +{ + const char *ext; + opt_var_ref_t var_ref; + cl_opt_var_ref_t cl_var_ref; + int mask; +}; + +/* Types for recording extension to internal flag. */ +struct riscv_ext_flag_table_t +{ + opt_var_ref_t var_ref; + cl_opt_var_ref_t cl_var_ref; + int mask; + + void clean (gcc_options *opts) const { opts->*var_ref &= ~mask; } + + void set (gcc_options *opts) const { opts->*var_ref |= mask; } + + bool check (cl_target_option *opts) const + { + return (opts->*cl_var_ref & mask); + } +}; + +/* Type for hold RISC-V extension version. */ +struct riscv_version_t +{ + riscv_version_t (int major_version, int minor_version, + enum riscv_isa_spec_class isa_spec_class + = ISA_SPEC_CLASS_NONE) + : major_version (major_version), minor_version (minor_version), + isa_spec_class (isa_spec_class) + {} + int major_version; + int minor_version; + enum riscv_isa_spec_class isa_spec_class; +}; + typedef bool (*riscv_implied_predicator_t) (const riscv_subset_list *); /* Type for implied ISA info. */ struct riscv_implied_info_t { - constexpr riscv_implied_info_t (const char *ext, const char *implied_ext, + constexpr riscv_implied_info_t (const char *implied_ext, riscv_implied_predicator_t predicator = nullptr) - : ext (ext), implied_ext (implied_ext), predicator (predicator){}; + : implied_ext (implied_ext), predicator (predicator) + {} - bool match (const riscv_subset_list *subset_list, const char *ext_name) const + bool match (const riscv_subset_list *subset_list) const { - if (strcmp (ext_name, ext) != 0) - return false; - if (predicator && !predicator (subset_list)) return false; return true; } - bool match (const riscv_subset_list *subset_list, - const riscv_subset_t *subset) const - { - return match (subset_list, subset->name.c_str()); - } - - const char *ext; const char *implied_ext; riscv_implied_predicator_t predicator; }; -/* Implied ISA info, must end with NULL sentinel. */ -static const riscv_implied_info_t riscv_implied_info[] = -{ - {"m", "zmmul"}, - - {"d", "f"}, - {"f", "zicsr"}, - {"d", "zicsr"}, - - {"a", "zaamo"}, - {"a", "zalrsc"}, - - {"c", "zca"}, - {"c", "zcf", - [] (const riscv_subset_list *subset_list) -> bool - { - return subset_list->xlen () == 32 && subset_list->lookup ("f"); - }}, - {"c", "zcd", - [] (const riscv_subset_list *subset_list) -> bool - { - return subset_list->lookup ("d"); - }}, - - {"zabha", "zaamo"}, - {"zacas", "zaamo"}, - {"zawrs", "zalrsc"}, - - {"zcmop", "zca"}, - - {"b", "zba"}, - {"b", "zbb"}, - {"b", "zbs"}, - - {"zdinx", "zfinx"}, - {"zfinx", "zicsr"}, - {"zdinx", "zicsr"}, - - {"zicfiss", "zicsr"}, - {"zicfiss", "zimop"}, - {"zicfilp", "zicsr"}, - - {"zk", "zkn"}, - {"zk", "zkr"}, - {"zk", "zkt"}, - {"zkn", "zbkb"}, - {"zkn", "zbkc"}, - {"zkn", "zbkx"}, - {"zkn", "zkne"}, - {"zkn", "zknd"}, - {"zkn", "zknh"}, - {"zks", "zbkb"}, - {"zks", "zbkc"}, - {"zks", "zbkx"}, - {"zks", "zksed"}, - {"zks", "zksh"}, - - {"v", "zvl128b"}, - {"v", "zve64d"}, - - {"zve32f", "f"}, - {"zve64f", "f"}, - {"zve64d", "d"}, - - {"zve32x", "zicsr"}, - {"zve32x", "zvl32b"}, - {"zve32f", "zve32x"}, - {"zve32f", "zvl32b"}, - - {"zve64x", "zve32x"}, - {"zve64x", "zvl64b"}, - {"zve64f", "zve32f"}, - {"zve64f", "zve64x"}, - {"zve64f", "zvl64b"}, - {"zve64d", "zve64f"}, - {"zve64d", "zvl64b"}, - - {"zvl64b", "zvl32b"}, - {"zvl128b", "zvl64b"}, - {"zvl256b", "zvl128b"}, - {"zvl512b", "zvl256b"}, - {"zvl1024b", "zvl512b"}, - {"zvl2048b", "zvl1024b"}, - {"zvl4096b", "zvl2048b"}, - {"zvl8192b", "zvl4096b"}, - {"zvl16384b", "zvl8192b"}, - {"zvl32768b", "zvl16384b"}, - {"zvl65536b", "zvl32768b"}, - - {"zvkn", "zvkned"}, - {"zvkn", "zvknhb"}, - {"zvkn", "zvkb"}, - {"zvkn", "zvkt"}, - {"zvknc", "zvkn"}, - {"zvknc", "zvbc"}, - {"zvkng", "zvkn"}, - {"zvkng", "zvkg"}, - {"zvks", "zvksed"}, - {"zvks", "zvksh"}, - {"zvks", "zvkb"}, - {"zvks", "zvkt"}, - {"zvksc", "zvks"}, - {"zvksc", "zvbc"}, - {"zvksg", "zvks"}, - {"zvksg", "zvkg"}, - {"zvbb", "zvkb"}, - {"zvbc", "zve64x"}, - {"zvkb", "zve32x"}, - {"zvkg", "zve32x"}, - {"zvkned", "zve32x"}, - {"zvknha", "zve32x"}, - {"zvknhb", "zve64x"}, - {"zvksed", "zve32x"}, - {"zvksh", "zve32x"}, - - {"zfbfmin", "zfhmin"}, - {"zfh", "zfhmin"}, - {"zfhmin", "f"}, - - {"zfa", "f"}, - - {"zvfbfmin", "zve32f"}, - {"zvfbfwma", "zvfbfmin"}, - {"zvfbfwma", "zfbfmin"}, - {"zvfhmin", "zve32f"}, - {"zvfh", "zve32f"}, - {"zvfh", "zfhmin"}, - - {"zhinx", "zhinxmin"}, - {"zhinxmin", "zfinx"}, - - {"zce", "zca"}, - {"zce", "zcb"}, - {"zce", "zcmp"}, - {"zce", "zcmt"}, - {"zcf", "zca"}, - {"zcd", "zca"}, - {"zcb", "zca"}, - {"zcmp", "zca"}, - {"zcmt", "zca"}, - {"zcmt", "zicsr"}, - {"zce", "zcf", - [] (const riscv_subset_list *subset_list) -> bool - { - return subset_list->xlen () == 32 && subset_list->lookup ("f"); - }}, - {"zca", "c", - [] (const riscv_subset_list *subset_list) -> bool - { - /* For RV32 Zca implies C for one of these combinations of - extensions: Zca, F_Zca_Zcf and FD_Zca_Zcf_Zcd. */ - if (subset_list->xlen () == 32) - { - if (subset_list->lookup ("d")) - return subset_list->lookup ("zcf") && subset_list->lookup ("zcd"); - - if (subset_list->lookup ("f")) - return subset_list->lookup ("zcf"); - - return true; - } - - /* For RV64 Zca implies C for one of these combinations of - extensions: Zca and FD_Zca_Zcd (Zcf is not available - for RV64). */ - if (subset_list->xlen () == 64) - { - if (subset_list->lookup ("d")) - return subset_list->lookup ("zcd"); - - return true; - } - - /* Do nothing for future RV128 specification. Behaviour - for this case is not yet well defined. */ - return false; - }}, - - {"smaia", "ssaia"}, - {"smstateen", "ssstateen"}, - {"smepmp", "zicsr"}, - {"ssaia", "zicsr"}, - {"sscofpmf", "zicsr"}, - {"ssstateen", "zicsr"}, - {"sstc", "zicsr"}, - - {"xsfvcp", "zve32x"}, +static void +apply_extra_extension_flags (const char *ext, + std::vector<riscv_ext_flag_table_t> &flag_table); - {NULL, NULL} +/* Class for hold the extension info. */ +class riscv_ext_info_t +{ +public: + riscv_ext_info_t (const char *ext, + const std::vector<riscv_implied_info_t> &implied_exts, + const std::vector<riscv_version_t> &supported_versions, + const std::vector<riscv_ext_flag_table_t> &flag_table, + int bitmask_group_id, int bitmask_group_bit_pos, + unsigned extra_extension_flags) + : m_ext (ext), m_implied_exts (implied_exts), + m_supported_versions (supported_versions), m_flag_table (flag_table), + m_bitmask_group_id (bitmask_group_id), + m_bitmask_group_bit_pos (bitmask_group_bit_pos), + m_extra_extension_flags (extra_extension_flags) + { + apply_extra_extension_flags (ext, m_flag_table); + } + + /* Return true if any change. */ + bool apply_implied_ext (riscv_subset_list *subset_list) const; + + const std::vector<riscv_implied_info_t> implied_exts () const + { + return m_implied_exts; + } + + bool need_combine_p () const + { + return m_extra_extension_flags & EXT_FLAG_MACRO; + } + + riscv_version_t default_version () const + { + if (m_supported_versions.size () == 1) + { + return *m_supported_versions.begin (); + } + + for (const riscv_version_t &ver : m_supported_versions) + { + if (ver.isa_spec_class == riscv_isa_spec + || ver.isa_spec_class == ISA_SPEC_CLASS_NONE) + return ver; + } + gcc_unreachable (); + } + + void clean_opts (gcc_options *opts) const + { + for (auto &flag : m_flag_table) + flag.clean (opts); + } + + void set_opts (gcc_options *opts) const + { + for (auto &flag : m_flag_table) + flag.set (opts); + } + + bool check_opts (cl_target_option *opts) const + { + bool result = true; + for (auto &flag : m_flag_table) + result = result && flag.check (opts); + return result; + } + + const std::vector<riscv_version_t> &supported_versions () const + { + return m_supported_versions; + } + +private: + const char *m_ext; + std::vector<riscv_implied_info_t> m_implied_exts; + std::vector<riscv_version_t> m_supported_versions; + std::vector<riscv_ext_flag_table_t> m_flag_table; + int m_bitmask_group_id; + int m_bitmask_group_bit_pos; + unsigned m_extra_extension_flags; +}; + +static const std::unordered_map<std::string, riscv_ext_info_t> riscv_ext_infos + = { +#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ + SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \ + BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \ + {std::string (#NAME), \ + riscv_ext_info_t (#NAME, std::vector<riscv_implied_info_t> DEP_EXTS, \ + std::vector<riscv_version_t> SUPPORTED_VERSIONS, \ + std::vector<riscv_ext_flag_table_t> ( \ + {{&gcc_options::x_riscv_##FLAG_GROUP##_subext, \ + &cl_target_option::x_riscv_##FLAG_GROUP##_subext, \ + MASK_##UPPERCAE_NAME}}), \ + BITMASK_GROUP_ID, BITMASK_BIT_POSITION, \ + EXTRA_EXTENSION_FLAGS)}, +#include "../../../config/riscv/riscv-ext.def" +#undef DEFINE_RISCV_EXT }; +static const riscv_ext_info_t & +get_riscv_ext_info (const std::string &ext) +{ + auto itr = riscv_ext_infos.find (ext); + if (itr == riscv_ext_infos.end ()) + { + gcc_unreachable (); + } + return itr->second; +} + +/* Return true if any change. */ +bool +riscv_ext_info_t::apply_implied_ext (riscv_subset_list *subset_list) const +{ + bool any_change = false; + for (const riscv_implied_info_t &implied_info : m_implied_exts) + { + /* Skip if implied extension already present. */ + if (subset_list->lookup (implied_info.implied_ext)) + continue; + + any_change = true; + if (!implied_info.match (subset_list)) + continue; + + /* Version of implied extension will get from current ISA spec + version. */ + subset_list->add (implied_info.implied_ext, true); + + /* Recursively add implied extension by implied_info->implied_ext. */ + const riscv_ext_info_t &implied_ext_info + = get_riscv_ext_info (implied_info.implied_ext); + implied_ext_info.apply_implied_ext (subset_list); + } + return any_change; +} + /* This structure holds version information for specific ISA version. */ struct riscv_ext_version @@ -280,234 +268,6 @@ struct riscv_profiles const char *profile_string; }; -/* All standard extensions defined in all supported ISA spec. */ -static const struct riscv_ext_version riscv_ext_version_table[] = -{ - /* name, ISA spec, major version, minor_version. */ - {"e", ISA_SPEC_CLASS_20191213, 2, 0}, - {"e", ISA_SPEC_CLASS_20190608, 2, 0}, - {"e", ISA_SPEC_CLASS_2P2, 2, 0}, - - {"i", ISA_SPEC_CLASS_20191213, 2, 1}, - {"i", ISA_SPEC_CLASS_20190608, 2, 1}, - {"i", ISA_SPEC_CLASS_2P2, 2, 0}, - - {"m", ISA_SPEC_CLASS_20191213, 2, 0}, - {"m", ISA_SPEC_CLASS_20190608, 2, 0}, - {"m", ISA_SPEC_CLASS_2P2, 2, 0}, - - {"a", ISA_SPEC_CLASS_20191213, 2, 1}, - {"a", ISA_SPEC_CLASS_20190608, 2, 0}, - {"a", ISA_SPEC_CLASS_2P2, 2, 0}, - - {"f", ISA_SPEC_CLASS_20191213, 2, 2}, - {"f", ISA_SPEC_CLASS_20190608, 2, 2}, - {"f", ISA_SPEC_CLASS_2P2, 2, 0}, - - {"d", ISA_SPEC_CLASS_20191213, 2, 2}, - {"d", ISA_SPEC_CLASS_20190608, 2, 2}, - {"d", ISA_SPEC_CLASS_2P2, 2, 0}, - - {"c", ISA_SPEC_CLASS_20191213, 2, 0}, - {"c", ISA_SPEC_CLASS_20190608, 2, 0}, - {"c", ISA_SPEC_CLASS_2P2, 2, 0}, - - {"b", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"h", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"v", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0}, - {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0}, - - {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0}, - {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0}, - - {"zicond", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"za64rs", ISA_SPEC_CLASS_NONE, 1, 0}, - {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zabha", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zacas", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zama16b", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zbs", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zhinx", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zhinxmin", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zbkb", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zbkc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zbkx", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zkne", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zknd", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zknh", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zkr", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zksed", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zksh", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zkt", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zihintpause", ISA_SPEC_CLASS_NONE, 2, 0}, - - {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0}, - {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0}, - {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0}, - {"zic64b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"ziccamoa", ISA_SPEC_CLASS_NONE, 1, 0}, - {"ziccif", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zicclsm", ISA_SPEC_CLASS_NONE, 1, 0}, - {"ziccrse", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zicfiss", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zicfilp", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zimop", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zcmop", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0}, - {"zihpm", ISA_SPEC_CLASS_NONE, 2, 0}, - - {"zk", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zkn", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zks", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"ztso", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zve32x", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zve32f", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zve64x", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zve64f", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zve64d", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zvbb", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvbc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkb", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkg", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkned", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvknha", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvknhb", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvksed", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvksh", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkn", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvknc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkng", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvks", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvksc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvksg", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkt", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zvl32b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl64b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl128b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl256b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl512b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl1024b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl2048b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl4096b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl8192b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl16384b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zfh", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvfbfwma", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvfh", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zfa", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zca", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zcb", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zce", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zcf", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zcd", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"sdtrig", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"smaia", ISA_SPEC_CLASS_NONE, 1, 0}, - {"smepmp", ISA_SPEC_CLASS_NONE, 1, 0}, - {"smstateen", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"ssaia", ISA_SPEC_CLASS_NONE, 1, 0}, - {"sscofpmf", ISA_SPEC_CLASS_NONE, 1, 0}, - {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0}, - {"sstc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"ssstrict", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"svade", ISA_SPEC_CLASS_NONE, 1, 0}, - {"svadu", ISA_SPEC_CLASS_NONE, 1, 0}, - {"svinval", ISA_SPEC_CLASS_NONE, 1, 0}, - {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0}, - {"svpbmt", ISA_SPEC_CLASS_NONE, 1, 0}, - {"svvptc", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xcvsimd", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadbs", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadcmo", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadcondmov", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadfmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadfmv", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadint", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadmac", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"xsfvcp", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xsfcease", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xsfvqmaccqoq", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xsfvqmaccdod", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xsfvfnrclipxfqf", ISA_SPEC_CLASS_NONE, 1, 0}, - - /* Terminate the list. */ - {NULL, ISA_SPEC_CLASS_NONE, 0, 0} -}; - -/* Combine extensions defined in this table */ -static const struct riscv_ext_version riscv_combine_info[] = -{ - {"a", ISA_SPEC_CLASS_20191213, 2, 1}, - {"b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zk", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zkn", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zks", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkn", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvknc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkng", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvks", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvksc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvksg", ISA_SPEC_CLASS_NONE, 1, 0}, - /* Terminate the list. */ - {NULL, ISA_SPEC_CLASS_NONE, 0, 0} -}; - /* This table records the mapping form RISC-V Profiles into march string. */ static const riscv_profiles riscv_profiles_table[] = { @@ -782,11 +542,8 @@ subset_cmp (const std::string &a, const std::string &b) static bool standard_extensions_p (const char *ext) { - const riscv_ext_version *ext_ver; - for (ext_ver = &riscv_ext_version_table[0]; ext_ver->name != NULL; ++ext_ver) - if (strcmp (ext, ext_ver->name) == 0) - return true; - return false; + auto itr = riscv_ext_infos.find (ext); + return itr != riscv_ext_infos.end (); } /* Add new subset to list. */ @@ -916,24 +673,19 @@ get_default_version (const char *ext, unsigned int *major_version, unsigned int *minor_version) { - const riscv_ext_version *ext_ver; - for (ext_ver = &riscv_ext_version_table[0]; - ext_ver->name != NULL; - ++ext_ver) - if (strcmp (ext, ext_ver->name) == 0) - { - if ((ext_ver->isa_spec_class == riscv_isa_spec) || - (ext_ver->isa_spec_class == ISA_SPEC_CLASS_NONE)) - { - *major_version = ext_ver->major_version; - *minor_version = ext_ver->minor_version; - return; - } - } + auto itr = riscv_ext_infos.find (ext); + if (itr == riscv_ext_infos.end ()) + { + /* Not found version info. */ + *major_version = 0; + *minor_version = 0; + return; + } - /* Not found version info. */ - *major_version = 0; - *minor_version = 0; + riscv_version_t ver = itr->second.default_version (); + /* Get the version info from riscv_ext_infos. */ + *major_version = ver.major_version; + *minor_version = ver.minor_version; } /* Add new subset to list, but using default version from ISA spec version. */ @@ -1337,25 +1089,8 @@ riscv_subset_list::parse_single_std_ext (const char *p, bool exact_single_p) void riscv_subset_list::handle_implied_ext (const char *ext) { - const riscv_implied_info_t *implied_info; - for (implied_info = &riscv_implied_info[0]; - implied_info->ext; - ++implied_info) - { - if (!implied_info->match (this, ext)) - continue; - - /* Skip if implied extension already present. */ - if (lookup (implied_info->implied_ext)) - continue; - - /* Version of implied extension will get from current ISA spec - version. */ - add (implied_info->implied_ext, true); - - /* Recursively add implied extension by implied_info->implied_ext. */ - handle_implied_ext (implied_info->implied_ext); - } + const riscv_ext_info_t &ext_info = get_riscv_ext_info (ext); + ext_info.apply_implied_ext (this); /* For RISC-V ISA version 2.2 or earlier version, zicsr and zifence is included in the base ISA. */ @@ -1376,14 +1111,13 @@ riscv_subset_list::check_implied_ext () riscv_subset_t *itr; for (itr = m_head; itr != NULL; itr = itr->next) { - const riscv_implied_info_t *implied_info; - for (implied_info = &riscv_implied_info[0]; implied_info->ext; - ++implied_info) + auto &ext = *itr; + auto &ext_info = get_riscv_ext_info (ext.name); + for (auto &implied_ext : ext_info.implied_exts ()) { - if (!implied_info->match (this, itr)) + if (!implied_ext.match (this)) continue; - - if (!lookup (implied_info->implied_ext)) + if (lookup (implied_ext.implied_ext) == NULL) return false; } } @@ -1394,27 +1128,23 @@ riscv_subset_list::check_implied_ext () void riscv_subset_list::handle_combine_ext () { - const riscv_ext_version *combine_info; - const riscv_implied_info_t *implied_info; - bool is_combined = false; - - for (combine_info = &riscv_combine_info[0]; combine_info->name; - ++combine_info) + for (const auto &[ext_name, ext_info] : riscv_ext_infos) { - /* Skip if combine extensions are present */ - if (lookup (combine_info->name)) + bool is_combined = true; + /* Skip if this extension don't need to combine. */ + if (!ext_info.need_combine_p ()) + continue; + /* Skip if combine extensions are present. */ + if (lookup (ext_name.c_str ())) continue; - /* Find all extensions of the combine extension */ - for (implied_info = &riscv_implied_info[0]; implied_info->ext; - ++implied_info) + /* Check all implied extensions is present. */ + for (const auto &implied_ext : ext_info.implied_exts ()) { - if (!implied_info->match (this, combine_info->name)) + if (!implied_ext.match (this)) continue; - if (lookup (implied_info->implied_ext)) - is_combined = true; - else + if (!lookup (implied_ext.implied_ext)) { is_combined = false; break; @@ -1424,11 +1154,9 @@ riscv_subset_list::handle_combine_ext () /* Add combine extensions */ if (is_combined) { - if (lookup (combine_info->name) == NULL) - { - add (combine_info->name, combine_info->major_version, - combine_info->minor_version, false, true); - } + riscv_version_t ver = ext_info.default_version(); + add (ext_name.c_str (), ver.major_version, + ver.minor_version, false, true); } } } @@ -1439,6 +1167,34 @@ riscv_subset_list::check_conflict_ext () if (lookup ("zcf") && m_xlen == 64) error_at (m_loc, "%<-march=%s%>: zcf extension supports in rv32 only", m_arch); + + if (lookup ("zilsd") && m_xlen == 64) + error_at (m_loc, "%<-march=%s%>: zilsd extension supports in rv32 only", + m_arch); + + if (lookup ("zclsd") && m_xlen == 64) + error_at (m_loc, "%<-march=%s%>: zclsd extension supports in rv32 only", + m_arch); + + if (lookup ("ssnpm") && m_xlen == 32) + error_at (m_loc, "%<-march=%s%>: ssnpm extension supports in rv64 only", + m_arch); + + if (lookup ("smnpm") && m_xlen == 32) + error_at (m_loc, "%<-march=%s%>: smnpm extension supports in rv64 only", + m_arch); + + if (lookup ("smmpm") && m_xlen == 32) + error_at (m_loc, "%<-march=%s%>: smmpm extension supports in rv64 only", + m_arch); + + if (lookup ("sspm") && m_xlen == 32) + error_at (m_loc, "%<-march=%s%>: sspm extension supports in rv64 only", + m_arch); + + if (lookup ("supm") && m_xlen == 32) + error_at (m_loc, "%<-march=%s%>: supm extension supports in rv64 only", + m_arch); if (lookup ("zfinx") && lookup ("f")) error_at (m_loc, @@ -1715,90 +1471,15 @@ riscv_arch_str (bool version_p) return std::string(); } -/* Type for pointer to member of gcc_options and cl_target_option. */ -typedef int (gcc_options::*opt_var_ref_t); -typedef int (cl_target_option::*cl_opt_var_ref_t); - -/* Types for recording extension to internal flag. */ -struct riscv_ext_flag_table_t { - const char *ext; - opt_var_ref_t var_ref; - cl_opt_var_ref_t cl_var_ref; - int mask; -}; - #define RISCV_EXT_FLAG_ENTRY(NAME, VAR, MASK) \ {NAME, &gcc_options::VAR, &cl_target_option::VAR, MASK} -/* Mapping table between extension to internal flag. */ -static const riscv_ext_flag_table_t riscv_ext_flag_table[] = -{ - RISCV_EXT_FLAG_ENTRY ("e", x_target_flags, MASK_RVE), - RISCV_EXT_FLAG_ENTRY ("m", x_target_flags, MASK_MUL), - RISCV_EXT_FLAG_ENTRY ("a", x_target_flags, MASK_ATOMIC), - RISCV_EXT_FLAG_ENTRY ("f", x_target_flags, MASK_HARD_FLOAT), - RISCV_EXT_FLAG_ENTRY ("d", x_target_flags, MASK_DOUBLE_FLOAT), - RISCV_EXT_FLAG_ENTRY ("c", x_target_flags, MASK_RVC), - RISCV_EXT_FLAG_ENTRY ("v", x_target_flags, MASK_FULL_V), - RISCV_EXT_FLAG_ENTRY ("v", x_target_flags, MASK_VECTOR), - - RISCV_EXT_FLAG_ENTRY ("zicsr", x_riscv_zi_subext, MASK_ZICSR), - RISCV_EXT_FLAG_ENTRY ("zifencei", x_riscv_zi_subext, MASK_ZIFENCEI), - RISCV_EXT_FLAG_ENTRY ("zicond", x_riscv_zi_subext, MASK_ZICOND), - - RISCV_EXT_FLAG_ENTRY ("za64rs", x_riscv_za_subext, MASK_ZA64RS), - RISCV_EXT_FLAG_ENTRY ("za128rs", x_riscv_za_subext, MASK_ZA128RS), - RISCV_EXT_FLAG_ENTRY ("zawrs", x_riscv_za_subext, MASK_ZAWRS), - RISCV_EXT_FLAG_ENTRY ("zaamo", x_riscv_za_subext, MASK_ZAAMO), - RISCV_EXT_FLAG_ENTRY ("zalrsc", x_riscv_za_subext, MASK_ZALRSC), - RISCV_EXT_FLAG_ENTRY ("zabha", x_riscv_za_subext, MASK_ZABHA), - RISCV_EXT_FLAG_ENTRY ("zacas", x_riscv_za_subext, MASK_ZACAS), - RISCV_EXT_FLAG_ENTRY ("zama16b", x_riscv_za_subext, MASK_ZAMA16B), - - RISCV_EXT_FLAG_ENTRY ("zba", x_riscv_zb_subext, MASK_ZBA), - RISCV_EXT_FLAG_ENTRY ("zbb", x_riscv_zb_subext, MASK_ZBB), - RISCV_EXT_FLAG_ENTRY ("zbc", x_riscv_zb_subext, MASK_ZBC), - RISCV_EXT_FLAG_ENTRY ("zbs", x_riscv_zb_subext, MASK_ZBS), - - RISCV_EXT_FLAG_ENTRY ("zfinx", x_riscv_zinx_subext, MASK_ZFINX), - RISCV_EXT_FLAG_ENTRY ("zdinx", x_riscv_zinx_subext, MASK_ZDINX), - RISCV_EXT_FLAG_ENTRY ("zhinx", x_riscv_zinx_subext, MASK_ZHINX), - RISCV_EXT_FLAG_ENTRY ("zhinxmin", x_riscv_zinx_subext, MASK_ZHINXMIN), - - RISCV_EXT_FLAG_ENTRY ("zbkb", x_riscv_zk_subext, MASK_ZBKB), - RISCV_EXT_FLAG_ENTRY ("zbkc", x_riscv_zk_subext, MASK_ZBKC), - RISCV_EXT_FLAG_ENTRY ("zbkx", x_riscv_zk_subext, MASK_ZBKX), - RISCV_EXT_FLAG_ENTRY ("zknd", x_riscv_zk_subext, MASK_ZKND), - RISCV_EXT_FLAG_ENTRY ("zkne", x_riscv_zk_subext, MASK_ZKNE), - RISCV_EXT_FLAG_ENTRY ("zknh", x_riscv_zk_subext, MASK_ZKNH), - RISCV_EXT_FLAG_ENTRY ("zkr", x_riscv_zk_subext, MASK_ZKR), - RISCV_EXT_FLAG_ENTRY ("zksed", x_riscv_zk_subext, MASK_ZKSED), - RISCV_EXT_FLAG_ENTRY ("zksh", x_riscv_zk_subext, MASK_ZKSH), - RISCV_EXT_FLAG_ENTRY ("zkt", x_riscv_zk_subext, MASK_ZKT), - - RISCV_EXT_FLAG_ENTRY ("zihintntl", x_riscv_zi_subext, MASK_ZIHINTNTL), - RISCV_EXT_FLAG_ENTRY ("zihintpause", x_riscv_zi_subext, MASK_ZIHINTPAUSE), - RISCV_EXT_FLAG_ENTRY ("ziccamoa", x_riscv_zi_subext, MASK_ZICCAMOA), - RISCV_EXT_FLAG_ENTRY ("ziccif", x_riscv_zi_subext, MASK_ZICCIF), - RISCV_EXT_FLAG_ENTRY ("zicclsm", x_riscv_zi_subext, MASK_ZICCLSM), - RISCV_EXT_FLAG_ENTRY ("ziccrse", x_riscv_zi_subext, MASK_ZICCRSE), - - RISCV_EXT_FLAG_ENTRY ("zicboz", x_riscv_zicmo_subext, MASK_ZICBOZ), - RISCV_EXT_FLAG_ENTRY ("zicbom", x_riscv_zicmo_subext, MASK_ZICBOM), - RISCV_EXT_FLAG_ENTRY ("zicbop", x_riscv_zicmo_subext, MASK_ZICBOP), - RISCV_EXT_FLAG_ENTRY ("zic64b", x_riscv_zicmo_subext, MASK_ZIC64B), - - RISCV_EXT_FLAG_ENTRY ("zicfiss", x_riscv_zi_subext, MASK_ZICFISS), - RISCV_EXT_FLAG_ENTRY ("zicfilp", x_riscv_zi_subext, MASK_ZICFILP), - - RISCV_EXT_FLAG_ENTRY ("zimop", x_riscv_mop_subext, MASK_ZIMOP), - RISCV_EXT_FLAG_ENTRY ("zcmop", x_riscv_mop_subext, MASK_ZCMOP), - - RISCV_EXT_FLAG_ENTRY ("zve32x", x_target_flags, MASK_VECTOR), - RISCV_EXT_FLAG_ENTRY ("zve32f", x_target_flags, MASK_VECTOR), - RISCV_EXT_FLAG_ENTRY ("zve64x", x_target_flags, MASK_VECTOR), - RISCV_EXT_FLAG_ENTRY ("zve64f", x_target_flags, MASK_VECTOR), - RISCV_EXT_FLAG_ENTRY ("zve64d", x_target_flags, MASK_VECTOR), +/* Mapping table between extension to internal flag, + this table is not needed to add manually unless there is speical rule. */ +static const riscv_extra_ext_flag_table_t riscv_extra_ext_flag_table[] = +{ + RISCV_EXT_FLAG_ENTRY ("zve32x", x_riscv_isa_flags, MASK_VECTOR), + RISCV_EXT_FLAG_ENTRY ("v", x_riscv_isa_flags, MASK_FULL_V), /* We don't need to put complete ELEN/ELEN_FP info here, due to the implication relation of vector extension. @@ -1815,108 +1496,40 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = RISCV_EXT_FLAG_ENTRY ("zvfhmin", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16), RISCV_EXT_FLAG_ENTRY ("zvfh", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16), - RISCV_EXT_FLAG_ENTRY ("zvbb", x_riscv_zvb_subext, MASK_ZVBB), - RISCV_EXT_FLAG_ENTRY ("zvbc", x_riscv_zvb_subext, MASK_ZVBC), - RISCV_EXT_FLAG_ENTRY ("zvkb", x_riscv_zvb_subext, MASK_ZVKB), - RISCV_EXT_FLAG_ENTRY ("zvkg", x_riscv_zvk_subext, MASK_ZVKG), - RISCV_EXT_FLAG_ENTRY ("zvkned", x_riscv_zvk_subext, MASK_ZVKNED), - RISCV_EXT_FLAG_ENTRY ("zvknha", x_riscv_zvk_subext, MASK_ZVKNHA), - RISCV_EXT_FLAG_ENTRY ("zvknhb", x_riscv_zvk_subext, MASK_ZVKNHB), - RISCV_EXT_FLAG_ENTRY ("zvksed", x_riscv_zvk_subext, MASK_ZVKSED), - RISCV_EXT_FLAG_ENTRY ("zvksh", x_riscv_zvk_subext, MASK_ZVKSH), - RISCV_EXT_FLAG_ENTRY ("zvkn", x_riscv_zvk_subext, MASK_ZVKN), - RISCV_EXT_FLAG_ENTRY ("zvknc", x_riscv_zvk_subext, MASK_ZVKNC), - RISCV_EXT_FLAG_ENTRY ("zvkng", x_riscv_zvk_subext, MASK_ZVKNG), - RISCV_EXT_FLAG_ENTRY ("zvks", x_riscv_zvk_subext, MASK_ZVKS), - RISCV_EXT_FLAG_ENTRY ("zvksc", x_riscv_zvk_subext, MASK_ZVKSC), - RISCV_EXT_FLAG_ENTRY ("zvksg", x_riscv_zvk_subext, MASK_ZVKSG), - RISCV_EXT_FLAG_ENTRY ("zvkt", x_riscv_zvk_subext, MASK_ZVKT), - - RISCV_EXT_FLAG_ENTRY ("zvl32b", x_riscv_zvl_flags, MASK_ZVL32B), - RISCV_EXT_FLAG_ENTRY ("zvl64b", x_riscv_zvl_flags, MASK_ZVL64B), - RISCV_EXT_FLAG_ENTRY ("zvl128b", x_riscv_zvl_flags, MASK_ZVL128B), - RISCV_EXT_FLAG_ENTRY ("zvl256b", x_riscv_zvl_flags, MASK_ZVL256B), - RISCV_EXT_FLAG_ENTRY ("zvl512b", x_riscv_zvl_flags, MASK_ZVL512B), - RISCV_EXT_FLAG_ENTRY ("zvl1024b", x_riscv_zvl_flags, MASK_ZVL1024B), - RISCV_EXT_FLAG_ENTRY ("zvl2048b", x_riscv_zvl_flags, MASK_ZVL2048B), - RISCV_EXT_FLAG_ENTRY ("zvl4096b", x_riscv_zvl_flags, MASK_ZVL4096B), - RISCV_EXT_FLAG_ENTRY ("zvl8192b", x_riscv_zvl_flags, MASK_ZVL8192B), - RISCV_EXT_FLAG_ENTRY ("zvl16384b", x_riscv_zvl_flags, MASK_ZVL16384B), - RISCV_EXT_FLAG_ENTRY ("zvl32768b", x_riscv_zvl_flags, MASK_ZVL32768B), - RISCV_EXT_FLAG_ENTRY ("zvl65536b", x_riscv_zvl_flags, MASK_ZVL65536B), - - RISCV_EXT_FLAG_ENTRY ("zfbfmin", x_riscv_zf_subext, MASK_ZFBFMIN), - RISCV_EXT_FLAG_ENTRY ("zfhmin", x_riscv_zf_subext, MASK_ZFHMIN), - RISCV_EXT_FLAG_ENTRY ("zfh", x_riscv_zf_subext, MASK_ZFH), - RISCV_EXT_FLAG_ENTRY ("zvfbfmin", x_riscv_zf_subext, MASK_ZVFBFMIN), - RISCV_EXT_FLAG_ENTRY ("zvfbfwma", x_riscv_zf_subext, MASK_ZVFBFWMA), - RISCV_EXT_FLAG_ENTRY ("zvfhmin", x_riscv_zf_subext, MASK_ZVFHMIN), - RISCV_EXT_FLAG_ENTRY ("zvfh", x_riscv_zf_subext, MASK_ZVFH), - - RISCV_EXT_FLAG_ENTRY ("zfa", x_riscv_zfa_subext, MASK_ZFA), - - RISCV_EXT_FLAG_ENTRY ("zmmul", x_riscv_zm_subext, MASK_ZMMUL), - - /* Code-size reduction extensions. */ - RISCV_EXT_FLAG_ENTRY ("zca", x_riscv_zc_subext, MASK_ZCA), - RISCV_EXT_FLAG_ENTRY ("zcb", x_riscv_zc_subext, MASK_ZCB), - RISCV_EXT_FLAG_ENTRY ("zce", x_riscv_zc_subext, MASK_ZCE), - RISCV_EXT_FLAG_ENTRY ("zcf", x_riscv_zc_subext, MASK_ZCF), - RISCV_EXT_FLAG_ENTRY ("zcd", x_riscv_zc_subext, MASK_ZCD), - RISCV_EXT_FLAG_ENTRY ("zcmp", x_riscv_zc_subext, MASK_ZCMP), - RISCV_EXT_FLAG_ENTRY ("zcmt", x_riscv_zc_subext, MASK_ZCMT), - - RISCV_EXT_FLAG_ENTRY ("svade", x_riscv_sv_subext, MASK_SVADE), - RISCV_EXT_FLAG_ENTRY ("svadu", x_riscv_sv_subext, MASK_SVADU), - RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL), - RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT), - RISCV_EXT_FLAG_ENTRY ("svvptc", x_riscv_sv_subext, MASK_SVVPTC), - - RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO), - - RISCV_EXT_FLAG_ENTRY ("xcvmac", x_riscv_xcv_subext, MASK_XCVMAC), - RISCV_EXT_FLAG_ENTRY ("xcvalu", x_riscv_xcv_subext, MASK_XCVALU), - RISCV_EXT_FLAG_ENTRY ("xcvelw", x_riscv_xcv_subext, MASK_XCVELW), - RISCV_EXT_FLAG_ENTRY ("xcvsimd", x_riscv_xcv_subext, MASK_XCVSIMD), - RISCV_EXT_FLAG_ENTRY ("xcvbi", x_riscv_xcv_subext, MASK_XCVBI), - - RISCV_EXT_FLAG_ENTRY ("xtheadba", x_riscv_xthead_subext, MASK_XTHEADBA), - RISCV_EXT_FLAG_ENTRY ("xtheadbb", x_riscv_xthead_subext, MASK_XTHEADBB), - RISCV_EXT_FLAG_ENTRY ("xtheadbs", x_riscv_xthead_subext, MASK_XTHEADBS), - RISCV_EXT_FLAG_ENTRY ("xtheadcmo", x_riscv_xthead_subext, MASK_XTHEADCMO), - RISCV_EXT_FLAG_ENTRY ("xtheadcondmov", x_riscv_xthead_subext, MASK_XTHEADCONDMOV), - RISCV_EXT_FLAG_ENTRY ("xtheadfmemidx", x_riscv_xthead_subext, MASK_XTHEADFMEMIDX), - RISCV_EXT_FLAG_ENTRY ("xtheadfmv", x_riscv_xthead_subext, MASK_XTHEADFMV), - RISCV_EXT_FLAG_ENTRY ("xtheadint", x_riscv_xthead_subext, MASK_XTHEADINT), - RISCV_EXT_FLAG_ENTRY ("xtheadmac", x_riscv_xthead_subext, MASK_XTHEADMAC), - RISCV_EXT_FLAG_ENTRY ("xtheadmemidx", x_riscv_xthead_subext, MASK_XTHEADMEMIDX), - RISCV_EXT_FLAG_ENTRY ("xtheadmempair", x_riscv_xthead_subext, MASK_XTHEADMEMPAIR), - RISCV_EXT_FLAG_ENTRY ("xtheadsync", x_riscv_xthead_subext, MASK_XTHEADSYNC), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_xthead_subext, MASK_XTHEADVECTOR), RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32), RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64), RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32), RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64), RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_flags, MASK_ZVL32B), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_flags, MASK_ZVL64B), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_flags, MASK_ZVL128B), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zf_subext, MASK_ZVFHMIN), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zf_subext, MASK_ZVFH), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_target_flags, MASK_FULL_V), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_target_flags, MASK_VECTOR), - - RISCV_EXT_FLAG_ENTRY ("xventanacondops", x_riscv_xventana_subext, MASK_XVENTANACONDOPS), - - RISCV_EXT_FLAG_ENTRY ("xsfvcp", x_riscv_sifive_subext, MASK_XSFVCP), - RISCV_EXT_FLAG_ENTRY ("xsfcease", x_riscv_sifive_subext, MASK_XSFCEASE), - RISCV_EXT_FLAG_ENTRY ("xsfvqmaccqoq", x_riscv_sifive_subext, MASK_XSFVQMACCQOQ), - RISCV_EXT_FLAG_ENTRY ("xsfvqmaccdod", x_riscv_sifive_subext, MASK_XSFVQMACCDOD), - RISCV_EXT_FLAG_ENTRY ("xsfvfnrclipxfqf", x_riscv_sifive_subext, MASK_XSFVFNRCLIPXFQF), + RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_subext, MASK_ZVL32B), + RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_subext, MASK_ZVL64B), + RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_subext, MASK_ZVL128B), + RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvf_subext, MASK_ZVFHMIN), + RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvf_subext, MASK_ZVFH), + RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_isa_flags, MASK_FULL_V), + RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_isa_flags, MASK_VECTOR), {NULL, NULL, NULL, 0} }; +/* Add extra extension flags into FLAG_TABLE for EXT. */ +static void +apply_extra_extension_flags (const char *ext, + std::vector<riscv_ext_flag_table_t> &flag_table) +{ + const riscv_extra_ext_flag_table_t *arch_ext_flag_tab; + for (arch_ext_flag_tab = &riscv_extra_ext_flag_table[0]; + arch_ext_flag_tab->ext; ++arch_ext_flag_tab) + { + if (strcmp (arch_ext_flag_tab->ext, ext) == 0) + { + flag_table.push_back ({arch_ext_flag_tab->var_ref, + arch_ext_flag_tab->cl_var_ref, + arch_ext_flag_tab->mask}); + } + } +} + /* Types for recording extension to RISC-V C-API bitmask. */ struct riscv_ext_bitmask_table_t { const char *ext; @@ -1943,24 +1556,21 @@ riscv_set_arch_by_subset_list (riscv_subset_list *subset_list, { if (opts) { - const riscv_ext_flag_table_t *arch_ext_flag_tab; /* Clean up target flags before we set. */ - for (arch_ext_flag_tab = &riscv_ext_flag_table[0]; arch_ext_flag_tab->ext; - ++arch_ext_flag_tab) - opts->*arch_ext_flag_tab->var_ref &= ~arch_ext_flag_tab->mask; + for (const auto &[ext_name, ext_info] : riscv_ext_infos) + ext_info.clean_opts (opts); if (subset_list->xlen () == 32) - opts->x_target_flags &= ~MASK_64BIT; + opts->x_riscv_isa_flags &= ~MASK_64BIT; else if (subset_list->xlen () == 64) - opts->x_target_flags |= MASK_64BIT; + opts->x_riscv_isa_flags |= MASK_64BIT; - for (arch_ext_flag_tab = &riscv_ext_flag_table[0]; - arch_ext_flag_tab->ext; - ++arch_ext_flag_tab) - { - if (subset_list->lookup (arch_ext_flag_tab->ext)) - opts->*arch_ext_flag_tab->var_ref |= arch_ext_flag_tab->mask; - } + for (const auto &[ext_name, ext_info] : riscv_ext_infos) + if (subset_list->lookup (ext_name.c_str ())) + { + /* Set the extension flag. */ + ext_info.set_opts (opts); + } } } @@ -1970,37 +1580,14 @@ bool riscv_ext_is_subset (struct cl_target_option *opts, struct cl_target_option *subset) { - const riscv_ext_flag_table_t *arch_ext_flag_tab; - for (arch_ext_flag_tab = &riscv_ext_flag_table[0]; - arch_ext_flag_tab->ext; - ++arch_ext_flag_tab) + for (const auto &[ext_name, ext_info] : riscv_ext_infos) { - if (subset->*arch_ext_flag_tab->cl_var_ref & arch_ext_flag_tab->mask) - { - if (!(opts->*arch_ext_flag_tab->cl_var_ref & arch_ext_flag_tab->mask)) - return false; - } + if (ext_info.check_opts (opts) && !ext_info.check_opts (subset)) + return false; } return true; } -/* Return the mask of ISA extension in x_target_flags of gcc_options. */ - -int -riscv_x_target_flags_isa_mask (void) -{ - int mask = 0; - const riscv_ext_flag_table_t *arch_ext_flag_tab; - for (arch_ext_flag_tab = &riscv_ext_flag_table[0]; - arch_ext_flag_tab->ext; - ++arch_ext_flag_tab) - { - if (arch_ext_flag_tab->var_ref == &gcc_options::x_target_flags) - mask |= arch_ext_flag_tab->mask; - } - return mask; -} - /* Get the minimal feature bits in Linux hwprobe of the given ISA string. Used for generating Function Multi-Versioning (FMV) dispatcher for RISC-V. @@ -2055,20 +1642,18 @@ riscv_minimal_hwprobe_feature_bits (const char *isa, search_q.pop (); /* Iterate through the implied extension table. */ - const riscv_implied_info_t *implied_info; - for (implied_info = &riscv_implied_info[0]; - implied_info->ext; - ++implied_info) + auto &ext_info = get_riscv_ext_info (search_ext); + for (const auto &implied_ext : ext_info.implied_exts ()) { /* When the search extension matches the implied extension and the implied extension has not been visited, mark the implied extension in the implied_exts set and push it into the queue. */ - if (implied_info->match (subset_list, search_ext) - && implied_exts.count (implied_info->implied_ext) == 0) + if (implied_ext.match (subset_list) + && implied_exts.count (implied_ext.implied_ext) == 0) { - implied_exts.insert (implied_info->implied_ext); - search_q.push (implied_info->implied_ext); + implied_exts.insert (implied_ext.implied_ext); + search_q.push (implied_ext.implied_ext); } } } @@ -2622,16 +2207,15 @@ riscv_arch_help (int, const char **) } }; std::map<std::string, std::set<unsigned>, extension_comparator> all_exts; - for (const riscv_ext_version &ext : riscv_ext_version_table) + for (const auto &[ext_name, ext_info] : riscv_ext_infos) { - if (!ext.name) - break; - if (ext.name[0] == 'g') - continue; - unsigned version_value = (ext.major_version * RISCV_MAJOR_VERSION_BASE) - + (ext.minor_version - * RISCV_MINOR_VERSION_BASE); - all_exts[ext.name].insert(version_value); + for (auto &supported_version : ext_info.supported_versions ()) + { + unsigned version_value + = (supported_version.major_version * RISCV_MAJOR_VERSION_BASE) + + (supported_version.minor_version * RISCV_MINOR_VERSION_BASE); + all_exts[ext_name].insert (version_value); + } } printf("All available -march extensions for RISC-V:\n"); diff --git a/gcc/config.gcc b/gcc/config.gcc index afbf82f..e552f469 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -558,6 +558,7 @@ riscv*) extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h riscv_th_vector.h sifive_vector.h" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h" + extra_options="${extra_options} riscv/riscv-ext.opt" ;; rs6000*-*-*) extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt" @@ -4459,7 +4460,7 @@ case "${target}" in case "$with_abi" in "" \ - | apcs-gnu | atpcs | aapcs | iwmmxt | aapcs-linux ) + | apcs-gnu | atpcs | aapcs | aapcs-linux ) #OK ;; *) @@ -5658,6 +5659,7 @@ case "${target}" in #TODO 'sm_[...]' list per 'nvptx-sm.def'. sm_30 | sm_35 | sm_37 \ | sm_52 | sm_53 \ + | sm_61 \ | sm_70 | sm_75 \ | sm_80 | sm_89 ) TM_MULTILIB_CONFIG="$TM_MULTILIB_CONFIG $nvptx_multilib" diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 5c30484..6dbc9fa 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4555,38 +4555,6 @@ [(set_attr "type" "csel")] ) -(define_expand "cmov<mode>6" - [(set (match_operand:GPI 0 "register_operand") - (if_then_else:GPI - (match_operator 1 "aarch64_comparison_operator" - [(match_operand:GPI 2 "register_operand") - (match_operand:GPI 3 "aarch64_plus_operand")]) - (match_operand:GPI 4 "register_operand") - (match_operand:GPI 5 "register_operand")))] - "" - " - operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], - operands[3]); - operands[3] = const0_rtx; - " -) - -(define_expand "cmov<mode>6" - [(set (match_operand:GPF 0 "register_operand") - (if_then_else:GPF - (match_operator 1 "aarch64_comparison_operator" - [(match_operand:GPF 2 "register_operand") - (match_operand:GPF 3 "aarch64_fp_compare_operand")]) - (match_operand:GPF 4 "register_operand") - (match_operand:GPF 5 "register_operand")))] - "" - " - operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], - operands[3]); - operands[3] = const0_rtx; - " -) - (define_insn "*cmov<mode>_insn" [(set (match_operand:ALLI 0 "register_operand") (if_then_else:ALLI diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h index cdce361..a9b0dfa 100644 --- a/gcc/config/arm/aout.h +++ b/gcc/config/arm/aout.h @@ -69,11 +69,6 @@ "d20", "?20", "d21", "?21", "d22", "?22", "d23", "?23", \ "d24", "?24", "d25", "?25", "d26", "?26", "d27", "?27", \ "d28", "?28", "d29", "?29", "d30", "?30", "d31", "?31", \ - "wr0", "wr1", "wr2", "wr3", \ - "wr4", "wr5", "wr6", "wr7", \ - "wr8", "wr9", "wr10", "wr11", \ - "wr12", "wr13", "wr14", "wr15", \ - "wcgr0", "wcgr1", "wcgr2", "wcgr3", \ "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0", \ "ra_auth_code" \ } diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.cc index c56ab5d..0ddc666 100644 --- a/gcc/config/arm/arm-builtins.cc +++ b/gcc/config/arm/arm-builtins.cc @@ -816,252 +816,6 @@ static arm_builtin_cde_datum cde_builtin_data[] = enum arm_builtins { - ARM_BUILTIN_GETWCGR0, - ARM_BUILTIN_GETWCGR1, - ARM_BUILTIN_GETWCGR2, - ARM_BUILTIN_GETWCGR3, - - ARM_BUILTIN_SETWCGR0, - ARM_BUILTIN_SETWCGR1, - ARM_BUILTIN_SETWCGR2, - ARM_BUILTIN_SETWCGR3, - - ARM_BUILTIN_WZERO, - - ARM_BUILTIN_WAVG2BR, - ARM_BUILTIN_WAVG2HR, - ARM_BUILTIN_WAVG2B, - ARM_BUILTIN_WAVG2H, - - ARM_BUILTIN_WACCB, - ARM_BUILTIN_WACCH, - ARM_BUILTIN_WACCW, - - ARM_BUILTIN_WMACS, - ARM_BUILTIN_WMACSZ, - ARM_BUILTIN_WMACU, - ARM_BUILTIN_WMACUZ, - - ARM_BUILTIN_WSADB, - ARM_BUILTIN_WSADBZ, - ARM_BUILTIN_WSADH, - ARM_BUILTIN_WSADHZ, - - ARM_BUILTIN_WALIGNI, - ARM_BUILTIN_WALIGNR0, - ARM_BUILTIN_WALIGNR1, - ARM_BUILTIN_WALIGNR2, - ARM_BUILTIN_WALIGNR3, - - ARM_BUILTIN_TMIA, - ARM_BUILTIN_TMIAPH, - ARM_BUILTIN_TMIABB, - ARM_BUILTIN_TMIABT, - ARM_BUILTIN_TMIATB, - ARM_BUILTIN_TMIATT, - - ARM_BUILTIN_TMOVMSKB, - ARM_BUILTIN_TMOVMSKH, - ARM_BUILTIN_TMOVMSKW, - - ARM_BUILTIN_TBCSTB, - ARM_BUILTIN_TBCSTH, - ARM_BUILTIN_TBCSTW, - - ARM_BUILTIN_WMADDS, - ARM_BUILTIN_WMADDU, - - ARM_BUILTIN_WPACKHSS, - ARM_BUILTIN_WPACKWSS, - ARM_BUILTIN_WPACKDSS, - ARM_BUILTIN_WPACKHUS, - ARM_BUILTIN_WPACKWUS, - ARM_BUILTIN_WPACKDUS, - - ARM_BUILTIN_WADDB, - ARM_BUILTIN_WADDH, - ARM_BUILTIN_WADDW, - ARM_BUILTIN_WADDSSB, - ARM_BUILTIN_WADDSSH, - ARM_BUILTIN_WADDSSW, - ARM_BUILTIN_WADDUSB, - ARM_BUILTIN_WADDUSH, - ARM_BUILTIN_WADDUSW, - ARM_BUILTIN_WSUBB, - ARM_BUILTIN_WSUBH, - ARM_BUILTIN_WSUBW, - ARM_BUILTIN_WSUBSSB, - ARM_BUILTIN_WSUBSSH, - ARM_BUILTIN_WSUBSSW, - ARM_BUILTIN_WSUBUSB, - ARM_BUILTIN_WSUBUSH, - ARM_BUILTIN_WSUBUSW, - - ARM_BUILTIN_WAND, - ARM_BUILTIN_WANDN, - ARM_BUILTIN_WOR, - ARM_BUILTIN_WXOR, - - ARM_BUILTIN_WCMPEQB, - ARM_BUILTIN_WCMPEQH, - ARM_BUILTIN_WCMPEQW, - ARM_BUILTIN_WCMPGTUB, - ARM_BUILTIN_WCMPGTUH, - ARM_BUILTIN_WCMPGTUW, - ARM_BUILTIN_WCMPGTSB, - ARM_BUILTIN_WCMPGTSH, - ARM_BUILTIN_WCMPGTSW, - - ARM_BUILTIN_TEXTRMSB, - ARM_BUILTIN_TEXTRMSH, - ARM_BUILTIN_TEXTRMSW, - ARM_BUILTIN_TEXTRMUB, - ARM_BUILTIN_TEXTRMUH, - ARM_BUILTIN_TEXTRMUW, - ARM_BUILTIN_TINSRB, - ARM_BUILTIN_TINSRH, - ARM_BUILTIN_TINSRW, - - ARM_BUILTIN_WMAXSW, - ARM_BUILTIN_WMAXSH, - ARM_BUILTIN_WMAXSB, - ARM_BUILTIN_WMAXUW, - ARM_BUILTIN_WMAXUH, - ARM_BUILTIN_WMAXUB, - ARM_BUILTIN_WMINSW, - ARM_BUILTIN_WMINSH, - ARM_BUILTIN_WMINSB, - ARM_BUILTIN_WMINUW, - ARM_BUILTIN_WMINUH, - ARM_BUILTIN_WMINUB, - - ARM_BUILTIN_WMULUM, - ARM_BUILTIN_WMULSM, - ARM_BUILTIN_WMULUL, - - ARM_BUILTIN_PSADBH, - ARM_BUILTIN_WSHUFH, - - ARM_BUILTIN_WSLLH, - ARM_BUILTIN_WSLLW, - ARM_BUILTIN_WSLLD, - ARM_BUILTIN_WSRAH, - ARM_BUILTIN_WSRAW, - ARM_BUILTIN_WSRAD, - ARM_BUILTIN_WSRLH, - ARM_BUILTIN_WSRLW, - ARM_BUILTIN_WSRLD, - ARM_BUILTIN_WRORH, - ARM_BUILTIN_WRORW, - ARM_BUILTIN_WRORD, - ARM_BUILTIN_WSLLHI, - ARM_BUILTIN_WSLLWI, - ARM_BUILTIN_WSLLDI, - ARM_BUILTIN_WSRAHI, - ARM_BUILTIN_WSRAWI, - ARM_BUILTIN_WSRADI, - ARM_BUILTIN_WSRLHI, - ARM_BUILTIN_WSRLWI, - ARM_BUILTIN_WSRLDI, - ARM_BUILTIN_WRORHI, - ARM_BUILTIN_WRORWI, - ARM_BUILTIN_WRORDI, - - ARM_BUILTIN_WUNPCKIHB, - ARM_BUILTIN_WUNPCKIHH, - ARM_BUILTIN_WUNPCKIHW, - ARM_BUILTIN_WUNPCKILB, - ARM_BUILTIN_WUNPCKILH, - ARM_BUILTIN_WUNPCKILW, - - ARM_BUILTIN_WUNPCKEHSB, - ARM_BUILTIN_WUNPCKEHSH, - ARM_BUILTIN_WUNPCKEHSW, - ARM_BUILTIN_WUNPCKEHUB, - ARM_BUILTIN_WUNPCKEHUH, - ARM_BUILTIN_WUNPCKEHUW, - ARM_BUILTIN_WUNPCKELSB, - ARM_BUILTIN_WUNPCKELSH, - ARM_BUILTIN_WUNPCKELSW, - ARM_BUILTIN_WUNPCKELUB, - ARM_BUILTIN_WUNPCKELUH, - ARM_BUILTIN_WUNPCKELUW, - - ARM_BUILTIN_WABSB, - ARM_BUILTIN_WABSH, - ARM_BUILTIN_WABSW, - - ARM_BUILTIN_WADDSUBHX, - ARM_BUILTIN_WSUBADDHX, - - ARM_BUILTIN_WABSDIFFB, - ARM_BUILTIN_WABSDIFFH, - ARM_BUILTIN_WABSDIFFW, - - ARM_BUILTIN_WADDCH, - ARM_BUILTIN_WADDCW, - - ARM_BUILTIN_WAVG4, - ARM_BUILTIN_WAVG4R, - - ARM_BUILTIN_WMADDSX, - ARM_BUILTIN_WMADDUX, - - ARM_BUILTIN_WMADDSN, - ARM_BUILTIN_WMADDUN, - - ARM_BUILTIN_WMULWSM, - ARM_BUILTIN_WMULWUM, - - ARM_BUILTIN_WMULWSMR, - ARM_BUILTIN_WMULWUMR, - - ARM_BUILTIN_WMULWL, - - ARM_BUILTIN_WMULSMR, - ARM_BUILTIN_WMULUMR, - - ARM_BUILTIN_WQMULM, - ARM_BUILTIN_WQMULMR, - - ARM_BUILTIN_WQMULWM, - ARM_BUILTIN_WQMULWMR, - - ARM_BUILTIN_WADDBHUSM, - ARM_BUILTIN_WADDBHUSL, - - ARM_BUILTIN_WQMIABB, - ARM_BUILTIN_WQMIABT, - ARM_BUILTIN_WQMIATB, - ARM_BUILTIN_WQMIATT, - - ARM_BUILTIN_WQMIABBN, - ARM_BUILTIN_WQMIABTN, - ARM_BUILTIN_WQMIATBN, - ARM_BUILTIN_WQMIATTN, - - ARM_BUILTIN_WMIABB, - ARM_BUILTIN_WMIABT, - ARM_BUILTIN_WMIATB, - ARM_BUILTIN_WMIATT, - - ARM_BUILTIN_WMIABBN, - ARM_BUILTIN_WMIABTN, - ARM_BUILTIN_WMIATBN, - ARM_BUILTIN_WMIATTN, - - ARM_BUILTIN_WMIAWBB, - ARM_BUILTIN_WMIAWBT, - ARM_BUILTIN_WMIAWTB, - ARM_BUILTIN_WMIAWTT, - - ARM_BUILTIN_WMIAWBBN, - ARM_BUILTIN_WMIAWBTN, - ARM_BUILTIN_WMIAWTBN, - ARM_BUILTIN_WMIAWTTN, - - ARM_BUILTIN_WMERGE, - ARM_BUILTIN_GET_FPSCR, ARM_BUILTIN_SET_FPSCR, ARM_BUILTIN_GET_FPSCR_NZCVQC, @@ -1878,115 +1632,6 @@ struct builtin_description static const struct builtin_description bdesc_2arg[] = { -#define IWMMXT_BUILTIN(code, string, builtin) \ - { isa_bit_iwmmxt, CODE_FOR_##code, \ - "__builtin_arm_" string, \ - ARM_BUILTIN_##builtin, UNKNOWN, 0 }, - -#define IWMMXT2_BUILTIN(code, string, builtin) \ - { isa_bit_iwmmxt2, CODE_FOR_##code, \ - "__builtin_arm_" string, \ - ARM_BUILTIN_##builtin, UNKNOWN, 0 }, - - IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB) - IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH) - IWMMXT_BUILTIN (addv2si3, "waddw", WADDW) - IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB) - IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH) - IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW) - IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB) - IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH) - IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW) - IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB) - IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH) - IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW) - IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB) - IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH) - IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW) - IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB) - IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH) - IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW) - IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL) - IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM) - IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM) - IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB) - IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH) - IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW) - IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB) - IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH) - IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW) - IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB) - IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH) - IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW) - IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB) - IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB) - IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH) - IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH) - IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW) - IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW) - IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB) - IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB) - IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH) - IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH) - IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW) - IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW) - IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND) - IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN) - IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR) - IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR) - IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B) - IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H) - IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR) - IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR) - IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB) - IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH) - IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW) - IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB) - IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH) - IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW) - IWMMXT2_BUILTIN (iwmmxt_waddsubhx, "waddsubhx", WADDSUBHX) - IWMMXT2_BUILTIN (iwmmxt_wsubaddhx, "wsubaddhx", WSUBADDHX) - IWMMXT2_BUILTIN (iwmmxt_wabsdiffb, "wabsdiffb", WABSDIFFB) - IWMMXT2_BUILTIN (iwmmxt_wabsdiffh, "wabsdiffh", WABSDIFFH) - IWMMXT2_BUILTIN (iwmmxt_wabsdiffw, "wabsdiffw", WABSDIFFW) - IWMMXT2_BUILTIN (iwmmxt_avg4, "wavg4", WAVG4) - IWMMXT2_BUILTIN (iwmmxt_avg4r, "wavg4r", WAVG4R) - IWMMXT2_BUILTIN (iwmmxt_wmulwsm, "wmulwsm", WMULWSM) - IWMMXT2_BUILTIN (iwmmxt_wmulwum, "wmulwum", WMULWUM) - IWMMXT2_BUILTIN (iwmmxt_wmulwsmr, "wmulwsmr", WMULWSMR) - IWMMXT2_BUILTIN (iwmmxt_wmulwumr, "wmulwumr", WMULWUMR) - IWMMXT2_BUILTIN (iwmmxt_wmulwl, "wmulwl", WMULWL) - IWMMXT2_BUILTIN (iwmmxt_wmulsmr, "wmulsmr", WMULSMR) - IWMMXT2_BUILTIN (iwmmxt_wmulumr, "wmulumr", WMULUMR) - IWMMXT2_BUILTIN (iwmmxt_wqmulm, "wqmulm", WQMULM) - IWMMXT2_BUILTIN (iwmmxt_wqmulmr, "wqmulmr", WQMULMR) - IWMMXT2_BUILTIN (iwmmxt_wqmulwm, "wqmulwm", WQMULWM) - IWMMXT2_BUILTIN (iwmmxt_wqmulwmr, "wqmulwmr", WQMULWMR) - IWMMXT_BUILTIN (iwmmxt_walignr0, "walignr0", WALIGNR0) - IWMMXT_BUILTIN (iwmmxt_walignr1, "walignr1", WALIGNR1) - IWMMXT_BUILTIN (iwmmxt_walignr2, "walignr2", WALIGNR2) - IWMMXT_BUILTIN (iwmmxt_walignr3, "walignr3", WALIGNR3) - -#define IWMMXT_BUILTIN2(code, builtin) \ - { isa_bit_iwmmxt, CODE_FOR_##code, NULL, \ - ARM_BUILTIN_##builtin, UNKNOWN, 0 }, - -#define IWMMXT2_BUILTIN2(code, builtin) \ - { isa_bit_iwmmxt2, CODE_FOR_##code, NULL, \ - ARM_BUILTIN_##builtin, UNKNOWN, 0 }, - - IWMMXT2_BUILTIN2 (iwmmxt_waddbhusm, WADDBHUSM) - IWMMXT2_BUILTIN2 (iwmmxt_waddbhusl, WADDBHUSL) - IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS) - IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS) - IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS) - IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS) - IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS) - IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS) - IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ) - IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ) - - #define FP_BUILTIN(L, U) \ {isa_nobit, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \ UNKNOWN, 0}, @@ -2013,31 +1658,6 @@ static const struct builtin_description bdesc_2arg[] = static const struct builtin_description bdesc_1arg[] = { - IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB) - IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH) - IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW) - IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB) - IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH) - IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW) - IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB) - IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH) - IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW) - IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB) - IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH) - IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW) - IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB) - IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH) - IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW) - IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB) - IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH) - IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW) - IWMMXT2_BUILTIN (iwmmxt_wabsv8qi3, "wabsb", WABSB) - IWMMXT2_BUILTIN (iwmmxt_wabsv4hi3, "wabsh", WABSH) - IWMMXT2_BUILTIN (iwmmxt_wabsv2si3, "wabsw", WABSW) - IWMMXT_BUILTIN (tbcstv8qi, "tbcstb", TBCSTB) - IWMMXT_BUILTIN (tbcstv4hi, "tbcsth", TBCSTH) - IWMMXT_BUILTIN (tbcstv2si, "tbcstw", TBCSTW) - #define CRYPTO1(L, U, R, A) CRYPTO_BUILTIN (L, U) #define CRYPTO2(L, U, R, A1, A2) #define CRYPTO3(L, U, R, A1, A2, A3) @@ -2059,387 +1679,6 @@ static const struct builtin_description bdesc_3arg[] = }; #undef CRYPTO_BUILTIN -/* Set up all the iWMMXt builtins. This is not called if - TARGET_IWMMXT is zero. */ - -static void -arm_init_iwmmxt_builtins (void) -{ - const struct builtin_description * d; - size_t i; - - tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode); - tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode); - tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode); - - tree v8qi_ftype_v8qi_v8qi_int - = build_function_type_list (V8QI_type_node, - V8QI_type_node, V8QI_type_node, - integer_type_node, NULL_TREE); - tree v4hi_ftype_v4hi_int - = build_function_type_list (V4HI_type_node, - V4HI_type_node, integer_type_node, NULL_TREE); - tree v2si_ftype_v2si_int - = build_function_type_list (V2SI_type_node, - V2SI_type_node, integer_type_node, NULL_TREE); - tree v2si_ftype_di_di - = build_function_type_list (V2SI_type_node, - long_long_integer_type_node, - long_long_integer_type_node, - NULL_TREE); - tree di_ftype_di_int - = build_function_type_list (long_long_integer_type_node, - long_long_integer_type_node, - integer_type_node, NULL_TREE); - tree di_ftype_di_int_int - = build_function_type_list (long_long_integer_type_node, - long_long_integer_type_node, - integer_type_node, - integer_type_node, NULL_TREE); - tree int_ftype_v8qi - = build_function_type_list (integer_type_node, - V8QI_type_node, NULL_TREE); - tree int_ftype_v4hi - = build_function_type_list (integer_type_node, - V4HI_type_node, NULL_TREE); - tree int_ftype_v2si - = build_function_type_list (integer_type_node, - V2SI_type_node, NULL_TREE); - tree int_ftype_v8qi_int - = build_function_type_list (integer_type_node, - V8QI_type_node, integer_type_node, NULL_TREE); - tree int_ftype_v4hi_int - = build_function_type_list (integer_type_node, - V4HI_type_node, integer_type_node, NULL_TREE); - tree int_ftype_v2si_int - = build_function_type_list (integer_type_node, - V2SI_type_node, integer_type_node, NULL_TREE); - tree v8qi_ftype_v8qi_int_int - = build_function_type_list (V8QI_type_node, - V8QI_type_node, integer_type_node, - integer_type_node, NULL_TREE); - tree v4hi_ftype_v4hi_int_int - = build_function_type_list (V4HI_type_node, - V4HI_type_node, integer_type_node, - integer_type_node, NULL_TREE); - tree v2si_ftype_v2si_int_int - = build_function_type_list (V2SI_type_node, - V2SI_type_node, integer_type_node, - integer_type_node, NULL_TREE); - /* Miscellaneous. */ - tree v8qi_ftype_v4hi_v4hi - = build_function_type_list (V8QI_type_node, - V4HI_type_node, V4HI_type_node, NULL_TREE); - tree v4hi_ftype_v2si_v2si - = build_function_type_list (V4HI_type_node, - V2SI_type_node, V2SI_type_node, NULL_TREE); - tree v8qi_ftype_v4hi_v8qi - = build_function_type_list (V8QI_type_node, - V4HI_type_node, V8QI_type_node, NULL_TREE); - tree v2si_ftype_v4hi_v4hi - = build_function_type_list (V2SI_type_node, - V4HI_type_node, V4HI_type_node, NULL_TREE); - tree v2si_ftype_v8qi_v8qi - = build_function_type_list (V2SI_type_node, - V8QI_type_node, V8QI_type_node, NULL_TREE); - tree v4hi_ftype_v4hi_di - = build_function_type_list (V4HI_type_node, - V4HI_type_node, long_long_integer_type_node, - NULL_TREE); - tree v2si_ftype_v2si_di - = build_function_type_list (V2SI_type_node, - V2SI_type_node, long_long_integer_type_node, - NULL_TREE); - tree di_ftype_void - = build_function_type_list (long_long_unsigned_type_node, NULL_TREE); - tree int_ftype_void - = build_function_type_list (integer_type_node, NULL_TREE); - tree di_ftype_v8qi - = build_function_type_list (long_long_integer_type_node, - V8QI_type_node, NULL_TREE); - tree di_ftype_v4hi - = build_function_type_list (long_long_integer_type_node, - V4HI_type_node, NULL_TREE); - tree di_ftype_v2si - = build_function_type_list (long_long_integer_type_node, - V2SI_type_node, NULL_TREE); - tree v2si_ftype_v4hi - = build_function_type_list (V2SI_type_node, - V4HI_type_node, NULL_TREE); - tree v4hi_ftype_v8qi - = build_function_type_list (V4HI_type_node, - V8QI_type_node, NULL_TREE); - tree v8qi_ftype_v8qi - = build_function_type_list (V8QI_type_node, - V8QI_type_node, NULL_TREE); - tree v4hi_ftype_v4hi - = build_function_type_list (V4HI_type_node, - V4HI_type_node, NULL_TREE); - tree v2si_ftype_v2si - = build_function_type_list (V2SI_type_node, - V2SI_type_node, NULL_TREE); - - tree di_ftype_di_v4hi_v4hi - = build_function_type_list (long_long_unsigned_type_node, - long_long_unsigned_type_node, - V4HI_type_node, V4HI_type_node, - NULL_TREE); - - tree di_ftype_v4hi_v4hi - = build_function_type_list (long_long_unsigned_type_node, - V4HI_type_node,V4HI_type_node, - NULL_TREE); - - tree v2si_ftype_v2si_v4hi_v4hi - = build_function_type_list (V2SI_type_node, - V2SI_type_node, V4HI_type_node, - V4HI_type_node, NULL_TREE); - - tree v2si_ftype_v2si_v8qi_v8qi - = build_function_type_list (V2SI_type_node, - V2SI_type_node, V8QI_type_node, - V8QI_type_node, NULL_TREE); - - tree di_ftype_di_v2si_v2si - = build_function_type_list (long_long_unsigned_type_node, - long_long_unsigned_type_node, - V2SI_type_node, V2SI_type_node, - NULL_TREE); - - tree di_ftype_di_di_int - = build_function_type_list (long_long_unsigned_type_node, - long_long_unsigned_type_node, - long_long_unsigned_type_node, - integer_type_node, NULL_TREE); - - tree void_ftype_int - = build_function_type_list (void_type_node, - integer_type_node, NULL_TREE); - - tree v8qi_ftype_char - = build_function_type_list (V8QI_type_node, - signed_char_type_node, NULL_TREE); - - tree v4hi_ftype_short - = build_function_type_list (V4HI_type_node, - short_integer_type_node, NULL_TREE); - - tree v2si_ftype_int - = build_function_type_list (V2SI_type_node, - integer_type_node, NULL_TREE); - - /* Normal vector binops. */ - tree v8qi_ftype_v8qi_v8qi - = build_function_type_list (V8QI_type_node, - V8QI_type_node, V8QI_type_node, NULL_TREE); - tree v4hi_ftype_v4hi_v4hi - = build_function_type_list (V4HI_type_node, - V4HI_type_node,V4HI_type_node, NULL_TREE); - tree v2si_ftype_v2si_v2si - = build_function_type_list (V2SI_type_node, - V2SI_type_node, V2SI_type_node, NULL_TREE); - tree di_ftype_di_di - = build_function_type_list (long_long_unsigned_type_node, - long_long_unsigned_type_node, - long_long_unsigned_type_node, - NULL_TREE); - - /* Add all builtins that are more or less simple operations on two - operands. */ - for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) - { - /* Use one of the operands; the target can have a different mode for - mask-generating compares. */ - machine_mode mode; - tree type; - - if (d->name == 0 - || !(d->feature == isa_bit_iwmmxt - || d->feature == isa_bit_iwmmxt2)) - continue; - - mode = insn_data[d->icode].operand[1].mode; - - switch (mode) - { - case E_V8QImode: - type = v8qi_ftype_v8qi_v8qi; - break; - case E_V4HImode: - type = v4hi_ftype_v4hi_v4hi; - break; - case E_V2SImode: - type = v2si_ftype_v2si_v2si; - break; - case E_DImode: - type = di_ftype_di_di; - break; - - default: - gcc_unreachable (); - } - - def_mbuiltin (d->feature, d->name, type, d->code); - } - - /* Add the remaining MMX insns with somewhat more complicated types. */ -#define iwmmx_mbuiltin(NAME, TYPE, CODE) \ - def_mbuiltin (isa_bit_iwmmxt, "__builtin_arm_" NAME, \ - (TYPE), ARM_BUILTIN_ ## CODE) - -#define iwmmx2_mbuiltin(NAME, TYPE, CODE) \ - def_mbuiltin (isa_bit_iwmmxt2, "__builtin_arm_" NAME, \ - (TYPE), ARM_BUILTIN_ ## CODE) - - iwmmx_mbuiltin ("wzero", di_ftype_void, WZERO); - iwmmx_mbuiltin ("setwcgr0", void_ftype_int, SETWCGR0); - iwmmx_mbuiltin ("setwcgr1", void_ftype_int, SETWCGR1); - iwmmx_mbuiltin ("setwcgr2", void_ftype_int, SETWCGR2); - iwmmx_mbuiltin ("setwcgr3", void_ftype_int, SETWCGR3); - iwmmx_mbuiltin ("getwcgr0", int_ftype_void, GETWCGR0); - iwmmx_mbuiltin ("getwcgr1", int_ftype_void, GETWCGR1); - iwmmx_mbuiltin ("getwcgr2", int_ftype_void, GETWCGR2); - iwmmx_mbuiltin ("getwcgr3", int_ftype_void, GETWCGR3); - - iwmmx_mbuiltin ("wsllh", v4hi_ftype_v4hi_di, WSLLH); - iwmmx_mbuiltin ("wsllw", v2si_ftype_v2si_di, WSLLW); - iwmmx_mbuiltin ("wslld", di_ftype_di_di, WSLLD); - iwmmx_mbuiltin ("wsllhi", v4hi_ftype_v4hi_int, WSLLHI); - iwmmx_mbuiltin ("wsllwi", v2si_ftype_v2si_int, WSLLWI); - iwmmx_mbuiltin ("wslldi", di_ftype_di_int, WSLLDI); - - iwmmx_mbuiltin ("wsrlh", v4hi_ftype_v4hi_di, WSRLH); - iwmmx_mbuiltin ("wsrlw", v2si_ftype_v2si_di, WSRLW); - iwmmx_mbuiltin ("wsrld", di_ftype_di_di, WSRLD); - iwmmx_mbuiltin ("wsrlhi", v4hi_ftype_v4hi_int, WSRLHI); - iwmmx_mbuiltin ("wsrlwi", v2si_ftype_v2si_int, WSRLWI); - iwmmx_mbuiltin ("wsrldi", di_ftype_di_int, WSRLDI); - - iwmmx_mbuiltin ("wsrah", v4hi_ftype_v4hi_di, WSRAH); - iwmmx_mbuiltin ("wsraw", v2si_ftype_v2si_di, WSRAW); - iwmmx_mbuiltin ("wsrad", di_ftype_di_di, WSRAD); - iwmmx_mbuiltin ("wsrahi", v4hi_ftype_v4hi_int, WSRAHI); - iwmmx_mbuiltin ("wsrawi", v2si_ftype_v2si_int, WSRAWI); - iwmmx_mbuiltin ("wsradi", di_ftype_di_int, WSRADI); - - iwmmx_mbuiltin ("wrorh", v4hi_ftype_v4hi_di, WRORH); - iwmmx_mbuiltin ("wrorw", v2si_ftype_v2si_di, WRORW); - iwmmx_mbuiltin ("wrord", di_ftype_di_di, WRORD); - iwmmx_mbuiltin ("wrorhi", v4hi_ftype_v4hi_int, WRORHI); - iwmmx_mbuiltin ("wrorwi", v2si_ftype_v2si_int, WRORWI); - iwmmx_mbuiltin ("wrordi", di_ftype_di_int, WRORDI); - - iwmmx_mbuiltin ("wshufh", v4hi_ftype_v4hi_int, WSHUFH); - - iwmmx_mbuiltin ("wsadb", v2si_ftype_v2si_v8qi_v8qi, WSADB); - iwmmx_mbuiltin ("wsadh", v2si_ftype_v2si_v4hi_v4hi, WSADH); - iwmmx_mbuiltin ("wmadds", v2si_ftype_v4hi_v4hi, WMADDS); - iwmmx2_mbuiltin ("wmaddsx", v2si_ftype_v4hi_v4hi, WMADDSX); - iwmmx2_mbuiltin ("wmaddsn", v2si_ftype_v4hi_v4hi, WMADDSN); - iwmmx_mbuiltin ("wmaddu", v2si_ftype_v4hi_v4hi, WMADDU); - iwmmx2_mbuiltin ("wmaddux", v2si_ftype_v4hi_v4hi, WMADDUX); - iwmmx2_mbuiltin ("wmaddun", v2si_ftype_v4hi_v4hi, WMADDUN); - iwmmx_mbuiltin ("wsadbz", v2si_ftype_v8qi_v8qi, WSADBZ); - iwmmx_mbuiltin ("wsadhz", v2si_ftype_v4hi_v4hi, WSADHZ); - - iwmmx_mbuiltin ("textrmsb", int_ftype_v8qi_int, TEXTRMSB); - iwmmx_mbuiltin ("textrmsh", int_ftype_v4hi_int, TEXTRMSH); - iwmmx_mbuiltin ("textrmsw", int_ftype_v2si_int, TEXTRMSW); - iwmmx_mbuiltin ("textrmub", int_ftype_v8qi_int, TEXTRMUB); - iwmmx_mbuiltin ("textrmuh", int_ftype_v4hi_int, TEXTRMUH); - iwmmx_mbuiltin ("textrmuw", int_ftype_v2si_int, TEXTRMUW); - iwmmx_mbuiltin ("tinsrb", v8qi_ftype_v8qi_int_int, TINSRB); - iwmmx_mbuiltin ("tinsrh", v4hi_ftype_v4hi_int_int, TINSRH); - iwmmx_mbuiltin ("tinsrw", v2si_ftype_v2si_int_int, TINSRW); - - iwmmx_mbuiltin ("waccb", di_ftype_v8qi, WACCB); - iwmmx_mbuiltin ("wacch", di_ftype_v4hi, WACCH); - iwmmx_mbuiltin ("waccw", di_ftype_v2si, WACCW); - - iwmmx_mbuiltin ("tmovmskb", int_ftype_v8qi, TMOVMSKB); - iwmmx_mbuiltin ("tmovmskh", int_ftype_v4hi, TMOVMSKH); - iwmmx_mbuiltin ("tmovmskw", int_ftype_v2si, TMOVMSKW); - - iwmmx2_mbuiltin ("waddbhusm", v8qi_ftype_v4hi_v8qi, WADDBHUSM); - iwmmx2_mbuiltin ("waddbhusl", v8qi_ftype_v4hi_v8qi, WADDBHUSL); - - iwmmx_mbuiltin ("wpackhss", v8qi_ftype_v4hi_v4hi, WPACKHSS); - iwmmx_mbuiltin ("wpackhus", v8qi_ftype_v4hi_v4hi, WPACKHUS); - iwmmx_mbuiltin ("wpackwus", v4hi_ftype_v2si_v2si, WPACKWUS); - iwmmx_mbuiltin ("wpackwss", v4hi_ftype_v2si_v2si, WPACKWSS); - iwmmx_mbuiltin ("wpackdus", v2si_ftype_di_di, WPACKDUS); - iwmmx_mbuiltin ("wpackdss", v2si_ftype_di_di, WPACKDSS); - - iwmmx_mbuiltin ("wunpckehub", v4hi_ftype_v8qi, WUNPCKEHUB); - iwmmx_mbuiltin ("wunpckehuh", v2si_ftype_v4hi, WUNPCKEHUH); - iwmmx_mbuiltin ("wunpckehuw", di_ftype_v2si, WUNPCKEHUW); - iwmmx_mbuiltin ("wunpckehsb", v4hi_ftype_v8qi, WUNPCKEHSB); - iwmmx_mbuiltin ("wunpckehsh", v2si_ftype_v4hi, WUNPCKEHSH); - iwmmx_mbuiltin ("wunpckehsw", di_ftype_v2si, WUNPCKEHSW); - iwmmx_mbuiltin ("wunpckelub", v4hi_ftype_v8qi, WUNPCKELUB); - iwmmx_mbuiltin ("wunpckeluh", v2si_ftype_v4hi, WUNPCKELUH); - iwmmx_mbuiltin ("wunpckeluw", di_ftype_v2si, WUNPCKELUW); - iwmmx_mbuiltin ("wunpckelsb", v4hi_ftype_v8qi, WUNPCKELSB); - iwmmx_mbuiltin ("wunpckelsh", v2si_ftype_v4hi, WUNPCKELSH); - iwmmx_mbuiltin ("wunpckelsw", di_ftype_v2si, WUNPCKELSW); - - iwmmx_mbuiltin ("wmacs", di_ftype_di_v4hi_v4hi, WMACS); - iwmmx_mbuiltin ("wmacsz", di_ftype_v4hi_v4hi, WMACSZ); - iwmmx_mbuiltin ("wmacu", di_ftype_di_v4hi_v4hi, WMACU); - iwmmx_mbuiltin ("wmacuz", di_ftype_v4hi_v4hi, WMACUZ); - - iwmmx_mbuiltin ("walign", v8qi_ftype_v8qi_v8qi_int, WALIGNI); - iwmmx_mbuiltin ("tmia", di_ftype_di_int_int, TMIA); - iwmmx_mbuiltin ("tmiaph", di_ftype_di_int_int, TMIAPH); - iwmmx_mbuiltin ("tmiabb", di_ftype_di_int_int, TMIABB); - iwmmx_mbuiltin ("tmiabt", di_ftype_di_int_int, TMIABT); - iwmmx_mbuiltin ("tmiatb", di_ftype_di_int_int, TMIATB); - iwmmx_mbuiltin ("tmiatt", di_ftype_di_int_int, TMIATT); - - iwmmx2_mbuiltin ("wabsb", v8qi_ftype_v8qi, WABSB); - iwmmx2_mbuiltin ("wabsh", v4hi_ftype_v4hi, WABSH); - iwmmx2_mbuiltin ("wabsw", v2si_ftype_v2si, WABSW); - - iwmmx2_mbuiltin ("wqmiabb", v2si_ftype_v2si_v4hi_v4hi, WQMIABB); - iwmmx2_mbuiltin ("wqmiabt", v2si_ftype_v2si_v4hi_v4hi, WQMIABT); - iwmmx2_mbuiltin ("wqmiatb", v2si_ftype_v2si_v4hi_v4hi, WQMIATB); - iwmmx2_mbuiltin ("wqmiatt", v2si_ftype_v2si_v4hi_v4hi, WQMIATT); - - iwmmx2_mbuiltin ("wqmiabbn", v2si_ftype_v2si_v4hi_v4hi, WQMIABBN); - iwmmx2_mbuiltin ("wqmiabtn", v2si_ftype_v2si_v4hi_v4hi, WQMIABTN); - iwmmx2_mbuiltin ("wqmiatbn", v2si_ftype_v2si_v4hi_v4hi, WQMIATBN); - iwmmx2_mbuiltin ("wqmiattn", v2si_ftype_v2si_v4hi_v4hi, WQMIATTN); - - iwmmx2_mbuiltin ("wmiabb", di_ftype_di_v4hi_v4hi, WMIABB); - iwmmx2_mbuiltin ("wmiabt", di_ftype_di_v4hi_v4hi, WMIABT); - iwmmx2_mbuiltin ("wmiatb", di_ftype_di_v4hi_v4hi, WMIATB); - iwmmx2_mbuiltin ("wmiatt", di_ftype_di_v4hi_v4hi, WMIATT); - - iwmmx2_mbuiltin ("wmiabbn", di_ftype_di_v4hi_v4hi, WMIABBN); - iwmmx2_mbuiltin ("wmiabtn", di_ftype_di_v4hi_v4hi, WMIABTN); - iwmmx2_mbuiltin ("wmiatbn", di_ftype_di_v4hi_v4hi, WMIATBN); - iwmmx2_mbuiltin ("wmiattn", di_ftype_di_v4hi_v4hi, WMIATTN); - - iwmmx2_mbuiltin ("wmiawbb", di_ftype_di_v2si_v2si, WMIAWBB); - iwmmx2_mbuiltin ("wmiawbt", di_ftype_di_v2si_v2si, WMIAWBT); - iwmmx2_mbuiltin ("wmiawtb", di_ftype_di_v2si_v2si, WMIAWTB); - iwmmx2_mbuiltin ("wmiawtt", di_ftype_di_v2si_v2si, WMIAWTT); - - iwmmx2_mbuiltin ("wmiawbbn", di_ftype_di_v2si_v2si, WMIAWBBN); - iwmmx2_mbuiltin ("wmiawbtn", di_ftype_di_v2si_v2si, WMIAWBTN); - iwmmx2_mbuiltin ("wmiawtbn", di_ftype_di_v2si_v2si, WMIAWTBN); - iwmmx2_mbuiltin ("wmiawttn", di_ftype_di_v2si_v2si, WMIAWTTN); - - iwmmx2_mbuiltin ("wmerge", di_ftype_di_di_int, WMERGE); - - iwmmx_mbuiltin ("tbcstb", v8qi_ftype_char, TBCSTB); - iwmmx_mbuiltin ("tbcsth", v4hi_ftype_short, TBCSTH); - iwmmx_mbuiltin ("tbcstw", v2si_ftype_int, TBCSTW); - -#undef iwmmx_mbuiltin -#undef iwmmx2_mbuiltin -} - static void arm_init_fp16_builtins (void) { @@ -2454,9 +1693,6 @@ arm_init_fp16_builtins (void) void arm_init_builtins (void) { - if (TARGET_REALLY_IWMMXT) - arm_init_iwmmxt_builtins (); - /* This creates the arm_simd_floatHF_type_node so must come before arm_init_neon_builtins which uses it. */ arm_init_fp16_builtins (); @@ -2546,15 +1782,11 @@ arm_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) clear instructions. */ static rtx -safe_vector_operand (rtx x, machine_mode mode) +safe_vector_operand (rtx x, machine_mode mode ATTRIBUTE_UNUSED) { if (x != const0_rtx) return x; - x = gen_reg_rtx (mode); - - emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x - : gen_rtx_SUBREG (DImode, x, 0))); - return x; + __builtin_unreachable (); } /* Function to expand ternary builtins. */ @@ -3266,21 +2498,10 @@ arm_general_expand_builtin (unsigned int fcode, const struct builtin_description * d; enum insn_code icode; tree arg0; - tree arg1; - tree arg2; rtx op0; rtx op1; - rtx op2; rtx pat; size_t i; - machine_mode tmode; - machine_mode mode0; - machine_mode mode1; - machine_mode mode2; - int opint; - int selector; - int mask; - int imm; if (fcode == ARM_BUILTIN_SIMD_LANE_CHECK) { @@ -3369,499 +2590,6 @@ arm_general_expand_builtin (unsigned int fcode, emit_insn (gen_cstoresi4 (target, op1, target, const0_rtx)); return target; - case ARM_BUILTIN_TEXTRMSB: - case ARM_BUILTIN_TEXTRMUB: - case ARM_BUILTIN_TEXTRMSH: - case ARM_BUILTIN_TEXTRMUH: - case ARM_BUILTIN_TEXTRMSW: - case ARM_BUILTIN_TEXTRMUW: - icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb - : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub - : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh - : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh - : CODE_FOR_iwmmxt_textrmw); - - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - op0 = expand_normal (arg0); - op1 = expand_normal (arg1); - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - { - /* @@@ better error message */ - error ("selector must be an immediate"); - return gen_reg_rtx (tmode); - } - - opint = INTVAL (op1); - if (fcode == ARM_BUILTIN_TEXTRMSB || fcode == ARM_BUILTIN_TEXTRMUB) - { - if (opint > 7 || opint < 0) - error ("the range of selector should be in 0 to 7"); - } - else if (fcode == ARM_BUILTIN_TEXTRMSH || fcode == ARM_BUILTIN_TEXTRMUH) - { - if (opint > 3 || opint < 0) - error ("the range of selector should be in 0 to 3"); - } - else /* ARM_BUILTIN_TEXTRMSW || ARM_BUILTIN_TEXTRMUW. */ - { - if (opint > 1 || opint < 0) - error ("the range of selector should be in 0 to 1"); - } - - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target, op0, op1); - if (! pat) - return 0; - emit_insn (pat); - return target; - - case ARM_BUILTIN_WALIGNI: - /* If op2 is immediate, call walighi, else call walighr. */ - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - arg2 = CALL_EXPR_ARG (exp, 2); - op0 = expand_normal (arg0); - op1 = expand_normal (arg1); - op2 = expand_normal (arg2); - if (CONST_INT_P (op2)) - { - icode = CODE_FOR_iwmmxt_waligni; - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - mode2 = insn_data[icode].operand[3].mode; - if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - gcc_assert ((*insn_data[icode].operand[3].predicate) (op2, mode2)); - selector = INTVAL (op2); - if (selector > 7 || selector < 0) - error ("the range of selector should be in 0 to 7"); - } - else - { - icode = CODE_FOR_iwmmxt_walignr; - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - mode2 = insn_data[icode].operand[3].mode; - if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - if (!(*insn_data[icode].operand[3].predicate) (op2, mode2)) - op2 = copy_to_mode_reg (mode2, op2); - } - if (target == 0 - || GET_MODE (target) != tmode - || !(*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target, op0, op1, op2); - if (!pat) - return 0; - emit_insn (pat); - return target; - - case ARM_BUILTIN_TINSRB: - case ARM_BUILTIN_TINSRH: - case ARM_BUILTIN_TINSRW: - case ARM_BUILTIN_WMERGE: - icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb - : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh - : fcode == ARM_BUILTIN_WMERGE ? CODE_FOR_iwmmxt_wmerge - : CODE_FOR_iwmmxt_tinsrw); - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - arg2 = CALL_EXPR_ARG (exp, 2); - op0 = expand_normal (arg0); - op1 = expand_normal (arg1); - op2 = expand_normal (arg2); - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - mode2 = insn_data[icode].operand[3].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) - { - error ("selector must be an immediate"); - return const0_rtx; - } - if (icode == CODE_FOR_iwmmxt_wmerge) - { - selector = INTVAL (op2); - if (selector > 7 || selector < 0) - error ("the range of selector should be in 0 to 7"); - } - if ((icode == CODE_FOR_iwmmxt_tinsrb) - || (icode == CODE_FOR_iwmmxt_tinsrh) - || (icode == CODE_FOR_iwmmxt_tinsrw)) - { - mask = 0x01; - selector= INTVAL (op2); - if (icode == CODE_FOR_iwmmxt_tinsrb && (selector < 0 || selector > 7)) - error ("the range of selector should be in 0 to 7"); - else if (icode == CODE_FOR_iwmmxt_tinsrh && (selector < 0 ||selector > 3)) - error ("the range of selector should be in 0 to 3"); - else if (icode == CODE_FOR_iwmmxt_tinsrw && (selector < 0 ||selector > 1)) - error ("the range of selector should be in 0 to 1"); - mask <<= selector; - op2 = GEN_INT (mask); - } - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target, op0, op1, op2); - if (! pat) - return 0; - emit_insn (pat); - return target; - - case ARM_BUILTIN_SETWCGR0: - case ARM_BUILTIN_SETWCGR1: - case ARM_BUILTIN_SETWCGR2: - case ARM_BUILTIN_SETWCGR3: - icode = (fcode == ARM_BUILTIN_SETWCGR0 ? CODE_FOR_iwmmxt_setwcgr0 - : fcode == ARM_BUILTIN_SETWCGR1 ? CODE_FOR_iwmmxt_setwcgr1 - : fcode == ARM_BUILTIN_SETWCGR2 ? CODE_FOR_iwmmxt_setwcgr2 - : CODE_FOR_iwmmxt_setwcgr3); - arg0 = CALL_EXPR_ARG (exp, 0); - op0 = expand_normal (arg0); - mode0 = insn_data[icode].operand[0].mode; - if (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - pat = GEN_FCN (icode) (op0); - if (!pat) - return 0; - emit_insn (pat); - return 0; - - case ARM_BUILTIN_GETWCGR0: - case ARM_BUILTIN_GETWCGR1: - case ARM_BUILTIN_GETWCGR2: - case ARM_BUILTIN_GETWCGR3: - icode = (fcode == ARM_BUILTIN_GETWCGR0 ? CODE_FOR_iwmmxt_getwcgr0 - : fcode == ARM_BUILTIN_GETWCGR1 ? CODE_FOR_iwmmxt_getwcgr1 - : fcode == ARM_BUILTIN_GETWCGR2 ? CODE_FOR_iwmmxt_getwcgr2 - : CODE_FOR_iwmmxt_getwcgr3); - tmode = insn_data[icode].operand[0].mode; - if (target == 0 - || GET_MODE (target) != tmode - || !(*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target); - if (!pat) - return 0; - emit_insn (pat); - return target; - - case ARM_BUILTIN_WSHUFH: - icode = CODE_FOR_iwmmxt_wshufh; - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - op0 = expand_normal (arg0); - op1 = expand_normal (arg1); - tmode = insn_data[icode].operand[0].mode; - mode1 = insn_data[icode].operand[1].mode; - mode2 = insn_data[icode].operand[2].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) - op0 = copy_to_mode_reg (mode1, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode2)) - { - error ("mask must be an immediate"); - return const0_rtx; - } - selector = INTVAL (op1); - if (selector < 0 || selector > 255) - error ("the range of mask should be in 0 to 255"); - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target, op0, op1); - if (! pat) - return 0; - emit_insn (pat); - return target; - - case ARM_BUILTIN_WMADDS: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmadds, exp, target); - case ARM_BUILTIN_WMADDSX: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddsx, exp, target); - case ARM_BUILTIN_WMADDSN: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddsn, exp, target); - case ARM_BUILTIN_WMADDU: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddu, exp, target); - case ARM_BUILTIN_WMADDUX: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddux, exp, target); - case ARM_BUILTIN_WMADDUN: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddun, exp, target); - case ARM_BUILTIN_WSADBZ: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target); - case ARM_BUILTIN_WSADHZ: - return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target); - - /* Several three-argument builtins. */ - case ARM_BUILTIN_WMACS: - case ARM_BUILTIN_WMACU: - case ARM_BUILTIN_TMIA: - case ARM_BUILTIN_TMIAPH: - case ARM_BUILTIN_TMIATT: - case ARM_BUILTIN_TMIATB: - case ARM_BUILTIN_TMIABT: - case ARM_BUILTIN_TMIABB: - case ARM_BUILTIN_WQMIABB: - case ARM_BUILTIN_WQMIABT: - case ARM_BUILTIN_WQMIATB: - case ARM_BUILTIN_WQMIATT: - case ARM_BUILTIN_WQMIABBN: - case ARM_BUILTIN_WQMIABTN: - case ARM_BUILTIN_WQMIATBN: - case ARM_BUILTIN_WQMIATTN: - case ARM_BUILTIN_WMIABB: - case ARM_BUILTIN_WMIABT: - case ARM_BUILTIN_WMIATB: - case ARM_BUILTIN_WMIATT: - case ARM_BUILTIN_WMIABBN: - case ARM_BUILTIN_WMIABTN: - case ARM_BUILTIN_WMIATBN: - case ARM_BUILTIN_WMIATTN: - case ARM_BUILTIN_WMIAWBB: - case ARM_BUILTIN_WMIAWBT: - case ARM_BUILTIN_WMIAWTB: - case ARM_BUILTIN_WMIAWTT: - case ARM_BUILTIN_WMIAWBBN: - case ARM_BUILTIN_WMIAWBTN: - case ARM_BUILTIN_WMIAWTBN: - case ARM_BUILTIN_WMIAWTTN: - case ARM_BUILTIN_WSADB: - case ARM_BUILTIN_WSADH: - icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs - : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu - : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia - : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph - : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb - : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt - : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb - : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt - : fcode == ARM_BUILTIN_WQMIABB ? CODE_FOR_iwmmxt_wqmiabb - : fcode == ARM_BUILTIN_WQMIABT ? CODE_FOR_iwmmxt_wqmiabt - : fcode == ARM_BUILTIN_WQMIATB ? CODE_FOR_iwmmxt_wqmiatb - : fcode == ARM_BUILTIN_WQMIATT ? CODE_FOR_iwmmxt_wqmiatt - : fcode == ARM_BUILTIN_WQMIABBN ? CODE_FOR_iwmmxt_wqmiabbn - : fcode == ARM_BUILTIN_WQMIABTN ? CODE_FOR_iwmmxt_wqmiabtn - : fcode == ARM_BUILTIN_WQMIATBN ? CODE_FOR_iwmmxt_wqmiatbn - : fcode == ARM_BUILTIN_WQMIATTN ? CODE_FOR_iwmmxt_wqmiattn - : fcode == ARM_BUILTIN_WMIABB ? CODE_FOR_iwmmxt_wmiabb - : fcode == ARM_BUILTIN_WMIABT ? CODE_FOR_iwmmxt_wmiabt - : fcode == ARM_BUILTIN_WMIATB ? CODE_FOR_iwmmxt_wmiatb - : fcode == ARM_BUILTIN_WMIATT ? CODE_FOR_iwmmxt_wmiatt - : fcode == ARM_BUILTIN_WMIABBN ? CODE_FOR_iwmmxt_wmiabbn - : fcode == ARM_BUILTIN_WMIABTN ? CODE_FOR_iwmmxt_wmiabtn - : fcode == ARM_BUILTIN_WMIATBN ? CODE_FOR_iwmmxt_wmiatbn - : fcode == ARM_BUILTIN_WMIATTN ? CODE_FOR_iwmmxt_wmiattn - : fcode == ARM_BUILTIN_WMIAWBB ? CODE_FOR_iwmmxt_wmiawbb - : fcode == ARM_BUILTIN_WMIAWBT ? CODE_FOR_iwmmxt_wmiawbt - : fcode == ARM_BUILTIN_WMIAWTB ? CODE_FOR_iwmmxt_wmiawtb - : fcode == ARM_BUILTIN_WMIAWTT ? CODE_FOR_iwmmxt_wmiawtt - : fcode == ARM_BUILTIN_WMIAWBBN ? CODE_FOR_iwmmxt_wmiawbbn - : fcode == ARM_BUILTIN_WMIAWBTN ? CODE_FOR_iwmmxt_wmiawbtn - : fcode == ARM_BUILTIN_WMIAWTBN ? CODE_FOR_iwmmxt_wmiawtbn - : fcode == ARM_BUILTIN_WMIAWTTN ? CODE_FOR_iwmmxt_wmiawttn - : fcode == ARM_BUILTIN_WSADB ? CODE_FOR_iwmmxt_wsadb - : CODE_FOR_iwmmxt_wsadh); - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - arg2 = CALL_EXPR_ARG (exp, 2); - op0 = expand_normal (arg0); - op1 = expand_normal (arg1); - op2 = expand_normal (arg2); - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - mode2 = insn_data[icode].operand[3].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) - op2 = copy_to_mode_reg (mode2, op2); - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target, op0, op1, op2); - if (! pat) - return 0; - emit_insn (pat); - return target; - - case ARM_BUILTIN_WZERO: - target = gen_reg_rtx (DImode); - emit_insn (gen_iwmmxt_clrdi (target)); - return target; - - case ARM_BUILTIN_WSRLHI: - case ARM_BUILTIN_WSRLWI: - case ARM_BUILTIN_WSRLDI: - case ARM_BUILTIN_WSLLHI: - case ARM_BUILTIN_WSLLWI: - case ARM_BUILTIN_WSLLDI: - case ARM_BUILTIN_WSRAHI: - case ARM_BUILTIN_WSRAWI: - case ARM_BUILTIN_WSRADI: - case ARM_BUILTIN_WRORHI: - case ARM_BUILTIN_WRORWI: - case ARM_BUILTIN_WRORDI: - case ARM_BUILTIN_WSRLH: - case ARM_BUILTIN_WSRLW: - case ARM_BUILTIN_WSRLD: - case ARM_BUILTIN_WSLLH: - case ARM_BUILTIN_WSLLW: - case ARM_BUILTIN_WSLLD: - case ARM_BUILTIN_WSRAH: - case ARM_BUILTIN_WSRAW: - case ARM_BUILTIN_WSRAD: - case ARM_BUILTIN_WRORH: - case ARM_BUILTIN_WRORW: - case ARM_BUILTIN_WRORD: - icode = (fcode == ARM_BUILTIN_WSRLHI ? CODE_FOR_lshrv4hi3_iwmmxt - : fcode == ARM_BUILTIN_WSRLWI ? CODE_FOR_lshrv2si3_iwmmxt - : fcode == ARM_BUILTIN_WSRLDI ? CODE_FOR_lshrdi3_iwmmxt - : fcode == ARM_BUILTIN_WSLLHI ? CODE_FOR_ashlv4hi3_iwmmxt - : fcode == ARM_BUILTIN_WSLLWI ? CODE_FOR_ashlv2si3_iwmmxt - : fcode == ARM_BUILTIN_WSLLDI ? CODE_FOR_ashldi3_iwmmxt - : fcode == ARM_BUILTIN_WSRAHI ? CODE_FOR_ashrv4hi3_iwmmxt - : fcode == ARM_BUILTIN_WSRAWI ? CODE_FOR_ashrv2si3_iwmmxt - : fcode == ARM_BUILTIN_WSRADI ? CODE_FOR_ashrdi3_iwmmxt - : fcode == ARM_BUILTIN_WRORHI ? CODE_FOR_rorv4hi3 - : fcode == ARM_BUILTIN_WRORWI ? CODE_FOR_rorv2si3 - : fcode == ARM_BUILTIN_WRORDI ? CODE_FOR_rordi3 - : fcode == ARM_BUILTIN_WSRLH ? CODE_FOR_lshrv4hi3_di - : fcode == ARM_BUILTIN_WSRLW ? CODE_FOR_lshrv2si3_di - : fcode == ARM_BUILTIN_WSRLD ? CODE_FOR_lshrdi3_di - : fcode == ARM_BUILTIN_WSLLH ? CODE_FOR_ashlv4hi3_di - : fcode == ARM_BUILTIN_WSLLW ? CODE_FOR_ashlv2si3_di - : fcode == ARM_BUILTIN_WSLLD ? CODE_FOR_ashldi3_di - : fcode == ARM_BUILTIN_WSRAH ? CODE_FOR_ashrv4hi3_di - : fcode == ARM_BUILTIN_WSRAW ? CODE_FOR_ashrv2si3_di - : fcode == ARM_BUILTIN_WSRAD ? CODE_FOR_ashrdi3_di - : fcode == ARM_BUILTIN_WRORH ? CODE_FOR_rorv4hi3_di - : fcode == ARM_BUILTIN_WRORW ? CODE_FOR_rorv2si3_di - : fcode == ARM_BUILTIN_WRORD ? CODE_FOR_rordi3_di - : CODE_FOR_nothing); - arg1 = CALL_EXPR_ARG (exp, 1); - op1 = expand_normal (arg1); - if (GET_MODE (op1) == VOIDmode) - { - imm = INTVAL (op1); - if ((fcode == ARM_BUILTIN_WRORWI || fcode == ARM_BUILTIN_WRORW) - && (imm < 0 || imm > 32)) - { - const char *builtin = (fcode == ARM_BUILTIN_WRORWI - ? "_mm_rori_pi32" : "_mm_ror_pi32"); - error ("the range of count should be in 0 to 32; " - "please check the intrinsic %qs in code", builtin); - } - else if ((fcode == ARM_BUILTIN_WRORHI || fcode == ARM_BUILTIN_WRORH) - && (imm < 0 || imm > 16)) - { - const char *builtin = (fcode == ARM_BUILTIN_WRORHI - ? "_mm_rori_pi16" : "_mm_ror_pi16"); - error ("the range of count should be in 0 to 16; " - "please check the intrinsic %qs in code", builtin); - } - else if ((fcode == ARM_BUILTIN_WRORDI || fcode == ARM_BUILTIN_WRORD) - && (imm < 0 || imm > 64)) - { - const char *builtin = (fcode == ARM_BUILTIN_WRORDI - ? "_mm_rori_si64" : "_mm_ror_si64"); - error ("the range of count should be in 0 to 64; " - "please check the intrinsic %qs in code", builtin); - } - else if (imm < 0) - { - const char *builtin; - switch (fcode) - { - case ARM_BUILTIN_WSRLHI: - builtin = "_mm_srli_pi16"; - break; - case ARM_BUILTIN_WSRLWI: - builtin = "_mm_srli_pi32"; - break; - case ARM_BUILTIN_WSRLDI: - builtin = "_mm_srli_si64"; - break; - case ARM_BUILTIN_WSLLHI: - builtin = "_mm_slli_pi16"; - break; - case ARM_BUILTIN_WSLLWI: - builtin = "_mm_slli_pi32"; - break; - case ARM_BUILTIN_WSLLDI: - builtin = "_mm_slli_si64"; - break; - case ARM_BUILTIN_WSRAHI: - builtin = "_mm_srai_pi16"; - break; - case ARM_BUILTIN_WSRAWI: - builtin = "_mm_srai_pi32"; - break; - case ARM_BUILTIN_WSRADI: - builtin = "_mm_srai_si64"; - break; - case ARM_BUILTIN_WSRLH: - builtin = "_mm_srl_pi16"; - break; - case ARM_BUILTIN_WSRLW: - builtin = "_mm_srl_pi32"; - break; - case ARM_BUILTIN_WSRLD: - builtin = "_mm_srl_si64"; - break; - case ARM_BUILTIN_WSLLH: - builtin = "_mm_sll_pi16"; - break; - case ARM_BUILTIN_WSLLW: - builtin = "_mm_sll_pi32"; - break; - case ARM_BUILTIN_WSLLD: - builtin = "_mm_sll_si64"; - break; - case ARM_BUILTIN_WSRAH: - builtin = "_mm_sra_pi16"; - break; - case ARM_BUILTIN_WSRAW: - builtin = "_mm_sra_si64"; - break; - default: - builtin = "_mm_sra_si64"; - break; - } - error ("the count should be no less than 0; " - "please check the intrinsic %qs in code", builtin); - } - } - return arm_expand_binop_builtin (icode, exp, target); - default: break; } diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc index 15e4080..d257e62 100644 --- a/gcc/config/arm/arm-c.cc +++ b/gcc/config/arm/arm-c.cc @@ -373,13 +373,6 @@ arm_cpu_builtins (struct cpp_reader* pfile) builtin_define (arm_arch_name); if (arm_arch_xscale) builtin_define ("__XSCALE__"); - if (arm_arch_iwmmxt) - { - builtin_define ("__IWMMXT__"); - builtin_define ("__ARM_WMMX"); - } - if (arm_arch_iwmmxt2) - builtin_define ("__IWMMXT2__"); /* ARMv6KZ was originally identified as the misspelled __ARM_ARCH_6ZK__. To preserve the existing behavior, the misspelled feature macro must still be defined. */ diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 1939d55..7f5a8c6 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -102,12 +102,6 @@ define feature armv8 # ARMv8 CRC32 instructions. define feature crc32 -# XScale v2 (Wireless MMX). -define feature iwmmxt - -# XScale Wireless MMX2. -define feature iwmmxt2 - # Architecture rel 8.1. define feature armv8_1 @@ -778,18 +772,19 @@ begin arch armv9-a option bf16 add bf16 FP_ARMv8 DOTPROD end arch armv9-a +# We no-longer support the iwmmxt{,2} extensions, so treat these like xscale. begin arch iwmmxt - tune for iwmmxt + tune for xscale tune flags LDSCHED STRONG XSCALE base 5TE - isa ARMv5te xscale iwmmxt + isa ARMv5te xscale end arch iwmmxt begin arch iwmmxt2 - tune for iwmmxt2 + tune for xscale tune flags LDSCHED STRONG XSCALE base 5TE - isa ARMv5te xscale iwmmxt iwmmxt2 + isa ARMv5te xscale end arch iwmmxt2 # CPU entries @@ -924,23 +919,12 @@ end cpu arm10e begin cpu xscale tune flags LDSCHED XSCALE + alias iwmmxt iwmmxt2 architecture armv5te isa xscale costs xscale end cpu xscale -begin cpu iwmmxt - tune flags LDSCHED XSCALE - architecture iwmmxt - costs xscale -end cpu iwmmxt - -begin cpu iwmmxt2 - tune flags LDSCHED XSCALE - architecture iwmmxt2 - costs xscale -end cpu iwmmxt2 - begin cpu fa606te tune flags LDSCHED architecture armv5te diff --git a/gcc/config/arm/arm-generic.md b/gcc/config/arm/arm-generic.md index c270056..a8af0e6 100644 --- a/gcc/config/arm/arm-generic.md +++ b/gcc/config/arm/arm-generic.md @@ -96,14 +96,14 @@ (and (eq_attr "generic_sched" "yes") (and (eq_attr "ldsched" "yes") (and (eq_attr "type" "load_byte,load_4") - (eq_attr "tune" "xscale,iwmmxt,iwmmxt2")))) + (eq_attr "tune" "xscale")))) "core") (define_insn_reservation "load_ldsched" 2 (and (eq_attr "generic_sched" "yes") (and (eq_attr "ldsched" "yes") (and (eq_attr "type" "load_byte,load_4") - (eq_attr "tune" "!xscale,iwmmxt,iwmmxt2")))) + (eq_attr "tune" "!xscale")))) "core") (define_insn_reservation "load_or_store" 2 diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h index 06a1939..5c543bf 100644 --- a/gcc/config/arm/arm-opts.h +++ b/gcc/config/arm/arm-opts.h @@ -46,7 +46,6 @@ enum arm_abi_type ARM_ABI_APCS, ARM_ABI_ATPCS, ARM_ABI_AAPCS, - ARM_ABI_IWMMXT, ARM_ABI_AAPCS_LINUX }; diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 254c731..ff7e765 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -190,8 +190,6 @@ extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool); extern void arm_set_return_address (rtx, rtx); extern int arm_eliminable_register (rtx); extern const char *arm_output_shift(rtx *, int); -extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool); -extern const char *arm_output_iwmmxt_tinsr (rtx *); extern unsigned int arm_sync_loop_insns (rtx , rtx *); extern int arm_attr_length_push_multi(rtx, rtx); extern int arm_attr_length_pop_multi(rtx *, bool, bool); @@ -475,12 +473,6 @@ extern int arm_ld_sched; /* Nonzero if this chip is a StrongARM. */ extern int arm_tune_strongarm; -/* Nonzero if this chip supports Intel Wireless MMX technology. */ -extern int arm_arch_iwmmxt; - -/* Nonzero if this chip supports Intel Wireless MMX2 technology. */ -extern int arm_arch_iwmmxt2; - /* Nonzero if this chip is an XScale. */ extern int arm_arch_xscale; diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index db7767a..544de84 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -67,12 +67,6 @@ EnumValue Enum(processor_type) String(xscale) Value( TARGET_CPU_xscale) EnumValue -Enum(processor_type) String(iwmmxt) Value( TARGET_CPU_iwmmxt) - -EnumValue -Enum(processor_type) String(iwmmxt2) Value( TARGET_CPU_iwmmxt2) - -EnumValue Enum(processor_type) String(fa606te) Value( TARGET_CPU_fa606te) EnumValue diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index a04d1ee..20b5f93 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -25,31 +25,30 @@ fa526,fa626,arm7tdmi, arm710t,arm9,arm9tdmi, arm920t,arm10tdmi,arm9e, - arm10e,xscale,iwmmxt, - iwmmxt2,fa606te,fa626te, - fmp626,fa726te,arm926ejs, - arm1026ejs,arm1136js,arm1136jfs, - arm1176jzs,arm1176jzfs,mpcorenovfp, - mpcore,arm1156t2s,arm1156t2fs, - cortexm1,cortexm0,cortexm0plus, - cortexm1smallmultiply,cortexm0smallmultiply,cortexm0plussmallmultiply, - genericv7a,cortexa5,cortexa7, - cortexa8,cortexa9,cortexa12, - cortexa15,cortexa17,cortexr4, - cortexr4f,cortexr5,cortexr7, - cortexr8,cortexm7,cortexm4, - cortexm3,marvell_pj4,cortexa15cortexa7, - cortexa17cortexa7,cortexa32,cortexa35, - cortexa53,cortexa57,cortexa72, - cortexa73,exynosm1,xgene1, - cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35, - cortexa73cortexa53,cortexa55,cortexa75, - cortexa76,cortexa76ae,cortexa77, - cortexa78,cortexa78ae,cortexa78c, - cortexa710,cortexx1,cortexx1c, - neoversen1,cortexa75cortexa55,cortexa76cortexa55, - neoversev1,neoversen2,cortexm23, - cortexm33,cortexm35p,cortexm52, - cortexm55,starmc1,cortexm85, - cortexr52,cortexr52plus" + arm10e,xscale,fa606te, + fa626te,fmp626,fa726te, + arm926ejs,arm1026ejs,arm1136js, + arm1136jfs,arm1176jzs,arm1176jzfs, + mpcorenovfp,mpcore,arm1156t2s, + arm1156t2fs,cortexm1,cortexm0, + cortexm0plus,cortexm1smallmultiply,cortexm0smallmultiply, + cortexm0plussmallmultiply,genericv7a,cortexa5, + cortexa7,cortexa8,cortexa9, + cortexa12,cortexa15,cortexa17, + cortexr4,cortexr4f,cortexr5, + cortexr7,cortexr8,cortexm7, + cortexm4,cortexm3,marvell_pj4, + cortexa15cortexa7,cortexa17cortexa7,cortexa32, + cortexa35,cortexa53,cortexa57, + cortexa72,cortexa73,exynosm1, + xgene1,cortexa57cortexa53,cortexa72cortexa53, + cortexa73cortexa35,cortexa73cortexa53,cortexa55, + cortexa75,cortexa76,cortexa76ae, + cortexa77,cortexa78,cortexa78ae, + cortexa78c,cortexa710,cortexx1, + cortexx1c,neoversen1,cortexa75cortexa55, + cortexa76cortexa55,neoversev1,neoversen2, + cortexm23,cortexm33,cortexm35p, + cortexm52,cortexm55,starmc1, + cortexm85,cortexr52,cortexr52plus" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 6bdb68a..8737c22 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -948,12 +948,6 @@ int arm_ld_sched = 0; /* Nonzero if this chip is a StrongARM. */ int arm_tune_strongarm = 0; -/* Nonzero if this chip supports Intel Wireless MMX technology. */ -int arm_arch_iwmmxt = 0; - -/* Nonzero if this chip supports Intel Wireless MMX2 technology. */ -int arm_arch_iwmmxt2 = 0; - /* Nonzero if this chip is an XScale. */ int arm_arch_xscale = 0; @@ -2970,11 +2964,6 @@ arm_option_check_internal (struct gcc_options *opts) { int flags = opts->x_target_flags; - /* iWMMXt and NEON are incompatible. */ - if (TARGET_IWMMXT - && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) - error ("iWMMXt and NEON are incompatible"); - /* Make sure that the processor choice does not conflict with any of the other command line choices. */ if (TARGET_ARM_P (flags) @@ -2997,10 +2986,6 @@ arm_option_check_internal (struct gcc_options *opts) warning (0, "%<-g%> with %<-mno-apcs-frame%> may not give sensible " "debugging"); - /* iWMMXt unsupported under Thumb mode. */ - if (TARGET_THUMB_P (flags) && TARGET_IWMMXT) - error ("iWMMXt unsupported under Thumb mode"); - if (TARGET_HARD_TP && TARGET_THUMB1_P (flags)) error ("cannot use %<-mtp=cp15%> with 16-bit Thumb"); @@ -3928,8 +3913,6 @@ arm_option_reconfigure_globals (void) arm_arch_thumb1 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb); arm_arch_thumb2 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb2); arm_arch_xscale = bitmap_bit_p (arm_active_target.isa, isa_bit_xscale); - arm_arch_iwmmxt = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt); - arm_arch_iwmmxt2 = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt2); arm_arch_thumb_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_tdiv); arm_arch_arm_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_adiv); arm_arch_crc = bitmap_bit_p (arm_active_target.isa, isa_bit_crc32); @@ -3997,12 +3980,6 @@ arm_options_perform_arch_sanity_checks (void) if (arm_arch5t) target_flags &= ~MASK_INTERWORK; - if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN) - error ("iwmmxt requires an AAPCS compatible ABI for proper operation"); - - if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT) - error ("iwmmxt abi requires an iwmmxt capable cpu"); - /* BPABI targets use linker tricks to allow interworking on cores without thumb support. */ if (TARGET_INTERWORK @@ -4043,9 +4020,7 @@ arm_options_perform_arch_sanity_checks (void) if (TARGET_AAPCS_BASED) { - if (arm_abi == ARM_ABI_IWMMXT) - arm_pcs_default = ARM_PCS_AAPCS_IWMMXT; - else if (TARGET_HARD_FLOAT_ABI) + if (TARGET_HARD_FLOAT_ABI) { arm_pcs_default = ARM_PCS_AAPCS_VFP; if (!bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv2) @@ -4555,11 +4530,6 @@ use_return_insn (int iscond, rtx sibling) if (reg_needs_saving_p (regno)) return 0; - if (TARGET_REALLY_IWMMXT) - for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) - if (reg_needs_saving_p (regno)) - return 0; - return 1; } @@ -6048,9 +6018,6 @@ arm_libcall_value_1 (machine_mode mode) { if (TARGET_AAPCS_BASED) return aapcs_libcall_value (mode); - else if (TARGET_IWMMXT_ABI - && arm_vector_mode_supported_p (mode)) - return gen_rtx_REG (mode, FIRST_IWMMXT_REGNUM); else return gen_rtx_REG (mode, ARG_REGISTER (1)); } @@ -6083,9 +6050,7 @@ arm_function_value_regno_p (const unsigned int regno) || (TARGET_32BIT && TARGET_AAPCS_BASED && TARGET_HARD_FLOAT - && regno == FIRST_VFP_REGNUM) - || (TARGET_IWMMXT_ABI - && regno == FIRST_IWMMXT_REGNUM)) + && regno == FIRST_VFP_REGNUM)) return true; return false; @@ -6102,8 +6067,6 @@ arm_apply_result_size (void) { if (TARGET_HARD_FLOAT_ABI) size += 32; - if (TARGET_IWMMXT_ABI) - size += 8; } return size; @@ -6265,7 +6228,6 @@ const struct pcs_attribute_arg #if 0 /* We could recognize these, but changes would be needed elsewhere * to implement them. */ - {"aapcs-iwmmxt", ARM_PCS_AAPCS_IWMMXT}, {"atpcs", ARM_PCS_ATPCS}, {"apcs", ARM_PCS_APCS}, #endif @@ -7195,26 +7157,12 @@ arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, /* On the ARM, the offset starts at 0. */ pcum->nregs = 0; - pcum->iwmmxt_nregs = 0; pcum->can_split = true; /* Varargs vectors are treated the same as long long. named_count avoids having to change the way arm handles 'named' */ pcum->named_count = 0; pcum->nargs = 0; - - if (TARGET_REALLY_IWMMXT && fntype) - { - tree fn_arg; - - for (fn_arg = TYPE_ARG_TYPES (fntype); - fn_arg; - fn_arg = TREE_CHAIN (fn_arg)) - pcum->named_count += 1; - - if (! pcum->named_count) - pcum->named_count = INT_MAX; - } } /* Return 2 if double word alignment is required for argument passing, @@ -7308,22 +7256,6 @@ arm_function_arg (cumulative_args_t pcum_v, const function_arg_info &arg) return pcum->aapcs_reg; } - /* Varargs vectors are treated the same as long long. - named_count avoids having to change the way arm handles 'named' */ - if (TARGET_IWMMXT_ABI - && arm_vector_mode_supported_p (arg.mode) - && pcum->named_count > pcum->nargs + 1) - { - if (pcum->iwmmxt_nregs <= 9) - return gen_rtx_REG (arg.mode, - pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); - else - { - pcum->can_split = false; - return NULL_RTX; - } - } - /* Put doubleword aligned quantities in even register pairs. */ if ((pcum->nregs & 1) && ARM_DOUBLEWORD_ALIGN) { @@ -7383,9 +7315,6 @@ arm_arg_partial_bytes (cumulative_args_t pcum_v, const function_arg_info &arg) return pcum->aapcs_partial; } - if (TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (arg.mode)) - return 0; - if (NUM_ARG_REGS > nregs && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (arg.mode, arg.type)) && pcum->can_split) @@ -7422,12 +7351,7 @@ arm_function_arg_advance (cumulative_args_t pcum_v, else { pcum->nargs += 1; - if (arm_vector_mode_supported_p (arg.mode) - && pcum->named_count > pcum->nargs - && TARGET_IWMMXT_ABI) - pcum->iwmmxt_nregs += 1; - else - pcum->nregs += ARM_NUM_REGS2 (arg.mode, arg.type); + pcum->nregs += ARM_NUM_REGS2 (arg.mode, arg.type); } } @@ -8906,12 +8830,6 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer, && INTVAL (index) > -1024 && (INTVAL (index) & 3) == 0); - if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) - return (code == CONST_INT - && INTVAL (index) < 1024 - && INTVAL (index) > -1024 - && (INTVAL (index) & 3) == 0); - if (GET_MODE_SIZE (mode) <= 4 && ! (arm_arch4 && (mode == HImode @@ -8991,17 +8909,6 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p) && INTVAL (index) > -256 && (INTVAL (index) & 3) == 0); - if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) - { - /* For DImode assume values will usually live in core regs - and only allow LDRD addressing modes. */ - if (!TARGET_LDRD || mode != DImode) - return (code == CONST_INT - && INTVAL (index) < 1024 - && INTVAL (index) > -1024 - && (INTVAL (index) & 3) == 0); - } - /* For quad modes, we restrict the constant offset to be slightly less than what the instruction format permits. We do this because for quad mode moves, we will actually decompose them into two separate @@ -12463,11 +12370,6 @@ arm_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, if ((IS_VFP_CLASS (from) && !IS_VFP_CLASS (to)) || (!IS_VFP_CLASS (from) && IS_VFP_CLASS (to))) return 15; - else if ((from == IWMMXT_REGS && to != IWMMXT_REGS) - || (from != IWMMXT_REGS && to == IWMMXT_REGS)) - return 4; - else if (from == IWMMXT_GR_REGS || to == IWMMXT_GR_REGS) - return 20; else return 2; } @@ -17583,8 +17485,7 @@ struct minipool_node rtx value; /* The mode of value. */ machine_mode mode; - /* The size of the value. With iWMMXt enabled - sizes > 4 also imply an alignment of 8-bytes. */ + /* The size of the value. */ int fix_size; }; @@ -20247,9 +20148,7 @@ output_move_double (rtx *operands, bool emit, int *count) } else { - /* Use a single insn if we can. - FIXME: IWMMXT allows offsets larger than ldrd can - handle, fix these up with a pair of ldr. */ + /* Use a single insn if we can. */ if (can_ldrd && (TARGET_THUMB2 || !CONST_INT_P (otherops[2]) @@ -20274,9 +20173,7 @@ output_move_double (rtx *operands, bool emit, int *count) } else { - /* Use a single insn if we can. - FIXME: IWMMXT allows offsets larger than ldrd can handle, - fix these up with a pair of ldr. */ + /* Use a single insn if we can. */ if (can_ldrd && (TARGET_THUMB2 || !CONST_INT_P (otherops[2]) @@ -20514,8 +20411,6 @@ output_move_double (rtx *operands, bool emit, int *count) otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0); otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1); - /* IWMMXT allows offsets larger than strd can handle, - fix these up with a pair of str. */ if (!TARGET_THUMB2 && CONST_INT_P (otherops[2]) && (INTVAL(otherops[2]) <= -256 @@ -21452,34 +21347,6 @@ arm_compute_save_core_reg_mask (void) if (cfun->machine->lr_save_eliminated) save_reg_mask &= ~ (1 << LR_REGNUM); - if (TARGET_REALLY_IWMMXT - && ((bit_count (save_reg_mask) - + ARM_NUM_INTS (crtl->args.pretend_args_size + - arm_compute_static_chain_stack_bytes()) - ) % 2) != 0) - { - /* The total number of registers that are going to be pushed - onto the stack is odd. We need to ensure that the stack - is 64-bit aligned before we start to save iWMMXt registers, - and also before we start to create locals. (A local variable - might be a double or long long which we will load/store using - an iWMMXt instruction). Therefore we need to push another - ARM register, so that the stack will be 64-bit aligned. We - try to avoid using the arg registers (r0 -r3) as they might be - used to pass values in a tail call. */ - for (reg = 4; reg <= 12; reg++) - if ((save_reg_mask & (1 << reg)) == 0) - break; - - if (reg <= 12) - save_reg_mask |= (1 << reg); - else - { - cfun->machine->sibcall_blocked = 1; - save_reg_mask |= (1 << 3); - } - } - /* We may need to push an additional register for use initializing the PIC base register. */ if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic @@ -21687,19 +21554,17 @@ output_return_instruction (rtx operand, bool really_return, bool reverse, if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) { - /* There are three possible reasons for the IP register - being saved. 1) a stack frame was created, in which case - IP contains the old stack pointer, or 2) an ISR routine - corrupted it, or 3) it was saved to align the stack on - iWMMXt. In case 1, restore IP into SP, otherwise just - restore IP. */ + /* There are two possible reasons for the IP register being saved. + 1) a stack frame was created, in which case IP contains the old + stack pointer, or 2) an ISR routine corrupted it. In case 1, + restore IP into SP, otherwise just restore IP. */ if (frame_pointer_needed) { live_regs_mask &= ~ (1 << IP_REGNUM); live_regs_mask |= (1 << SP_REGNUM); } else - gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT); + gcc_assert (IS_INTERRUPT (func_type)); } /* On some ARM architectures it is faster to use LDR rather than @@ -23151,8 +23016,6 @@ arm_compute_frame_layout (void) if (TARGET_32BIT) { - unsigned int regno; - offsets->saved_regs_mask = arm_compute_save_core_reg_mask (); core_saved = bit_count (offsets->saved_regs_mask) * 4; saved = core_saved; @@ -23161,16 +23024,6 @@ arm_compute_frame_layout (void) preserve that condition at any subroutine call. We also require the soft frame pointer to be doubleword aligned. */ - if (TARGET_REALLY_IWMMXT) - { - /* Check for the call-saved iWMMXt registers. */ - for (regno = FIRST_IWMMXT_REGNUM; - regno <= LAST_IWMMXT_REGNUM; - regno++) - if (reg_needs_saving_p (regno)) - saved += 8; - } - func_type = arm_current_func_type (); /* Space for saved VFP registers. */ if (! IS_VOLATILE (func_type) @@ -23386,18 +23239,6 @@ arm_save_coproc_regs(void) int saved_size = 0; unsigned reg; unsigned start_reg; - rtx insn; - - if (TARGET_REALLY_IWMMXT) - for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) - if (reg_needs_saving_p (reg)) - { - insn = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); - insn = gen_rtx_MEM (V2SImode, insn); - insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg)); - RTX_FRAME_RELATED_P (insn) = 1; - saved_size += 8; - } if (TARGET_VFP_BASE) { @@ -24556,42 +24397,9 @@ arm_print_operand (FILE *stream, rtx x, int code) return; case 'U': - if (!REG_P (x) - || REGNO (x) < FIRST_IWMMXT_GR_REGNUM - || REGNO (x) > LAST_IWMMXT_GR_REGNUM) - /* Bad value for wCG register number. */ - { - output_operand_lossage ("invalid operand for code '%c'", code); - return; - } - - else - fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM); - return; - - /* Print an iWMMXt control register name. */ case 'w': - if (!CONST_INT_P (x) - || INTVAL (x) < 0 - || INTVAL (x) >= 16) - /* Bad value for wC register number. */ - { - output_operand_lossage ("invalid operand for code '%c'", code); - return; - } - - else - { - static const char * wc_reg_names [16] = - { - "wCID", "wCon", "wCSSF", "wCASF", - "wC4", "wC5", "wC6", "wC7", - "wCGR0", "wCGR1", "wCGR2", "wCGR3", - "wC12", "wC13", "wC14", "wC15" - }; - - fputs (wc_reg_names [INTVAL (x)], stream); - } + /* Former iWMMXT support, removed after GCC-15. */ + output_operand_lossage ("obsolete iWMMXT format code '%c'", code); return; /* Print the high single-precision register of a VFP double-precision @@ -25926,15 +25734,6 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode) return false; } - if (TARGET_REALLY_IWMMXT) - { - if (IS_IWMMXT_GR_REGNUM (regno)) - return mode == SImode; - - if (IS_IWMMXT_REGNUM (regno)) - return VALID_IWMMXT_REG_MODE (mode); - } - /* We allow almost any value to be stored in the general registers. Restrict doubleword quantities to even register pairs in ARM state so that we can use ldrd. The same restriction applies for MVE @@ -26040,12 +25839,6 @@ arm_regno_class (int regno) return VFP_HI_REGS; } - if (IS_IWMMXT_REGNUM (regno)) - return IWMMXT_REGS; - - if (IS_IWMMXT_GR_REGNUM (regno)) - return IWMMXT_GR_REGS; - return NO_REGS; } @@ -27963,27 +27756,6 @@ arm_expand_epilogue_apcs_frame (bool really_return) gen_rtx_REG (SImode, IP_REGNUM)); } - if (TARGET_IWMMXT) - { - /* The frame pointer is guaranteed to be non-double-word aligned, as - it is set to double-word-aligned old_stack_pointer - 4. */ - rtx_insn *insn; - int lrm_count = (num_regs % 2) ? (num_regs + 2) : (num_regs + 1); - - for (i = LAST_IWMMXT_REGNUM; i >= FIRST_IWMMXT_REGNUM; i--) - if (reg_needs_saving_p (i)) - { - rtx addr = gen_frame_mem (V2SImode, - plus_constant (Pmode, hard_frame_pointer_rtx, - - lrm_count * 4)); - insn = emit_insn (gen_movsi (gen_rtx_REG (V2SImode, i), addr)); - REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE, - gen_rtx_REG (V2SImode, i), - NULL_RTX); - lrm_count += 2; - } - } - /* saved_regs_mask should contain IP which contains old stack pointer at the time of activation creation. Since SP and IP are adjacent registers, we can restore the value directly into SP. */ @@ -28196,23 +27968,6 @@ arm_expand_epilogue (bool really_return) stack_pointer_rtx); } - if (TARGET_IWMMXT) - for (i = FIRST_IWMMXT_REGNUM; i <= LAST_IWMMXT_REGNUM; i++) - if (reg_needs_saving_p (i)) - { - rtx_insn *insn; - rtx addr = gen_rtx_MEM (V2SImode, - gen_rtx_POST_INC (SImode, - stack_pointer_rtx)); - set_mem_alias_set (addr, get_frame_alias_set ()); - insn = emit_insn (gen_movsi (gen_rtx_REG (V2SImode, i), addr)); - REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE, - gen_rtx_REG (V2SImode, i), - NULL_RTX); - arm_add_cfa_adjust_cfa_note (insn, UNITS_PER_WORD, - stack_pointer_rtx, stack_pointer_rtx); - } - if (saved_regs_mask) { rtx insn; @@ -29853,7 +29608,7 @@ arm_vector_mode_supported_p (machine_mode mode) || mode == V8BFmode)) return true; - if ((TARGET_NEON || TARGET_IWMMXT) + if (TARGET_NEON && ((mode == V2SImode) || (mode == V4HImode) || (mode == V8QImode))) @@ -29945,19 +29700,6 @@ arm_preferred_simd_mode (scalar_mode mode) default:; } - if (TARGET_REALLY_IWMMXT) - switch (mode) - { - case E_SImode: - return V2SImode; - case E_HImode: - return V4HImode; - case E_QImode: - return V8QImode; - - default:; - } - if (TARGET_HAVE_MVE) switch (mode) { @@ -30039,12 +29781,6 @@ arm_debugger_regno (unsigned int regno) return 256 + (regno - FIRST_VFP_REGNUM) / 2; } - if (IS_IWMMXT_GR_REGNUM (regno)) - return 104 + regno - FIRST_IWMMXT_GR_REGNUM; - - if (IS_IWMMXT_REGNUM (regno)) - return 112 + regno - FIRST_IWMMXT_REGNUM; - if (IS_PAC_REGNUM (regno)) return DWARF_PAC_REGNUM; @@ -30631,95 +30367,6 @@ arm_output_shift(rtx * operands, int set_flags) return ""; } -/* Output assembly for a WMMX immediate shift instruction. */ -const char * -arm_output_iwmmxt_shift_immediate (const char *insn_name, rtx *operands, bool wror_or_wsra) -{ - int shift = INTVAL (operands[2]); - char templ[50]; - machine_mode opmode = GET_MODE (operands[0]); - - gcc_assert (shift >= 0); - - /* If the shift value in the register versions is > 63 (for D qualifier), - 31 (for W qualifier) or 15 (for H qualifier). */ - if (((opmode == V4HImode) && (shift > 15)) - || ((opmode == V2SImode) && (shift > 31)) - || ((opmode == DImode) && (shift > 63))) - { - if (wror_or_wsra) - { - sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, 32); - output_asm_insn (templ, operands); - if (opmode == DImode) - { - sprintf (templ, "%s\t%%0, %%0, #%d", insn_name, 32); - output_asm_insn (templ, operands); - } - } - else - { - /* The destination register will contain all zeros. */ - sprintf (templ, "wzero\t%%0"); - output_asm_insn (templ, operands); - } - return ""; - } - - if ((opmode == DImode) && (shift > 32)) - { - sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, 32); - output_asm_insn (templ, operands); - sprintf (templ, "%s\t%%0, %%0, #%d", insn_name, shift - 32); - output_asm_insn (templ, operands); - } - else - { - sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, shift); - output_asm_insn (templ, operands); - } - return ""; -} - -/* Output assembly for a WMMX tinsr instruction. */ -const char * -arm_output_iwmmxt_tinsr (rtx *operands) -{ - int mask = INTVAL (operands[3]); - int i; - char templ[50]; - int units = mode_nunits[GET_MODE (operands[0])]; - gcc_assert ((mask & (mask - 1)) == 0); - for (i = 0; i < units; ++i) - { - if ((mask & 0x01) == 1) - { - break; - } - mask >>= 1; - } - gcc_assert (i < units); - { - switch (GET_MODE (operands[0])) - { - case E_V8QImode: - sprintf (templ, "tinsrb%%?\t%%0, %%2, #%d", i); - break; - case E_V4HImode: - sprintf (templ, "tinsrh%%?\t%%0, %%2, #%d", i); - break; - case E_V2SImode: - sprintf (templ, "tinsrw%%?\t%%0, %%2, #%d", i); - break; - default: - gcc_unreachable (); - break; - } - output_asm_insn (templ, operands); - } - return ""; -} - /* Output an arm casesi dispatch sequence. Used by arm_casesi_internal insn. Responsible for the handling of switch statements in arm. */ const char * @@ -31092,26 +30739,6 @@ arm_conditional_register_usage (void) fixed_regs[VPR_REGNUM] = 0; } - if (TARGET_REALLY_IWMMXT && !TARGET_GENERAL_REGS_ONLY) - { - regno = FIRST_IWMMXT_GR_REGNUM; - /* The 2002/10/09 revision of the XScale ABI has wCG0 - and wCG1 as call-preserved registers. The 2002/11/21 - revision changed this so that all wCG registers are - scratch registers. */ - for (regno = FIRST_IWMMXT_GR_REGNUM; - regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) - fixed_regs[regno] = 0; - /* The XScale ABI has wR0 - wR9 as scratch registers, - the rest as call-preserved registers. */ - for (regno = FIRST_IWMMXT_REGNUM; - regno <= LAST_IWMMXT_REGNUM; ++ regno) - { - fixed_regs[regno] = 0; - call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; - } - } - if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) { fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 08d3f0d..2e9d678 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -137,13 +137,6 @@ emission of floating point pcs attributes. */ #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) /* Use hardware floating point calling convention. */ #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) -#define TARGET_IWMMXT (arm_arch_iwmmxt) -#define TARGET_IWMMXT2 (arm_arch_iwmmxt2) -#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT \ - && !TARGET_GENERAL_REGS_ONLY) -#define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT \ - && !TARGET_GENERAL_REGS_ONLY) -#define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) #define TARGET_ARM (! TARGET_THUMB) #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ #define TARGET_BACKTRACE (crtl->is_leaf \ @@ -526,12 +519,6 @@ extern int arm_ld_sched; /* Nonzero if this chip is a StrongARM. */ extern int arm_tune_strongarm; -/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ -extern int arm_arch_iwmmxt; - -/* Nonzero if this chip supports Intel Wireless MMX2 technology. */ -extern int arm_arch_iwmmxt2; - /* Nonzero if this chip is an XScale. */ extern int arm_arch_xscale; @@ -855,10 +842,6 @@ extern const int arm_arch_cde_coproc_bits[]; 1,1,1,1,1,1,1,1, \ 1,1,1,1,1,1,1,1, \ 1,1,1,1,1,1,1,1, \ - /* IWMMXT regs. */ \ - 1,1,1,1,1,1,1,1, \ - 1,1,1,1,1,1,1,1, \ - 1,1,1,1, \ /* Specials. */ \ 1,1,1,1,1,1,1,1 \ } @@ -885,10 +868,6 @@ extern const int arm_arch_cde_coproc_bits[]; 1,1,1,1,1,1,1,1, \ 1,1,1,1,1,1,1,1, \ 1,1,1,1,1,1,1,1, \ - /* IWMMXT regs. */ \ - 1,1,1,1,1,1,1,1, \ - 1,1,1,1,1,1,1,1, \ - 1,1,1,1, \ /* Specials. */ \ 1,1,1,1,1,1,1,1 \ } @@ -1010,23 +989,11 @@ extern const int arm_arch_cde_coproc_bits[]; /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM SP_REGNUM -#define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) -#define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) - -/* Need to sync with WCGR in iwmmxt.md. */ -#define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) -#define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) - -#define IS_IWMMXT_REGNUM(REGNUM) \ - (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) -#define IS_IWMMXT_GR_REGNUM(REGNUM) \ - (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) - /* Base register for access to local variables of the function. */ -#define FRAME_POINTER_REGNUM 102 +#define FRAME_POINTER_REGNUM (CC_REGNUM + 2) /* Base register for access to arguments of the function. */ -#define ARG_POINTER_REGNUM 103 +#define ARG_POINTER_REGNUM (FRAME_POINTER_REGNUM + 1) #define FIRST_VFP_REGNUM 16 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) @@ -1067,9 +1034,8 @@ extern const int arm_arch_cde_coproc_bits[]; /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP + 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC. */ -/* Intel Wireless MMX Technology registers add 16 + 4 more. */ /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ -#define FIRST_PSEUDO_REGISTER 108 +#define FIRST_PSEUDO_REGISTER 88 #define DWARF_PAC_REGNUM 143 @@ -1086,9 +1052,6 @@ extern const int arm_arch_cde_coproc_bits[]; #define SUBTARGET_FRAME_POINTER_REQUIRED 0 #endif -#define VALID_IWMMXT_REG_MODE(MODE) \ - (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) - /* Modes valid for Neon D registers. */ #define VALID_NEON_DREG_MODE(MODE) \ ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ @@ -1168,9 +1131,9 @@ extern const int arm_arch_cde_coproc_bits[]; /* The conditions under which vector modes are supported for general arithmetic by any vector extension. */ -#define ARM_HAVE_V8QI_ARITH (ARM_HAVE_NEON_V8QI_ARITH || TARGET_REALLY_IWMMXT) -#define ARM_HAVE_V4HI_ARITH (ARM_HAVE_NEON_V4HI_ARITH || TARGET_REALLY_IWMMXT) -#define ARM_HAVE_V2SI_ARITH (ARM_HAVE_NEON_V2SI_ARITH || TARGET_REALLY_IWMMXT) +#define ARM_HAVE_V8QI_ARITH (ARM_HAVE_NEON_V8QI_ARITH) +#define ARM_HAVE_V4HI_ARITH (ARM_HAVE_NEON_V4HI_ARITH) +#define ARM_HAVE_V2SI_ARITH (ARM_HAVE_NEON_V2SI_ARITH) #define ARM_HAVE_V16QI_ARITH (ARM_HAVE_NEON_V16QI_ARITH || TARGET_HAVE_MVE) #define ARM_HAVE_V8HI_ARITH (ARM_HAVE_NEON_V8HI_ARITH || TARGET_HAVE_MVE) @@ -1204,9 +1167,9 @@ extern const int arm_arch_cde_coproc_bits[]; /* The conditions under which vector modes are supported by load/store instructions by any vector extension. */ -#define ARM_HAVE_V8QI_LDST (ARM_HAVE_NEON_V8QI_LDST || TARGET_REALLY_IWMMXT) -#define ARM_HAVE_V4HI_LDST (ARM_HAVE_NEON_V4HI_LDST || TARGET_REALLY_IWMMXT) -#define ARM_HAVE_V2SI_LDST (ARM_HAVE_NEON_V2SI_LDST || TARGET_REALLY_IWMMXT) +#define ARM_HAVE_V8QI_LDST (ARM_HAVE_NEON_V8QI_LDST) +#define ARM_HAVE_V4HI_LDST (ARM_HAVE_NEON_V4HI_LDST) +#define ARM_HAVE_V2SI_LDST (ARM_HAVE_NEON_V2SI_LDST) #define ARM_HAVE_V16QI_LDST (ARM_HAVE_NEON_V16QI_LDST || TARGET_HAVE_MVE) #define ARM_HAVE_V8HI_LDST (ARM_HAVE_NEON_V8HI_LDST || TARGET_HAVE_MVE) @@ -1238,8 +1201,6 @@ extern int arm_regs_in_sequence[]; function. */ #define VREG(X) (FIRST_VFP_REGNUM + (X)) -#define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) -#define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) #define REG_ALLOC_ORDER \ { \ @@ -1265,12 +1226,6 @@ extern int arm_regs_in_sequence[]; VREG(20), VREG(21), VREG(22), VREG(23), \ VREG(24), VREG(25), VREG(26), VREG(27), \ VREG(28), VREG(29), VREG(30), VREG(31), \ - /* IWMMX registers. */ \ - WREG(0), WREG(1), WREG(2), WREG(3), \ - WREG(4), WREG(5), WREG(6), WREG(7), \ - WREG(8), WREG(9), WREG(10), WREG(11), \ - WREG(12), WREG(13), WREG(14), WREG(15), \ - WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ /* Registers not for general use. */ \ CC_REGNUM, VFPCC_REGNUM, \ FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ @@ -1315,8 +1270,6 @@ enum reg_class VFP_LO_REGS, VFP_HI_REGS, VFP_REGS, - IWMMXT_REGS, - IWMMXT_GR_REGS, CC_REG, VFPCC_REG, SFP_REG, @@ -1346,8 +1299,6 @@ enum reg_class "VFP_LO_REGS", \ "VFP_HI_REGS", \ "VFP_REGS", \ - "IWMMXT_REGS", \ - "IWMMXT_GR_REGS", \ "CC_REG", \ "VFPCC_REG", \ "SFP_REG", \ @@ -1363,29 +1314,27 @@ enum reg_class of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ { \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ - { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ - { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ - { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ - { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ - { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ - { 0x00005555, 0x00000000, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \ - { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ - { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ - { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ - { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ - { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ - { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ - { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000800 }, /* PAC_REG. */ \ - { 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /* GENERAL_AND_VPR_REGS. */ \ - { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000040F } /* ALL_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ + { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \ + { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ + { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ + { 0x00005F00, 0x00000000, 0x00000000 }, /* HI_REGS */ \ + { 0x0000100F, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ + { 0x00005555, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \ + { 0x00005FFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ + { 0x00007FFF, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ + { 0xFFFF0000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ + { 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_LO_REGS */ \ + { 0x00000000, 0xFFFF0000, 0x0000FFFF }, /* VFP_HI_REGS */ \ + { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF }, /* VFP_REGS */ \ + { 0x00000000, 0x00000000, 0x00010000 }, /* CC_REG */ \ + { 0x00000000, 0x00000000, 0x00020000 }, /* VFPCC_REG */ \ + { 0x00000000, 0x00000000, 0x00040000 }, /* SFP_REG */ \ + { 0x00000000, 0x00000000, 0x00080000 }, /* AFP_REG */ \ + { 0x00000000, 0x00000000, 0x00400000 }, /* VPR_REG. */ \ + { 0x00000000, 0x00000000, 0x00800000 }, /* PAC_REG. */ \ + { 0x00005FFF, 0x00000000, 0x00400000 }, /* GENERAL_AND_VPR_REGS. */ \ + { 0xFFFF7FFF, 0xFFFFFFFF, 0x0040FFFF } /* ALL_REGS. */ \ } #define FP_SYSREGS \ @@ -1460,39 +1409,34 @@ extern const char *fp_sysreg_names[NB_FP_SYSREGS]; /* Return the register class of a scratch register needed to copy IN into or out of a register in CLASS in MODE. If it can be done directly, NO_REGS is returned. */ -#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ - /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ - ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ - ? coproc_secondary_reload_class (MODE, X, FALSE) \ - : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ - ? coproc_secondary_reload_class (MODE, X, TRUE) \ - : TARGET_32BIT \ - ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ - ? GENERAL_REGS : NO_REGS) \ - : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) +#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ + /* Restrict which direct reloads are allowed for VFP regs. */ \ + ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ + ? coproc_secondary_reload_class (MODE, X, FALSE) \ + : (TARGET_32BIT \ + ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ + ? GENERAL_REGS \ + : NO_REGS) \ + : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))) /* If we need to load shorts byte-at-a-time, then we need a scratch. */ -#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ - /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ - ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ - ? coproc_secondary_reload_class (MODE, X, FALSE) : \ - (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ - coproc_secondary_reload_class (MODE, X, TRUE) : \ - (TARGET_32BIT ? \ - (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ - && CONSTANT_P (X)) \ - ? GENERAL_REGS : \ - (((MODE) == HImode && ! arm_arch4 \ - && (MEM_P (X) \ - || ((REG_P (X) || GET_CODE (X) == SUBREG) \ - && true_regnum (X) == -1))) \ - ? GENERAL_REGS : NO_REGS) \ - : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) +#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ + /* Restrict which direct reloads are allowed for VFP regs. */ \ + ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ + ? coproc_secondary_reload_class (MODE, X, FALSE) \ + : (TARGET_32BIT \ + ? (((MODE) == HImode \ + && ! arm_arch4 \ + && (MEM_P (X) \ + || ((REG_P (X) || GET_CODE (X) == SUBREG) \ + && true_regnum (X) == -1))) \ + ? GENERAL_REGS \ + : NO_REGS) \ + : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. - ARM regs are UNITS_PER_WORD bits. - FIXME: Is this true for iWMMX? */ + ARM regs are UNITS_PER_WORD bits. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ (CLASS == VPR_REG) \ ? CEIL (GET_MODE_SIZE (MODE), 2) \ @@ -1672,7 +1616,6 @@ enum arm_pcs { ARM_PCS_AAPCS, /* Base standard AAPCS. */ ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ - ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ /* This must be the last AAPCS variant. */ ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ ARM_PCS_ATPCS, /* ATPCS. */ @@ -1690,8 +1633,6 @@ typedef struct { /* This is the number of registers of arguments scanned so far. */ int nregs; - /* This is the number of iWMMXt register arguments scanned so far. */ - int iwmmxt_nregs; int named_count; int nargs; /* Which procedure call variant to use for this call. */ @@ -1739,9 +1680,7 @@ typedef struct #define FUNCTION_ARG_REGNO_P(REGNO) \ (IN_RANGE ((REGNO), 0, 3) \ || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \ - && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ - || (TARGET_IWMMXT_ABI \ - && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) + && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15))) /* If your target environment doesn't prefix user functions with an diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 597ef67..5e5e112 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -37,12 +37,12 @@ (LR_REGNUM 14) ; Return address register (PC_REGNUM 15) ; Program counter (LAST_ARM_REGNUM 15) ; - (CC_REGNUM 100) ; Condition code pseudo register - (VFPCC_REGNUM 101) ; VFP Condition code pseudo register - (APSRQ_REGNUM 104) ; Q bit pseudo register - (APSRGE_REGNUM 105) ; GE bits pseudo register - (VPR_REGNUM 106) ; Vector Predication Register - MVE register. - (RA_AUTH_CODE 107) ; Pseudo register to save PAC. + (CC_REGNUM 80) ; Condition code pseudo register + (VFPCC_REGNUM 81) ; VFP Condition code pseudo register + (APSRQ_REGNUM 84) ; Q bit pseudo register + (APSRGE_REGNUM 85) ; GE bits pseudo register + (VPR_REGNUM 86) ; Vector Predication Register - MVE register. + (RA_AUTH_CODE 87) ; Pseudo register to save PAC. ] ) ;; 3rd operand to select_dominance_cc_mode @@ -149,7 +149,7 @@ ; This attribute is used to compute attribute "enabled", ; use type "any" to enable an alternative in all cases. (define_attr "arch" "any, a, t, 32, t1, t2, v6,nov6, v6t2, \ - v8mb, fix_vlldm, iwmmxt, iwmmxt2, armv6_or_vfpv3, \ + v8mb, fix_vlldm, armv6_or_vfpv3, \ neon, mve" (const_string "any")) @@ -197,10 +197,6 @@ (match_test "fix_vlldm")) (const_string "yes") - (and (eq_attr "arch" "iwmmxt2") - (match_test "TARGET_REALLY_IWMMXT2")) - (const_string "yes") - (and (eq_attr "arch" "armv6_or_vfpv3") (match_test "arm_arch6 || TARGET_VFP3")) (const_string "yes") @@ -362,18 +358,7 @@ alus_ext, alus_imm, alus_sreg,\ alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\ logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\ - logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\ - wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\ - wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\ - wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\ - wmmx_wshufh, wmmx_wcmpeq, wmmx_wcmpgt, wmmx_wmax, wmmx_wmin, wmmx_wpack,\ - wmmx_wunpckih, wmmx_wunpckil, wmmx_wunpckeh, wmmx_wunpckel, wmmx_wror,\ - wmmx_wsra, wmmx_wsrl, wmmx_wsll, wmmx_wmadd, wmmx_tmia, wmmx_tmiaph,\ - wmmx_tmiaxy, wmmx_tbcst, wmmx_tmovmsk, wmmx_wacc, wmmx_waligni,\ - wmmx_walignr, wmmx_tandc, wmmx_textrc, wmmx_torc, wmmx_torvsc, wmmx_wsad,\ - wmmx_wabs, wmmx_wabsdiff, wmmx_waddsubhx, wmmx_wsubaddhx, wmmx_wavg4,\ - wmmx_wmulw, wmmx_wqmulm, wmmx_wqmulwm, wmmx_waddbhus, wmmx_wqmiaxy,\ - wmmx_wmiaxy, wmmx_wmiawxy, wmmx_wmerge") + logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel") (const_string "single") (const_string "multi"))) @@ -435,7 +420,6 @@ (const_string "yes") (const_string "no")))) -(include "marvell-f-iwmmxt.md") (include "arm-generic.md") (include "arm926ejs.md") (include "arm1020e.md") @@ -2893,14 +2877,12 @@ ;; Split DImode and, ior, xor operations. Simply perform the logical ;; operation on the upper and lower halves of the registers. ;; This is needed for atomic operations in arm_split_atomic_op. -;; Avoid splitting IWMMXT instructions. (define_split [(set (match_operand:DI 0 "s_register_operand" "") (match_operator:DI 6 "logical_binary_operator" [(match_operand:DI 1 "s_register_operand" "") (match_operand:DI 2 "s_register_operand" "")]))] - "TARGET_32BIT && reload_completed - && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)])) (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))] " @@ -6345,7 +6327,6 @@ "TARGET_32BIT && !(TARGET_HARD_FLOAT) && !(TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT) - && !TARGET_IWMMXT && ( register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" "* @@ -6554,7 +6535,7 @@ (define_insn "*arm_movsi_insn" [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m") (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk"))] - "TARGET_ARM && !TARGET_IWMMXT && !TARGET_HARD_FLOAT + "TARGET_ARM && !TARGET_HARD_FLOAT && ( register_operand (operands[0], SImode) || register_operand (operands[1], SImode))" "@ @@ -13123,10 +13104,8 @@ [(set_attr "conds" "unconditional") (set_attr "type" "nop")]) -;; Vector bits common to IWMMXT, Neon and MVE +;; Vector bits common to Neon and MVE (include "vec-common.md") -;; Load the Intel Wireless Multimedia Extension patterns -(include "iwmmxt.md") ;; Load the VFP co-processor patterns (include "vfp.md") ;; Thumb-1 patterns diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index 042cb54..d5eeeae 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -58,9 +58,6 @@ EnumValue Enum(arm_abi_type) String(aapcs) Value(ARM_ABI_AAPCS) EnumValue -Enum(arm_abi_type) String(iwmmxt) Value(ARM_ABI_IWMMXT) - -EnumValue Enum(arm_abi_type) String(aapcs-linux) Value(ARM_ABI_AAPCS_LINUX) mabort-on-noreturn diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 9f1a37a..24743a8 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -19,11 +19,12 @@ ;; <http://www.gnu.org/licenses/>. ;; The following register constraints have been used: -;; - in ARM/Thumb-2 state: t, w, x, y, z +;; - in ARM/Thumb-2 state: t, w, x ;; - in Thumb state: h, b ;; - in both states: l, c, k, q, Cs, Ts, US ;; In ARM state, 'l' is an alias for 'r' ;; 'f' and 'v' were previously used for FPA and MAVERICK registers. +;; 'y' and 'z' were previously used for iWMMX registers (removed after gcc-15) ;; The following normal constraints have been used: ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M @@ -39,7 +40,7 @@ ;; in all states: Pg ;; The following memory constraints have been used: -;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Uo, Up, Uf, Ux, Ul, Uz +;; in ARM/Thumb-2 state: Uh, Ut, Uv, Un, Um, Us, Uo, Up, Uf, Ux, Ul, Uz ;; in ARM state: Uq ;; in Thumb state: Uu, Uw ;; in all states: Q @@ -112,13 +113,6 @@ (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS" "The VFP registers @code{d0}-@code{d7}.") -(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS" - "The Intel iWMMX co-processor registers.") - -(define_register_constraint "z" - "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS" - "The Intel iWMMX GR registers.") - (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS" "In Thumb state the core registers @code{r0}-@code{r7}.") @@ -478,12 +472,6 @@ ? arm_coproc_mem_operand_no_writeback (op) : neon_vector_mem_operand (op, 2, true)"))) -(define_memory_constraint "Uy" - "@internal - In ARM/Thumb-2 state a valid iWMMX load/store address." - (and (match_code "mem") - (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)"))) - (define_memory_constraint "Un" "@internal In ARM/Thumb-2 state a valid address for Neon doubleword vector diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 743fe48..0c163ed 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -59,30 +59,25 @@ ;; A list of modes which the VFP unit can handle (define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")]) -;; Integer element sizes implemented by IWMMXT. -(define_mode_iterator VMMX [V2SI V4HI V8QI]) - -(define_mode_iterator VMMX2 [V4HI V2SI]) - ;; Integer element sizes for shifts. (define_mode_iterator VSHFT [V4HI V2SI DI]) -;; Integer and float modes supported by Neon and IWMMXT. +;; Integer and float modes supported by Neon. (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) -;; Integer and float modes supported by Neon, IWMMXT and MVE. +;; Integer and float modes supported by Neon and MVE. (define_mode_iterator VNIM1 [V16QI V8HI V4SI V4SF V2DI]) -;; Integer and float modes supported by Neon and IWMMXT but not MVE. +;; Integer and float modes supported by Neon but not MVE. (define_mode_iterator VNINOTM1 [V2SI V4HI V8QI V2SF]) -;; Integer and float modes supported by Neon and IWMMXT, except V2DI. +;; Integer and float modes supported by Neon, except V2DI. (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) -;; Integer modes supported by Neon and IWMMXT +;; Integer modes supported by Neon (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) -;; Integer modes supported by Neon and IWMMXT, except V2DI +;; Integer modes supported by Neon, except V2DI (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) ;; Double-width vector modes, on which we support arithmetic (no HF!) @@ -1644,9 +1639,6 @@ ;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM. (define_mode_attr arch [(CC_Z "32") (SI "t1")]) -;; Determine element size suffix from vector mode. -(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) - ;; vtbl<n> suffix for NEON vector modes. (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md deleted file mode 100644 index 0aa5dcd..0000000 --- a/gcc/config/arm/iwmmxt.md +++ /dev/null @@ -1,1766 +0,0 @@ -;; Patterns for the Intel Wireless MMX technology architecture. -;; Copyright (C) 2003-2025 Free Software Foundation, Inc. -;; Contributed by Red Hat. - -;; This file is part of GCC. - -;; GCC is free software; you can redistribute it and/or modify it under -;; the terms of the GNU General Public License as published by the Free -;; Software Foundation; either version 3, or (at your option) any later -;; version. - -;; GCC is distributed in the hope that it will be useful, but WITHOUT -;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -;; License for more details. - -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING3. If not see -;; <http://www.gnu.org/licenses/>. - -;; Register numbers. Need to sync with FIRST_IWMMXT_GR_REGNUM in arm.h -(define_constants - [(WCGR0 96) - (WCGR1 97) - (WCGR2 98) - (WCGR3 99) - ] -) - -(define_insn "tbcstv8qi" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_duplicate:V8QI (match_operand:QI 1 "s_register_operand" "r")))] - "TARGET_REALLY_IWMMXT" - "tbcstb%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tbcst")] -) - -(define_insn "tbcstv4hi" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_duplicate:V4HI (match_operand:HI 1 "s_register_operand" "r")))] - "TARGET_REALLY_IWMMXT" - "tbcsth%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tbcst")] -) - -(define_insn "tbcstv2si" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_duplicate:V2SI (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_REALLY_IWMMXT" - "tbcstw%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tbcst")] -) - -(define_insn "iwmmxt_iordi3" - [(set (match_operand:DI 0 "register_operand" "=y") - (ior:DI (match_operand:DI 1 "register_operand" "%y") - (match_operand:DI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wor%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "length" "4") - (set_attr "type" "wmmx_wor")] -) - -(define_insn "iwmmxt_xordi3" - [(set (match_operand:DI 0 "register_operand" "=y") - (xor:DI (match_operand:DI 1 "register_operand" "%y") - (match_operand:DI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wxor%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "length" "4") - (set_attr "type" "wmmx_wxor")] -) - -(define_insn "iwmmxt_anddi3" - [(set (match_operand:DI 0 "register_operand" "=y") - (and:DI (match_operand:DI 1 "register_operand" "%y") - (match_operand:DI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wand%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "length" "4") - (set_attr "type" "wmmx_wand")] -) - -(define_insn "iwmmxt_nanddi3" - [(set (match_operand:DI 0 "register_operand" "=y") - (and:DI (match_operand:DI 1 "register_operand" "y") - (not:DI (match_operand:DI 2 "register_operand" "y"))))] - "TARGET_REALLY_IWMMXT" - "wandn%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wandn")] -) - -(define_insn "*iwmmxt_arm_movdi" - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m,y,y,r, y,Uy,*w, r,*w,*w, *Uv") - (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r,y,r,y,Uy,y, r,*w,*w,*Uvi,*w"))] - "TARGET_REALLY_IWMMXT - && ( register_operand (operands[0], DImode) - || register_operand (operands[1], DImode))" - "* - switch (which_alternative) - { - case 0: - case 1: - case 2: - return \"#\"; - case 3: case 4: - return output_move_double (operands, true, NULL); - case 5: - return \"wmov%?\\t%0,%1\"; - case 6: - return \"tmcrr%?\\t%0,%Q1,%R1\"; - case 7: - return \"tmrrc%?\\t%Q0,%R0,%1\"; - case 8: - return \"wldrd%?\\t%0,%1\"; - case 9: - return \"wstrd%?\\t%1,%0\"; - case 10: - return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; - case 11: - return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; - case 12: - if (TARGET_VFP_SINGLE) - return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\"; - else - return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; - case 13: case 14: - return output_move_vfp (operands); - default: - gcc_unreachable (); - } - " - [(set (attr "length") (cond [(eq_attr "alternative" "0,3,4") (const_int 8) - (eq_attr "alternative" "1") (const_int 12) - (eq_attr "alternative" "2") (const_int 16) - (eq_attr "alternative" "12") - (if_then_else - (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1)) - (const_int 8) - (const_int 4))] - (const_int 4))) - (set_attr "type" "*,*,*,load_8,store_8,*,*,*,*,*,f_mcrr,f_mrrc,\ - ffarithd,f_loadd,f_stored") - (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,1020,*") - (set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*")] -) - -(define_insn "*iwmmxt_movsi_insn" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk, m,z,r,?z,?Uy,*t, r,*t,*t ,*Uv") - (match_operand:SI 1 "general_operand" " rk,I,K,j,mi,rk,r,z,Uy, z, r,*t,*t,*Uvi, *t"))] - "TARGET_REALLY_IWMMXT - && ( register_operand (operands[0], SImode) - || register_operand (operands[1], SImode))" - "* - switch (which_alternative) - { - case 0: return \"mov\\t%0, %1\"; - case 1: return \"mov\\t%0, %1\"; - case 2: return \"mvn\\t%0, #%B1\"; - case 3: return \"movw\\t%0, %1\"; - case 4: return \"ldr\\t%0, %1\"; - case 5: return \"str\\t%1, %0\"; - case 6: return \"tmcr\\t%0, %1\"; - case 7: return \"tmrc\\t%0, %1\"; - case 8: return arm_output_load_gr (operands); - case 9: return \"wstrw\\t%1, %0\"; - case 10:return \"fmsr\\t%0, %1\"; - case 11:return \"fmrs\\t%0, %1\"; - case 12:return \"fcpys\\t%0, %1\\t%@ int\"; - case 13: case 14: - return output_move_vfp (operands); - default: - gcc_unreachable (); - }" - [(set_attr "type" "*,*,*,*,load_4,store_4,*,*,*,*,f_mcr,f_mrc,\ - fmov,f_loads,f_stores") - (set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*") - (set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024, *,*,*,*,1020,*") - (set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *, 1012,*,*,*,1008,*") - ;; Note - the "predicable" attribute is not allowed to have alternatives. - ;; Since the wSTRw wCx instruction is not predicable, we cannot support - ;; predicating any of the alternatives in this template. Instead, - ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn. - (set_attr "predicable" "no") - ;; Also - we have to pretend that these insns clobber the condition code - ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize - ;; them. - (set_attr "conds" "clob")] -) - -;; Because iwmmxt_movsi_insn is not predicable, we provide the -;; cond_exec version explicitly, with appropriate constraints. - -(define_insn "*cond_iwmmxt_movsi_insn" - [(cond_exec - (match_operator 2 "arm_comparison_operator" - [(match_operand 3 "cc_register" "") - (const_int 0)]) - (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r") - (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z")))] - "TARGET_REALLY_IWMMXT - && ( register_operand (operands[0], SImode) - || register_operand (operands[1], SImode))" - "* - switch (which_alternative) - { - case 0: return \"mov%?\\t%0, %1\"; - case 1: return \"mvn%?\\t%0, #%B1\"; - case 2: return \"ldr%?\\t%0, %1\"; - case 3: return \"str%?\\t%1, %0\"; - case 4: return \"tmcr%?\\t%0, %1\"; - default: return \"tmrc%?\\t%0, %1\"; - }" - [(set_attr "type" "*,*,load_4,store_4,*,*") - (set_attr "pool_range" "*,*,4096, *,*,*") - (set_attr "neg_pool_range" "*,*,4084, *,*,*")] -) - -(define_insn "mov<mode>_internal" - [(set (match_operand:VMMX 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r,?m") - (match_operand:VMMX 1 "general_operand" "y,y,mi,y,r,r,mi,r"))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: return \"wmov%?\\t%0, %1\"; - case 1: return \"wstrd%?\\t%1, %0\"; - case 2: return \"wldrd%?\\t%0, %1\"; - case 3: return \"tmrrc%?\\t%Q0, %R0, %1\"; - case 4: return \"tmcrr%?\\t%0, %Q1, %R1\"; - case 5: return \"#\"; - default: return output_move_double (operands, true, NULL); - }" - [(set_attr "predicable" "yes") - (set_attr "length" "4, 4, 4,4,4,8, 8,8") - (set_attr "type" "wmmx_wmov,wmmx_wstr,wmmx_wldr,wmmx_tmrrc,wmmx_tmcrr,*,load_4,store_4") - (set_attr "pool_range" "*, *, 256,*,*,*, 256,*") - (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244,*")] -) - -(define_expand "iwmmxt_setwcgr0" - [(set (reg:SI WCGR0) - (match_operand:SI 0 "register_operand"))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_expand "iwmmxt_setwcgr1" - [(set (reg:SI WCGR1) - (match_operand:SI 0 "register_operand"))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_expand "iwmmxt_setwcgr2" - [(set (reg:SI WCGR2) - (match_operand:SI 0 "register_operand"))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_expand "iwmmxt_setwcgr3" - [(set (reg:SI WCGR3) - (match_operand:SI 0 "register_operand"))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_expand "iwmmxt_getwcgr0" - [(set (match_operand:SI 0 "register_operand") - (reg:SI WCGR0))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_expand "iwmmxt_getwcgr1" - [(set (match_operand:SI 0 "register_operand") - (reg:SI WCGR1))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_expand "iwmmxt_getwcgr2" - [(set (match_operand:SI 0 "register_operand") - (reg:SI WCGR2))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_expand "iwmmxt_getwcgr3" - [(set (match_operand:SI 0 "register_operand") - (reg:SI WCGR3))] - "TARGET_REALLY_IWMMXT" - {} -) - -(define_insn "*and<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (and:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wand\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wand")] -) - -(define_insn "*ior<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (ior:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wor\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wor")] -) - -(define_insn "*xor<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (xor:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wxor\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wxor")] -) - - -;; Vector add/subtract - -(define_insn "*add<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (plus:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wadd<MMX_char>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "ssaddv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "waddbss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "ssaddv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "waddhss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "ssaddv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "waddwss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "usaddv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "waddbus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "usaddv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "waddhus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "usaddv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "waddwus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "*sub<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (minus:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsub<MMX_char>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsub")] -) - -(define_insn "sssubv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsubbss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsub")] -) - -(define_insn "sssubv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsubhss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsub")] -) - -(define_insn "sssubv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsubwss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsub")] -) - -(define_insn "ussubv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsubbus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsub")] -) - -(define_insn "ussubv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsubhus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsub")] -) - -(define_insn "ussubv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsubwus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsub")] -) - -(define_insn "*mulv4hi3_iwmmxt" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (mult:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wmulul%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmul")] -) - -(define_insn "smulv4hi3_highpart" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (truncate:V4HI - (lshiftrt:V4SI - (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) - (const_int 16))))] - "TARGET_REALLY_IWMMXT" - "wmulsm%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmul")] -) - -(define_insn "umulv4hi3_highpart" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (truncate:V4HI - (lshiftrt:V4SI - (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) - (const_int 16))))] - "TARGET_REALLY_IWMMXT" - "wmulum%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmul")] -) - -(define_insn "iwmmxt_wmacs" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:DI 1 "register_operand" "0") - (match_operand:V4HI 2 "register_operand" "y") - (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))] - "TARGET_REALLY_IWMMXT" - "wmacs%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmac")] -) - -(define_insn "iwmmxt_wmacsz" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))] - "TARGET_REALLY_IWMMXT" - "wmacsz%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmac")] -) - -(define_insn "iwmmxt_wmacu" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:DI 1 "register_operand" "0") - (match_operand:V4HI 2 "register_operand" "y") - (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))] - "TARGET_REALLY_IWMMXT" - "wmacu%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmac")] -) - -(define_insn "iwmmxt_wmacuz" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))] - "TARGET_REALLY_IWMMXT" - "wmacuz%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmac")] -) - -;; Same as xordi3, but don't show input operands so that we don't think -;; they are live. -(define_insn "iwmmxt_clrdi" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(const_int 0)] UNSPEC_CLRDI))] - "TARGET_REALLY_IWMMXT" - "wxor%?\\t%0, %0, %0" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wxor")] -) - -;; Seems like cse likes to generate these, so we have to support them. - -(define_insn "iwmmxt_clrv8qi" - [(set (match_operand:V8QI 0 "s_register_operand" "=y") - (const_vector:V8QI [(const_int 0) (const_int 0) - (const_int 0) (const_int 0) - (const_int 0) (const_int 0) - (const_int 0) (const_int 0)]))] - "TARGET_REALLY_IWMMXT" - "wxor%?\\t%0, %0, %0" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wxor")] -) - -(define_insn "iwmmxt_clrv4hi" - [(set (match_operand:V4HI 0 "s_register_operand" "=y") - (const_vector:V4HI [(const_int 0) (const_int 0) - (const_int 0) (const_int 0)]))] - "TARGET_REALLY_IWMMXT" - "wxor%?\\t%0, %0, %0" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wxor")] -) - -(define_insn "iwmmxt_clrv2si" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (const_vector:V2SI [(const_int 0) (const_int 0)]))] - "TARGET_REALLY_IWMMXT" - "wxor%?\\t%0, %0, %0" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wxor")] -) - -;; Unsigned averages/sum of absolute differences - -(define_insn "iwmmxt_uavgrndv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (truncate:V8QI - (lshiftrt:V8HI - (plus:V8HI - (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y"))) - (const_vector:V8HI [(const_int 1) - (const_int 1) - (const_int 1) - (const_int 1) - (const_int 1) - (const_int 1) - (const_int 1) - (const_int 1)])) - (const_int 1))))] - "TARGET_REALLY_IWMMXT" - "wavg2br%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wavg2")] -) - -(define_insn "iwmmxt_uavgrndv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (truncate:V4HI - (lshiftrt:V4SI - (plus:V4SI - (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) - (const_vector:V4SI [(const_int 1) - (const_int 1) - (const_int 1) - (const_int 1)])) - (const_int 1))))] - "TARGET_REALLY_IWMMXT" - "wavg2hr%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wavg2")] -) - -(define_insn "iwmmxt_uavgv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (truncate:V8QI - (lshiftrt:V8HI - (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y"))) - (const_int 1))))] - "TARGET_REALLY_IWMMXT" - "wavg2b%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wavg2")] -) - -(define_insn "iwmmxt_uavgv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (truncate:V4HI - (lshiftrt:V4SI - (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) - (const_int 1))))] - "TARGET_REALLY_IWMMXT" - "wavg2h%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wavg2")] -) - -;; Insert/extract/shuffle - -(define_insn "iwmmxt_tinsrb" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_merge:V8QI - (vec_duplicate:V8QI - (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r"))) - (match_operand:V8QI 1 "register_operand" "0") - (match_operand:SI 3 "immediate_operand" "i")))] - "TARGET_REALLY_IWMMXT" - "* - { - return arm_output_iwmmxt_tinsr (operands); - } - " - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tinsr")] -) - -(define_insn "iwmmxt_tinsrh" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_merge:V4HI - (vec_duplicate:V4HI - (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r"))) - (match_operand:V4HI 1 "register_operand" "0") - (match_operand:SI 3 "immediate_operand" "i")))] - "TARGET_REALLY_IWMMXT" - "* - { - return arm_output_iwmmxt_tinsr (operands); - } - " - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tinsr")] -) - -(define_insn "iwmmxt_tinsrw" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_merge:V2SI - (vec_duplicate:V2SI - (match_operand:SI 2 "nonimmediate_operand" "r")) - (match_operand:V2SI 1 "register_operand" "0") - (match_operand:SI 3 "immediate_operand" "i")))] - "TARGET_REALLY_IWMMXT" - "* - { - return arm_output_iwmmxt_tinsr (operands); - } - " - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tinsr")] -) - -(define_insn "iwmmxt_textrmub" - [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y") - (parallel - [(match_operand:SI 2 "immediate_operand" "i")]))))] - "TARGET_REALLY_IWMMXT" - "textrmub%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_textrm")] -) - -(define_insn "iwmmxt_textrmsb" - [(set (match_operand:SI 0 "register_operand" "=r") - (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y") - (parallel - [(match_operand:SI 2 "immediate_operand" "i")]))))] - "TARGET_REALLY_IWMMXT" - "textrmsb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_textrm")] -) - -(define_insn "iwmmxt_textrmuh" - [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") - (parallel - [(match_operand:SI 2 "immediate_operand" "i")]))))] - "TARGET_REALLY_IWMMXT" - "textrmuh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_textrm")] -) - -(define_insn "iwmmxt_textrmsh" - [(set (match_operand:SI 0 "register_operand" "=r") - (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") - (parallel - [(match_operand:SI 2 "immediate_operand" "i")]))))] - "TARGET_REALLY_IWMMXT" - "textrmsh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_textrm")] -) - -;; There are signed/unsigned variants of this instruction, but they are -;; pointless. -(define_insn "iwmmxt_textrmw" - [(set (match_operand:SI 0 "register_operand" "=r") - (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") - (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] - "TARGET_REALLY_IWMMXT" - "textrmsw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_textrm")] -) - -(define_insn "iwmmxt_wshufh" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_WSHUFH))] - "TARGET_REALLY_IWMMXT" - "wshufh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wshufh")] -) - -;; Mask-generating comparisons -;; -;; Note - you cannot use patterns like these here: -;; -;; (set (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>))) -;; -;; Because GCC will assume that the truth value (1 or 0) is installed -;; into the entire destination vector, (with the '1' going into the least -;; significant element of the vector). This is not how these instructions -;; behave. - -(define_insn "eqv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")] - VUNSPEC_WCMP_EQ))] - "TARGET_REALLY_IWMMXT" - "wcmpeqb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpeq")] -) - -(define_insn "eqv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] - VUNSPEC_WCMP_EQ))] - "TARGET_REALLY_IWMMXT" - "wcmpeqh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpeq")] -) - -(define_insn "eqv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec_volatile:V2SI - [(match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")] - VUNSPEC_WCMP_EQ))] - "TARGET_REALLY_IWMMXT" - "wcmpeqw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpeq")] -) - -(define_insn "gtuv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")] - VUNSPEC_WCMP_GTU))] - "TARGET_REALLY_IWMMXT" - "wcmpgtub%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpgt")] -) - -(define_insn "gtuv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] - VUNSPEC_WCMP_GTU))] - "TARGET_REALLY_IWMMXT" - "wcmpgtuh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpgt")] -) - -(define_insn "gtuv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")] - VUNSPEC_WCMP_GTU))] - "TARGET_REALLY_IWMMXT" - "wcmpgtuw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpgt")] -) - -(define_insn "gtv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")] - VUNSPEC_WCMP_GT))] - "TARGET_REALLY_IWMMXT" - "wcmpgtsb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpgt")] -) - -(define_insn "gtv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] - VUNSPEC_WCMP_GT))] - "TARGET_REALLY_IWMMXT" - "wcmpgtsh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpgt")] -) - -(define_insn "gtv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")] - VUNSPEC_WCMP_GT))] - "TARGET_REALLY_IWMMXT" - "wcmpgtsw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wcmpgt")] -) - -;; Max/min insns - -(define_insn "*smax<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (smax:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wmaxs<MMX_char>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmax")] -) - -(define_insn "*umax<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (umax:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wmaxu<MMX_char>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmax")] -) - -(define_insn "*smin<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (smin:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wmins<MMX_char>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmin")] -) - -(define_insn "*umin<mode>3_iwmmxt" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (umin:VMMX (match_operand:VMMX 1 "register_operand" "y") - (match_operand:VMMX 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wminu<MMX_char>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmin")] -) - -;; Pack/unpack insns. - -(define_insn "iwmmxt_wpackhss" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_concat:V8QI - (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y")) - (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] - "TARGET_REALLY_IWMMXT" - "wpackhss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wpack")] -) - -(define_insn "iwmmxt_wpackwss" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_concat:V4HI - (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y")) - (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] - "TARGET_REALLY_IWMMXT" - "wpackwss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wpack")] -) - -(define_insn "iwmmxt_wpackdss" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_concat:V2SI - (ss_truncate:SI (match_operand:DI 1 "register_operand" "y")) - (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))] - "TARGET_REALLY_IWMMXT" - "wpackdss%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wpack")] -) - -(define_insn "iwmmxt_wpackhus" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_concat:V8QI - (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y")) - (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] - "TARGET_REALLY_IWMMXT" - "wpackhus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wpack")] -) - -(define_insn "iwmmxt_wpackwus" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_concat:V4HI - (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y")) - (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] - "TARGET_REALLY_IWMMXT" - "wpackwus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wpack")] -) - -(define_insn "iwmmxt_wpackdus" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_concat:V2SI - (us_truncate:SI (match_operand:DI 1 "register_operand" "y")) - (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))] - "TARGET_REALLY_IWMMXT" - "wpackdus%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wpack")] -) - -(define_insn "iwmmxt_wunpckihb" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_merge:V8QI - (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y") - (parallel [(const_int 4) - (const_int 0) - (const_int 5) - (const_int 1) - (const_int 6) - (const_int 2) - (const_int 7) - (const_int 3)])) - (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") - (parallel [(const_int 0) - (const_int 4) - (const_int 1) - (const_int 5) - (const_int 2) - (const_int 6) - (const_int 3) - (const_int 7)])) - (const_int 85)))] - "TARGET_REALLY_IWMMXT" - "wunpckihb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckih")] -) - -(define_insn "iwmmxt_wunpckihh" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_merge:V4HI - (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y") - (parallel [(const_int 2) - (const_int 0) - (const_int 3) - (const_int 1)])) - (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 0) - (const_int 2) - (const_int 1) - (const_int 3)])) - (const_int 5)))] - "TARGET_REALLY_IWMMXT" - "wunpckihh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckih")] -) - -(define_insn "iwmmxt_wunpckihw" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_merge:V2SI - (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y") - (parallel [(const_int 1) - (const_int 0)])) - (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") - (parallel [(const_int 0) - (const_int 1)])) - (const_int 1)))] - "TARGET_REALLY_IWMMXT" - "wunpckihw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckih")] -) - -(define_insn "iwmmxt_wunpckilb" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_merge:V8QI - (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y") - (parallel [(const_int 0) - (const_int 4) - (const_int 1) - (const_int 5) - (const_int 2) - (const_int 6) - (const_int 3) - (const_int 7)])) - (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") - (parallel [(const_int 4) - (const_int 0) - (const_int 5) - (const_int 1) - (const_int 6) - (const_int 2) - (const_int 7) - (const_int 3)])) - (const_int 85)))] - "TARGET_REALLY_IWMMXT" - "wunpckilb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckil")] -) - -(define_insn "iwmmxt_wunpckilh" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_merge:V4HI - (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y") - (parallel [(const_int 0) - (const_int 2) - (const_int 1) - (const_int 3)])) - (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 2) - (const_int 0) - (const_int 3) - (const_int 1)])) - (const_int 5)))] - "TARGET_REALLY_IWMMXT" - "wunpckilh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckil")] -) - -(define_insn "iwmmxt_wunpckilw" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_merge:V2SI - (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y") - (parallel [(const_int 0) - (const_int 1)])) - (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") - (parallel [(const_int 1) - (const_int 0)])) - (const_int 1)))] - "TARGET_REALLY_IWMMXT" - "wunpckilw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckil")] -) - -(define_insn "iwmmxt_wunpckehub" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_select:V4HI - (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (parallel [(const_int 4) (const_int 5) - (const_int 6) (const_int 7)])))] - "TARGET_REALLY_IWMMXT" - "wunpckehub%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckeh")] -) - -(define_insn "iwmmxt_wunpckehuh" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_select:V2SI - (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 2) (const_int 3)])))] - "TARGET_REALLY_IWMMXT" - "wunpckehuh%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckeh")] -) - -(define_insn "iwmmxt_wunpckehuw" - [(set (match_operand:DI 0 "register_operand" "=y") - (vec_select:DI - (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (parallel [(const_int 1)])))] - "TARGET_REALLY_IWMMXT" - "wunpckehuw%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckeh")] -) - -(define_insn "iwmmxt_wunpckehsb" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_select:V4HI - (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (parallel [(const_int 4) (const_int 5) - (const_int 6) (const_int 7)])))] - "TARGET_REALLY_IWMMXT" - "wunpckehsb%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckeh")] -) - -(define_insn "iwmmxt_wunpckehsh" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_select:V2SI - (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 2) (const_int 3)])))] - "TARGET_REALLY_IWMMXT" - "wunpckehsh%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckeh")] -) - -(define_insn "iwmmxt_wunpckehsw" - [(set (match_operand:DI 0 "register_operand" "=y") - (vec_select:DI - (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (parallel [(const_int 1)])))] - "TARGET_REALLY_IWMMXT" - "wunpckehsw%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckeh")] -) - -(define_insn "iwmmxt_wunpckelub" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_select:V4HI - (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (parallel [(const_int 0) (const_int 1) - (const_int 2) (const_int 3)])))] - "TARGET_REALLY_IWMMXT" - "wunpckelub%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckel")] -) - -(define_insn "iwmmxt_wunpckeluh" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_select:V2SI - (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 0) (const_int 1)])))] - "TARGET_REALLY_IWMMXT" - "wunpckeluh%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckel")] -) - -(define_insn "iwmmxt_wunpckeluw" - [(set (match_operand:DI 0 "register_operand" "=y") - (vec_select:DI - (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (parallel [(const_int 0)])))] - "TARGET_REALLY_IWMMXT" - "wunpckeluw%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckel")] -) - -(define_insn "iwmmxt_wunpckelsb" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_select:V4HI - (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (parallel [(const_int 0) (const_int 1) - (const_int 2) (const_int 3)])))] - "TARGET_REALLY_IWMMXT" - "wunpckelsb%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckel")] -) - -(define_insn "iwmmxt_wunpckelsh" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (vec_select:V2SI - (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 0) (const_int 1)])))] - "TARGET_REALLY_IWMMXT" - "wunpckelsh%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckel")] -) - -(define_insn "iwmmxt_wunpckelsw" - [(set (match_operand:DI 0 "register_operand" "=y") - (vec_select:DI - (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (parallel [(const_int 0)])))] - "TARGET_REALLY_IWMMXT" - "wunpckelsw%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wunpckel")] -) - -;; Shifts - -(define_insn "ror<mode>3" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:SI 2 "imm_or_reg_operand" "z,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wror<MMX_char>g%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wror, wmmx_wror")] -) - -(define_insn "ashr<mode>3_iwmmxt" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:SI 2 "imm_or_reg_operand" "z,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wsra<MMX_char>g%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wsra, wmmx_wsra")] -) - -(define_insn "lshr<mode>3_iwmmxt" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:SI 2 "imm_or_reg_operand" "z,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wsrl<MMX_char>g%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wsrl, wmmx_wsrl")] -) - -(define_insn "ashl<mode>3_iwmmxt" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:SI 2 "imm_or_reg_operand" "z,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wsll<MMX_char>g%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wsll, wmmx_wsll")] -) - -(define_insn "ror<mode>3_di" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:DI 2 "imm_or_reg_operand" "y,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wror<MMX_char>%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wror, wmmx_wror")] -) - -(define_insn "ashr<mode>3_di" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:DI 2 "imm_or_reg_operand" "y,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wsra<MMX_char>%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wsra, wmmx_wsra")] -) - -(define_insn "lshr<mode>3_di" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:DI 2 "register_operand" "y,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wsrl<MMX_char>%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wsrl, wmmx_wsrl")] -) - -(define_insn "ashl<mode>3_di" - [(set (match_operand:VSHFT 0 "register_operand" "=y,y") - (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") - (match_operand:DI 2 "imm_or_reg_operand" "y,i")))] - "TARGET_REALLY_IWMMXT" - "* - switch (which_alternative) - { - case 0: - return \"wsll<MMX_char>%?\\t%0, %1, %2\"; - case 1: - return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false); - default: - gcc_unreachable (); - } - " - [(set_attr "predicable" "yes") - (set_attr "arch" "*, iwmmxt2") - (set_attr "type" "wmmx_wsll, wmmx_wsll")] -) - -(define_insn "iwmmxt_wmadds" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (plus:V2SI - (mult:V2SI - (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 1) (const_int 3)])) - (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")) - (parallel [(const_int 1) (const_int 3)]))) - (mult:V2SI - (vec_select:V2SI (sign_extend:V4SI (match_dup 1)) - (parallel [(const_int 0) (const_int 2)])) - (vec_select:V2SI (sign_extend:V4SI (match_dup 2)) - (parallel [(const_int 0) (const_int 2)])))))] - "TARGET_REALLY_IWMMXT" - "wmadds%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmadd")] -) - -(define_insn "iwmmxt_wmaddu" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (plus:V2SI - (mult:V2SI - (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 1) (const_int 3)])) - (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")) - (parallel [(const_int 1) (const_int 3)]))) - (mult:V2SI - (vec_select:V2SI (zero_extend:V4SI (match_dup 1)) - (parallel [(const_int 0) (const_int 2)])) - (vec_select:V2SI (zero_extend:V4SI (match_dup 2)) - (parallel [(const_int 0) (const_int 2)])))))] - "TARGET_REALLY_IWMMXT" - "wmaddu%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmadd")] -) - -(define_insn "iwmmxt_tmia" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (mult:DI (sign_extend:DI - (match_operand:SI 2 "register_operand" "r")) - (sign_extend:DI - (match_operand:SI 3 "register_operand" "r")))))] - "TARGET_REALLY_IWMMXT" - "tmia%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmia")] -) - -(define_insn "iwmmxt_tmiaph" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI (sign_extend:DI - (truncate:HI (match_operand:SI 2 "register_operand" "r"))) - (sign_extend:DI - (truncate:HI (match_operand:SI 3 "register_operand" "r")))) - (mult:DI (sign_extend:DI - (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16)))) - (sign_extend:DI - (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))] - "TARGET_REALLY_IWMMXT" - "tmiaph%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmiaph")] -) - -(define_insn "iwmmxt_tmiabb" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (mult:DI (sign_extend:DI - (truncate:HI (match_operand:SI 2 "register_operand" "r"))) - (sign_extend:DI - (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))] - "TARGET_REALLY_IWMMXT" - "tmiabb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmiaxy")] -) - -(define_insn "iwmmxt_tmiatb" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (mult:DI (sign_extend:DI - (truncate:HI - (ashiftrt:SI - (match_operand:SI 2 "register_operand" "r") - (const_int 16)))) - (sign_extend:DI - (truncate:HI - (match_operand:SI 3 "register_operand" "r"))))))] - "TARGET_REALLY_IWMMXT" - "tmiatb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmiaxy")] -) - -(define_insn "iwmmxt_tmiabt" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (mult:DI (sign_extend:DI - (truncate:HI - (match_operand:SI 2 "register_operand" "r"))) - (sign_extend:DI - (truncate:HI - (ashiftrt:SI - (match_operand:SI 3 "register_operand" "r") - (const_int 16)))))))] - "TARGET_REALLY_IWMMXT" - "tmiabt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmiaxy")] -) - -(define_insn "iwmmxt_tmiatt" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (mult:DI (sign_extend:DI - (truncate:HI - (ashiftrt:SI - (match_operand:SI 2 "register_operand" "r") - (const_int 16)))) - (sign_extend:DI - (truncate:HI - (ashiftrt:SI - (match_operand:SI 3 "register_operand" "r") - (const_int 16)))))))] - "TARGET_REALLY_IWMMXT" - "tmiatt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmiaxy")] -) - -(define_insn "iwmmxt_tmovmskb" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] - "TARGET_REALLY_IWMMXT" - "tmovmskb%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmovmsk")] -) - -(define_insn "iwmmxt_tmovmskh" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] - "TARGET_REALLY_IWMMXT" - "tmovmskh%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmovmsk")] -) - -(define_insn "iwmmxt_tmovmskw" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] - "TARGET_REALLY_IWMMXT" - "tmovmskw%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tmovmsk")] -) - -(define_insn "iwmmxt_waccb" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))] - "TARGET_REALLY_IWMMXT" - "waccb%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wacc")] -) - -(define_insn "iwmmxt_wacch" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))] - "TARGET_REALLY_IWMMXT" - "wacch%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wacc")] -) - -(define_insn "iwmmxt_waccw" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))] - "TARGET_REALLY_IWMMXT" - "waccw%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wacc")] -) - -;; use unspec here to prevent 8 * imm to be optimized by cse -(define_insn "iwmmxt_waligni" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (unspec:V8QI [(subreg:V8QI - (ashiftrt:TI - (subreg:TI (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")) 0) - (mult:SI - (match_operand:SI 3 "immediate_operand" "i") - (const_int 8))) 0)] UNSPEC_WALIGNI))] - "TARGET_REALLY_IWMMXT" - "waligni%?\\t%0, %1, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_waligni")] -) - -(define_insn "iwmmxt_walignr" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (subreg:V8QI (ashiftrt:TI - (subreg:TI (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")) 0) - (mult:SI - (zero_extract:SI (match_operand:SI 3 "register_operand" "z") (const_int 3) (const_int 0)) - (const_int 8))) 0))] - "TARGET_REALLY_IWMMXT" - "walignr%U3%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_walignr")] -) - -(define_insn "iwmmxt_walignr0" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (subreg:V8QI (ashiftrt:TI - (subreg:TI (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")) 0) - (mult:SI - (zero_extract:SI (reg:SI WCGR0) (const_int 3) (const_int 0)) - (const_int 8))) 0))] - "TARGET_REALLY_IWMMXT" - "walignr0%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_walignr")] -) - -(define_insn "iwmmxt_walignr1" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (subreg:V8QI (ashiftrt:TI - (subreg:TI (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")) 0) - (mult:SI - (zero_extract:SI (reg:SI WCGR1) (const_int 3) (const_int 0)) - (const_int 8))) 0))] - "TARGET_REALLY_IWMMXT" - "walignr1%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_walignr")] -) - -(define_insn "iwmmxt_walignr2" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (subreg:V8QI (ashiftrt:TI - (subreg:TI (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")) 0) - (mult:SI - (zero_extract:SI (reg:SI WCGR2) (const_int 3) (const_int 0)) - (const_int 8))) 0))] - "TARGET_REALLY_IWMMXT" - "walignr2%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_walignr")] -) - -(define_insn "iwmmxt_walignr3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (subreg:V8QI (ashiftrt:TI - (subreg:TI (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")) 0) - (mult:SI - (zero_extract:SI (reg:SI WCGR3) (const_int 3) (const_int 0)) - (const_int 8))) 0))] - "TARGET_REALLY_IWMMXT" - "walignr3%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_walignr")] -) - -(define_insn "iwmmxt_wsadb" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [ - (match_operand:V2SI 1 "register_operand" "0") - (match_operand:V8QI 2 "register_operand" "y") - (match_operand:V8QI 3 "register_operand" "y")] UNSPEC_WSAD))] - "TARGET_REALLY_IWMMXT" - "wsadb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsad")] -) - -(define_insn "iwmmxt_wsadh" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [ - (match_operand:V2SI 1 "register_operand" "0") - (match_operand:V4HI 2 "register_operand" "y") - (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WSAD))] - "TARGET_REALLY_IWMMXT" - "wsadh%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsad")] -) - -(define_insn "iwmmxt_wsadbz" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))] - "TARGET_REALLY_IWMMXT" - "wsadbz%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsad")] -) - -(define_insn "iwmmxt_wsadhz" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))] - "TARGET_REALLY_IWMMXT" - "wsadhz%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsad")] -) - -(include "iwmmxt2.md") diff --git a/gcc/config/arm/iwmmxt2.md b/gcc/config/arm/iwmmxt2.md deleted file mode 100644 index 74cd148..0000000 --- a/gcc/config/arm/iwmmxt2.md +++ /dev/null @@ -1,903 +0,0 @@ -;; Patterns for the Intel Wireless MMX technology architecture. -;; Copyright (C) 2011-2025 Free Software Foundation, Inc. -;; Written by Marvell, Inc. -;; -;; This file is part of GCC. -;; -;; GCC is free software; you can redistribute it and/or modify it -;; under the terms of the GNU General Public License as published -;; by the Free Software Foundation; either version 3, or (at your -;; option) any later version. - -;; GCC is distributed in the hope that it will be useful, but WITHOUT -;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -;; License for more details. - -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING3. If not see -;; <http://www.gnu.org/licenses/>. - -(define_insn "iwmmxt_wabs<mode>3" - [(set (match_operand:VMMX 0 "register_operand" "=y") - (unspec:VMMX [(match_operand:VMMX 1 "register_operand" "y")] UNSPEC_WABS))] - "TARGET_REALLY_IWMMXT" - "wabs<MMX_char>%?\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wabs")] -) - -(define_insn "iwmmxt_wabsdiffb" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (truncate:V8QI - (abs:V8HI - (minus:V8HI - (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y"))))))] - "TARGET_REALLY_IWMMXT" - "wabsdiffb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wabsdiff")] -) - -(define_insn "iwmmxt_wabsdiffh" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (truncate: V4HI - (abs:V4SI - (minus:V4SI - (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))))))] - "TARGET_REALLY_IWMMXT" - "wabsdiffh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wabsdiff")] -) - -(define_insn "iwmmxt_wabsdiffw" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (truncate: V2SI - (abs:V2DI - (minus:V2DI - (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (zero_extend:V2DI (match_operand:V2SI 2 "register_operand" "y"))))))] - "TARGET_REALLY_IWMMXT" - "wabsdiffw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wabsdiff")] -) - -(define_insn "iwmmxt_waddsubhx" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_merge:V4HI - (ss_minus:V4HI - (match_operand:V4HI 1 "register_operand" "y") - (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)]))) - (ss_plus:V4HI - (match_dup 1) - (vec_select:V4HI (match_dup 2) - (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)]))) - (const_int 10)))] - "TARGET_REALLY_IWMMXT" - "waddsubhx%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_waddsubhx")] -) - -(define_insn "iwmmxt_wsubaddhx" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (vec_merge:V4HI - (ss_plus:V4HI - (match_operand:V4HI 1 "register_operand" "y") - (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)]))) - (ss_minus:V4HI - (match_dup 1) - (vec_select:V4HI (match_dup 2) - (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)]))) - (const_int 10)))] - "TARGET_REALLY_IWMMXT" - "wsubaddhx%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wsubaddhx")] -) - -(define_insn "addc<mode>3" - [(set (match_operand:VMMX2 0 "register_operand" "=y") - (unspec:VMMX2 - [(plus:VMMX2 - (match_operand:VMMX2 1 "register_operand" "y") - (match_operand:VMMX2 2 "register_operand" "y"))] UNSPEC_WADDC))] - "TARGET_REALLY_IWMMXT" - "wadd<MMX_char>c%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wadd")] -) - -(define_insn "iwmmxt_avg4" -[(set (match_operand:V8QI 0 "register_operand" "=y") - (truncate:V8QI - (vec_select:V8HI - (vec_merge:V8HI - (lshiftrt:V8HI - (plus:V8HI - (plus:V8HI - (plus:V8HI - (plus:V8HI - (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y"))) - (vec_select:V8HI (zero_extend:V8HI (match_dup 1)) - (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2) - (const_int 3) (const_int 4) (const_int 5) (const_int 6)]))) - (vec_select:V8HI (zero_extend:V8HI (match_dup 2)) - (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2) - (const_int 3) (const_int 4) (const_int 5) (const_int 6)]))) - (const_vector:V8HI [(const_int 1) (const_int 1) (const_int 1) (const_int 1) - (const_int 1) (const_int 1) (const_int 1) (const_int 1)])) - (const_int 2)) - (const_vector:V8HI [(const_int 0) (const_int 0) (const_int 0) (const_int 0) - (const_int 0) (const_int 0) (const_int 0) (const_int 0)]) - (const_int 254)) - (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 4) - (const_int 5) (const_int 6) (const_int 7) (const_int 0)]))))] - "TARGET_REALLY_IWMMXT" - "wavg4%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wavg4")] -) - -(define_insn "iwmmxt_avg4r" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (truncate:V8QI - (vec_select:V8HI - (vec_merge:V8HI - (lshiftrt:V8HI - (plus:V8HI - (plus:V8HI - (plus:V8HI - (plus:V8HI - (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) - (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y"))) - (vec_select:V8HI (zero_extend:V8HI (match_dup 1)) - (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2) - (const_int 3) (const_int 4) (const_int 5) (const_int 6)]))) - (vec_select:V8HI (zero_extend:V8HI (match_dup 2)) - (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2) - (const_int 3) (const_int 4) (const_int 5) (const_int 6)]))) - (const_vector:V8HI [(const_int 2) (const_int 2) (const_int 2) (const_int 2) - (const_int 2) (const_int 2) (const_int 2) (const_int 2)])) - (const_int 2)) - (const_vector:V8HI [(const_int 0) (const_int 0) (const_int 0) (const_int 0) - (const_int 0) (const_int 0) (const_int 0) (const_int 0)]) - (const_int 254)) - (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 4) - (const_int 5) (const_int 6) (const_int 7) (const_int 0)]))))] - "TARGET_REALLY_IWMMXT" - "wavg4r%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wavg4")] -) - -(define_insn "iwmmxt_wmaddsx" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (plus:V2SI - (mult:V2SI - (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 1) (const_int 3)])) - (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")) - (parallel [(const_int 0) (const_int 2)]))) - (mult:V2SI - (vec_select:V2SI (sign_extend:V4SI (match_dup 1)) - (parallel [(const_int 0) (const_int 2)])) - (vec_select:V2SI (sign_extend:V4SI (match_dup 2)) - (parallel [(const_int 1) (const_int 3)])))))] - "TARGET_REALLY_IWMMXT" - "wmaddsx%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmadd")] -) - -(define_insn "iwmmxt_wmaddux" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (plus:V2SI - (mult:V2SI - (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 1) (const_int 3)])) - (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")) - (parallel [(const_int 0) (const_int 2)]))) - (mult:V2SI - (vec_select:V2SI (zero_extend:V4SI (match_dup 1)) - (parallel [(const_int 0) (const_int 2)])) - (vec_select:V2SI (zero_extend:V4SI (match_dup 2)) - (parallel [(const_int 1) (const_int 3)])))))] - "TARGET_REALLY_IWMMXT" - "wmaddux%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmadd")] -) - -(define_insn "iwmmxt_wmaddsn" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (minus:V2SI - (mult:V2SI - (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 0) (const_int 2)])) - (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")) - (parallel [(const_int 0) (const_int 2)]))) - (mult:V2SI - (vec_select:V2SI (sign_extend:V4SI (match_dup 1)) - (parallel [(const_int 1) (const_int 3)])) - (vec_select:V2SI (sign_extend:V4SI (match_dup 2)) - (parallel [(const_int 1) (const_int 3)])))))] - "TARGET_REALLY_IWMMXT" - "wmaddsn%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmadd")] -) - -(define_insn "iwmmxt_wmaddun" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (minus:V2SI - (mult:V2SI - (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (parallel [(const_int 0) (const_int 2)])) - (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")) - (parallel [(const_int 0) (const_int 2)]))) - (mult:V2SI - (vec_select:V2SI (zero_extend:V4SI (match_dup 1)) - (parallel [(const_int 1) (const_int 3)])) - (vec_select:V2SI (zero_extend:V4SI (match_dup 2)) - (parallel [(const_int 1) (const_int 3)])))))] - "TARGET_REALLY_IWMMXT" - "wmaddun%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmadd")] -) - -(define_insn "iwmmxt_wmulwsm" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (truncate:V2SI - (ashiftrt:V2DI - (mult:V2DI - (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" "y"))) - (const_int 32))))] - "TARGET_REALLY_IWMMXT" - "wmulwsm%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmulw")] -) - -(define_insn "iwmmxt_wmulwum" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (truncate:V2SI - (lshiftrt:V2DI - (mult:V2DI - (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (zero_extend:V2DI (match_operand:V2SI 2 "register_operand" "y"))) - (const_int 32))))] - "TARGET_REALLY_IWMMXT" - "wmulwum%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmulw")] -) - -(define_insn "iwmmxt_wmulsmr" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (truncate:V4HI - (ashiftrt:V4SI - (plus:V4SI - (mult:V4SI - (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) - (const_vector:V4SI [(const_int 32768) - (const_int 32768) - (const_int 32768)])) - (const_int 16))))] - "TARGET_REALLY_IWMMXT" - "wmulsmr%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmul")] -) - -(define_insn "iwmmxt_wmulumr" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (truncate:V4HI - (lshiftrt:V4SI - (plus:V4SI - (mult:V4SI - (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) - (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) - (const_vector:V4SI [(const_int 32768) - (const_int 32768) - (const_int 32768) - (const_int 32768)])) - (const_int 16))))] - "TARGET_REALLY_IWMMXT" - "wmulumr%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmul")] -) - -(define_insn "iwmmxt_wmulwsmr" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (truncate:V2SI - (ashiftrt:V2DI - (plus:V2DI - (mult:V2DI - (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" "y"))) - (const_vector:V2DI [(const_int 2147483648) - (const_int 2147483648)])) - (const_int 32))))] - "TARGET_REALLY_IWMMXT" - "wmulwsmr%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmul")] -) - -(define_insn "iwmmxt_wmulwumr" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (truncate:V2SI - (lshiftrt:V2DI - (plus:V2DI - (mult:V2DI - (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) - (zero_extend:V2DI (match_operand:V2SI 2 "register_operand" "y"))) - (const_vector:V2DI [(const_int 2147483648) - (const_int 2147483648)])) - (const_int 32))))] - "TARGET_REALLY_IWMMXT" - "wmulwumr%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmulw")] -) - -(define_insn "iwmmxt_wmulwl" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (mult:V2SI - (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wmulwl%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmulw")] -) - -(define_insn "iwmmxt_wqmulm" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WQMULM))] - "TARGET_REALLY_IWMMXT" - "wqmulm%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmulm")] -) - -(define_insn "iwmmxt_wqmulwm" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")] UNSPEC_WQMULWM))] - "TARGET_REALLY_IWMMXT" - "wqmulwm%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmulwm")] -) - -(define_insn "iwmmxt_wqmulmr" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WQMULMR))] - "TARGET_REALLY_IWMMXT" - "wqmulmr%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmulm")] -) - -(define_insn "iwmmxt_wqmulwmr" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")] UNSPEC_WQMULWMR))] - "TARGET_REALLY_IWMMXT" - "wqmulwmr%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmulwm")] -) - -(define_insn "iwmmxt_waddbhusm" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_concat:V8QI - (const_vector:V4QI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)]) - (us_truncate:V4QI - (ss_plus:V4HI - (match_operand:V4HI 1 "register_operand" "y") - (zero_extend:V4HI - (vec_select:V4QI (match_operand:V8QI 2 "register_operand" "y") - (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)])))))))] - "TARGET_REALLY_IWMMXT" - "waddbhusm%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_waddbhus")] -) - -(define_insn "iwmmxt_waddbhusl" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_concat:V8QI - (us_truncate:V4QI - (ss_plus:V4HI - (match_operand:V4HI 1 "register_operand" "y") - (zero_extend:V4HI - (vec_select:V4QI (match_operand:V8QI 2 "register_operand" "y") - (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))) - (const_vector:V4QI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)])))] - "TARGET_REALLY_IWMMXT" - "waddbhusl%?\\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_waddbhus")] -) - -(define_insn "iwmmxt_wqmiabb" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxy))] - "TARGET_REALLY_IWMMXT" - "wqmiabb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wqmiabt" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxy))] - "TARGET_REALLY_IWMMXT" - "wqmiabt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wqmiatb" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxy))] - "TARGET_REALLY_IWMMXT" - "wqmiatb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wqmiatt" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxy))] - "TARGET_REALLY_IWMMXT" - "wqmiatt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wqmiabbn" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxyn))] - "TARGET_REALLY_IWMMXT" - "wqmiabbn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wqmiabtn" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxyn))] - "TARGET_REALLY_IWMMXT" - "wqmiabtn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wqmiatbn" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxyn))] - "TARGET_REALLY_IWMMXT" - "wqmiatbn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wqmiattn" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0") - (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48)) - (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16)) - (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxyn))] - "TARGET_REALLY_IWMMXT" - "wqmiattn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wqmiaxy")] -) - -(define_insn "iwmmxt_wmiabb" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 0)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 0)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 2)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 2)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiabb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiabt" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 0)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 1)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 2)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 3)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiabt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiatb" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 1)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 0)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 3)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 2)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiatb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiatt" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 1)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 1)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 3)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 3)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiatt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiabbn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 0)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 0)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 2)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 2)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiabbn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiabtn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 0)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 1)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 2)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 3)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiabtn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiatbn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 1)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 0)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 3)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 2)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiatbn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiattn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI (match_operand:DI 1 "register_operand" "0") - (plus:DI - (mult:DI - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 2 "register_operand" "y") - (parallel [(const_int 1)]))) - (sign_extend:DI - (vec_select:HI (match_operand:V4HI 3 "register_operand" "y") - (parallel [(const_int 1)])))) - (mult:DI - (sign_extend:DI - (vec_select:HI (match_dup 2) - (parallel [(const_int 3)]))) - (sign_extend:DI - (vec_select:HI (match_dup 3) - (parallel [(const_int 3)])))))))] - "TARGET_REALLY_IWMMXT" - "wmiattn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiaxy")] -) - -(define_insn "iwmmxt_wmiawbb" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawbb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmiawbt" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawbt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmiawtb" - [(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawtb%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmiawtt" -[(set (match_operand:DI 0 "register_operand" "=y") - (plus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawtt%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmiawbbn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawbbn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmiawbtn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawbtn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmiawtbn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawtbn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmiawttn" - [(set (match_operand:DI 0 "register_operand" "=y") - (minus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI - (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)]))) - (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))] - "TARGET_REALLY_IWMMXT" - "wmiawttn%?\\t%0, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmiawxy")] -) - -(define_insn "iwmmxt_wmerge" - [(set (match_operand:DI 0 "register_operand" "=y") - (ior:DI - (ashift:DI - (match_operand:DI 2 "register_operand" "y") - (minus:SI - (const_int 64) - (mult:SI - (match_operand:SI 3 "immediate_operand" "i") - (const_int 8)))) - (lshiftrt:DI - (ashift:DI - (match_operand:DI 1 "register_operand" "y") - (mult:SI - (match_dup 3) - (const_int 8))) - (mult:SI - (match_dup 3) - (const_int 8)))))] - "TARGET_REALLY_IWMMXT" - "wmerge%?\\t%0, %1, %2, %3" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_wmerge")] -) - -(define_insn "iwmmxt_tandc<mode>3" - [(set (reg:CC CC_REGNUM) - (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TANDC) 0)) - (unspec:CC [(reg:SI 15)] UNSPEC_TANDC)] - "TARGET_REALLY_IWMMXT" - "tandc<MMX_char>%?\\t r15" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_tandc")] -) - -(define_insn "iwmmxt_torc<mode>3" - [(set (reg:CC CC_REGNUM) - (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TORC) 0)) - (unspec:CC [(reg:SI 15)] UNSPEC_TORC)] - "TARGET_REALLY_IWMMXT" - "torc<MMX_char>%?\\t r15" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_torc")] -) - -(define_insn "iwmmxt_torvsc<mode>3" - [(set (reg:CC CC_REGNUM) - (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TORVSC) 0)) - (unspec:CC [(reg:SI 15)] UNSPEC_TORVSC)] - "TARGET_REALLY_IWMMXT" - "torvsc<MMX_char>%?\\t r15" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_torvsc")] -) - -(define_insn "iwmmxt_textrc<mode>3" - [(set (reg:CC CC_REGNUM) - (subreg:CC (unspec:VMMX [(const_int 0) - (match_operand:SI 0 "immediate_operand" "i")] UNSPEC_TEXTRC) 0)) - (unspec:CC [(reg:SI 15)] UNSPEC_TEXTRC)] - "TARGET_REALLY_IWMMXT" - "textrc<MMX_char>%?\\t r15, %0" - [(set_attr "predicable" "yes") - (set_attr "type" "wmmx_textrc")] -) diff --git a/gcc/config/arm/marvell-f-iwmmxt.md b/gcc/config/arm/marvell-f-iwmmxt.md deleted file mode 100644 index c9c7b00..0000000 --- a/gcc/config/arm/marvell-f-iwmmxt.md +++ /dev/null @@ -1,189 +0,0 @@ -;; Marvell WMMX2 pipeline description -;; Copyright (C) 2011-2025 Free Software Foundation, Inc. -;; Written by Marvell, Inc. - -;; This file is part of GCC. - -;; GCC is free software; you can redistribute it and/or modify it -;; under the terms of the GNU General Public License as published -;; by the Free Software Foundation; either version 3, or (at your -;; option) any later version. - -;; GCC is distributed in the hope that it will be useful, but WITHOUT -;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -;; License for more details. - -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING3. If not see -;; <http://www.gnu.org/licenses/>. - - -(define_automaton "marvell_f_iwmmxt") - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; Pipelines -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -;; This is a 7-stage pipelines: -;; -;; MD | MI | ME1 | ME2 | ME3 | ME4 | MW -;; -;; There are various bypasses modelled to a greater or lesser extent. -;; -;; Latencies in this file correspond to the number of cycles after -;; the issue stage that it takes for the result of the instruction to -;; be computed, or for its side-effects to occur. - -(define_cpu_unit "mf_iwmmxt_MD" "marvell_f_iwmmxt") -(define_cpu_unit "mf_iwmmxt_MI" "marvell_f_iwmmxt") -(define_cpu_unit "mf_iwmmxt_ME1" "marvell_f_iwmmxt") -(define_cpu_unit "mf_iwmmxt_ME2" "marvell_f_iwmmxt") -(define_cpu_unit "mf_iwmmxt_ME3" "marvell_f_iwmmxt") -(define_cpu_unit "mf_iwmmxt_ME4" "marvell_f_iwmmxt") -(define_cpu_unit "mf_iwmmxt_MW" "marvell_f_iwmmxt") - -(define_reservation "mf_iwmmxt_ME" - "mf_iwmmxt_ME1,mf_iwmmxt_ME2,mf_iwmmxt_ME3,mf_iwmmxt_ME4" -) - -(define_reservation "mf_iwmmxt_pipeline" - "mf_iwmmxt_MD, mf_iwmmxt_MI, mf_iwmmxt_ME, mf_iwmmxt_MW" -) - -;; An attribute to indicate whether our reservations are applicable. -(define_attr "marvell_f_iwmmxt" "yes,no" - (const (if_then_else (symbol_ref "arm_arch_iwmmxt") - (const_string "yes") (const_string "no")))) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; instruction classes -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -;; An attribute appended to instructions for classification - -(define_attr "wmmxt_shift" "yes,no" - (if_then_else (eq_attr "type" "wmmx_wror, wmmx_wsll, wmmx_wsra, wmmx_wsrl") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_pack" "yes,no" - (if_then_else (eq_attr "type" "wmmx_waligni, wmmx_walignr, wmmx_wmerge,\ - wmmx_wpack, wmmx_wshufh, wmmx_wunpckeh,\ - wmmx_wunpckih, wmmx_wunpckel, wmmx_wunpckil") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_mult_c1" "yes,no" - (if_then_else (eq_attr "type" "wmmx_wmac, wmmx_wmadd, wmmx_wmiaxy,\ - wmmx_wmiawxy, wmmx_wmulw, wmmx_wqmiaxy,\ - wmmx_wqmulwm") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_mult_c2" "yes,no" - (if_then_else (eq_attr "type" "wmmx_wmul, wmmx_wqmulm") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_alu_c1" "yes,no" - (if_then_else (eq_attr "type" "wmmx_wabs, wmmx_wabsdiff, wmmx_wand,\ - wmmx_wandn, wmmx_wmov, wmmx_wor, wmmx_wxor") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_alu_c2" "yes,no" - (if_then_else (eq_attr "type" "wmmx_wacc, wmmx_wadd, wmmx_waddsubhx,\ - wmmx_wavg2, wmmx_wavg4, wmmx_wcmpeq,\ - wmmx_wcmpgt, wmmx_wmax, wmmx_wmin,\ - wmmx_wsub, wmmx_waddbhus, wmmx_wsubaddhx") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_alu_c3" "yes,no" - (if_then_else (eq_attr "type" "wmmx_wsad") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_transfer_c1" "yes,no" - (if_then_else (eq_attr "type" "wmmx_tbcst, wmmx_tinsr,\ - wmmx_tmcr, wmmx_tmcrr") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_transfer_c2" "yes,no" - (if_then_else (eq_attr "type" "wmmx_textrm, wmmx_tmovmsk,\ - wmmx_tmrc, wmmx_tmrrc") - (const_string "yes") (const_string "no")) -) - -(define_attr "wmmxt_transfer_c3" "yes,no" - (if_then_else (eq_attr "type" "wmmx_tmia, wmmx_tmiaph, wmmx_tmiaxy") - (const_string "yes") (const_string "no")) -) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; Main description -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -(define_insn_reservation "marvell_f_iwmmxt_alu_c1" 1 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_alu_c1" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_pack" 1 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_pack" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_shift" 1 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_shift" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_transfer_c1" 1 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_transfer_c1" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_transfer_c2" 5 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_transfer_c2" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_alu_c2" 2 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_alu_c2" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_alu_c3" 3 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_alu_c3" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_transfer_c3" 4 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_transfer_c3" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_mult_c1" 4 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_mult_c1" "yes")) - "mf_iwmmxt_pipeline") - -;There is a forwarding path from ME3 stage -(define_insn_reservation "marvell_f_iwmmxt_mult_c2" 3 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "wmmxt_mult_c2" "yes")) - "mf_iwmmxt_pipeline") - -(define_insn_reservation "marvell_f_iwmmxt_wstr" 0 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "type" "wmmx_wstr")) - "mf_iwmmxt_pipeline") - -;There is a forwarding path from MW stage -(define_insn_reservation "marvell_f_iwmmxt_wldr" 5 - (and (eq_attr "marvell_f_iwmmxt" "yes") - (eq_attr "type" "wmmx_wldr")) - "mf_iwmmxt_pipeline") diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 75c06d9..57d4ec6 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -806,14 +806,8 @@ ;;------------------------------------------------------------------------- ;; -;; iWMMXt predicates -;; - -(define_predicate "imm_or_reg_operand" - (ior (match_operand 0 "immediate_operand") - (match_operand 0 "register_operand"))) - ;; Neon predicates +;; (define_predicate "const_multiple_of_8_operand" (match_code "const_int") diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm index 641f8f5..670f574 100644 --- a/gcc/config/arm/t-arm +++ b/gcc/config/arm/t-arm @@ -50,11 +50,8 @@ MD_INCLUDES= $(srcdir)/config/arm/arm1020e.md \ $(srcdir)/config/arm/fa726te.md \ $(srcdir)/config/arm/fmp626.md \ $(srcdir)/config/arm/iterators.md \ - $(srcdir)/config/arm/iwmmxt.md \ - $(srcdir)/config/arm/iwmmxt2.md \ $(srcdir)/config/arm/ldmstm.md \ $(srcdir)/config/arm/ldrdstrd.md \ - $(srcdir)/config/arm/marvell-f-iwmmxt.md \ $(srcdir)/config/arm/mve.md \ $(srcdir)/config/arm/neon.md \ $(srcdir)/config/arm/predicates.md \ diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 172c974..019f9d4 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -235,7 +235,7 @@ (define_insn "*thumb2_movsi_insn" [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,lk*r,m") (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,lk*r"))] - "TARGET_THUMB2 && !TARGET_IWMMXT && !TARGET_HARD_FLOAT + "TARGET_THUMB2 && !TARGET_HARD_FLOAT && ( register_operand (operands[0], SImode) || register_operand (operands[1], SImode))" { diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index b72c871..e517b91 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -184,70 +184,6 @@ ; untyped insn without type information - default, and error, ; case. ; -; The classification below is for instructions used by the Wireless MMX -; Technology. Each attribute value is used to classify an instruction of the -; same name or family. -; -; wmmx_tandc -; wmmx_tbcst -; wmmx_textrc -; wmmx_textrm -; wmmx_tinsr -; wmmx_tmcr -; wmmx_tmcrr -; wmmx_tmia -; wmmx_tmiaph -; wmmx_tmiaxy -; wmmx_tmrc -; wmmx_tmrrc -; wmmx_tmovmsk -; wmmx_torc -; wmmx_torvsc -; wmmx_wabs -; wmmx_wdiff -; wmmx_wacc -; wmmx_wadd -; wmmx_waddbhus -; wmmx_waddsubhx -; wmmx_waligni -; wmmx_walignr -; wmmx_wand -; wmmx_wandn -; wmmx_wavg2 -; wmmx_wavg4 -; wmmx_wcmpeq -; wmmx_wcmpgt -; wmmx_wmac -; wmmx_wmadd -; wmmx_wmax -; wmmx_wmerge -; wmmx_wmiawxy -; wmmx_wmiaxy -; wmmx_wmin -; wmmx_wmov -; wmmx_wmul -; wmmx_wmulw -; wmmx_wldr -; wmmx_wor -; wmmx_wpack -; wmmx_wqmiaxy -; wmmx_wqmulm -; wmmx_wqmulwm -; wmmx_wror -; wmmx_wsad -; wmmx_wshufh -; wmmx_wsll -; wmmx_wsra -; wmmx_wsrl -; wmmx_wstr -; wmmx_wsub -; wmmx_wsubaddhx -; wmmx_wunpckeh -; wmmx_wunpckel -; wmmx_wunpckih -; wmmx_wunpckil -; wmmx_wxor -; ; The classification below is for NEON instructions. If a new neon type is ; added, please ensure this is added to the is_neon_type attribute below too. ; @@ -714,65 +650,6 @@ umull,\ umulls,\ untyped,\ - wmmx_tandc,\ - wmmx_tbcst,\ - wmmx_textrc,\ - wmmx_textrm,\ - wmmx_tinsr,\ - wmmx_tmcr,\ - wmmx_tmcrr,\ - wmmx_tmia,\ - wmmx_tmiaph,\ - wmmx_tmiaxy,\ - wmmx_tmrc,\ - wmmx_tmrrc,\ - wmmx_tmovmsk,\ - wmmx_torc,\ - wmmx_torvsc,\ - wmmx_wabs,\ - wmmx_wabsdiff,\ - wmmx_wacc,\ - wmmx_wadd,\ - wmmx_waddbhus,\ - wmmx_waddsubhx,\ - wmmx_waligni,\ - wmmx_walignr,\ - wmmx_wand,\ - wmmx_wandn,\ - wmmx_wavg2,\ - wmmx_wavg4,\ - wmmx_wcmpeq,\ - wmmx_wcmpgt,\ - wmmx_wmac,\ - wmmx_wmadd,\ - wmmx_wmax,\ - wmmx_wmerge,\ - wmmx_wmiawxy,\ - wmmx_wmiaxy,\ - wmmx_wmin,\ - wmmx_wmov,\ - wmmx_wmul,\ - wmmx_wmulw,\ - wmmx_wldr,\ - wmmx_wor,\ - wmmx_wpack,\ - wmmx_wqmiaxy,\ - wmmx_wqmulm,\ - wmmx_wqmulwm,\ - wmmx_wror,\ - wmmx_wsad,\ - wmmx_wshufh,\ - wmmx_wsll,\ - wmmx_wsra,\ - wmmx_wsrl,\ - wmmx_wstr,\ - wmmx_wsub,\ - wmmx_wsubaddhx,\ - wmmx_wunpckeh,\ - wmmx_wunpckel,\ - wmmx_wunpckih,\ - wmmx_wunpckil,\ - wmmx_wxor,\ \ neon_add,\ neon_add_q,\ diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index a03609d..c1ee972 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -21,7 +21,6 @@ ;; UNSPEC Usage: ;; Note: sin and cos are no-longer used. ;; Unspec enumerators for Neon are defined in neon.md. -;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md (define_c_enum "unspec" [ UNSPEC_PUSH_MULT ; `push multiple' operation: @@ -42,17 +41,6 @@ ; and stack frame generation. Operand 0 is the ; register to "use". UNSPEC_CHECK_ARCH ; Set CCs to indicate 26-bit or 32-bit mode. - UNSPEC_WSHUFH ; Used by the intrinsic form of the iWMMXt WSHUFH instruction. - UNSPEC_WACC ; Used by the intrinsic form of the iWMMXt WACC instruction. - UNSPEC_TMOVMSK ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction. - UNSPEC_WSAD ; Used by the intrinsic form of the iWMMXt WSAD instruction. - UNSPEC_WSADZ ; Used by the intrinsic form of the iWMMXt WSADZ instruction. - UNSPEC_WMACS ; Used by the intrinsic form of the iWMMXt WMACS instruction. - UNSPEC_WMACU ; Used by the intrinsic form of the iWMMXt WMACU instruction. - UNSPEC_WMACSZ ; Used by the intrinsic form of the iWMMXt WMACSZ instruction. - UNSPEC_WMACUZ ; Used by the intrinsic form of the iWMMXt WMACUZ instruction. - UNSPEC_CLRDI ; Used by the intrinsic form of the iWMMXt CLRDI instruction. - UNSPEC_WALIGNI ; Used by the intrinsic form of the iWMMXt WALIGN instruction. UNSPEC_TLS ; A symbol that has been treated properly for TLS usage. UNSPEC_PIC_LABEL ; A label used for PIC access that does not appear in the ; instruction stream. @@ -164,18 +152,6 @@ (define_c_enum "unspec" [ - UNSPEC_WADDC ; Used by the intrinsic form of the iWMMXt WADDC instruction. - UNSPEC_WABS ; Used by the intrinsic form of the iWMMXt WABS instruction. - UNSPEC_WQMULWMR ; Used by the intrinsic form of the iWMMXt WQMULWMR instruction. - UNSPEC_WQMULMR ; Used by the intrinsic form of the iWMMXt WQMULMR instruction. - UNSPEC_WQMULWM ; Used by the intrinsic form of the iWMMXt WQMULWM instruction. - UNSPEC_WQMULM ; Used by the intrinsic form of the iWMMXt WQMULM instruction. - UNSPEC_WQMIAxyn ; Used by the intrinsic form of the iWMMXt WMIAxyn instruction. - UNSPEC_WQMIAxy ; Used by the intrinsic form of the iWMMXt WMIAxy instruction. - UNSPEC_TANDC ; Used by the intrinsic form of the iWMMXt TANDC instruction. - UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction. - UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction. - UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction. UNSPEC_GET_FPSCR_NZCVQC ; Represent fetch of FPSCR_nzcvqc content. ]) @@ -205,12 +181,7 @@ ; a 64-bit object. VUNSPEC_POOL_16 ; `pool-entry(16)'. An entry in the constant pool for ; a 128-bit object. - VUNSPEC_TMRC ; Used by the iWMMXt TMRC instruction. - VUNSPEC_TMCR ; Used by the iWMMXt TMCR instruction. VUNSPEC_ALIGN8 ; 8-byte alignment version of VUNSPEC_ALIGN - VUNSPEC_WCMP_EQ ; Used by the iWMMXt WCMPEQ instructions - VUNSPEC_WCMP_GTU ; Used by the iWMMXt WCMPGTU instructions - VUNSPEC_WCMP_GT ; Used by the iwMMXT WCMPGT instructions VUNSPEC_EH_RETURN ; Use to override the return address for exception ; handling. VUNSPEC_ATOMIC_CAS ; Represent an atomic compare swap. diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index a485d05..061165e 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -1,4 +1,4 @@ -;; Machine Description for shared bits common to IWMMXT and Neon. +;; Machine Description for shared bits common to Neon and MVE. ;; Copyright (C) 2006-2025 Free Software Foundation, Inc. ;; Written by CodeSourcery. ;; @@ -24,7 +24,6 @@ [(set (match_operand:VNIM1 0 "nonimmediate_operand") (match_operand:VNIM1 1 "general_operand"))] "TARGET_NEON - || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode)) || (TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" { @@ -46,8 +45,7 @@ (define_expand "mov<mode>" [(set (match_operand:VNINOTM1 0 "nonimmediate_operand") (match_operand:VNINOTM1 1 "general_operand"))] - "TARGET_NEON - || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" + "TARGET_NEON" { gcc_checking_assert (aligned_operand (operands[0], <MODE>mode)); gcc_checking_assert (aligned_operand (operands[1], <MODE>mode)); @@ -83,7 +81,7 @@ }) ;; Vector arithmetic. Expanders are blank, then unnamed insns implement -;; patterns separately for Neon, IWMMXT and MVE. +;; patterns separately for Neon and MVE. (define_expand "add<mode>3" [(set (match_operand:VDQ 0 "s_register_operand") @@ -103,10 +101,7 @@ [(set (match_operand:VDQWH 0 "s_register_operand") (mult:VDQWH (match_operand:VDQWH 1 "s_register_operand") (match_operand:VDQWH 2 "s_register_operand")))] - "ARM_HAVE_<MODE>_ARITH - && (!TARGET_REALLY_IWMMXT - || <MODE>mode == V4HImode - || <MODE>mode == V2SImode)" + "ARM_HAVE_<MODE>_ARITH" ) (define_expand "smin<mode>3" @@ -216,13 +211,13 @@ (define_expand "one_cmpl<mode>2" [(set (match_operand:VDQ 0 "s_register_operand") (not:VDQ (match_operand:VDQ 1 "s_register_operand")))] - "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_ARITH" ) (define_expand "<absneg_str><mode>2" [(set (match_operand:VDQWH 0 "s_register_operand" "") (ABSNEG:VDQWH (match_operand:VDQWH 1 "s_register_operand" "")))] - "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_ARITH" ) (define_expand "cadd<rot><mode>3" @@ -295,8 +290,7 @@ [(set (match_operand:VDQ 0 "nonimmediate_operand") (unspec:VDQ [(match_operand:VDQ 1 "general_operand")] UNSPEC_MISALIGNED_ACCESS))] - "ARM_HAVE_<MODE>_LDST && !BYTES_BIG_ENDIAN - && unaligned_access && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_LDST && !BYTES_BIG_ENDIAN && unaligned_access" { rtx *memloc; bool for_store = false; @@ -373,7 +367,7 @@ (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w,w") (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Ds")] VSHLQ))] - "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_ARITH" "@ <mve_insn>.<supf>%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2 * return neon_output_shift_immediate (\"vshl\", 'i', &operands[2], <MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode), true);" @@ -385,7 +379,7 @@ [(set (match_operand:VDQIW 0 "s_register_operand" "") (ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "") (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "")))] - "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_ARITH" { emit_insn (gen_mve_vshlq_u<mode> (operands[0], operands[1], operands[2])); DONE; @@ -398,7 +392,7 @@ [(set (match_operand:VDQIW 0 "s_register_operand") (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand") (match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))] - "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_ARITH" { if (s_register_operand (operands[2], <MODE>mode)) { @@ -416,7 +410,7 @@ [(set (match_operand:VDQIW 0 "s_register_operand") (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand") (match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))] - "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_ARITH" { if (s_register_operand (operands[2], <MODE>mode)) { @@ -606,8 +600,7 @@ (define_expand "clz<mode>2" [(set (match_operand:VDQIW 0 "s_register_operand") (clz:VDQIW (match_operand:VDQIW 1 "s_register_operand")))] - "ARM_HAVE_<MODE>_ARITH - && !TARGET_REALLY_IWMMXT" + "ARM_HAVE_<MODE>_ARITH" ) (define_expand "vec_init<mode><V_elem_l>" [(match_operand:VDQX 0 "s_register_operand") diff --git a/gcc/config/nvptx/gen-multilib-matches-tests b/gcc/config/nvptx/gen-multilib-matches-tests index a07f19a..fbfae88 100644 --- a/gcc/config/nvptx/gen-multilib-matches-tests +++ b/gcc/config/nvptx/gen-multilib-matches-tests @@ -18,6 +18,7 @@ AEMM .=misa?sm_35 AEMM .=misa?sm_37 AEMM .=misa?sm_52 AEMM .=misa?sm_53 +AEMM .=misa?sm_61 AEMM .=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 @@ -32,14 +33,15 @@ AEMM .=misa?sm_35 AEMM .=misa?sm_37 AEMM .=misa?sm_52 AEMM .=misa?sm_53 +AEMM .=misa?sm_61 AEMM .=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 CMMC -BEGIN '--with-arch=sm_30', '--with-multilib-list=sm_30,sm_35,sm_37,sm_52,sm_53,sm_70,sm_75,sm_80,sm_89' +BEGIN '--with-arch=sm_30', '--with-multilib-list=sm_30,sm_35,sm_37,sm_52,sm_53,sm_61,sm_70,sm_75,sm_80,sm_89' SMOID sm_30 -SMOIL sm_30 sm_35 sm_37 sm_52 sm_53 sm_70 sm_75 sm_80 sm_89 +SMOIL sm_30 sm_35 sm_37 sm_52 sm_53 sm_61 sm_70 sm_75 sm_80 sm_89 AEMM .=misa?sm_30 CMMC @@ -52,6 +54,7 @@ AEMM .=misa?sm_35 AEMM .=misa?sm_37 AEMM .=misa?sm_52 AEMM .=misa?sm_53 +AEMM .=misa?sm_61 AEMM .=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 @@ -65,6 +68,7 @@ AEMM .=misa?sm_35 AEMM .=misa?sm_37 AEMM .=misa?sm_52 AEMM .=misa?sm_53 +AEMM .=misa?sm_61 AEMM .=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 @@ -79,6 +83,7 @@ AEMM misa?sm_30=misa?sm_35 AEMM .=misa?sm_37 AEMM .=misa?sm_52 AEMM .=misa?sm_53 +AEMM .=misa?sm_61 AEMM .=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 @@ -93,6 +98,7 @@ AEMM misa?sm_35=misa?sm_30 AEMM misa?sm_35=misa?sm_37 AEMM .=misa?sm_52 AEMM .=misa?sm_53 +AEMM .=misa?sm_61 AEMM .=misa?sm_70 AEMM misa?sm_75=misa?sm_80 AEMM misa?sm_75=misa?sm_89 @@ -106,6 +112,7 @@ AEMM misa?sm_30=misa?sm_35 AEMM misa?sm_30=misa?sm_37 AEMM misa?sm_30=misa?sm_52 AEMM .=misa?sm_53 +AEMM .=misa?sm_61 AEMM .=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 @@ -119,19 +126,55 @@ AEMM misa?sm_37=misa?sm_30 AEMM misa?sm_37=misa?sm_35 AEMM misa?sm_37=misa?sm_52 AEMM .=misa?sm_53 +AEMM .=misa?sm_61 AEMM .=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 AEMM .=misa?sm_89 CMMC -BEGIN '--with-arch=sm_53', '--with-multilib-list=sm_53=sm_30,sm_35,sm_37,sm_52,sm_70,sm_75,sm_80,sm_89' +BEGIN '--with-arch=sm_53', '--with-multilib-list=sm_30,sm_35,sm_37,sm_52,sm_61,sm_70,sm_75,sm_80,sm_89' SMOID sm_53 -SMOIL sm_53 sm_30 sm_35 sm_37 sm_52 sm_70 sm_75 sm_80 sm_89 +SMOIL sm_53 sm_30 sm_35 sm_37 sm_52 sm_61 sm_70 sm_75 sm_80 sm_89 AEMM .=misa?sm_53 CMMC +BEGIN '--with-arch=sm_61', '--with-multilib-list=sm_61,sm_30' +SMOID sm_61 +SMOIL sm_61 sm_30 +AEMM misa?sm_30=misa?sm_35 +AEMM misa?sm_30=misa?sm_37 +AEMM misa?sm_30=misa?sm_52 +AEMM misa?sm_30=misa?sm_53 +AEMM .=misa?sm_61 +AEMM .=misa?sm_70 +AEMM .=misa?sm_75 +AEMM .=misa?sm_80 +AEMM .=misa?sm_89 +CMMC + +BEGIN '--with-arch=sm_61', '--with-multilib-list=sm_61,sm_37' +SMOID sm_61 +SMOIL sm_61 sm_37 +AEMM misa?sm_37=misa?sm_30 +AEMM misa?sm_37=misa?sm_35 +AEMM misa?sm_37=misa?sm_52 +AEMM misa?sm_37=misa?sm_53 +AEMM .=misa?sm_61 +AEMM .=misa?sm_70 +AEMM .=misa?sm_75 +AEMM .=misa?sm_80 +AEMM .=misa?sm_89 +CMMC + +BEGIN '--with-arch=sm_61', '--with-multilib-list=sm_30,sm_35,sm_37,sm_52,sm_61,sm_70,sm_75,sm_80,sm_89' +SMOID sm_61 +SMOIL sm_61 sm_30 sm_35 sm_37 sm_52 sm_53 sm_70 sm_75 sm_80 sm_89 +AEMM .=misa?sm_61 +CMMC + + BEGIN '--with-arch=sm_70', '--with-multilib-list=sm_70' SMOID sm_70 SMOIL sm_70 @@ -140,6 +183,7 @@ AEMM .=misa?sm_35 AEMM .=misa?sm_37 AEMM .=misa?sm_52 AEMM .=misa?sm_53 +AEMM .=misa?sm_61 AEMM .=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 @@ -153,6 +197,7 @@ AEMM misa?sm_30=misa?sm_35 AEMM misa?sm_30=misa?sm_37 AEMM misa?sm_30=misa?sm_52 AEMM misa?sm_30=misa?sm_53 +AEMM misa?sm_30=misa?sm_61 AEMM .=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 @@ -166,6 +211,7 @@ AEMM misa?sm_53=misa?sm_30 AEMM misa?sm_53=misa?sm_35 AEMM misa?sm_53=misa?sm_37 AEMM misa?sm_53=misa?sm_52 +AEMM misa?sm_53=misa?sm_61 AEMM .=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 @@ -178,6 +224,7 @@ SMOIL sm_70 sm_53 sm_30 AEMM misa?sm_30=misa?sm_35 AEMM misa?sm_30=misa?sm_37 AEMM misa?sm_30=misa?sm_52 +AEMM misa?sm_53=misa?sm_61 AEMM .=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 @@ -192,6 +239,7 @@ AEMM misa?sm_30=misa?sm_35 AEMM misa?sm_30=misa?sm_37 AEMM misa?sm_30=misa?sm_52 AEMM misa?sm_30=misa?sm_53 +AEMM misa?sm_30=misa?sm_61 AEMM misa?sm_30=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 @@ -205,6 +253,7 @@ AEMM misa?sm_53=misa?sm_30 AEMM misa?sm_53=misa?sm_35 AEMM misa?sm_53=misa?sm_37 AEMM misa?sm_53=misa?sm_52 +AEMM misa?sm_53=misa?sm_61 AEMM misa?sm_53=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 @@ -217,6 +266,7 @@ SMOIL sm_75 sm_30 sm_53 AEMM misa?sm_30=misa?sm_35 AEMM misa?sm_30=misa?sm_37 AEMM misa?sm_30=misa?sm_52 +AEMM misa?sm_53=misa?sm_61 AEMM misa?sm_53=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 @@ -232,6 +282,7 @@ AEMM .=misa?sm_35 AEMM .=misa?sm_37 AEMM .=misa?sm_52 AEMM .=misa?sm_53 +AEMM .=misa?sm_61 AEMM .=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 @@ -245,6 +296,7 @@ AEMM misa?sm_30=misa?sm_35 AEMM misa?sm_30=misa?sm_37 AEMM misa?sm_30=misa?sm_52 AEMM misa?sm_30=misa?sm_53 +AEMM misa?sm_30=misa?sm_61 AEMM misa?sm_30=misa?sm_70 AEMM misa?sm_30=misa?sm_75 AEMM .=misa?sm_80 @@ -259,6 +311,7 @@ AEMM misa?sm_75=misa?sm_35 AEMM misa?sm_75=misa?sm_37 AEMM misa?sm_75=misa?sm_52 AEMM misa?sm_75=misa?sm_53 +AEMM misa?sm_75=misa?sm_61 AEMM misa?sm_75=misa?sm_70 AEMM .=misa?sm_80 AEMM .=misa?sm_89 @@ -273,6 +326,7 @@ AEMM .=misa?sm_35 AEMM .=misa?sm_37 AEMM .=misa?sm_52 AEMM .=misa?sm_53 +AEMM .=misa?sm_61 AEMM .=misa?sm_70 AEMM .=misa?sm_75 AEMM .=misa?sm_80 @@ -286,6 +340,7 @@ AEMM misa?sm_52=misa?sm_30 AEMM misa?sm_52=misa?sm_35 AEMM misa?sm_52=misa?sm_37 AEMM misa?sm_52=misa?sm_53 +AEMM misa?sm_52=misa?sm_61 AEMM misa?sm_52=misa?sm_70 AEMM misa?sm_52=misa?sm_75 AEMM misa?sm_52=misa?sm_80 @@ -293,8 +348,8 @@ AEMM .=misa?sm_89 CMMC -BEGIN '--with-arch=sm_89', '--with-multilib-list=sm_89,sm_30,sm_35,sm_37,sm_52,sm_53,sm_70,sm_75,sm_80' +BEGIN '--with-arch=sm_89', '--with-multilib-list=sm_89,sm_30,sm_35,sm_37,sm_52,sm_53,sm_61,sm_70,sm_75,sm_80' SMOID sm_89 -SMOIL sm_89 sm_30 sm_35 sm_37 sm_52 sm_53 sm_70 sm_75 sm_80 +SMOIL sm_89 sm_30 sm_35 sm_37 sm_52 sm_53 sm_61 sm_70 sm_75 sm_80 AEMM .=misa?sm_89 CMMC diff --git a/gcc/config/nvptx/nvptx-gen.h b/gcc/config/nvptx/nvptx-gen.h index 893df41..f5b9899 100644 --- a/gcc/config/nvptx/nvptx-gen.h +++ b/gcc/config/nvptx/nvptx-gen.h @@ -26,6 +26,7 @@ #define TARGET_SM37 (ptx_isa_option >= PTX_ISA_SM37) #define TARGET_SM52 (ptx_isa_option >= PTX_ISA_SM52) #define TARGET_SM53 (ptx_isa_option >= PTX_ISA_SM53) +#define TARGET_SM61 (ptx_isa_option >= PTX_ISA_SM61) #define TARGET_SM70 (ptx_isa_option >= PTX_ISA_SM70) #define TARGET_SM75 (ptx_isa_option >= PTX_ISA_SM75) #define TARGET_SM80 (ptx_isa_option >= PTX_ISA_SM80) diff --git a/gcc/config/nvptx/nvptx-gen.opt b/gcc/config/nvptx/nvptx-gen.opt index f45e8ef..bbae32d 100644 --- a/gcc/config/nvptx/nvptx-gen.opt +++ b/gcc/config/nvptx/nvptx-gen.opt @@ -39,6 +39,9 @@ EnumValue Enum(ptx_isa) String(sm_53) Value(PTX_ISA_SM53) EnumValue +Enum(ptx_isa) String(sm_61) Value(PTX_ISA_SM61) + +EnumValue Enum(ptx_isa) String(sm_70) Value(PTX_ISA_SM70) EnumValue diff --git a/gcc/config/nvptx/nvptx-opts.h b/gcc/config/nvptx/nvptx-opts.h index d886701..07bcd32 100644 --- a/gcc/config/nvptx/nvptx-opts.h +++ b/gcc/config/nvptx/nvptx-opts.h @@ -40,6 +40,7 @@ enum ptx_version PTX_VERSION_3_1, PTX_VERSION_4_1, PTX_VERSION_4_2, + PTX_VERSION_5_0, PTX_VERSION_6_0, PTX_VERSION_6_3, PTX_VERSION_7_0, diff --git a/gcc/config/nvptx/nvptx-sm.def b/gcc/config/nvptx/nvptx-sm.def index 1485f89..9f9e864 100644 --- a/gcc/config/nvptx/nvptx-sm.def +++ b/gcc/config/nvptx/nvptx-sm.def @@ -25,6 +25,7 @@ NVPTX_SM (35, NVPTX_SM_SEP) NVPTX_SM (37, NVPTX_SM_SEP) NVPTX_SM (52, NVPTX_SM_SEP) NVPTX_SM (53, NVPTX_SM_SEP) +NVPTX_SM (61, NVPTX_SM_SEP) NVPTX_SM (70, NVPTX_SM_SEP) NVPTX_SM (75, NVPTX_SM_SEP) NVPTX_SM (80, NVPTX_SM_SEP) diff --git a/gcc/config/nvptx/nvptx.cc b/gcc/config/nvptx/nvptx.cc index f893971..b1c476e 100644 --- a/gcc/config/nvptx/nvptx.cc +++ b/gcc/config/nvptx/nvptx.cc @@ -220,6 +220,8 @@ first_ptx_version_supporting_sm (enum ptx_isa sm) return PTX_VERSION_4_1; case PTX_ISA_SM53: return PTX_VERSION_4_2; + case PTX_ISA_SM61: + return PTX_VERSION_5_0; case PTX_ISA_SM70: return PTX_VERSION_6_0; case PTX_ISA_SM75: @@ -268,6 +270,8 @@ ptx_version_to_string (enum ptx_version v) return "4.1"; case PTX_VERSION_4_2: return "4.2"; + case PTX_VERSION_5_0: + return "5.0"; case PTX_VERSION_6_0: return "6.0"; case PTX_VERSION_6_3: @@ -294,6 +298,8 @@ ptx_version_to_number (enum ptx_version v, bool major_p) return major_p ? 4 : 1; case PTX_VERSION_4_2: return major_p ? 4 : 2; + case PTX_VERSION_5_0: + return major_p ? 5 : 0; case PTX_VERSION_6_0: return major_p ? 6 : 0; case PTX_VERSION_6_3: diff --git a/gcc/config/nvptx/nvptx.h b/gcc/config/nvptx/nvptx.h index 35ef4bd..a2bb2fb 100644 --- a/gcc/config/nvptx/nvptx.h +++ b/gcc/config/nvptx/nvptx.h @@ -101,6 +101,7 @@ PTX ISA Version 3.1. */ #define TARGET_PTX_4_1 (ptx_version_option >= PTX_VERSION_4_1) #define TARGET_PTX_4_2 (ptx_version_option >= PTX_VERSION_4_2) +#define TARGET_PTX_5_0 (ptx_version_option >= PTX_VERSION_5_0) #define TARGET_PTX_6_0 (ptx_version_option >= PTX_VERSION_6_0) #define TARGET_PTX_6_3 (ptx_version_option >= PTX_VERSION_6_3) #define TARGET_PTX_7_0 (ptx_version_option >= PTX_VERSION_7_0) diff --git a/gcc/config/nvptx/nvptx.opt b/gcc/config/nvptx/nvptx.opt index ce9fbc7..d326ca4 100644 --- a/gcc/config/nvptx/nvptx.opt +++ b/gcc/config/nvptx/nvptx.opt @@ -88,10 +88,10 @@ march-map=sm_60 Target RejectNegative Alias(misa=,sm_53) march-map=sm_61 -Target RejectNegative Alias(misa=,sm_53) +Target RejectNegative Alias(misa=,sm_61) march-map=sm_62 -Target RejectNegative Alias(misa=,sm_53) +Target RejectNegative Alias(misa=,sm_61) march-map=sm_70 Target RejectNegative Alias(misa=,sm_70) @@ -134,6 +134,9 @@ EnumValue Enum(ptx_version) String(4.2) Value(PTX_VERSION_4_2) EnumValue +Enum(ptx_version) String(5.0) Value(PTX_VERSION_5_0) + +EnumValue Enum(ptx_version) String(6.0) Value(PTX_VERSION_6_0) EnumValue diff --git a/gcc/config/riscv/gen-riscv-ext-opt.cc b/gcc/config/riscv/gen-riscv-ext-opt.cc new file mode 100644 index 0000000..17b8f5b --- /dev/null +++ b/gcc/config/riscv/gen-riscv-ext-opt.cc @@ -0,0 +1,105 @@ +#include <vector> +#include <string> +#include <set> +#include <stdio.h> +#include "riscv-opts.h" + +struct version_t +{ + int major; + int minor; + version_t (int major, int minor, + enum riscv_isa_spec_class spec = ISA_SPEC_CLASS_NONE) + : major (major), minor (minor) + {} + bool operator<(const version_t &other) const + { + if (major != other.major) + return major < other.major; + return minor < other.minor; + } + + bool operator== (const version_t &other) const + { + return major == other.major && minor == other.minor; + } +}; + +static void +print_ext_doc_entry (const std::string &ext_name, const std::string &full_name, + const std::string &desc, + const std::vector<version_t> &supported_versions) +{ + // Implementation of the function to print the documentation entry + // for the extension. + std::set<version_t> unique_versions; + for (const auto &version : supported_versions) + unique_versions.insert (version); + printf ("@item %s\n", ext_name.c_str ()); + printf ("@tab"); + for (const auto &version : unique_versions) + { + printf (" %d.%d", version.major, version.minor); + } + printf ("\n"); + printf ("@tab %s", full_name.c_str ()); + if (desc.size ()) + printf (", %s", desc.c_str ()); + printf ("\n\n"); +} + +int +main () +{ + puts ("; Target options for the RISC-V port of the compiler"); + puts (";"); + puts ("; Copyright (C) 2025 Free Software Foundation, Inc."); + puts (";"); + puts ("; This file is part of GCC."); + puts (";"); + puts ( + "; GCC is free software; you can redistribute it and/or modify it under"); + puts ( + "; the terms of the GNU General Public License as published by the Free"); + puts ( + "; Software Foundation; either version 3, or (at your option) any later"); + puts ("; version."); + puts (";"); + puts ("; GCC is distributed in the hope that it will be useful, but WITHOUT"); + puts ("; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY"); + puts ("; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public"); + puts ("; License for more details."); + puts (";"); + puts ("; You should have received a copy of the GNU General Public License"); + puts ("; along with GCC; see the file COPYING3. If not see "); + puts ("; <http://www.gnu.org/licenses/>."); + + puts ("; This file is generated automatically using"); + puts ("; gcc/config/riscv/gen-riscv-ext-opt.cc from:"); + puts ("; gcc/config/riscv/riscv-ext.def"); + puts (""); + puts ("; Please *DO NOT* edit manually."); + + std::set<std::string> all_vars; +#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ + SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \ + BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \ + all_vars.insert ("riscv_" #FLAG_GROUP "_subext"); +#include "riscv-ext.def" +#undef DEFINE_RISCV_EXT + + for (auto var : all_vars) + { + puts ("TargetVariable"); + printf ("int %s\n\n", var.c_str ()); + } + +#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ + SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \ + BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \ + puts ("Mask(" #UPPERCAE_NAME ") Var(riscv_" #FLAG_GROUP "_subext)\n"); +#include "riscv-ext.def" +#undef DEFINE_RISCV_EXT + + return 0; +} diff --git a/gcc/config/riscv/gen-riscv-ext-texi.cc b/gcc/config/riscv/gen-riscv-ext-texi.cc new file mode 100644 index 0000000..e15fdbf --- /dev/null +++ b/gcc/config/riscv/gen-riscv-ext-texi.cc @@ -0,0 +1,88 @@ +#include <vector> +#include <string> +#include <set> +#include <stdio.h> +#include "riscv-opts.h" + +struct version_t +{ + int major; + int minor; + version_t (int major, int minor, + enum riscv_isa_spec_class spec = ISA_SPEC_CLASS_NONE) + : major (major), minor (minor) + {} + bool operator<(const version_t &other) const + { + if (major != other.major) + return major < other.major; + return minor < other.minor; + } + + bool operator== (const version_t &other) const + { + return major == other.major && minor == other.minor; + } +}; + +static void +print_ext_doc_entry (const std::string &ext_name, const std::string &full_name, + const std::string &desc, + const std::vector<version_t> &supported_versions) +{ + // Implementation of the function to print the documentation entry + // for the extension. + std::set<version_t> unique_versions; + for (const auto &version : supported_versions) + unique_versions.insert (version); + printf ("@item %s\n", ext_name.c_str ()); + printf ("@tab"); + for (const auto &version : unique_versions) + { + printf (" %d.%d", version.major, version.minor); + } + printf ("\n"); + printf ("@tab %s", full_name.c_str ()); + if (desc.size ()) + printf (", %s", desc.c_str ()); + printf ("\n\n"); +} + +int +main () +{ + puts ("@c Copyright (C) 2025 Free Software Foundation, Inc."); + puts ("@c This is part of the GCC manual."); + puts ("@c For copying conditions, see the file gcc/doc/include/fdl.texi."); + puts (""); + puts ("@c This file is generated automatically using"); + puts ("@c gcc/config/riscv/gen-riscv-ext-texi.cc from:"); + puts ("@c gcc/config/riscv/riscv-ext.def"); + puts ("@c gcc/config/riscv/riscv-opts.h"); + puts (""); + puts ("@c Please *DO NOT* edit manually."); + puts (""); + puts ("@multitable @columnfractions .10 .10 .80"); + puts ("@headitem Extension Name @tab Supported Version @tab Description"); + puts (""); + + /* g extension is a very speical extension that no clear version... */ + puts ("@item g"); + puts ("@tab -"); + puts ( + "@tab General-purpose computing base extension, @samp{g} will expand to"); + puts ("@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and"); + puts ("@samp{zifencei}."); + puts (""); + +#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ + SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \ + BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \ + print_ext_doc_entry (#NAME, FULL_NAME, DESC, \ + std::vector<version_t> SUPPORTED_VERSIONS); +#include "riscv-ext.def" +#undef DEFINE_RISCV_EXT + + puts ("@end multitable"); + return 0; +} diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index ab6dc83..1ff1968 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -36,10 +36,10 @@ along with GCC; see the file COPYING3. If not see struct pragma_intrinsic_flags { - int intrinsic_target_flags; + int intrinsic_riscv_isa_flags; int intrinsic_riscv_vector_elen_flags; - int intrinsic_riscv_zvl_flags; + int intrinsic_riscv_zvl_subext; int intrinsic_riscv_zvb_subext; int intrinsic_riscv_zvk_subext; }; @@ -47,16 +47,16 @@ struct pragma_intrinsic_flags static void riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *flags) { - flags->intrinsic_target_flags = target_flags; + flags->intrinsic_riscv_isa_flags = riscv_isa_flags; flags->intrinsic_riscv_vector_elen_flags = riscv_vector_elen_flags; - flags->intrinsic_riscv_zvl_flags = riscv_zvl_flags; + flags->intrinsic_riscv_zvl_subext = riscv_zvl_subext; flags->intrinsic_riscv_zvb_subext = riscv_zvb_subext; flags->intrinsic_riscv_zvk_subext = riscv_zvk_subext; - target_flags = target_flags + riscv_isa_flags = riscv_isa_flags | MASK_VECTOR; - riscv_zvl_flags = riscv_zvl_flags + riscv_zvl_subext = riscv_zvl_subext | MASK_ZVL32B | MASK_ZVL64B | MASK_ZVL128B @@ -97,10 +97,10 @@ riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *flags) static void riscv_pragma_intrinsic_flags_restore (struct pragma_intrinsic_flags *flags) { - target_flags = flags->intrinsic_target_flags; + riscv_isa_flags = flags->intrinsic_riscv_isa_flags; riscv_vector_elen_flags = flags->intrinsic_riscv_vector_elen_flags; - riscv_zvl_flags = flags->intrinsic_riscv_zvl_flags; + riscv_zvl_subext = flags->intrinsic_riscv_zvl_subext; riscv_zvb_subext = flags->intrinsic_riscv_zvb_subext; riscv_zvk_subext = flags->intrinsic_riscv_zvk_subext; } diff --git a/gcc/config/riscv/riscv-ext-corev.def b/gcc/config/riscv/riscv-ext-corev.def new file mode 100644 index 0000000..eb97399 --- /dev/null +++ b/gcc/config/riscv/riscv-ext-corev.def @@ -0,0 +1,87 @@ +/* CORE-V extension definition file for RISC-V. + Copyright (C) 2025 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. + +Please run `make riscv-regen` in build folder to make sure updated anything. + +Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ + +DEFINE_RISCV_EXT( + /* NAME */ xcvalu, + /* UPPERCAE_NAME */ XCVALU, + /* FULL_NAME */ "Core-V miscellaneous ALU extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xcv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xcvbi, + /* UPPERCAE_NAME */ XCVBI, + /* FULL_NAME */ "xcvbi extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xcv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xcvelw, + /* UPPERCAE_NAME */ XCVELW, + /* FULL_NAME */ "Core-V event load word extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xcv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xcvmac, + /* UPPERCAE_NAME */ XCVMAC, + /* FULL_NAME */ "Core-V multiply-accumulate extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xcv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xcvsimd, + /* UPPERCAE_NAME */ XCVSIMD, + /* FULL_NAME */ "xcvsimd extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xcv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) diff --git a/gcc/config/riscv/riscv-ext-sifive.def b/gcc/config/riscv/riscv-ext-sifive.def new file mode 100644 index 0000000..c8d79da --- /dev/null +++ b/gcc/config/riscv/riscv-ext-sifive.def @@ -0,0 +1,87 @@ +/* SiFive extension definition file for RISC-V. + Copyright (C) 2025 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. + +Please run `make riscv-regen` in build folder to make sure updated anything. + +Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ + +DEFINE_RISCV_EXT( + /* NAME */ xsfcease, + /* UPPERCAE_NAME */ XSFCEASE, + /* FULL_NAME */ "xsfcease extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xsf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xsfvcp, + /* UPPERCAE_NAME */ XSFVCP, + /* FULL_NAME */ "xsfvcp extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xsf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xsfvfnrclipxfqf, + /* UPPERCAE_NAME */ XSFVFNRCLIPXFQF, + /* FULL_NAME */ "xsfvfnrclipxfqf extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xsf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xsfvqmaccdod, + /* UPPERCAE_NAME */ XSFVQMACCDOD, + /* FULL_NAME */ "xsfvqmaccdod extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xsf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xsfvqmaccqoq, + /* UPPERCAE_NAME */ XSFVQMACCQOQ, + /* FULL_NAME */ "xsfvqmaccqoq extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xsf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) diff --git a/gcc/config/riscv/riscv-ext-thead.def b/gcc/config/riscv/riscv-ext-thead.def new file mode 100644 index 0000000..327d2ae --- /dev/null +++ b/gcc/config/riscv/riscv-ext-thead.def @@ -0,0 +1,191 @@ +/* T-head extension definition file for RISC-V. + Copyright (C) 2025 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. + +Please run `make riscv-regen` in build folder to make sure updated anything. + +Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ + +DEFINE_RISCV_EXT( + /* NAME */ xtheadba, + /* UPPERCAE_NAME */ XTHEADBA, + /* FULL_NAME */ "T-head address calculation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadbb, + /* UPPERCAE_NAME */ XTHEADBB, + /* FULL_NAME */ "T-head basic bit-manipulation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadbs, + /* UPPERCAE_NAME */ XTHEADBS, + /* FULL_NAME */ "T-head single-bit instructions extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadcmo, + /* UPPERCAE_NAME */ XTHEADCMO, + /* FULL_NAME */ "T-head cache management operations extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadcondmov, + /* UPPERCAE_NAME */ XTHEADCONDMOV, + /* FULL_NAME */ "T-head conditional move extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadfmemidx, + /* UPPERCAE_NAME */ XTHEADFMEMIDX, + /* FULL_NAME */ "T-head indexed memory operations for floating-point registers extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadfmv, + /* UPPERCAE_NAME */ XTHEADFMV, + /* FULL_NAME */ "T-head double floating-point high-bit data transmission extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadint, + /* UPPERCAE_NAME */ XTHEADINT, + /* FULL_NAME */ "T-head acceleration interruption extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadmac, + /* UPPERCAE_NAME */ XTHEADMAC, + /* FULL_NAME */ "T-head multiply-accumulate extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadmemidx, + /* UPPERCAE_NAME */ XTHEADMEMIDX, + /* FULL_NAME */ "T-head indexed memory operation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadmempair, + /* UPPERCAE_NAME */ XTHEADMEMPAIR, + /* FULL_NAME */ "T-head two-GPR memory operation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadsync, + /* UPPERCAE_NAME */ XTHEADSYNC, + /* FULL_NAME */ "T-head multi-core synchronization extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadvector, + /* UPPERCAE_NAME */ XTHEADVECTOR, + /* FULL_NAME */ "xtheadvector extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) diff --git a/gcc/config/riscv/riscv-ext-ventana.def b/gcc/config/riscv/riscv-ext-ventana.def new file mode 100644 index 0000000..deed47f --- /dev/null +++ b/gcc/config/riscv/riscv-ext-ventana.def @@ -0,0 +1,35 @@ +/* Ventana extension definition file for RISC-V. + Copyright (C) 2025 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. + +Please run `make riscv-regen` in build folder to make sure updated anything. + +Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ + +DEFINE_RISCV_EXT( + /* NAME */ xventanacondops, + /* UPPERCAE_NAME */ XVENTANACONDOPS, + /* FULL_NAME */ "Ventana integer conditional operations extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xventana, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def new file mode 100644 index 0000000..34742d9 --- /dev/null +++ b/gcc/config/riscv/riscv-ext.def @@ -0,0 +1,1824 @@ +/* RISC-V extension definition file for RISC-V. + Copyright (C) 2025 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. + +Please run `make riscv-regen` in build folder to make sure updated anything. + +Format of DEFINE_RISCV_EXT: + NAME: + The name of the extension, e.g. "i". + UPPERCASE_NAME: + The name of the extension in uppercase, e.g. "ZBA", this used + for generate TARGET_<ext-name> marco and MASK_<ext-name> macro. + For those extension only named with single letter, it should also come with + 'RV', e.g. 'v' should use 'RVV' here. + Some of old extension like 'i' and 'm' are not follow the rule. + FULL_NAME: + The full name of the extension, e.g. "Base integer extension". + DESC: + A short description of the extension, this will used during generating + documentation, GNU Texinfo format can be used this field. + URL: + A URL for the extension. + DEP_EXTS: + A list of dependent extensions, this is a list of strings or + a list of tuples. The first element of the tuple is the name + of the extension and the second element is a function that + takes a subset_list and returns true if the extension should be added as + a dependent extension, `c` and `zca` are examples of this. + SUPPORTED_VERSIONS: + A list of tuples, each tuple contains the major version number, minor + version number and the class of the specification. The version number is a + list of integers, e.g. {2, 0} for version 2.0. The class is + a string, e.g. "ISA_SPEC_CLASS_20191213", the class of the + specification is not required for any new extension. + FLAG_GROUP: + The group of the extension, this is used to group extensions + together. The group is a string, e.g. "base", "zi", "zm", "za", "zf", + "zc", "zb", "zk" and "zi". + This should be auto generated in theory in some day... + BITMASK_GROUP_ID: + The group id of the extension for the __riscv_feature_bits. + this field should sync with riscv-c-api-doc, and keep BITMASK_NOT_YET_ALLOCATED + if not got allocated. + https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask-definitions + BITMASK_BIT_POSITION: + The bit position of the extension for the __riscv_feature_bits. + this field should sync with riscv-c-api-doc, and keep BITMASK_NOT_YET_ALLOCATED + if not got allocated. + https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask-definitions + EXTRA_EXTENSION_FLAGS: + Extra flags for the extension, this is a bitmask of the + extra flags. The extra flags are: + - EXT_FLAG_MACRO: Set this flag if this extension is just a macro of set of + extensions, and not define any new instrcutions, new CSRs or new + behaviors, the example is `b` extension is just a macro of `zba`, `zbb` + and `zbs`. +*/ + +DEFINE_RISCV_EXT( + /* NAME */ e, + /* UPPERCAE_NAME */ RVE, + /* FULL_NAME */ "Reduced base integer extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ i, + /* UPPERCAE_NAME */ RVI, + /* FULL_NAME */ "Base integer extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{2, 1, ISA_SPEC_CLASS_20191213}, + {2, 1, ISA_SPEC_CLASS_20190608}, + {2, 0, ISA_SPEC_CLASS_2P2}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 8, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ m, + /* UPPERCAE_NAME */ MUL, + /* FULL_NAME */ "Integer multiplication and division extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zmmul"}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 12, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ a, + /* UPPERCAE_NAME */ ATOMIC, + /* FULL_NAME */ "Atomic extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zaamo", "zalrsc"}), + /* SUPPORTED_VERSIONS */ ({{2, 1, ISA_SPEC_CLASS_20191213}, + {2, 0, ISA_SPEC_CLASS_20190608}, + {2, 0, ISA_SPEC_CLASS_2P2}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 0, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ f, + /* UPPERCAE_NAME */ HARD_FLOAT, + /* FULL_NAME */ "Single-precision floating-point extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{2, 2, ISA_SPEC_CLASS_20191213}, + {2, 2, ISA_SPEC_CLASS_20190608}, + {2, 0, ISA_SPEC_CLASS_2P2}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 5, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ d, + /* UPPERCAE_NAME */ DOUBLE_FLOAT, + /* FULL_NAME */ "Double-precision floating-point extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"f", "zicsr"}), + /* SUPPORTED_VERSIONS */ ({{2, 2, ISA_SPEC_CLASS_20191213}, + {2, 2, ISA_SPEC_CLASS_20190608}, + {2, 0, ISA_SPEC_CLASS_2P2}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 3, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ c, + /* UPPERCAE_NAME */ RVC, + /* FULL_NAME */ "Compressed extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca", + {"zcf", + [] (const riscv_subset_list *subset_list) -> bool + { + return subset_list->xlen () == 32 + && subset_list->lookup ("f"); + }}, + {"zcd", + [] (const riscv_subset_list *subset_list) -> bool + { + return subset_list->lookup ("d"); + }}}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 2, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ b, + /* UPPERCAE_NAME */ RVB, + /* FULL_NAME */ "b extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zba", "zbb", "zbs"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ v, + /* UPPERCAE_NAME */ RVV, + /* FULL_NAME */ "Vector extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl128b", "zve64d"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 21, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ h, + /* UPPERCAE_NAME */ RVH, + /* FULL_NAME */ "Hypervisor extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zic64b, + /* UPPERCAE_NAME */ ZIC64B, + /* FULL_NAME */ "Cache block size isf 64 bytes", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicbom, + /* UPPERCAE_NAME */ ZICBOM, + /* FULL_NAME */ "Cache-block management extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicbop, + /* UPPERCAE_NAME */ ZICBOP, + /* FULL_NAME */ "Cache-block prefetch extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicboz, + /* UPPERCAE_NAME */ ZICBOZ, + /* FULL_NAME */ "Cache-block zero extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 37, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ziccamoa, + /* UPPERCAE_NAME */ ZICCAMOA, + /* FULL_NAME */ "Main memory supports all atomics in A", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ziccif, + /* UPPERCAE_NAME */ ZICCIF, + /* FULL_NAME */ "Main memory supports instruction fetch with atomicity requirement", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicclsm, + /* UPPERCAE_NAME */ ZICCLSM, + /* FULL_NAME */ "Main memory supports misaligned loads/stores", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ziccrse, + /* UPPERCAE_NAME */ ZICCRSE, + /* FULL_NAME */ "Main memory supports forward progress on LR/SC sequences", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicfilp, + /* UPPERCAE_NAME */ ZICFILP, + /* FULL_NAME */ "zicfilp extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicfiss, + /* UPPERCAE_NAME */ ZICFISS, + /* FULL_NAME */ "zicfiss extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr", "zimop"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicntr, + /* UPPERCAE_NAME */ ZICNTR, + /* FULL_NAME */ "Standard extension for base counters and timers", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicond, + /* UPPERCAE_NAME */ ZICOND, + /* FULL_NAME */ "Integer conditional operations extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 38, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicsr, + /* UPPERCAE_NAME */ ZICSR, + /* FULL_NAME */ "Control and status register access extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zifencei, + /* UPPERCAE_NAME */ ZIFENCEI, + /* FULL_NAME */ "Instruction-fetch fence extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zihintntl, + /* UPPERCAE_NAME */ ZIHINTNTL, + /* FULL_NAME */ "Non-temporal locality hints extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 39, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zihintpause, + /* UPPERCAE_NAME */ ZIHINTPAUSE, + /* FULL_NAME */ "Pause hint extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 40, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zihpm, + /* UPPERCAE_NAME */ ZIHPM, + /* FULL_NAME */ "Standard extension for hardware performance counters", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zimop, + /* UPPERCAE_NAME */ ZIMOP, + /* FULL_NAME */ "zimop extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 1, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zilsd, + /* UPPERCAE_NAME */ ZILSD, + /* FULL_NAME */ "Load/Store pair instructions extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 1, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zmmul, + /* UPPERCAE_NAME */ ZMMUL, + /* FULL_NAME */ "Integer multiplication extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zm, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ za128rs, + /* UPPERCAE_NAME */ ZA128RS, + /* FULL_NAME */ "Reservation set size of 128 bytes", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ za64rs, + /* UPPERCAE_NAME */ ZA64RS, + /* FULL_NAME */ "Reservation set size of 64 bytes", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zaamo, + /* UPPERCAE_NAME */ ZAAMO, + /* FULL_NAME */ "zaamo extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zabha, + /* UPPERCAE_NAME */ ZABHA, + /* FULL_NAME */ "zabha extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zaamo"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zacas, + /* UPPERCAE_NAME */ ZACAS, + /* FULL_NAME */ "zacas extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zaamo"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 26, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zalrsc, + /* UPPERCAE_NAME */ ZALRSC, + /* FULL_NAME */ "zalrsc extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zawrs, + /* UPPERCAE_NAME */ ZAWRS, + /* FULL_NAME */ "Wait-on-reservation-set extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zalrsc"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 7, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zama16b, + /* UPPERCAE_NAME */ ZAMA16B, + /* FULL_NAME */ "Zama16b extension", + /* DESC */ "Misaligned loads, stores, and AMOs to main memory regions that do" + " not cross a naturally aligned 16-byte boundary are atomic.", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zfa, + /* UPPERCAE_NAME */ ZFA, + /* FULL_NAME */ "Additional floating-point extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"f"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zf, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 34, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zfbfmin, + /* UPPERCAE_NAME */ ZFBFMIN, + /* FULL_NAME */ "zfbfmin extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zfhmin"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zfh, + /* UPPERCAE_NAME */ ZFH, + /* FULL_NAME */ "Half-precision floating-point extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zfhmin"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zf, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 35, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zfhmin, + /* UPPERCAE_NAME */ ZFHMIN, + /* FULL_NAME */ "Minimal half-precision floating-point extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"f"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zf, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 36, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zfinx, + /* UPPERCAE_NAME */ ZFINX, + /* FULL_NAME */ "Single-precision floating-point in integer registers extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zinx, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zdinx, + /* UPPERCAE_NAME */ ZDINX, + /* FULL_NAME */ "Double-precision floating-point in integer registers extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zfinx", "zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zinx, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zca, + /* UPPERCAE_NAME */ ZCA, + /* FULL_NAME */ "Integer compressed instruction extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({{"c", +[] (const riscv_subset_list *subset_list) -> bool +{ + /* For RV32 Zca implies C for one of these combinations of + extensions: Zca, F_Zca_Zcf and FD_Zca_Zcf_Zcd. */ + if (subset_list->xlen () == 32) + { + if (subset_list->lookup ("d")) + return subset_list->lookup ("zcf") && subset_list->lookup ("zcd"); + + if (subset_list->lookup ("f")) + return subset_list->lookup ("zcf"); + + return true; + } + + /* For RV64 Zca implies C for one of these combinations of + extensions: Zca and FD_Zca_Zcd (Zcf is not available + for RV64). */ + if (subset_list->xlen () == 64) + { + if (subset_list->lookup ("d")) + return subset_list->lookup ("zcd"); + + return true; + } + + /* Do nothing for future RV128 specification. Behaviour + for this case is not yet well defined. */ + return false; + +}}}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 2, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zcb, + /* UPPERCAE_NAME */ ZCB, + /* FULL_NAME */ "Simple compressed instruction extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 3, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zcd, + /* UPPERCAE_NAME */ ZCD, + /* FULL_NAME */ "Compressed double-precision floating point loads and stores extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 4, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zce, + /* UPPERCAE_NAME */ ZCE, + /* FULL_NAME */ "Compressed instruction extensions for embedded processors", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca", "zcb", "zcmp", "zcmt", + {"zcf", + [] (const riscv_subset_list *subset_list) -> bool + { + return subset_list->xlen () == 32 + && subset_list->lookup ("f"); + }}}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zcf, + /* UPPERCAE_NAME */ ZCF, + /* FULL_NAME */ "Compressed single-precision floating point loads and stores extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 5, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zcmop, + /* UPPERCAE_NAME */ ZCMOP, + /* FULL_NAME */ "zcmop extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 6, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zcmp, + /* UPPERCAE_NAME */ ZCMP, + /* FULL_NAME */ "Compressed push pop extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zcmt, + /* UPPERCAE_NAME */ ZCMT, + /* FULL_NAME */ "Table jump instruction extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca", "zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zclsd, + /* UPPERCAE_NAME */ ZCLSD, + /* FULL_NAME */ "Compressed load/store pair instructions extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca", "zilsd"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zba, + /* UPPERCAE_NAME */ ZBA, + /* FULL_NAME */ "Address calculation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 27, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zbb, + /* UPPERCAE_NAME */ ZBB, + /* FULL_NAME */ "Basic bit manipulation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 28, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zbc, + /* UPPERCAE_NAME */ ZBC, + /* FULL_NAME */ "Carry-less multiplication extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 29, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zbkb, + /* UPPERCAE_NAME */ ZBKB, + /* FULL_NAME */ "Cryptography bit-manipulation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 30, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zbkc, + /* UPPERCAE_NAME */ ZBKC, + /* FULL_NAME */ "Cryptography carry-less multiply extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 31, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zbkx, + /* UPPERCAE_NAME */ ZBKX, + /* FULL_NAME */ "Cryptography crossbar permutation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 32, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zbs, + /* UPPERCAE_NAME */ ZBS, + /* FULL_NAME */ "Single-bit operation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 33, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zk, + /* UPPERCAE_NAME */ ZK, + /* FULL_NAME */ "Standard scalar cryptography extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zkn", "zkr", "zkt"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zkn, + /* UPPERCAE_NAME */ ZKN, + /* FULL_NAME */ "NIST algorithm suite extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zknd, + /* UPPERCAE_NAME */ ZKND, + /* FULL_NAME */ "AES Decryption extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 41, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zkne, + /* UPPERCAE_NAME */ ZKNE, + /* FULL_NAME */ "AES Encryption extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 42, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zknh, + /* UPPERCAE_NAME */ ZKNH, + /* FULL_NAME */ "Hash function extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 43, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zkr, + /* UPPERCAE_NAME */ ZKR, + /* FULL_NAME */ "Entropy source extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zks, + /* UPPERCAE_NAME */ ZKS, + /* FULL_NAME */ "ShangMi algorithm suite extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zbkb", "zbkc", "zbkx", "zksed", "zksh"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zksed, + /* UPPERCAE_NAME */ ZKSED, + /* FULL_NAME */ "SM4 block cipher extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 44, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zksh, + /* UPPERCAE_NAME */ ZKSH, + /* FULL_NAME */ "SM3 hash function extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 45, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zkt, + /* UPPERCAE_NAME */ ZKT, + /* FULL_NAME */ "Data independent execution latency extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 46, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ztso, + /* UPPERCAE_NAME */ ZTSO, + /* FULL_NAME */ "Total store ordering extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zt, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 47, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvbb, + /* UPPERCAE_NAME */ ZVBB, + /* FULL_NAME */ "Vector basic bit-manipulation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvkb"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 48, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvbc, + /* UPPERCAE_NAME */ ZVBC, + /* FULL_NAME */ "Vector carryless multiplication extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve64x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 49, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zve32f, + /* UPPERCAE_NAME */ ZVE32F, + /* FULL_NAME */ "Vector extensions for embedded processors", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"f", "zve32x", "zvl32b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zve, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 61, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zve32x, + /* UPPERCAE_NAME */ ZVE32X, + /* FULL_NAME */ "Vector extensions for embedded processors", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr", "zvl32b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zve, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 60, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zve64d, + /* UPPERCAE_NAME */ ZVE64D, + /* FULL_NAME */ "Vector extensions for embedded processors", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"d", "zve64f", "zvl64b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zve, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 0, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zve64f, + /* UPPERCAE_NAME */ ZVE64F, + /* FULL_NAME */ "Vector extensions for embedded processors", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"f", "zve32f", "zve64x", "zvl64b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zve, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 63, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zve64x, + /* UPPERCAE_NAME */ ZVE64X, + /* FULL_NAME */ "Vector extensions for embedded processors", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x", "zvl64b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zve, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 62, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvfbfmin, + /* UPPERCAE_NAME */ ZVFBFMIN, + /* FULL_NAME */ "Vector BF16 converts extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32f"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvfbfwma, + /* UPPERCAE_NAME */ ZVFBFWMA, + /* FULL_NAME */ "zvfbfwma extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvfbfmin", "zfbfmin"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvfh, + /* UPPERCAE_NAME */ ZVFH, + /* FULL_NAME */ "Vector half-precision floating-point extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32f", "zfhmin"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvf, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 50, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvfhmin, + /* UPPERCAE_NAME */ ZVFHMIN, + /* FULL_NAME */ "Vector minimal half-precision floating-point extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32f"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvf, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 51, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvkb, + /* UPPERCAE_NAME */ ZVKB, + /* FULL_NAME */ "Vector cryptography bit-manipulation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 52, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvkg, + /* UPPERCAE_NAME */ ZVKG, + /* FULL_NAME */ "Vector GCM/GMAC extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 53, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvkn, + /* UPPERCAE_NAME */ ZVKN, + /* FULL_NAME */ "Vector NIST Algorithm Suite extension", + /* DESC */ "@samp{zvkn} will expand to", + /* URL */ , + /* DEP_EXTS */ ({"zvkned", "zvknhb", "zvkb", "zvkt"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zvknc, + /* UPPERCAE_NAME */ ZVKNC, + /* FULL_NAME */ "Vector NIST Algorithm Suite with carryless multiply extension, @samp{zvknc}", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvkn", "zvbc"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zvkned, + /* UPPERCAE_NAME */ ZVKNED, + /* FULL_NAME */ "Vector AES block cipher extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 54, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvkng, + /* UPPERCAE_NAME */ ZVKNG, + /* FULL_NAME */ "Vector NIST Algorithm Suite with GCM extension, @samp{zvkng} will expand", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvkn", "zvkg"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zvknha, + /* UPPERCAE_NAME */ ZVKNHA, + /* FULL_NAME */ "Vector SHA-2 secure hash extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 55, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvknhb, + /* UPPERCAE_NAME */ ZVKNHB, + /* FULL_NAME */ "Vector SHA-2 secure hash extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve64x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 56, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvks, + /* UPPERCAE_NAME */ ZVKS, + /* FULL_NAME */ "Vector ShangMi algorithm suite extension, @samp{zvks} will expand", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvksed", "zvksh", "zvkb", "zvkt"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zvksc, + /* UPPERCAE_NAME */ ZVKSC, + /* FULL_NAME */ "Vector ShangMi algorithm suite with carryless multiplication extension,", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvks", "zvbc"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zvksed, + /* UPPERCAE_NAME */ ZVKSED, + /* FULL_NAME */ "Vector SM4 Block Cipher extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 57, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvksg, + /* UPPERCAE_NAME */ ZVKSG, + /* FULL_NAME */ "Vector ShangMi algorithm suite with GCM extension, @samp{zvksg} will expand", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvks", "zvkg"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zvksh, + /* UPPERCAE_NAME */ ZVKSH, + /* FULL_NAME */ "Vector SM3 Secure Hash extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 58, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvkt, + /* UPPERCAE_NAME */ ZVKT, + /* FULL_NAME */ "Vector data independent execution latency extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 59, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl1024b, + /* UPPERCAE_NAME */ ZVL1024B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl512b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl128b, + /* UPPERCAE_NAME */ ZVL128B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl64b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl16384b, + /* UPPERCAE_NAME */ ZVL16384B, + /* FULL_NAME */ "zvl16384b extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl8192b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl2048b, + /* UPPERCAE_NAME */ ZVL2048B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl1024b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl256b, + /* UPPERCAE_NAME */ ZVL256B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl128b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl32768b, + /* UPPERCAE_NAME */ ZVL32768B, + /* FULL_NAME */ "zvl32768b extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl16384b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl32b, + /* UPPERCAE_NAME */ ZVL32B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl4096b, + /* UPPERCAE_NAME */ ZVL4096B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl2048b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl512b, + /* UPPERCAE_NAME */ ZVL512B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl256b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl64b, + /* UPPERCAE_NAME */ ZVL64B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl32b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl65536b, + /* UPPERCAE_NAME */ ZVL65536B, + /* FULL_NAME */ "zvl65536b extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl32768b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl8192b, + /* UPPERCAE_NAME */ ZVL8192B, + /* FULL_NAME */ "zvl8192b extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl4096b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zhinx, + /* UPPERCAE_NAME */ ZHINX, + /* FULL_NAME */ "Half-precision floating-point in integer registers extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zhinxmin"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zinx, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zhinxmin, + /* UPPERCAE_NAME */ ZHINXMIN, + /* FULL_NAME */ "Minimal half-precision floating-point in integer registers extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zfinx"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zinx, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ sdtrig, + /* UPPERCAE_NAME */ SDTRIG, + /* FULL_NAME */ "sdtrig extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sd, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ smaia, + /* UPPERCAE_NAME */ SMAIA, + /* FULL_NAME */ "Advanced interrupt architecture extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"ssaia"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sm, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ smepmp, + /* UPPERCAE_NAME */ SMEPMP, + /* FULL_NAME */ "PMP Enhancements for memory access and execution prevention on Machine mode", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sm, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ smmpm, + /* UPPERCAE_NAME */ SMMPM, + /* FULL_NAME */ "smmpm extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sm, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ smnpm, + /* UPPERCAE_NAME */ SMNPM, + /* FULL_NAME */ "smnpm extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sm, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ smstateen, + /* UPPERCAE_NAME */ SMSTATEEN, + /* FULL_NAME */ "State enable extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"ssstateen"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sm, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ssaia, + /* UPPERCAE_NAME */ SSAIA, + /* FULL_NAME */ "Advanced interrupt architecture extension for supervisor-mode", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ sscofpmf, + /* UPPERCAE_NAME */ SSCOFPMF, + /* FULL_NAME */ "Count overflow & filtering extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ssnpm, + /* UPPERCAE_NAME */ SSNPM, + /* FULL_NAME */ "ssnpm extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ sspm, + /* UPPERCAE_NAME */ SSPM, + /* FULL_NAME */ "sspm extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ssstateen, + /* UPPERCAE_NAME */ SSSTATEEN, + /* FULL_NAME */ "State-enable extension for supervisor-mode", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ sstc, + /* UPPERCAE_NAME */ SSTC, + /* FULL_NAME */ "Supervisor-mode timer interrupts extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ssstrict, + /* UPPERCAE_NAME */ SSSTRICT, + /* FULL_NAME */ "ssstrict extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ supm, + /* UPPERCAE_NAME */ SUPM, + /* FULL_NAME */ "supm extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ su, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ svinval, + /* UPPERCAE_NAME */ SVINVAL, + /* FULL_NAME */ "Fine-grained address-translation cache invalidation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ svnapot, + /* UPPERCAE_NAME */ SVNAPOT, + /* FULL_NAME */ "NAPOT translation contiguity extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ svpbmt, + /* UPPERCAE_NAME */ SVPBMT, + /* FULL_NAME */ "Page-based memory types extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ svvptc, + /* UPPERCAE_NAME */ SVVPTC, + /* FULL_NAME */ "svvptc extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ svadu, + /* UPPERCAE_NAME */ SVADU, + /* FULL_NAME */ "Hardware Updating of A/D Bits extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ svade, + /* UPPERCAE_NAME */ SVADE, + /* FULL_NAME */ "Cause exception when hardware updating of A/D bits is disabled", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +#include "riscv-ext-corev.def" +#include "riscv-ext-sifive.def" +#include "riscv-ext-thead.def" +#include "riscv-ext-ventana.def" diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt new file mode 100644 index 0000000..0c56dc9 --- /dev/null +++ b/gcc/config/riscv/riscv-ext.opt @@ -0,0 +1,404 @@ +; Target options for the RISC-V port of the compiler +; +; Copyright (C) 2025 Free Software Foundation, Inc. +; +; This file is part of GCC. +; +; GCC is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License as published by the Free +; Software Foundation; either version 3, or (at your option) any later +; version. +; +; GCC is distributed in the hope that it will be useful, but WITHOUT +; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +; License for more details. +; +; You should have received a copy of the GNU General Public License +; along with GCC; see the file COPYING3. If not see +; <http://www.gnu.org/licenses/>. +; This file is generated automatically using +; gcc/config/riscv/gen-riscv-ext-opt.cc from: +; gcc/config/riscv/riscv-ext.def + +; Please *DO NOT* edit manually. +TargetVariable +int riscv_base_subext + +TargetVariable +int riscv_sd_subext + +TargetVariable +int riscv_sm_subext + +TargetVariable +int riscv_ss_subext + +TargetVariable +int riscv_su_subext + +TargetVariable +int riscv_sv_subext + +TargetVariable +int riscv_xcv_subext + +TargetVariable +int riscv_xsf_subext + +TargetVariable +int riscv_xthead_subext + +TargetVariable +int riscv_xventana_subext + +TargetVariable +int riscv_za_subext + +TargetVariable +int riscv_zb_subext + +TargetVariable +int riscv_zc_subext + +TargetVariable +int riscv_zf_subext + +TargetVariable +int riscv_zi_subext + +TargetVariable +int riscv_zinx_subext + +TargetVariable +int riscv_zk_subext + +TargetVariable +int riscv_zm_subext + +TargetVariable +int riscv_zt_subext + +TargetVariable +int riscv_zvb_subext + +TargetVariable +int riscv_zve_subext + +TargetVariable +int riscv_zvf_subext + +TargetVariable +int riscv_zvk_subext + +TargetVariable +int riscv_zvl_subext + +Mask(RVE) Var(riscv_base_subext) + +Mask(RVI) Var(riscv_base_subext) + +Mask(MUL) Var(riscv_base_subext) + +Mask(ATOMIC) Var(riscv_base_subext) + +Mask(HARD_FLOAT) Var(riscv_base_subext) + +Mask(DOUBLE_FLOAT) Var(riscv_base_subext) + +Mask(RVC) Var(riscv_base_subext) + +Mask(RVB) Var(riscv_base_subext) + +Mask(RVV) Var(riscv_base_subext) + +Mask(RVH) Var(riscv_base_subext) + +Mask(ZIC64B) Var(riscv_zi_subext) + +Mask(ZICBOM) Var(riscv_zi_subext) + +Mask(ZICBOP) Var(riscv_zi_subext) + +Mask(ZICBOZ) Var(riscv_zi_subext) + +Mask(ZICCAMOA) Var(riscv_zi_subext) + +Mask(ZICCIF) Var(riscv_zi_subext) + +Mask(ZICCLSM) Var(riscv_zi_subext) + +Mask(ZICCRSE) Var(riscv_zi_subext) + +Mask(ZICFILP) Var(riscv_zi_subext) + +Mask(ZICFISS) Var(riscv_zi_subext) + +Mask(ZICNTR) Var(riscv_zi_subext) + +Mask(ZICOND) Var(riscv_zi_subext) + +Mask(ZICSR) Var(riscv_zi_subext) + +Mask(ZIFENCEI) Var(riscv_zi_subext) + +Mask(ZIHINTNTL) Var(riscv_zi_subext) + +Mask(ZIHINTPAUSE) Var(riscv_zi_subext) + +Mask(ZIHPM) Var(riscv_zi_subext) + +Mask(ZIMOP) Var(riscv_zi_subext) + +Mask(ZILSD) Var(riscv_zi_subext) + +Mask(ZMMUL) Var(riscv_zm_subext) + +Mask(ZA128RS) Var(riscv_za_subext) + +Mask(ZA64RS) Var(riscv_za_subext) + +Mask(ZAAMO) Var(riscv_za_subext) + +Mask(ZABHA) Var(riscv_za_subext) + +Mask(ZACAS) Var(riscv_za_subext) + +Mask(ZALRSC) Var(riscv_za_subext) + +Mask(ZAWRS) Var(riscv_za_subext) + +Mask(ZAMA16B) Var(riscv_za_subext) + +Mask(ZFA) Var(riscv_zf_subext) + +Mask(ZFBFMIN) Var(riscv_zf_subext) + +Mask(ZFH) Var(riscv_zf_subext) + +Mask(ZFHMIN) Var(riscv_zf_subext) + +Mask(ZFINX) Var(riscv_zinx_subext) + +Mask(ZDINX) Var(riscv_zinx_subext) + +Mask(ZCA) Var(riscv_zc_subext) + +Mask(ZCB) Var(riscv_zc_subext) + +Mask(ZCD) Var(riscv_zc_subext) + +Mask(ZCE) Var(riscv_zc_subext) + +Mask(ZCF) Var(riscv_zc_subext) + +Mask(ZCMOP) Var(riscv_zc_subext) + +Mask(ZCMP) Var(riscv_zc_subext) + +Mask(ZCMT) Var(riscv_zc_subext) + +Mask(ZCLSD) Var(riscv_zc_subext) + +Mask(ZBA) Var(riscv_zb_subext) + +Mask(ZBB) Var(riscv_zb_subext) + +Mask(ZBC) Var(riscv_zb_subext) + +Mask(ZBKB) Var(riscv_zb_subext) + +Mask(ZBKC) Var(riscv_zb_subext) + +Mask(ZBKX) Var(riscv_zb_subext) + +Mask(ZBS) Var(riscv_zb_subext) + +Mask(ZK) Var(riscv_zk_subext) + +Mask(ZKN) Var(riscv_zk_subext) + +Mask(ZKND) Var(riscv_zk_subext) + +Mask(ZKNE) Var(riscv_zk_subext) + +Mask(ZKNH) Var(riscv_zk_subext) + +Mask(ZKR) Var(riscv_zk_subext) + +Mask(ZKS) Var(riscv_zk_subext) + +Mask(ZKSED) Var(riscv_zk_subext) + +Mask(ZKSH) Var(riscv_zk_subext) + +Mask(ZKT) Var(riscv_zk_subext) + +Mask(ZTSO) Var(riscv_zt_subext) + +Mask(ZVBB) Var(riscv_zvb_subext) + +Mask(ZVBC) Var(riscv_zvb_subext) + +Mask(ZVE32F) Var(riscv_zve_subext) + +Mask(ZVE32X) Var(riscv_zve_subext) + +Mask(ZVE64D) Var(riscv_zve_subext) + +Mask(ZVE64F) Var(riscv_zve_subext) + +Mask(ZVE64X) Var(riscv_zve_subext) + +Mask(ZVFBFMIN) Var(riscv_zvf_subext) + +Mask(ZVFBFWMA) Var(riscv_zvf_subext) + +Mask(ZVFH) Var(riscv_zvf_subext) + +Mask(ZVFHMIN) Var(riscv_zvf_subext) + +Mask(ZVKB) Var(riscv_zvk_subext) + +Mask(ZVKG) Var(riscv_zvk_subext) + +Mask(ZVKN) Var(riscv_zvk_subext) + +Mask(ZVKNC) Var(riscv_zvk_subext) + +Mask(ZVKNED) Var(riscv_zvk_subext) + +Mask(ZVKNG) Var(riscv_zvk_subext) + +Mask(ZVKNHA) Var(riscv_zvk_subext) + +Mask(ZVKNHB) Var(riscv_zvk_subext) + +Mask(ZVKS) Var(riscv_zvk_subext) + +Mask(ZVKSC) Var(riscv_zvk_subext) + +Mask(ZVKSED) Var(riscv_zvk_subext) + +Mask(ZVKSG) Var(riscv_zvk_subext) + +Mask(ZVKSH) Var(riscv_zvk_subext) + +Mask(ZVKT) Var(riscv_zvk_subext) + +Mask(ZVL1024B) Var(riscv_zvl_subext) + +Mask(ZVL128B) Var(riscv_zvl_subext) + +Mask(ZVL16384B) Var(riscv_zvl_subext) + +Mask(ZVL2048B) Var(riscv_zvl_subext) + +Mask(ZVL256B) Var(riscv_zvl_subext) + +Mask(ZVL32768B) Var(riscv_zvl_subext) + +Mask(ZVL32B) Var(riscv_zvl_subext) + +Mask(ZVL4096B) Var(riscv_zvl_subext) + +Mask(ZVL512B) Var(riscv_zvl_subext) + +Mask(ZVL64B) Var(riscv_zvl_subext) + +Mask(ZVL65536B) Var(riscv_zvl_subext) + +Mask(ZVL8192B) Var(riscv_zvl_subext) + +Mask(ZHINX) Var(riscv_zinx_subext) + +Mask(ZHINXMIN) Var(riscv_zinx_subext) + +Mask(SDTRIG) Var(riscv_sd_subext) + +Mask(SMAIA) Var(riscv_sm_subext) + +Mask(SMEPMP) Var(riscv_sm_subext) + +Mask(SMMPM) Var(riscv_sm_subext) + +Mask(SMNPM) Var(riscv_sm_subext) + +Mask(SMSTATEEN) Var(riscv_sm_subext) + +Mask(SSAIA) Var(riscv_ss_subext) + +Mask(SSCOFPMF) Var(riscv_ss_subext) + +Mask(SSNPM) Var(riscv_ss_subext) + +Mask(SSPM) Var(riscv_ss_subext) + +Mask(SSSTATEEN) Var(riscv_ss_subext) + +Mask(SSTC) Var(riscv_ss_subext) + +Mask(SSSTRICT) Var(riscv_ss_subext) + +Mask(SUPM) Var(riscv_su_subext) + +Mask(SVINVAL) Var(riscv_sv_subext) + +Mask(SVNAPOT) Var(riscv_sv_subext) + +Mask(SVPBMT) Var(riscv_sv_subext) + +Mask(SVVPTC) Var(riscv_sv_subext) + +Mask(SVADU) Var(riscv_sv_subext) + +Mask(SVADE) Var(riscv_sv_subext) + +Mask(XCVALU) Var(riscv_xcv_subext) + +Mask(XCVBI) Var(riscv_xcv_subext) + +Mask(XCVELW) Var(riscv_xcv_subext) + +Mask(XCVMAC) Var(riscv_xcv_subext) + +Mask(XCVSIMD) Var(riscv_xcv_subext) + +Mask(XSFCEASE) Var(riscv_xsf_subext) + +Mask(XSFVCP) Var(riscv_xsf_subext) + +Mask(XSFVFNRCLIPXFQF) Var(riscv_xsf_subext) + +Mask(XSFVQMACCDOD) Var(riscv_xsf_subext) + +Mask(XSFVQMACCQOQ) Var(riscv_xsf_subext) + +Mask(XTHEADBA) Var(riscv_xthead_subext) + +Mask(XTHEADBB) Var(riscv_xthead_subext) + +Mask(XTHEADBS) Var(riscv_xthead_subext) + +Mask(XTHEADCMO) Var(riscv_xthead_subext) + +Mask(XTHEADCONDMOV) Var(riscv_xthead_subext) + +Mask(XTHEADFMEMIDX) Var(riscv_xthead_subext) + +Mask(XTHEADFMV) Var(riscv_xthead_subext) + +Mask(XTHEADINT) Var(riscv_xthead_subext) + +Mask(XTHEADMAC) Var(riscv_xthead_subext) + +Mask(XTHEADMEMIDX) Var(riscv_xthead_subext) + +Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext) + +Mask(XTHEADSYNC) Var(riscv_xthead_subext) + +Mask(XTHEADVECTOR) Var(riscv_xthead_subext) + +Mask(XVENTANACONDOPS) Var(riscv_xventana_subext) + diff --git a/gcc/config/riscv/riscv-ext.opt.urls b/gcc/config/riscv/riscv-ext.opt.urls new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/gcc/config/riscv/riscv-ext.opt.urls diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 9766b89..0f3bca5 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -136,16 +136,16 @@ enum rvv_vector_bits_enum { /* Bit of riscv_zvl_flags will set continually, N-1 bit will set if N-bit is set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use popcount to calculate the minimal VLEN. */ -#define TARGET_MIN_VLEN \ - ((riscv_zvl_flags == 0) \ - ? 0 \ - : 32 << (__builtin_popcount (riscv_zvl_flags) - 1)) +#define TARGET_MIN_VLEN \ + ((riscv_zvl_subext == 0) \ + ? 0 \ + : 32 << (__builtin_popcount (riscv_zvl_subext) - 1)) /* Same as TARGET_MIN_VLEN, but take an OPTS as gcc_options. */ #define TARGET_MIN_VLEN_OPTS(opts) \ - ((opts->x_riscv_zvl_flags == 0) \ + ((opts->x_riscv_zvl_subext == 0) \ ? 0 \ - : 32 << (__builtin_popcount (opts->x_riscv_zvl_flags) - 1)) + : 32 << (__builtin_popcount (opts->x_riscv_zvl_subext) - 1)) /* The maximum LMUL according to user configuration. */ #define TARGET_MAX_LMUL \ @@ -164,4 +164,12 @@ enum riscv_tls_type { #define GPR2VR_COST_UNPROVIDED -1 +/* Extra extension flags, used for carry extra info for a RISC-V extension. */ +enum +{ + EXT_FLAG_MACRO = 1 << 0, +}; + +#define BITMASK_NOT_YET_ALLOCATED -1 + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h index 7b3fdae..c5d9fab 100644 --- a/gcc/config/riscv/riscv-subset.h +++ b/gcc/config/riscv/riscv-subset.h @@ -129,6 +129,5 @@ extern bool riscv_minimal_hwprobe_feature_bits (const char *, location_t); extern bool riscv_ext_is_subset (struct cl_target_option *, struct cl_target_option *); -extern int riscv_x_target_flags_isa_mask (void); #endif /* ! GCC_RISCV_SUBSET_H */ diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index f3c706bf..f652a12 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -3842,26 +3842,26 @@ check_required_extensions (const function_instance &instance) required_extensions |= RVV_REQUIRE_RV64BIT; } - uint64_t riscv_isa_flags = 0; + uint64_t isa_flags = 0; if (TARGET_VECTOR_ELEN_BF_16) - riscv_isa_flags |= RVV_REQUIRE_ELEN_BF_16; + isa_flags |= RVV_REQUIRE_ELEN_BF_16; if (TARGET_VECTOR_ELEN_FP_16) - riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_16; + isa_flags |= RVV_REQUIRE_ELEN_FP_16; if (TARGET_VECTOR_ELEN_FP_32) - riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_32; + isa_flags |= RVV_REQUIRE_ELEN_FP_32; if (TARGET_VECTOR_ELEN_FP_64) - riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_64; + isa_flags |= RVV_REQUIRE_ELEN_FP_64; if (TARGET_VECTOR_ELEN_64) - riscv_isa_flags |= RVV_REQUIRE_ELEN_64; + isa_flags |= RVV_REQUIRE_ELEN_64; if (TARGET_64BIT) - riscv_isa_flags |= RVV_REQUIRE_RV64BIT; + isa_flags |= RVV_REQUIRE_RV64BIT; if (TARGET_FULL_V) - riscv_isa_flags |= RVV_REQUIRE_FULL_V; + isa_flags |= RVV_REQUIRE_FULL_V; if (TARGET_MIN_VLEN > 32) - riscv_isa_flags |= RVV_REQUIRE_MIN_VLEN_64; + isa_flags |= RVV_REQUIRE_MIN_VLEN_64; - uint64_t missing_extensions = required_extensions & ~riscv_isa_flags; + uint64_t missing_extensions = required_extensions & ~isa_flags; if (missing_extensions != 0) return false; return true; diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8b77a35..d28aee4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7918,11 +7918,9 @@ riscv_can_inline_p (tree caller, tree callee) struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree); struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree); - int isa_flag_mask = riscv_x_target_flags_isa_mask (); - - /* Callee and caller should have the same target options except for ISA. */ - int callee_target_flags = callee_opts->x_target_flags & ~isa_flag_mask; - int caller_target_flags = caller_opts->x_target_flags & ~isa_flag_mask; + /* Callee and caller should have the same target options. */ + int callee_target_flags = callee_opts->x_target_flags; + int caller_target_flags = caller_opts->x_target_flags; if (callee_target_flags != caller_target_flags) return false; diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 80593ee..527e095 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -168,23 +168,14 @@ momit-leaf-frame-pointer Target Mask(OMIT_LEAF_FRAME_POINTER) Save Omit the frame pointer in leaf functions. -Mask(64BIT) - -Mask(MUL) - -Mask(ATOMIC) - -Mask(HARD_FLOAT) - -Mask(DOUBLE_FLOAT) - -Mask(RVC) +TargetVariable +int riscv_isa_flags -Mask(RVE) +Mask(64BIT) Var(riscv_isa_flags) -Mask(VECTOR) +Mask(VECTOR) Var(riscv_isa_flags) -Mask(FULL_V) +Mask(FULL_V) Var(riscv_isa_flags) mriscv-attribute Target Var(riscv_emit_attribute_p) Init(-1) @@ -233,95 +224,6 @@ TargetVariable long riscv_stack_protector_guard_offset = 0 TargetVariable -int riscv_zi_subext - -Mask(ZICSR) Var(riscv_zi_subext) - -Mask(ZIFENCEI) Var(riscv_zi_subext) - -Mask(ZIHINTNTL) Var(riscv_zi_subext) - -Mask(ZIHINTPAUSE) Var(riscv_zi_subext) - -Mask(ZICOND) Var(riscv_zi_subext) - -Mask(ZICCAMOA) Var(riscv_zi_subext) - -Mask(ZICCIF) Var(riscv_zi_subext) - -Mask(ZICCLSM) Var(riscv_zi_subext) - -Mask(ZICCRSE) Var(riscv_zi_subext) - -Mask(ZICFISS) Var(riscv_zi_subext) - -Mask(ZICFILP) Var(riscv_zi_subext) - -TargetVariable -int riscv_za_subext - -Mask(ZAWRS) Var(riscv_za_subext) - -Mask(ZAAMO) Var(riscv_za_subext) - -Mask(ZALRSC) Var(riscv_za_subext) - -Mask(ZABHA) Var(riscv_za_subext) - -Mask(ZACAS) Var(riscv_za_subext) - -Mask(ZA64RS) Var(riscv_za_subext) - -Mask(ZA128RS) Var(riscv_za_subext) - -Mask(ZAMA16B) Var(riscv_za_subext) - -TargetVariable -int riscv_zb_subext - -Mask(ZBA) Var(riscv_zb_subext) - -Mask(ZBB) Var(riscv_zb_subext) - -Mask(ZBC) Var(riscv_zb_subext) - -Mask(ZBS) Var(riscv_zb_subext) - -TargetVariable -int riscv_zinx_subext - -Mask(ZFINX) Var(riscv_zinx_subext) - -Mask(ZDINX) Var(riscv_zinx_subext) - -Mask(ZHINX) Var(riscv_zinx_subext) - -Mask(ZHINXMIN) Var(riscv_zinx_subext) - -TargetVariable -int riscv_zk_subext - -Mask(ZBKB) Var(riscv_zk_subext) - -Mask(ZBKC) Var(riscv_zk_subext) - -Mask(ZBKX) Var(riscv_zk_subext) - -Mask(ZKNE) Var(riscv_zk_subext) - -Mask(ZKND) Var(riscv_zk_subext) - -Mask(ZKNH) Var(riscv_zk_subext) - -Mask(ZKR) Var(riscv_zk_subext) - -Mask(ZKSED) Var(riscv_zk_subext) - -Mask(ZKSH) Var(riscv_zk_subext) - -Mask(ZKT) Var(riscv_zk_subext) - -TargetVariable int riscv_vector_elen_flags Mask(VECTOR_ELEN_32) Var(riscv_vector_elen_flags) @@ -337,211 +239,6 @@ Mask(VECTOR_ELEN_FP_16) Var(riscv_vector_elen_flags) Mask(VECTOR_ELEN_BF_16) Var(riscv_vector_elen_flags) TargetVariable -int riscv_zvl_flags - -Mask(ZVL32B) Var(riscv_zvl_flags) - -Mask(ZVL64B) Var(riscv_zvl_flags) - -Mask(ZVL128B) Var(riscv_zvl_flags) - -Mask(ZVL256B) Var(riscv_zvl_flags) - -Mask(ZVL512B) Var(riscv_zvl_flags) - -Mask(ZVL1024B) Var(riscv_zvl_flags) - -Mask(ZVL2048B) Var(riscv_zvl_flags) - -Mask(ZVL4096B) Var(riscv_zvl_flags) - -Mask(ZVL8192B) Var(riscv_zvl_flags) - -Mask(ZVL16384B) Var(riscv_zvl_flags) - -Mask(ZVL32768B) Var(riscv_zvl_flags) - -Mask(ZVL65536B) Var(riscv_zvl_flags) - -TargetVariable -int riscv_zvb_subext - -Mask(ZVBB) Var(riscv_zvb_subext) - -Mask(ZVBC) Var(riscv_zvb_subext) - -Mask(ZVKB) Var(riscv_zvb_subext) - -TargetVariable -int riscv_zvk_subext - -Mask(ZVKG) Var(riscv_zvk_subext) - -Mask(ZVKNED) Var(riscv_zvk_subext) - -Mask(ZVKNHA) Var(riscv_zvk_subext) - -Mask(ZVKNHB) Var(riscv_zvk_subext) - -Mask(ZVKSED) Var(riscv_zvk_subext) - -Mask(ZVKSH) Var(riscv_zvk_subext) - -Mask(ZVKN) Var(riscv_zvk_subext) - -Mask(ZVKNC) Var(riscv_zvk_subext) - -Mask(ZVKNG) Var(riscv_zvk_subext) - -Mask(ZVKS) Var(riscv_zvk_subext) - -Mask(ZVKSC) Var(riscv_zvk_subext) - -Mask(ZVKSG) Var(riscv_zvk_subext) - -Mask(ZVKT) Var(riscv_zvk_subext) - -TargetVariable -int riscv_zicmo_subext - -Mask(ZICBOZ) Var(riscv_zicmo_subext) - -Mask(ZICBOM) Var(riscv_zicmo_subext) - -Mask(ZICBOP) Var(riscv_zicmo_subext) - -Mask(ZIC64B) Var(riscv_zicmo_subext) - -TargetVariable -int riscv_mop_subext - -Mask(ZIMOP) Var(riscv_mop_subext) - -Mask(ZCMOP) Var(riscv_mop_subext) - -TargetVariable -int riscv_zf_subext - -Mask(ZFBFMIN) Var(riscv_zf_subext) - -Mask(ZFHMIN) Var(riscv_zf_subext) - -Mask(ZFH) Var(riscv_zf_subext) - -Mask(ZVFBFMIN) Var(riscv_zf_subext) - -Mask(ZVFBFWMA) Var(riscv_zf_subext) - -Mask(ZVFHMIN) Var(riscv_zf_subext) - -Mask(ZVFH) Var(riscv_zf_subext) - -TargetVariable -int riscv_zfa_subext - -Mask(ZFA) Var(riscv_zfa_subext) - -TargetVariable -int riscv_zm_subext - -Mask(ZMMUL) Var(riscv_zm_subext) - -TargetVariable -int riscv_zc_subext - -Mask(ZCA) Var(riscv_zc_subext) - -Mask(ZCB) Var(riscv_zc_subext) - -Mask(ZCE) Var(riscv_zc_subext) - -Mask(ZCF) Var(riscv_zc_subext) - -Mask(ZCD) Var(riscv_zc_subext) - -Mask(ZCMP) Var(riscv_zc_subext) - -Mask(ZCMT) Var(riscv_zc_subext) - -Mask(XCVBI) Var(riscv_xcv_subext) - -TargetVariable -int riscv_sv_subext - -Mask(SVADE) Var(riscv_sv_subext) - -Mask(SVADU) Var(riscv_sv_subext) - -Mask(SVINVAL) Var(riscv_sv_subext) - -Mask(SVNAPOT) Var(riscv_sv_subext) - -Mask(SVVPTC) Var(riscv_sv_subext) - -TargetVariable -int riscv_ztso_subext - -Mask(ZTSO) Var(riscv_ztso_subext) - -TargetVariable -int riscv_xcv_subext - -Mask(XCVMAC) Var(riscv_xcv_subext) - -Mask(XCVALU) Var(riscv_xcv_subext) - -Mask(XCVELW) Var(riscv_xcv_subext) - -Mask(XCVSIMD) Var(riscv_xcv_subext) - -TargetVariable -int riscv_xthead_subext - -Mask(XTHEADBA) Var(riscv_xthead_subext) - -Mask(XTHEADBB) Var(riscv_xthead_subext) - -Mask(XTHEADBS) Var(riscv_xthead_subext) - -Mask(XTHEADCMO) Var(riscv_xthead_subext) - -Mask(XTHEADCONDMOV) Var(riscv_xthead_subext) - -Mask(XTHEADFMEMIDX) Var(riscv_xthead_subext) - -Mask(XTHEADFMV) Var(riscv_xthead_subext) - -Mask(XTHEADINT) Var(riscv_xthead_subext) - -Mask(XTHEADMAC) Var(riscv_xthead_subext) - -Mask(XTHEADMEMIDX) Var(riscv_xthead_subext) - -Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext) - -Mask(XTHEADSYNC) Var(riscv_xthead_subext) - -Mask(XTHEADVECTOR) Var(riscv_xthead_subext) - -TargetVariable -int riscv_xventana_subext - -Mask(XVENTANACONDOPS) Var(riscv_xventana_subext) - -TargetVariable -int riscv_sifive_subext - -Mask(XSFVCP) Var(riscv_sifive_subext) - -Mask(XSFCEASE) Var(riscv_sifive_subext) - -Mask(XSFVQMACCQOQ) Var(riscv_sifive_subext) - -Mask(XSFVQMACCDOD) Var(riscv_sifive_subext) - -Mask(XSFVFNRCLIPXFQF) Var(riscv_sifive_subext) - -TargetVariable int riscv_fmv_priority = 0 Enum diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv index 12e2b6e..e99d668 100644 --- a/gcc/config/riscv/t-riscv +++ b/gcc/config/riscv/t-riscv @@ -187,3 +187,46 @@ s-riscv-vector-type-indexer.gen.defs: build/genrvv-type-indexer$(build_exeext) $(STAMP) s-riscv-vector-type-indexer.gen.defs genprog+=rvv-type-indexer + +RISCV_EXT_DEFS = \ + $(srcdir)/config/riscv/riscv-ext.def \ + $(srcdir)/config/riscv/riscv-ext-corev.def \ + $(srcdir)/config/riscv/riscv-ext.def \ + $(srcdir)/config/riscv/riscv-ext-sifive.def \ + $(srcdir)/config/riscv/riscv-ext-thead.def \ + $(srcdir)/config/riscv/riscv-ext-ventana.def + +$(srcdir)/config/riscv/riscv-ext.opt: $(RISCV_EXT_DEFS) + +$(srcdir)/config/riscv/riscv-ext.opt: s-riscv-ext.opt ; @true + +build/gen-riscv-ext-opt$(build_exeext): $(srcdir)/config/riscv/gen-riscv-ext-opt.cc \ + $(RISCV_EXT_DEFS) + $(CXX_FOR_BUILD) $(CXXFLAGS_FOR_BUILD) $< -o $@ + +s-riscv-ext.opt: build/gen-riscv-ext-opt$(build_exeext) + $(RUN_GEN) build/gen-riscv-ext-opt$(build_exeext) > tmp-riscv-ext.opt + $(SHELL) $(srcdir)/../move-if-change tmp-riscv-ext.opt $(srcdir)/config/riscv/riscv-ext.opt + $(STAMP) s-riscv-ext.opt + +build/gen-riscv-ext-texi$(build_exeext): $(srcdir)/config/riscv/gen-riscv-ext-texi.cc \ + $(RISCV_EXT_DEFS) + $(CXX_FOR_BUILD) $(CXXFLAGS_FOR_BUILD) $< -o $@ + + +$(srcdir)/doc/riscv-ext.texi: $(RISCV_EXT_DEFS) +$(srcdir)/doc/riscv-ext.texi: s-riscv-ext.texi ; @true + +# Generate the doc when generating option file. +$(srcdir)/config/riscv/riscv-ext.opt: s-riscv-ext.texi ; @true + +s-riscv-ext.texi: build/gen-riscv-ext-texi$(build_exeext) + $(RUN_GEN) build/gen-riscv-ext-texi$(build_exeext) > tmp-riscv-ext.texi + $(SHELL) $(srcdir)/../move-if-change tmp-riscv-ext.texi $(srcdir)/doc/riscv-ext.texi + $(STAMP) s-riscv-ext.texi + +# Run `riscv-regen' after you changed or added anything from riscv-ext*.def + +.PHONY: riscv-regen + +riscv-regen: s-riscv-ext.texi s-riscv-ext.opt diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index f9b93e6..764e158 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,8 @@ +2025-05-12 Jason Merrill <jason@redhat.com> + + PR c++/120012 + * class.cc (check_non_pod_aggregate): Check is_empty_class. + 2025-05-10 Jason Merrill <jason@redhat.com> PR c++/120204 diff --git a/gcc/cp/class.cc b/gcc/cp/class.cc index 2764bb5..db39e57 100644 --- a/gcc/cp/class.cc +++ b/gcc/cp/class.cc @@ -6879,8 +6879,10 @@ check_non_pod_aggregate (tree field) tree type = TREE_TYPE (field); if (TYPE_IDENTIFIER (type) == as_base_identifier) type = TYPE_CONTEXT (type); - if (!CLASS_TYPE_P (type) || (!CLASSTYPE_NON_POD_AGGREGATE (type) - && !CLASSTYPE_NON_AGGREGATE_POD (type))) + if (!CLASS_TYPE_P (type) + || is_empty_class (type) + || (!CLASSTYPE_NON_POD_AGGREGATE (type) + && !CLASSTYPE_NON_AGGREGATE_POD (type))) return; tree size = end_of_class (type, (DECL_FIELD_IS_BASE (field) ? eoc_nvsize : eoc_nv_or_dsize)); diff --git a/gcc/diagnostic-format-html.cc b/gcc/diagnostic-format-html.cc index 2d642df..6bb1caf 100644 --- a/gcc/diagnostic-format-html.cc +++ b/gcc/diagnostic-format-html.cc @@ -27,11 +27,14 @@ along with GCC; see the file COPYING3. If not see #include "diagnostic-metadata.h" #include "diagnostic-format.h" #include "diagnostic-format-html.h" +#include "diagnostic-format-text.h" #include "diagnostic-output-file.h" #include "diagnostic-buffer.h" #include "selftest.h" #include "selftest-diagnostic.h" #include "pretty-print-format-impl.h" +#include "pretty-print-urlifier.h" +#include "edit-context.h" #include "intl.h" namespace xml { @@ -280,8 +283,8 @@ public: friend class diagnostic_html_format_buffer; html_builder (diagnostic_context &context, - pretty_printer &pp, - const line_maps *line_maps); + pretty_printer &pp, + const line_maps *line_maps); void on_report_diagnostic (const diagnostic_info &diagnostic, diagnostic_t orig_diag_kind, @@ -303,11 +306,27 @@ public: m_printer = &pp; } + std::unique_ptr<xml::element> + make_element_for_metadata (const diagnostic_metadata &metadata); + + std::unique_ptr<xml::element> + make_element_for_source (const diagnostic_info &diagnostic); + + std::unique_ptr<xml::element> + make_element_for_path (const diagnostic_path &path); + + std::unique_ptr<xml::element> + make_element_for_patch (const diagnostic_info &diagnostic); + private: std::unique_ptr<xml::element> make_element_for_diagnostic (const diagnostic_info &diagnostic, diagnostic_t orig_diag_kind); + std::unique_ptr<xml::element> + make_metadata_element (label_text label, + label_text url); + diagnostic_context &m_context; pretty_printer *m_printer; const line_maps *m_line_maps; @@ -560,28 +579,11 @@ html_builder::make_element_for_diagnostic (const diagnostic_info &diagnostic, if (diagnostic.metadata) { - int cwe = diagnostic.metadata->get_cwe (); - if (cwe) - { - diag_element->add_text (label_text::borrow (" ")); - auto cwe_span = make_span (label_text::borrow ("gcc-cwe-metadata")); - cwe_span->add_text (label_text::borrow ("[")); - { - auto anchor = std::make_unique<xml::element> ("a", true); - anchor->set_attr ("href", label_text::take (get_cwe_url (cwe))); - pretty_printer pp; - pp_printf (&pp, "CWE-%i", cwe); - anchor->add_text - (label_text::take (xstrdup (pp_formatted_text (&pp)))); - cwe_span->add_child (std::move (anchor)); - } - cwe_span->add_text (label_text::borrow ("]")); - diag_element->add_child (std::move (cwe_span)); - } + diag_element->add_text (label_text::borrow (" ")); + diag_element->add_child + (make_element_for_metadata (*diagnostic.metadata)); } - // TODO: show any rules - label_text option_text = label_text::take (m_context.make_option_name (diagnostic.option_id, orig_diag_kind, diagnostic.kind)); @@ -608,20 +610,122 @@ html_builder::make_element_for_diagnostic (const diagnostic_info &diagnostic, diag_element->add_child (std::move (option_span)); } + /* Source (and fix-it hints). */ + if (auto source_element = make_element_for_source (diagnostic)) + diag_element->add_child (std::move (source_element)); + + /* Execution path. */ + if (auto path = diagnostic.richloc->get_path ()) + if (auto path_element = make_element_for_path (*path)) + diag_element->add_child (std::move (path_element)); + + if (auto patch_element = make_element_for_patch (diagnostic)) + diag_element->add_child (std::move (patch_element)); + + return diag_element; +} + +std::unique_ptr<xml::element> +html_builder::make_element_for_source (const diagnostic_info &diagnostic) +{ + // TODO: ideally we'd like to capture elements within the following: + m_context.m_last_location = UNKNOWN_LOCATION; + pp_clear_output_area (m_printer); + diagnostic_show_locus (&m_context, + m_context.m_source_printing, + diagnostic.richloc, diagnostic.kind, + m_printer); + auto text = label_text::take (xstrdup (pp_formatted_text (m_printer))); + pp_clear_output_area (m_printer); + + if (strlen (text.get ()) == 0) + return nullptr; + + auto pre = std::make_unique<xml::element> ("pre", true); + pre->set_attr ("class", label_text::borrow ("gcc-annotated-source")); + pre->add_text (std::move (text)); + return pre; +} + +std::unique_ptr<xml::element> +html_builder::make_element_for_path (const diagnostic_path &path) +{ + m_context.m_last_location = UNKNOWN_LOCATION; + diagnostic_text_output_format text_format (m_context); + pp_show_color (text_format.get_printer ()) = false; + pp_buffer (text_format.get_printer ())->m_flush_p = false; + // TODO: ideally we'd like to capture elements within the following: + text_format.print_path (path); + auto text = label_text::take + (xstrdup (pp_formatted_text (text_format.get_printer ()))); + + if (strlen (text.get ()) == 0) + return nullptr; + + auto pre = std::make_unique<xml::element> ("pre", true); + pre->set_attr ("class", label_text::borrow ("gcc-execution-path")); + pre->add_text (std::move (text)); + return pre; +} + +std::unique_ptr<xml::element> +html_builder::make_element_for_patch (const diagnostic_info &diagnostic) +{ + edit_context ec (m_context.get_file_cache ()); + ec.add_fixits (diagnostic.richloc); + if (char *diff = ec.generate_diff (true)) + if (strlen (diff) > 0) + { + auto element = std::make_unique<xml::element> ("pre", true); + element->set_attr ("class", label_text::borrow ("gcc-generated-patch")); + element->add_text (label_text::take (diff)); + return element; + } + return nullptr; +} + +std::unique_ptr<xml::element> +html_builder::make_metadata_element (label_text label, + label_text url) +{ + auto item = make_span (label_text::borrow ("gcc-metadata-item")); + item->add_text (label_text::borrow ("[")); { - auto pre = std::make_unique<xml::element> ("pre", true); - pre->set_attr ("class", label_text::borrow ("gcc-annotated-source")); - // TODO: ideally we'd like to capture elements within the following: - diagnostic_show_locus (&m_context, m_context.m_source_printing, - diagnostic.richloc, diagnostic.kind, - m_printer); - pre->add_text - (label_text::take (xstrdup (pp_formatted_text (m_printer)))); - pp_clear_output_area (m_printer); - diag_element->add_child (std::move (pre)); + auto anchor = std::make_unique<xml::element> ("a", true); + anchor->set_attr ("href", std::move (url)); + anchor->add_child (std::make_unique<xml::text> (std::move (label))); + item->add_child (std::move (anchor)); } + item->add_text (label_text::borrow ("]")); + return item; +} - return diag_element; +std::unique_ptr<xml::element> +html_builder::make_element_for_metadata (const diagnostic_metadata &metadata) +{ + auto span_metadata = make_span (label_text::borrow ("gcc-metadata")); + + int cwe = metadata.get_cwe (); + if (cwe) + { + pretty_printer pp; + pp_printf (&pp, "CWE-%i", cwe); + label_text label = label_text::take (xstrdup (pp_formatted_text (&pp))); + label_text url = label_text::take (get_cwe_url (cwe)); + span_metadata->add_child + (make_metadata_element (std::move (label), std::move (url))); + } + + for (unsigned idx = 0; idx < metadata.get_num_rules (); ++idx) + { + auto &rule = metadata.get_rule (idx); + label_text label = label_text::take (rule.make_description ()); + label_text url = label_text::take (rule.make_url ()); + span_metadata->add_child + (make_metadata_element (std::move (label), std::move (url))); + } + + return span_metadata; } /* Implementation of diagnostic_context::m_diagrams.m_emission_cb @@ -734,6 +838,8 @@ public: return m_builder.get_document (); } + html_builder &get_builder () { return m_builder; } + protected: html_output_format (diagnostic_context &context, const line_maps *line_maps) @@ -852,6 +958,11 @@ public: return m_format->get_document (); } + html_builder &get_builder () const + { + return m_format->get_builder (); + } + private: class html_buffered_output_format : public html_output_format { @@ -880,7 +991,7 @@ test_simple_log () test_html_diagnostic_context dc; rich_location richloc (line_table, UNKNOWN_LOCATION); - dc.report (DK_ERROR, richloc, nullptr, 0, "this is a test: %i", 42); + dc.report (DK_ERROR, richloc, nullptr, 0, "this is a test: %qs", "foo"); const xml::document &doc = dc.get_document (); @@ -899,20 +1010,70 @@ test_simple_log () " <body>\n" " <div class=\"gcc-diagnostic-list\">\n" " <div class=\"gcc-diagnostic\">\n" - " <span class=\"gcc-message\">this is a test: 42</span>\n" - " <pre class=\"gcc-annotated-source\"></pre>\n" + " <span class=\"gcc-message\">this is a test: `<span class=\"gcc-quoted-text\">foo</span>'</span>\n" " </div>\n" " </div>\n" " </body>\n" "</html>")); } +static void +test_metadata () +{ + test_html_diagnostic_context dc; + html_builder &b = dc.get_builder (); + + { + diagnostic_metadata metadata; + metadata.add_cwe (415); + auto element = b.make_element_for_metadata (metadata); + pretty_printer pp; + element->write_as_xml (&pp, 0, true); + ASSERT_STREQ + (pp_formatted_text (&pp), + "\n" + "<span class=\"gcc-metadata\">" + "<span class=\"gcc-metadata-item\">" + "[" + "<a href=\"https://cwe.mitre.org/data/definitions/415.html\">" + "CWE-415" + "</a>" + "]" + "</span>" + "</span>"); + } + + { + diagnostic_metadata metadata; + diagnostic_metadata::precanned_rule rule ("MISC-42", + "http://example.com"); + metadata.add_rule (rule); + auto element = b.make_element_for_metadata (metadata); + pretty_printer pp; + element->write_as_xml (&pp, 0, true); + ASSERT_STREQ + (pp_formatted_text (&pp), + "\n" + "<span class=\"gcc-metadata\">" + "<span class=\"gcc-metadata-item\">" + "[" + "<a href=\"http://example.com\">" + "MISC-42" + "</a>" + "]" + "</span>" + "</span>"); + } +} + /* Run all of the selftests within this file. */ void diagnostic_format_html_cc_tests () { + auto_fix_quotes fix_quotes; test_simple_log (); + test_metadata (); } } // namespace selftest diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 212d248..40ccf22 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -17905,7 +17905,6 @@ instructions, but allow the compiler to schedule those calls. * Alpha Built-in Functions:: * ARC Built-in Functions:: * ARC SIMD Built-in Functions:: -* ARM iWMMXt Built-in Functions:: * ARM C Language Extensions (ACLE):: * ARM Floating Point Status and Control Intrinsics:: * ARM ARMv8-M Security Extensions:: @@ -18521,160 +18520,6 @@ _v4hi __builtin_arc_vaddsub4h (__v4hi, __v4hi); _v4hi __builtin_arc_vsubadd4h (__v4hi, __v4hi); @end example -@node ARM iWMMXt Built-in Functions -@subsection ARM iWMMXt Built-in Functions - -These built-in functions are available for the ARM family of -processors when the @option{-mcpu=iwmmxt} switch is used: - -@smallexample -typedef int v2si __attribute__ ((vector_size (8))); -typedef short v4hi __attribute__ ((vector_size (8))); -typedef char v8qi __attribute__ ((vector_size (8))); - -int __builtin_arm_getwcgr0 (void); -void __builtin_arm_setwcgr0 (int); -int __builtin_arm_getwcgr1 (void); -void __builtin_arm_setwcgr1 (int); -int __builtin_arm_getwcgr2 (void); -void __builtin_arm_setwcgr2 (int); -int __builtin_arm_getwcgr3 (void); -void __builtin_arm_setwcgr3 (int); -int __builtin_arm_textrmsb (v8qi, int); -int __builtin_arm_textrmsh (v4hi, int); -int __builtin_arm_textrmsw (v2si, int); -int __builtin_arm_textrmub (v8qi, int); -int __builtin_arm_textrmuh (v4hi, int); -int __builtin_arm_textrmuw (v2si, int); -v8qi __builtin_arm_tinsrb (v8qi, int, int); -v4hi __builtin_arm_tinsrh (v4hi, int, int); -v2si __builtin_arm_tinsrw (v2si, int, int); -long long __builtin_arm_tmia (long long, int, int); -long long __builtin_arm_tmiabb (long long, int, int); -long long __builtin_arm_tmiabt (long long, int, int); -long long __builtin_arm_tmiaph (long long, int, int); -long long __builtin_arm_tmiatb (long long, int, int); -long long __builtin_arm_tmiatt (long long, int, int); -int __builtin_arm_tmovmskb (v8qi); -int __builtin_arm_tmovmskh (v4hi); -int __builtin_arm_tmovmskw (v2si); -long long __builtin_arm_waccb (v8qi); -long long __builtin_arm_wacch (v4hi); -long long __builtin_arm_waccw (v2si); -v8qi __builtin_arm_waddb (v8qi, v8qi); -v8qi __builtin_arm_waddbss (v8qi, v8qi); -v8qi __builtin_arm_waddbus (v8qi, v8qi); -v4hi __builtin_arm_waddh (v4hi, v4hi); -v4hi __builtin_arm_waddhss (v4hi, v4hi); -v4hi __builtin_arm_waddhus (v4hi, v4hi); -v2si __builtin_arm_waddw (v2si, v2si); -v2si __builtin_arm_waddwss (v2si, v2si); -v2si __builtin_arm_waddwus (v2si, v2si); -v8qi __builtin_arm_walign (v8qi, v8qi, int); -long long __builtin_arm_wand(long long, long long); -long long __builtin_arm_wandn (long long, long long); -v8qi __builtin_arm_wavg2b (v8qi, v8qi); -v8qi __builtin_arm_wavg2br (v8qi, v8qi); -v4hi __builtin_arm_wavg2h (v4hi, v4hi); -v4hi __builtin_arm_wavg2hr (v4hi, v4hi); -v8qi __builtin_arm_wcmpeqb (v8qi, v8qi); -v4hi __builtin_arm_wcmpeqh (v4hi, v4hi); -v2si __builtin_arm_wcmpeqw (v2si, v2si); -v8qi __builtin_arm_wcmpgtsb (v8qi, v8qi); -v4hi __builtin_arm_wcmpgtsh (v4hi, v4hi); -v2si __builtin_arm_wcmpgtsw (v2si, v2si); -v8qi __builtin_arm_wcmpgtub (v8qi, v8qi); -v4hi __builtin_arm_wcmpgtuh (v4hi, v4hi); -v2si __builtin_arm_wcmpgtuw (v2si, v2si); -long long __builtin_arm_wmacs (long long, v4hi, v4hi); -long long __builtin_arm_wmacsz (v4hi, v4hi); -long long __builtin_arm_wmacu (long long, v4hi, v4hi); -long long __builtin_arm_wmacuz (v4hi, v4hi); -v4hi __builtin_arm_wmadds (v4hi, v4hi); -v4hi __builtin_arm_wmaddu (v4hi, v4hi); -v8qi __builtin_arm_wmaxsb (v8qi, v8qi); -v4hi __builtin_arm_wmaxsh (v4hi, v4hi); -v2si __builtin_arm_wmaxsw (v2si, v2si); -v8qi __builtin_arm_wmaxub (v8qi, v8qi); -v4hi __builtin_arm_wmaxuh (v4hi, v4hi); -v2si __builtin_arm_wmaxuw (v2si, v2si); -v8qi __builtin_arm_wminsb (v8qi, v8qi); -v4hi __builtin_arm_wminsh (v4hi, v4hi); -v2si __builtin_arm_wminsw (v2si, v2si); -v8qi __builtin_arm_wminub (v8qi, v8qi); -v4hi __builtin_arm_wminuh (v4hi, v4hi); -v2si __builtin_arm_wminuw (v2si, v2si); -v4hi __builtin_arm_wmulsm (v4hi, v4hi); -v4hi __builtin_arm_wmulul (v4hi, v4hi); -v4hi __builtin_arm_wmulum (v4hi, v4hi); -long long __builtin_arm_wor (long long, long long); -v2si __builtin_arm_wpackdss (long long, long long); -v2si __builtin_arm_wpackdus (long long, long long); -v8qi __builtin_arm_wpackhss (v4hi, v4hi); -v8qi __builtin_arm_wpackhus (v4hi, v4hi); -v4hi __builtin_arm_wpackwss (v2si, v2si); -v4hi __builtin_arm_wpackwus (v2si, v2si); -long long __builtin_arm_wrord (long long, long long); -long long __builtin_arm_wrordi (long long, int); -v4hi __builtin_arm_wrorh (v4hi, long long); -v4hi __builtin_arm_wrorhi (v4hi, int); -v2si __builtin_arm_wrorw (v2si, long long); -v2si __builtin_arm_wrorwi (v2si, int); -v2si __builtin_arm_wsadb (v2si, v8qi, v8qi); -v2si __builtin_arm_wsadbz (v8qi, v8qi); -v2si __builtin_arm_wsadh (v2si, v4hi, v4hi); -v2si __builtin_arm_wsadhz (v4hi, v4hi); -v4hi __builtin_arm_wshufh (v4hi, int); -long long __builtin_arm_wslld (long long, long long); -long long __builtin_arm_wslldi (long long, int); -v4hi __builtin_arm_wsllh (v4hi, long long); -v4hi __builtin_arm_wsllhi (v4hi, int); -v2si __builtin_arm_wsllw (v2si, long long); -v2si __builtin_arm_wsllwi (v2si, int); -long long __builtin_arm_wsrad (long long, long long); -long long __builtin_arm_wsradi (long long, int); -v4hi __builtin_arm_wsrah (v4hi, long long); -v4hi __builtin_arm_wsrahi (v4hi, int); -v2si __builtin_arm_wsraw (v2si, long long); -v2si __builtin_arm_wsrawi (v2si, int); -long long __builtin_arm_wsrld (long long, long long); -long long __builtin_arm_wsrldi (long long, int); -v4hi __builtin_arm_wsrlh (v4hi, long long); -v4hi __builtin_arm_wsrlhi (v4hi, int); -v2si __builtin_arm_wsrlw (v2si, long long); -v2si __builtin_arm_wsrlwi (v2si, int); -v8qi __builtin_arm_wsubb (v8qi, v8qi); -v8qi __builtin_arm_wsubbss (v8qi, v8qi); -v8qi __builtin_arm_wsubbus (v8qi, v8qi); -v4hi __builtin_arm_wsubh (v4hi, v4hi); -v4hi __builtin_arm_wsubhss (v4hi, v4hi); -v4hi __builtin_arm_wsubhus (v4hi, v4hi); -v2si __builtin_arm_wsubw (v2si, v2si); -v2si __builtin_arm_wsubwss (v2si, v2si); -v2si __builtin_arm_wsubwus (v2si, v2si); -v4hi __builtin_arm_wunpckehsb (v8qi); -v2si __builtin_arm_wunpckehsh (v4hi); -long long __builtin_arm_wunpckehsw (v2si); -v4hi __builtin_arm_wunpckehub (v8qi); -v2si __builtin_arm_wunpckehuh (v4hi); -long long __builtin_arm_wunpckehuw (v2si); -v4hi __builtin_arm_wunpckelsb (v8qi); -v2si __builtin_arm_wunpckelsh (v4hi); -long long __builtin_arm_wunpckelsw (v2si); -v4hi __builtin_arm_wunpckelub (v8qi); -v2si __builtin_arm_wunpckeluh (v4hi); -long long __builtin_arm_wunpckeluw (v2si); -v8qi __builtin_arm_wunpckihb (v8qi, v8qi); -v4hi __builtin_arm_wunpckihh (v4hi, v4hi); -v2si __builtin_arm_wunpckihw (v2si, v2si); -v8qi __builtin_arm_wunpckilb (v8qi, v8qi); -v4hi __builtin_arm_wunpckilh (v4hi, v4hi); -v2si __builtin_arm_wunpckilw (v2si, v2si); -long long __builtin_arm_wxor (long long, long long); -long long __builtin_arm_wzero (); -@end smallexample - - @node ARM C Language Extensions (ACLE) @subsection ARM C Language Extensions (ACLE) diff --git a/gcc/doc/gm2.texi b/gcc/doc/gm2.texi index cb52e8c..8293da4 100644 --- a/gcc/doc/gm2.texi +++ b/gcc/doc/gm2.texi @@ -1495,7 +1495,7 @@ from @samp{bad} will cause an overflow to @samp{foo}. If we compile the code with the following options: @example -$ gm2 -g -fsoft-check-all -O2 -c assignvalue.mod +$ gm2 -g -fsoft-check-all -O2 -fm2-plugin -c assignvalue.mod assignvalue.mod:16:0:inevitable that this error will occur at run time, assignment will result in an overflow @end example diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index a0f1a93..ee71801 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -23520,7 +23520,7 @@ These @samp{-m} options are defined for the ARM port: @opindex mabi @item -mabi=@var{name} Generate code for the specified ABI@. Permissible values are: @samp{apcs-gnu}, -@samp{atpcs}, @samp{aapcs}, @samp{aapcs-linux} and @samp{iwmmxt}. +@samp{atpcs}, @samp{aapcs} and @samp{aapcs-linux}. @opindex mapcs-frame @item -mapcs-frame @@ -30698,6 +30698,7 @@ Generate code for the specified PTX ISA target architecture. Valid architecture strings are @samp{sm_30}, @samp{sm_35}, @samp{sm_37}, @samp{sm_52}, @samp{sm_53}, +@samp{sm_61}, @samp{sm_70}, @samp{sm_75}, @samp{sm_80}, and @samp{sm_89}. The default depends on how the compiler has been configured, see @@ -30724,6 +30725,7 @@ Generate code for the specified PTX ISA version. Valid version strings are @samp{3.1}, @samp{4.1}, @samp{4.2}, +@samp{5.0}, @samp{6.0}, @samp{6.3}, @samp{7.0}, @samp{7.3}, and @samp{7.8}. The default PTX ISA version is the one that added support for the @@ -31143,501 +31145,8 @@ syntax @samp{<major>p<minor>} or @samp{<major>}, (e.g.@: @samp{m2p1} or @end table Supported extension are listed below: -@multitable @columnfractions .10 .10 .80 -@headitem Extension Name @tab Supported Version @tab Description -@item i -@tab 2.0, 2.1 -@tab Base integer extension. - -@item e -@tab 2.0 -@tab Reduced base integer extension. - -@item g -@tab - -@tab General-purpose computing base extension, @samp{g} will expand to -@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and -@samp{zifencei}. - -@item m -@tab 2.0 -@tab Integer multiplication and division extension. - -@item a -@tab 2.0, 2.1 -@tab Atomic extension. - -@item f -@tab 2.0, 2.2 -@tab Single-precision floating-point extension. - -@item d -@tab 2.0, 2.2 -@tab Double-precision floating-point extension. - -@item c -@tab 2.0 -@tab Compressed extension. - -@item h -@tab 1.0 -@tab Hypervisor extension. - -@item v -@tab 1.0 -@tab Vector extension. - -@item zicsr -@tab 2.0 -@tab Control and status register access extension. - -@item zifencei -@tab 2.0 -@tab Instruction-fetch fence extension. - -@item zicond -@tab 1.0 -@tab Integer conditional operations extension. - -@item za64rs -@tab 1.0 -@tab Reservation set size of 64 bytes. - -@item za128rs -@tab 1.0 -@tab Reservation set size of 128 bytes. - -@item zawrs -@tab 1.0 -@tab Wait-on-reservation-set extension. - -@item zba -@tab 1.0 -@tab Address calculation extension. - -@item zbb -@tab 1.0 -@tab Basic bit manipulation extension. - -@item zbc -@tab 1.0 -@tab Carry-less multiplication extension. - -@item zbs -@tab 1.0 -@tab Single-bit operation extension. - -@item zfinx -@tab 1.0 -@tab Single-precision floating-point in integer registers extension. - -@item zdinx -@tab 1.0 -@tab Double-precision floating-point in integer registers extension. - -@item zhinx -@tab 1.0 -@tab Half-precision floating-point in integer registers extension. - -@item zhinxmin -@tab 1.0 -@tab Minimal half-precision floating-point in integer registers extension. - -@item zbkb -@tab 1.0 -@tab Cryptography bit-manipulation extension. - -@item zbkc -@tab 1.0 -@tab Cryptography carry-less multiply extension. - -@item zbkx -@tab 1.0 -@tab Cryptography crossbar permutation extension. - -@item zkne -@tab 1.0 -@tab AES Encryption extension. - -@item zknd -@tab 1.0 -@tab AES Decryption extension. - -@item zknh -@tab 1.0 -@tab Hash function extension. - -@item zkr -@tab 1.0 -@tab Entropy source extension. - -@item zksed -@tab 1.0 -@tab SM4 block cipher extension. - -@item zksh -@tab 1.0 -@tab SM3 hash function extension. - -@item zkt -@tab 1.0 -@tab Data independent execution latency extension. - -@item zk -@tab 1.0 -@tab Standard scalar cryptography extension. - -@item zkn -@tab 1.0 -@tab NIST algorithm suite extension. - -@item zks -@tab 1.0 -@tab ShangMi algorithm suite extension. -@item zihintntl -@tab 1.0 -@tab Non-temporal locality hints extension. - -@item zihintpause -@tab 1.0 -@tab Pause hint extension. - -@item zicboz -@tab 1.0 -@tab Cache-block zero extension. - -@item zicbom -@tab 1.0 -@tab Cache-block management extension. - -@item zicbop -@tab 1.0 -@tab Cache-block prefetch extension. - -@item zic64b -@tab 1.0 -@tab Cache block size isf 64 bytes. - -@item ziccamoa -@tab 1.0 -@tab Main memory supports all atomics in A. - -@item ziccif -@tab 1.0 -@tab Main memory supports instruction fetch with atomicity requirement. - -@item zicclsm -@tab 1.0 -@tab Main memory supports misaligned loads/stores. - -@item ziccrse -@tab 1.0 -@tab Main memory supports forward progress on LR/SC sequences. - -@item zicntr -@tab 2.0 -@tab Standard extension for base counters and timers. - -@item zihpm -@tab 2.0 -@tab Standard extension for hardware performance counters. - -@item ztso -@tab 1.0 -@tab Total store ordering extension. - -@item zve32x -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve32f -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve64x -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve64f -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve64d -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zvl32b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl64b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl128b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl256b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl512b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl1024b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl2048b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl4096b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvbb -@tab 1.0 -@tab Vector basic bit-manipulation extension. - -@item zvbc -@tab 1.0 -@tab Vector carryless multiplication extension. - -@item zvkb -@tab 1.0 -@tab Vector cryptography bit-manipulation extension. - -@item zvkg -@tab 1.0 -@tab Vector GCM/GMAC extension. - -@item zvkned -@tab 1.0 -@tab Vector AES block cipher extension. - -@item zvknha -@tab 1.0 -@tab Vector SHA-2 secure hash extension. - -@item zvknhb -@tab 1.0 -@tab Vector SHA-2 secure hash extension. - -@item zvksed -@tab 1.0 -@tab Vector SM4 Block Cipher extension. - -@item zvksh -@tab 1.0 -@tab Vector SM3 Secure Hash extension. - -@item zvkn -@tab 1.0 -@tab Vector NIST Algorithm Suite extension, @samp{zvkn} will expand to -@samp{zvkned}, @samp{zvknhb}, @samp{zvkb} and @samp{zvkt}. - -@item zvknc -@tab 1.0 -@tab Vector NIST Algorithm Suite with carryless multiply extension, @samp{zvknc} -will expand to @samp{zvkn} and @samp{zvbc}. - -@item zvkng -@tab 1.0 -@tab Vector NIST Algorithm Suite with GCM extension, @samp{zvkng} will expand -to @samp{zvkn} and @samp{zvkg}. - -@item zvks -@tab 1.0 -@tab Vector ShangMi algorithm suite extension, @samp{zvks} will expand -to @samp{zvksed}, @samp{zvksh}, @samp{zvkb} and @samp{zvkt}. - -@item zvksc -@tab 1.0 -@tab Vector ShangMi algorithm suite with carryless multiplication extension, -@samp{zvksc} will expand to @samp{zvks} and @samp{zvbc}. - -@item zvksg -@tab 1.0 -@tab Vector ShangMi algorithm suite with GCM extension, @samp{zvksg} will expand -to @samp{zvks} and @samp{zvkg}. - -@item zvkt -@tab 1.0 -@tab Vector data independent execution latency extension. - -@item zfh -@tab 1.0 -@tab Half-precision floating-point extension. - -@item zfhmin -@tab 1.0 -@tab Minimal half-precision floating-point extension. - -@item zvfh -@tab 1.0 -@tab Vector half-precision floating-point extension. - -@item zvfhmin -@tab 1.0 -@tab Vector minimal half-precision floating-point extension. - -@item zvfbfmin -@tab 1.0 -@tab Vector BF16 converts extension. - -@item zfa -@tab 1.0 -@tab Additional floating-point extension. - -@item zmmul -@tab 1.0 -@tab Integer multiplication extension. - -@item zca -@tab 1.0 -@tab Integer compressed instruction extension. - -@item zcf -@tab 1.0 -@tab Compressed single-precision floating point loads and stores extension. - -@item zcd -@tab 1.0 -@tab Compressed double-precision floating point loads and stores extension. - -@item zcb -@tab 1.0 -@tab Simple compressed instruction extension. - -@item zce -@tab 1.0 -@tab Compressed instruction extensions for embedded processors. - -@item zcmp -@tab 1.0 -@tab Compressed push pop extension. - -@item zcmt -@tab 1.0 -@tab Table jump instruction extension. - -@item smaia -@tab 1.0 -@tab Advanced interrupt architecture extension. - -@item smepmp -@tab 1.0 -@tab PMP Enhancements for memory access and execution prevention on Machine mode. - -@item smstateen -@tab 1.0 -@tab State enable extension. - -@item ssaia -@tab 1.0 -@tab Advanced interrupt architecture extension for supervisor-mode. - -@item sscofpmf -@tab 1.0 -@tab Count overflow & filtering extension. - -@item ssstateen -@tab 1.0 -@tab State-enable extension for supervisor-mode. - -@item sstc -@tab 1.0 -@tab Supervisor-mode timer interrupts extension. - -@item svade -@tab 1.0 -@tab Cause exception when hardware updating of A/D bits is disabled - -@item svadu -@tab 1.0 -@tab Hardware Updating of A/D Bits extension. - -@item svinval -@tab 1.0 -@tab Fine-grained address-translation cache invalidation extension. - -@item svnapot -@tab 1.0 -@tab NAPOT translation contiguity extension. - -@item svpbmt -@tab 1.0 -@tab Page-based memory types extension. - -@item xcvmac -@tab 1.0 -@tab Core-V multiply-accumulate extension. - -@item xcvalu -@tab 1.0 -@tab Core-V miscellaneous ALU extension. - -@item xcvelw -@tab 1.0 -@tab Core-V event load word extension. - -@item xtheadba -@tab 1.0 -@tab T-head address calculation extension. - -@item xtheadbb -@tab 1.0 -@tab T-head basic bit-manipulation extension. - -@item xtheadbs -@tab 1.0 -@tab T-head single-bit instructions extension. - -@item xtheadcmo -@tab 1.0 -@tab T-head cache management operations extension. - -@item xtheadcondmov -@tab 1.0 -@tab T-head conditional move extension. - -@item xtheadfmemidx -@tab 1.0 -@tab T-head indexed memory operations for floating-point registers extension. - -@item xtheadfmv -@tab 1.0 -@tab T-head double floating-point high-bit data transmission extension. - -@item xtheadint -@tab 1.0 -@tab T-head acceleration interruption extension. - -@item xtheadmac -@tab 1.0 -@tab T-head multiply-accumulate extension. - -@item xtheadmemidx -@tab 1.0 -@tab T-head indexed memory operation extension. - -@item xtheadmempair -@tab 1.0 -@tab T-head two-GPR memory operation extension. - -@item xtheadsync -@tab 1.0 -@tab T-head multi-core synchronization extension. - -@item xventanacondops -@tab 1.0 -@tab Ventana integer conditional operations extension. - -@end multitable +@include riscv-ext.texi When @option{-march=} is not specified, use the setting from @option{-mcpu}. diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index ae7a601..f6314af 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -2171,12 +2171,6 @@ VFP floating-point registers @code{d0}-@code{d31} and the appropriate subset @code{d0}-@code{d15} based on command line options. Used for 64 bit values only. Not valid for Thumb1. -@item y -The iWMMX co-processor registers. - -@item z -The iWMMX GR registers. - @item G The floating-point constant 0.0 @@ -2210,9 +2204,6 @@ A symbol in the text segment of the current file @item Uv A memory reference suitable for VFP load/store insns (reg+constant offset) -@item Uy -A memory reference suitable for iWMMXt load/store instructions. - @item Uq A memory reference suitable for the ARMv4 ldrsb instruction. @end table diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi new file mode 100644 index 0000000..968654b --- /dev/null +++ b/gcc/doc/riscv-ext.texi @@ -0,0 +1,637 @@ +@c Copyright (C) 2025 Free Software Foundation, Inc. +@c This is part of the GCC manual. +@c For copying conditions, see the file gcc/doc/include/fdl.texi. + +@c This file is generated automatically using +@c gcc/config/riscv/gen-riscv-ext-texi.cc from: +@c gcc/config/riscv/riscv-ext.def +@c gcc/config/riscv/riscv-opts.h + +@c Please *DO NOT* edit manually. + +@multitable @columnfractions .10 .10 .80 +@headitem Extension Name @tab Supported Version @tab Description + +@item g +@tab - +@tab General-purpose computing base extension, @samp{g} will expand to +@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and +@samp{zifencei}. + +@item e +@tab 2.0 +@tab Reduced base integer extension + +@item i +@tab 2.0 2.1 +@tab Base integer extension + +@item m +@tab 2.0 +@tab Integer multiplication and division extension + +@item a +@tab 2.0 2.1 +@tab Atomic extension + +@item f +@tab 2.0 2.2 +@tab Single-precision floating-point extension + +@item d +@tab 2.0 2.2 +@tab Double-precision floating-point extension + +@item c +@tab 2.0 +@tab Compressed extension + +@item b +@tab 1.0 +@tab b extension + +@item v +@tab 1.0 +@tab Vector extension + +@item h +@tab 1.0 +@tab Hypervisor extension + +@item zic64b +@tab 1.0 +@tab Cache block size isf 64 bytes + +@item zicbom +@tab 1.0 +@tab Cache-block management extension + +@item zicbop +@tab 1.0 +@tab Cache-block prefetch extension + +@item zicboz +@tab 1.0 +@tab Cache-block zero extension + +@item ziccamoa +@tab 1.0 +@tab Main memory supports all atomics in A + +@item ziccif +@tab 1.0 +@tab Main memory supports instruction fetch with atomicity requirement + +@item zicclsm +@tab 1.0 +@tab Main memory supports misaligned loads/stores + +@item ziccrse +@tab 1.0 +@tab Main memory supports forward progress on LR/SC sequences + +@item zicfilp +@tab 1.0 +@tab zicfilp extension + +@item zicfiss +@tab 1.0 +@tab zicfiss extension + +@item zicntr +@tab 2.0 +@tab Standard extension for base counters and timers + +@item zicond +@tab 1.0 +@tab Integer conditional operations extension + +@item zicsr +@tab 2.0 +@tab Control and status register access extension + +@item zifencei +@tab 2.0 +@tab Instruction-fetch fence extension + +@item zihintntl +@tab 1.0 +@tab Non-temporal locality hints extension + +@item zihintpause +@tab 2.0 +@tab Pause hint extension + +@item zihpm +@tab 2.0 +@tab Standard extension for hardware performance counters + +@item zimop +@tab 1.0 +@tab zimop extension + +@item zilsd +@tab 1.0 +@tab Load/Store pair instructions extension + +@item zmmul +@tab 1.0 +@tab Integer multiplication extension + +@item za128rs +@tab 1.0 +@tab Reservation set size of 128 bytes + +@item za64rs +@tab 1.0 +@tab Reservation set size of 64 bytes + +@item zaamo +@tab 1.0 +@tab zaamo extension + +@item zabha +@tab 1.0 +@tab zabha extension + +@item zacas +@tab 1.0 +@tab zacas extension + +@item zalrsc +@tab 1.0 +@tab zalrsc extension + +@item zawrs +@tab 1.0 +@tab Wait-on-reservation-set extension + +@item zama16b +@tab 1.0 +@tab Zama16b extension, Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic. + +@item zfa +@tab 1.0 +@tab Additional floating-point extension + +@item zfbfmin +@tab 1.0 +@tab zfbfmin extension + +@item zfh +@tab 1.0 +@tab Half-precision floating-point extension + +@item zfhmin +@tab 1.0 +@tab Minimal half-precision floating-point extension + +@item zfinx +@tab 1.0 +@tab Single-precision floating-point in integer registers extension + +@item zdinx +@tab 1.0 +@tab Double-precision floating-point in integer registers extension + +@item zca +@tab 1.0 +@tab Integer compressed instruction extension + +@item zcb +@tab 1.0 +@tab Simple compressed instruction extension + +@item zcd +@tab 1.0 +@tab Compressed double-precision floating point loads and stores extension + +@item zce +@tab 1.0 +@tab Compressed instruction extensions for embedded processors + +@item zcf +@tab 1.0 +@tab Compressed single-precision floating point loads and stores extension + +@item zcmop +@tab 1.0 +@tab zcmop extension + +@item zcmp +@tab 1.0 +@tab Compressed push pop extension + +@item zcmt +@tab 1.0 +@tab Table jump instruction extension + +@item zclsd +@tab 1.0 +@tab Compressed load/store pair instructions extension + +@item zba +@tab 1.0 +@tab Address calculation extension + +@item zbb +@tab 1.0 +@tab Basic bit manipulation extension + +@item zbc +@tab 1.0 +@tab Carry-less multiplication extension + +@item zbkb +@tab 1.0 +@tab Cryptography bit-manipulation extension + +@item zbkc +@tab 1.0 +@tab Cryptography carry-less multiply extension + +@item zbkx +@tab 1.0 +@tab Cryptography crossbar permutation extension + +@item zbs +@tab 1.0 +@tab Single-bit operation extension + +@item zk +@tab 1.0 +@tab Standard scalar cryptography extension + +@item zkn +@tab 1.0 +@tab NIST algorithm suite extension + +@item zknd +@tab 1.0 +@tab AES Decryption extension + +@item zkne +@tab 1.0 +@tab AES Encryption extension + +@item zknh +@tab 1.0 +@tab Hash function extension + +@item zkr +@tab 1.0 +@tab Entropy source extension + +@item zks +@tab 1.0 +@tab ShangMi algorithm suite extension + +@item zksed +@tab 1.0 +@tab SM4 block cipher extension + +@item zksh +@tab 1.0 +@tab SM3 hash function extension + +@item zkt +@tab 1.0 +@tab Data independent execution latency extension + +@item ztso +@tab 1.0 +@tab Total store ordering extension + +@item zvbb +@tab 1.0 +@tab Vector basic bit-manipulation extension + +@item zvbc +@tab 1.0 +@tab Vector carryless multiplication extension + +@item zve32f +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zve32x +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zve64d +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zve64f +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zve64x +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zvfbfmin +@tab 1.0 +@tab Vector BF16 converts extension + +@item zvfbfwma +@tab 1.0 +@tab zvfbfwma extension + +@item zvfh +@tab 1.0 +@tab Vector half-precision floating-point extension + +@item zvfhmin +@tab 1.0 +@tab Vector minimal half-precision floating-point extension + +@item zvkb +@tab 1.0 +@tab Vector cryptography bit-manipulation extension + +@item zvkg +@tab 1.0 +@tab Vector GCM/GMAC extension + +@item zvkn +@tab 1.0 +@tab Vector NIST Algorithm Suite extension, @samp{zvkn} will expand to + +@item zvknc +@tab 1.0 +@tab Vector NIST Algorithm Suite with carryless multiply extension, @samp{zvknc} + +@item zvkned +@tab 1.0 +@tab Vector AES block cipher extension + +@item zvkng +@tab 1.0 +@tab Vector NIST Algorithm Suite with GCM extension, @samp{zvkng} will expand + +@item zvknha +@tab 1.0 +@tab Vector SHA-2 secure hash extension + +@item zvknhb +@tab 1.0 +@tab Vector SHA-2 secure hash extension + +@item zvks +@tab 1.0 +@tab Vector ShangMi algorithm suite extension, @samp{zvks} will expand + +@item zvksc +@tab 1.0 +@tab Vector ShangMi algorithm suite with carryless multiplication extension, + +@item zvksed +@tab 1.0 +@tab Vector SM4 Block Cipher extension + +@item zvksg +@tab 1.0 +@tab Vector ShangMi algorithm suite with GCM extension, @samp{zvksg} will expand + +@item zvksh +@tab 1.0 +@tab Vector SM3 Secure Hash extension + +@item zvkt +@tab 1.0 +@tab Vector data independent execution latency extension + +@item zvl1024b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl128b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl16384b +@tab 1.0 +@tab zvl16384b extension + +@item zvl2048b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl256b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl32768b +@tab 1.0 +@tab zvl32768b extension + +@item zvl32b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl4096b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl512b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl64b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl65536b +@tab 1.0 +@tab zvl65536b extension + +@item zvl8192b +@tab 1.0 +@tab zvl8192b extension + +@item zhinx +@tab 1.0 +@tab Half-precision floating-point in integer registers extension + +@item zhinxmin +@tab 1.0 +@tab Minimal half-precision floating-point in integer registers extension + +@item sdtrig +@tab 1.0 +@tab sdtrig extension + +@item smaia +@tab 1.0 +@tab Advanced interrupt architecture extension + +@item smepmp +@tab 1.0 +@tab PMP Enhancements for memory access and execution prevention on Machine mode + +@item smmpm +@tab 1.0 +@tab smmpm extension + +@item smnpm +@tab 1.0 +@tab smnpm extension + +@item smstateen +@tab 1.0 +@tab State enable extension + +@item ssaia +@tab 1.0 +@tab Advanced interrupt architecture extension for supervisor-mode + +@item sscofpmf +@tab 1.0 +@tab Count overflow & filtering extension + +@item ssnpm +@tab 1.0 +@tab ssnpm extension + +@item sspm +@tab 1.0 +@tab sspm extension + +@item ssstateen +@tab 1.0 +@tab State-enable extension for supervisor-mode + +@item sstc +@tab 1.0 +@tab Supervisor-mode timer interrupts extension + +@item ssstrict +@tab 1.0 +@tab ssstrict extension + +@item supm +@tab 1.0 +@tab supm extension + +@item svinval +@tab 1.0 +@tab Fine-grained address-translation cache invalidation extension + +@item svnapot +@tab 1.0 +@tab NAPOT translation contiguity extension + +@item svpbmt +@tab 1.0 +@tab Page-based memory types extension + +@item svvptc +@tab 1.0 +@tab svvptc extension + +@item svadu +@tab 1.0 +@tab Hardware Updating of A/D Bits extension + +@item svade +@tab 1.0 +@tab Cause exception when hardware updating of A/D bits is disabled + +@item xcvalu +@tab 1.0 +@tab Core-V miscellaneous ALU extension + +@item xcvbi +@tab 1.0 +@tab xcvbi extension + +@item xcvelw +@tab 1.0 +@tab Core-V event load word extension + +@item xcvmac +@tab 1.0 +@tab Core-V multiply-accumulate extension + +@item xcvsimd +@tab 1.0 +@tab xcvsimd extension + +@item xsfcease +@tab 1.0 +@tab xsfcease extension + +@item xsfvcp +@tab 1.0 +@tab xsfvcp extension + +@item xsfvfnrclipxfqf +@tab 1.0 +@tab xsfvfnrclipxfqf extension + +@item xsfvqmaccdod +@tab 1.0 +@tab xsfvqmaccdod extension + +@item xsfvqmaccqoq +@tab 1.0 +@tab xsfvqmaccqoq extension + +@item xtheadba +@tab 1.0 +@tab T-head address calculation extension + +@item xtheadbb +@tab 1.0 +@tab T-head basic bit-manipulation extension + +@item xtheadbs +@tab 1.0 +@tab T-head single-bit instructions extension + +@item xtheadcmo +@tab 1.0 +@tab T-head cache management operations extension + +@item xtheadcondmov +@tab 1.0 +@tab T-head conditional move extension + +@item xtheadfmemidx +@tab 1.0 +@tab T-head indexed memory operations for floating-point registers extension + +@item xtheadfmv +@tab 1.0 +@tab T-head double floating-point high-bit data transmission extension + +@item xtheadint +@tab 1.0 +@tab T-head acceleration interruption extension + +@item xtheadmac +@tab 1.0 +@tab T-head multiply-accumulate extension + +@item xtheadmemidx +@tab 1.0 +@tab T-head indexed memory operation extension + +@item xtheadmempair +@tab 1.0 +@tab T-head two-GPR memory operation extension + +@item xtheadsync +@tab 1.0 +@tab T-head multi-core synchronization extension + +@item xtheadvector +@tab 1.0 +@tab xtheadvector extension + +@item xventanacondops +@tab 1.0 +@tab Ventana integer conditional operations extension + +@end multitable diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 65eeecc..1c718c4 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2042,10 +2042,6 @@ ARM target uses emulated floating point operations. ARM target supports @code{-mfpu=vfp -mfloat-abi=hard}. Some multilibs may be incompatible with these options. -@item arm_iwmmxt_ok -ARM target supports @code{-mcpu=iwmmxt}. -Some multilibs may be incompatible with this option. - @item arm_neon ARM target supports generating NEON instructions. diff --git a/gcc/lto-streamer-out.cc b/gcc/lto-streamer-out.cc index a055d12..86d3384 100644 --- a/gcc/lto-streamer-out.cc +++ b/gcc/lto-streamer-out.cc @@ -1256,7 +1256,17 @@ hash_tree (struct streamer_tree_cache_d *cache, hash_map<tree, hashval_t> *map, if (CODE_CONTAINS_STRUCT (code, TS_DECL_COMMON)) { - hstate.add_hwi (DECL_MODE (t)); + /* Similar to TYPE_MODE, avoid streaming out host-specific DECL_MODE + for aggregate type with offloading enabled, and while streaming-in + recompute appropriate DECL_MODE for accelerator. */ + if (lto_stream_offload_p + && (VAR_P (t) + || TREE_CODE (t) == PARM_DECL + || TREE_CODE (t) == FIELD_DECL) + && AGGREGATE_TYPE_P (TREE_TYPE (t))) + hstate.add_hwi (VOIDmode); + else + hstate.add_hwi (DECL_MODE (t)); hstate.add_flag (DECL_NONLOCAL (t)); hstate.add_flag (DECL_VIRTUAL_P (t)); hstate.add_flag (DECL_IGNORED_P (t)); @@ -1354,7 +1364,19 @@ hash_tree (struct streamer_tree_cache_d *cache, hash_map<tree, hashval_t> *map, if (CODE_CONTAINS_STRUCT (code, TS_TYPE_COMMON)) { - hstate.add_hwi (TYPE_MODE (t)); + /* For offloading, avoid streaming out TYPE_MODE for aggregate type since + it may be host-specific. For eg, aarch64 uses OImode for ARRAY_TYPE + whose size is 256-bits, which is not representable on accelerator. + Instead stream out VOIDmode, and while streaming-in, recompute + appropriate TYPE_MODE for accelerator. */ + if (lto_stream_offload_p + && (AGGREGATE_TYPE_P (t) || VECTOR_TYPE_P (t))) + hstate.add_hwi (VOIDmode); + /* for VECTOR_TYPE, TYPE_MODE reevaluates the mode using target_flags + not necessary valid in a global context. + Use the raw value previously set by layout_type. */ + else + hstate.add_hwi (TYPE_MODE_RAW (t)); /* TYPE_NO_FORCE_BLK is private to stor-layout and need no streaming. */ hstate.add_flag (TYPE_PACKED (t)); diff --git a/gcc/match.pd b/gcc/match.pd index ab496d9..f405068 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -3242,7 +3242,21 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) SAT_U_ADD = IMAGPART (SUM) != 0 ? -1 : REALPART (SUM) */ (cond^ (ne (imagpart (IFN_ADD_OVERFLOW@2 @0 INTEGER_CST@1)) integer_zerop) integer_minus_onep (realpart @2)) - (if (types_match (type, @0) && int_fits_type_p (@1, type))))) + (if (types_match (type, @0) && int_fits_type_p (@1, type)))) + (match (unsigned_integer_sat_add @0 @1) + /* WIDEN_SUM = (WT)X + (WT)Y + SAT_U_ADD = WIDEN_SUM > MAX ? MAX : (NT)WIDEN_SUM */ + (cond^ (le (plus (convert@2 @0) (convert@3 @1)) INTEGER_CST@4) + (plus:c @0 @1) integer_minus_onep) + (if (types_match (type, @0, @1) && types_match (@2, @3)) + (with + { + unsigned precision = TYPE_PRECISION (type); + unsigned widen_precision = TYPE_PRECISION (TREE_TYPE (@2)); + wide_int max = wi::mask (precision, false, widen_precision); + wide_int c4 = wi::to_wide (@4); + } + (if (wi::eq_p (c4, max) && widen_precision > precision)))))) /* Saturation sub for unsigned integer. */ (if (INTEGRAL_TYPE_P (type) && TYPE_UNSIGNED (type)) diff --git a/gcc/optabs.cc b/gcc/optabs.cc index 0a14b1e..fe68a25 100644 --- a/gcc/optabs.cc +++ b/gcc/optabs.cc @@ -4304,9 +4304,6 @@ can_compare_p (enum rtx_code code, machine_mode mode, && (icode = optab_handler (cstore_optab, mode)) != CODE_FOR_nothing && insn_operand_matches (icode, 1, test)) return true; - if (purpose == ccp_cmov - && optab_handler (cmov_optab, mode) != CODE_FOR_nothing) - return true; mode = GET_MODE_WIDER_MODE (mode).else_void (); PUT_MODE (test, mode); diff --git a/gcc/optabs.def b/gcc/optabs.def index 23f7923..0c1435d 100644 --- a/gcc/optabs.def +++ b/gcc/optabs.def @@ -294,7 +294,6 @@ OPTAB_D (cond_len_fnms_optab, "cond_len_fnms$a") OPTAB_D (cond_len_neg_optab, "cond_len_neg$a") OPTAB_D (cond_len_one_cmpl_optab, "cond_len_one_cmpl$a") OPTAB_D (vcond_mask_len_optab, "vcond_mask_len_$a") -OPTAB_D (cmov_optab, "cmov$a6") OPTAB_D (cstore_optab, "cstore$a4") OPTAB_D (ctrap_optab, "ctrap$a4") OPTAB_D (addv4_optab, "addv$I$a4") diff --git a/gcc/optabs.h b/gcc/optabs.h index 23fa77b..ae525c8 100644 --- a/gcc/optabs.h +++ b/gcc/optabs.h @@ -244,11 +244,10 @@ extern void emit_unop_insn (enum insn_code, rtx, rtx, enum rtx_code); extern void emit_libcall_block (rtx_insn *, rtx, rtx, rtx); /* The various uses that a comparison can have; used by can_compare_p: - jumps, conditional moves, store flag operations. */ + jumps, store flag operations. */ enum can_compare_purpose { ccp_jump, - ccp_cmov, ccp_store_flag }; diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog index a9ed995..cfc235c 100644 --- a/gcc/po/ChangeLog +++ b/gcc/po/ChangeLog @@ -1,3 +1,7 @@ +2025-05-12 Joseph Myers <josmyers@redhat.com> + + * sv.po: Update. + 2025-04-30 Joseph Myers <josmyers@redhat.com> * be.po, da.po, de.po, el.po, es.po, fi.po, fr.po, hr.po, id.po, diff --git a/gcc/po/sv.po b/gcc/po/sv.po index 3296bed..31e5502 100644 --- a/gcc/po/sv.po +++ b/gcc/po/sv.po @@ -32,7 +32,7 @@ msgstr "" "Project-Id-Version: gcc 15.1.0\n" "Report-Msgid-Bugs-To: https://gcc.gnu.org/bugs/\n" "POT-Creation-Date: 2025-04-23 19:27+0000\n" -"PO-Revision-Date: 2025-04-28 09:09+0200\n" +"PO-Revision-Date: 2025-05-10 14:36+0200\n" "Last-Translator: Göran Uddeborg <goeran@uddeborg.se>\n" "Language-Team: Swedish <tp-sv@listor.tp-sv.se>\n" "Language: sv\n" @@ -75706,10 +75706,9 @@ msgid "Expected associate name at %C" msgstr "Ett associationsnamn förväntade vid %C" #: fortran/match.cc:1940 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Bad continuation line at %C" +#, gcc-internal-format, gfc-internal-format msgid "Bad bounds remapping list at %C" -msgstr "Felaktig fortsättningsrad vid %C" +msgstr "Felaktig litea på gränsavbildningar vid %C" #: fortran/match.cc:1946 #, gcc-internal-format, gfc-internal-format @@ -75747,10 +75746,9 @@ msgid "The associate name %s with an assumed rank target at %L must have a bound msgstr "Det associerade namnet %s med ett mål med antagen ordning vid %L måste ha en lista för omavbildning av gränser (lista av nedtregräns:övregräns för varje dimension)" #: fortran/match.cc:2018 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "The assumed-rank array at %C shall not have a codimension" +#, gcc-internal-format, gfc-internal-format msgid "The assumed rank target at %C must be contiguous" -msgstr "Vektorn med antagen ordning vid %C får inte ha en co-dimension" +msgstr "Målet med antagen ordning vid %C måste vara sammanhängande" #: fortran/match.cc:2037 #, gcc-internal-format @@ -75783,16 +75781,14 @@ msgid "DO CONCURRENT construct at %C" msgstr "DO CONCURRENT-konstruktion vid %C" #: fortran/match.cc:2826 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "selector %qs specified more than once in set %qs" +#, gcc-internal-format, gfc-internal-format msgid "DEFAULT (NONE) specified more than once in DO CONCURRENT at %C" -msgstr "väljaren %qs anges mer än en gång i mängden %qs" +msgstr "DEFAULT (NONE) anges mer än en gång i DO CONCURRENT vid %C" #: fortran/match.cc:2915 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Expected structure component name at %C" +#, gcc-internal-format, gfc-internal-format msgid "Expected reduction operator or function name at %C" -msgstr "Postkomponentnamn förväntades vid %C" +msgstr "En reduktionsoperator eller ett funktionsnamn förväntades vid %C" #: fortran/match.cc:2935 fortran/openmp.cc:2439 fortran/openmp.cc:2475 #: fortran/openmp.cc:2885 fortran/openmp.cc:2910 @@ -75801,28 +75797,24 @@ msgid "Expected %<:%> at %C" msgstr "%<:%> förväntades vid %C" #: fortran/match.cc:2945 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Expected variable name at %C" +#, gcc-internal-format, gfc-internal-format msgid "Expected variable name in reduction list at %C" -msgstr "Variabelnamn förväntades vid %C" +msgstr "Variabelnamn förväntades i reduktionslistan vid %C" #: fortran/match.cc:2964 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Expected association list at %C" +#, gcc-internal-format, gfc-internal-format msgid "Expected ',' or ')' in reduction list at %C" -msgstr "Associationslista förväntades vid %C" +msgstr "”,” eller ”)” förväntades i reduktionslistan vid %C" #: fortran/match.cc:2970 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "PROCEDURE list at %C" +#, gcc-internal-format, gfc-internal-format msgid "REDUCE locality spec at %L" -msgstr "PROCEDURE-lista vid %C" +msgstr "REDUCE-likalitestsspecifikation vid %L" #: fortran/match.cc:2977 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Invalid type-spec at %C" +#, gcc-internal-format, gfc-internal-format msgid "Locality spec at %L" -msgstr "Ogiltig typspecifikation vid %C" +msgstr "Lokalitetsspecifikation vid %L" #: fortran/match.cc:3112 #, gcc-internal-format @@ -76920,16 +76912,14 @@ msgid "Unexpected junk at %C" msgstr "Oväntad skräp vid %C" #: fortran/openmp.cc:464 -#, fuzzy, gcc-internal-format -#| msgid "%<omp_all_memory%> at %C not permitted in this clause" +#, gcc-internal-format msgid "%<omp_all_memory%> at %L not permitted in this clause" -msgstr "%<omp_all_memory%> vid %C är inte tillåtet i denna klausul" +msgstr "%<omp_all_memory%> vid %L är inte tillåtet i denna klausul" #: fortran/openmp.cc:509 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "List item shall not be coindexed at %C" +#, gcc-internal-format, gfc-internal-format msgid "List item shall not be coindexed at %L" -msgstr "Listobjektet skall inte vara co-indexerat vid %C" +msgstr "Listobjektet skall inte vara co-indexerat vid %L" #: fortran/openmp.cc:535 #, gcc-internal-format @@ -76937,10 +76927,9 @@ msgid "%qs at %L is part of the common block %</%s/%> and may only be specificed msgstr "%qs vid %L är del av common-blocket %</%s/%> och kan endast anges implicit via det namngivna common-blocket" #: fortran/openmp.cc:562 -#, fuzzy, gcc-internal-format -#| msgid "COMMON block /%s/ not found at %C" +#, gcc-internal-format msgid "COMMON block %</%s/%> not found at %L" -msgstr "COMMON-block /%s/ finns inte vid %C" +msgstr "COMMON-block %</%s/%> finns inte vid %L" #: fortran/openmp.cc:606 fortran/openmp.cc:696 #, gcc-internal-format, gfc-internal-format @@ -76958,10 +76947,9 @@ msgid "Syntax error in OpenMP detach clause at %C" msgstr "Syntaxfel i OpenMP-frånkopplingsklausul vid %C" #: fortran/openmp.cc:755 -#, fuzzy, gcc-internal-format -#| msgid "%<omp_all_memory%> used with dependence-type other than OUT or INOUT at %C" +#, gcc-internal-format msgid "%<omp_all_memory%> used with dependence-type other than OUT or INOUT at %L" -msgstr "%<omp_all_memory%> använt med en annan beroendetyp än OUT eller INOUT vid %C" +msgstr "%<omp_all_memory%> använt med en annan beroendetyp än OUT eller INOUT vid %L" #: fortran/openmp.cc:808 #, gcc-internal-format, gfc-internal-format @@ -76969,10 +76957,9 @@ msgid "Syntax error in OpenMP SINK dependence-type list at %C" msgstr "Syntaxfel i OpenMP DEPEND SINK beroendetyplista vid %C" #: fortran/openmp.cc:871 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Syntax error in OpenACC expression list at %C" +#, gcc-internal-format, gfc-internal-format msgid "Syntax error in OpenMP expression list at %C" -msgstr "Syntaxfel i OpenACC-uttryckslista vid %C" +msgstr "Syntaxfel i OpenMP-uttryckslista vid %C" #: fortran/openmp.cc:873 #, gcc-internal-format, gfc-internal-format @@ -77040,8 +77027,7 @@ msgid "Invalid combined or composite directive at %L" msgstr "Ogiltigt kombinerat eller sammansatt direktiv vid %L" #: fortran/openmp.cc:1644 -#, fuzzy, gcc-internal-format -#| msgid "Invalid %qs directive at %L in %s clause: declarative, informational and meta directives not permitted" +#, gcc-internal-format msgid "Invalid %qs directive at %L in %s clause: declarative, informational, and meta directives not permitted" msgstr "Felaktigt %qs-direktiv vid %L i %s-klausul: direktiven declarative, informational och meta är inte tillåtna" @@ -77073,52 +77059,44 @@ msgid "Unexpected %<(%> at %C" msgstr "Oväntat %<(%> vid %C" #: fortran/openmp.cc:1909 -#, fuzzy, gcc-internal-format -#| msgid "expected %<{%> at %C" +#, gcc-internal-format msgid "Expected %<{%> at %C" msgstr "%<{%> förväntades vid %C" #: fortran/openmp.cc:1919 -#, fuzzy, gcc-internal-format -#| msgid "expected trait selector name at %C" +#, gcc-internal-format msgid "Duplicated %<fr%> preference-selector-name at %C" -msgstr "trait-väljarnamn förväntades vid %C" +msgstr "Dubblerad %<fr%>-preferensväljarnamn vid %C" #: fortran/openmp.cc:1944 fortran/openmp.cc:2082 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "expected constant integer expression with valid sync-hint value" +#, gcc-internal-format, gfc-internal-format msgid "Expected constant scalar integer expression or non-empty default-kind character literal at %L" -msgstr "konstant heltalsuttryck med giltigt sync-hint-värde förväntades" +msgstr "Ett konstant skalärt heltalsuttryck eller en icke-tom standardsorts teckenliteral vid %L" #: fortran/openmp.cc:1958 fortran/openmp.cc:2095 -#, fuzzy, gcc-internal-format -#| msgid "Unknown procedure name %qs at %C" +#, gcc-internal-format msgid "Unknown foreign runtime identifier %qd at %L" -msgstr "Okänt procedurnamn %qs vid %C" +msgstr "Okänd främmande körtidsidentifierare %qd vid %L" #: fortran/openmp.cc:1972 fortran/openmp.cc:2107 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Unexpected character in variable list at %C" +#, gcc-internal-format, gfc-internal-format msgid "Unexpected null character in character literal at %L" -msgstr "Oväntat tecken i variabellista vid %C" +msgstr "Oväntat null-tecken i teckenliteralen vid %L" #: fortran/openmp.cc:1979 fortran/openmp.cc:2114 -#, fuzzy, gcc-internal-format -#| msgid "Unknown procedure name %qs at %C" +#, gcc-internal-format msgid "Unknown foreign runtime identifier %qs at %L" -msgstr "Okänt procedurnamn %qs vid %C" +msgstr "Okänd främmande körtidsidentifierare %qs vid %L" #: fortran/openmp.cc:1986 fortran/openmp.cc:7079 -#, fuzzy, gcc-internal-format -#| msgid "expected %<)%> at %C" +#, gcc-internal-format msgid "Expected %<)%> at %C" msgstr "%<)%> förväntades vid %C" #: fortran/openmp.cc:2002 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "expected identifier or string literal at %C" +#, gcc-internal-format, gfc-internal-format msgid "Expected default-kind character literal at %L" -msgstr "identifierare eller strängkonstant förväntades vid %C" +msgstr "En standardsorts teckenliteral förväntades vid %L" #: fortran/openmp.cc:2013 #, gcc-internal-format @@ -77126,64 +77104,54 @@ msgid "Character literal at %L must start with %<ompx_%>" msgstr "Teckenliteralen vid %L måste börja med %<ompx_%>" #: fortran/openmp.cc:2021 -#, fuzzy, gcc-internal-format -#| msgid "Unexpected character in variable list at %C" +#, gcc-internal-format msgid "Unexpected null or %<,%> character in character literal at %L" -msgstr "Oväntat tecken i variabellista vid %C" +msgstr "Oväntat null eller %<,%>-tecken i teckenliteralen vid %L" #: fortran/openmp.cc:2038 -#, fuzzy, gcc-internal-format -#| msgid "Expected %<)%> or %<,%> at %C" +#, gcc-internal-format msgid "Expected %<fr(%> or %<attr(%> at %C" -msgstr "%<)%> eller %<,%> förväntades vid %C" +msgstr "%<fr(%> eller %<attr(%> förväntades vid %C" #: fortran/openmp.cc:2045 -#, fuzzy, gcc-internal-format -#| msgid "Expected %<,%> or %<)%> at %C" +#, gcc-internal-format msgid "Expected %<,%> or %<}%> at %C" -msgstr "%<,%> eller %<)%> förväntades vid %C" +msgstr "%<,%> eller %<}%> förväntades vid %C" #: fortran/openmp.cc:2161 -#, fuzzy, gcc-internal-format -#| msgid "Duplicate access-specifier at %C" +#, gcc-internal-format msgid "Duplicate %<prefer_type%> modifier at %C" -msgstr "Dubblerad åtkomstspecifikation vid %C" +msgstr "Dubblerad modifierare %<prefer_type%> vid %C" #: fortran/openmp.cc:2173 fortran/openmp.cc:2209 fortran/openmp.cc:2231 -#, fuzzy, gcc-internal-format -#| msgid "Expected %<,%> or %<)%> at %C" +#, gcc-internal-format msgid "Expected %<,%> or %<:%> at %C" -msgstr "%<,%> eller %<)%> förväntades vid %C" +msgstr "%<,%> eller %<:%> förväntades vid %C" #: fortran/openmp.cc:2186 -#, fuzzy, gcc-internal-format -#| msgid "Expected %<(%> after %qs at %C" +#, gcc-internal-format msgid "Expected %<(%> after %<prefer_type%> at %C" -msgstr "%<(%> förväntades efter %qs vid %C" +msgstr "%<(%> förväntades efter %<prefer_type%> vid %C" #: fortran/openmp.cc:2194 -#, fuzzy, gcc-internal-format -#| msgid "expected %<match%> at %C" +#, gcc-internal-format msgid "Duplicate %<targetsync%> at %C" -msgstr "%<match%> förväntades vid %C" +msgstr "Dubblerat %<targetsync%> vid %C" #: fortran/openmp.cc:2216 -#, fuzzy, gcc-internal-format -#| msgid "Duplicate %s attribute at %L" +#, gcc-internal-format msgid "Duplicate %<target%> at %C" -msgstr "Dubblerat %s-attribut vid %L" +msgstr "Dubblerat %<target%> vid %C" #: fortran/openmp.cc:2234 -#, fuzzy, gcc-internal-format -#| msgid "Expected %<)%> or %<,%> at %C" +#, gcc-internal-format msgid "Expected %<prefer_type%>, %<target%>, or %<targetsync%> at %C" -msgstr "%<)%> eller %<,%> förväntades vid %C" +msgstr "%<prefer_type%> %<target%> eller %<targetsync%> förväntades vid %C" #: fortran/openmp.cc:2242 -#, fuzzy, gcc-internal-format -#| msgid "Expected %<)%> or %<,%> at %C" +#, gcc-internal-format msgid "Missing required %<target%> and/or %<targetsync%> modifier at %C" -msgstr "%<)%> eller %<,%> förväntades vid %C" +msgstr "Nödvändig modifierare %<target%> och/eller %<targetsync%> saknas vid %C" #: fortran/openmp.cc:2295 #, gcc-internal-format @@ -77361,10 +77329,9 @@ msgid "ORDERED clause argument not constant positive integer at %C" msgstr "ORDERED-klausulargument är inte ett konstant positivt heltal vid %C" #: fortran/openmp.cc:3912 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "ORDERED clause argument not constant positive integer at %C" +#, gcc-internal-format, gfc-internal-format msgid "PARTIAL clause argument not constant positive integer at %C" -msgstr "ORDERED-klausulargument är inte ett konstant positivt heltal vid %C" +msgstr "Klausulargumentet PARTIAL är inte ett konstant positivt heltal vid %C" #: fortran/openmp.cc:4194 #, gcc-internal-format, gfc-internal-format @@ -77715,28 +77682,24 @@ msgid "expected expression at %C" msgstr "uttryck förväntades vid %C" #: fortran/openmp.cc:6477 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "property must be a constant logical expression at %C" +#, gcc-internal-format, gfc-internal-format msgid "property must be a logical expression at %L" -msgstr "egenskapen måste vara ett konstant logiskt uttryck vid %C" +msgstr "egenskapen måste vara ett logiskt uttryck vid %L" #: fortran/openmp.cc:6481 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "property must be a constant integer expression at %C" +#, gcc-internal-format, gfc-internal-format msgid "property must be an integer expression at %L" -msgstr "egenskapen måste vara ett konstant heltalsuttryck vid %C" +msgstr "egenskapen måste vara ett heltalsuttryck vid %L" #: fortran/openmp.cc:6488 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "property must be a constant logical expression at %C" +#, gcc-internal-format, gfc-internal-format msgid "property must be a constant logical expression at %L" -msgstr "egenskapen måste vara ett konstant logiskt uttryck vid %C" +msgstr "egenskapen måste vara ett konstant logiskt uttryck vid %L" #: fortran/openmp.cc:6492 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "property must be a constant integer expression at %C" +#, gcc-internal-format, gfc-internal-format msgid "property must be a constant integer expression at %L" -msgstr "egenskapen måste vara ett konstant heltalsuttryck vid %C" +msgstr "egenskapen måste vara ett konstant heltalsuttryck vid %L" #: fortran/openmp.cc:6506 #, gcc-internal-format, gfc-internal-format @@ -77784,46 +77747,39 @@ msgid "%qs clause at %L specified more than once" msgstr "Klausulen %qs vid %L angiven mer än en gång" #: fortran/openmp.cc:6776 -#, fuzzy, gcc-internal-format -#| msgid "expected %<ancestor%> or %<device_num%>" +#, gcc-internal-format msgid "expected %<nothing%>, %<need_device_ptr%> or %<need_device_addr%> at %C" -msgstr "%<ancestor%> eller %<device_num%> förväntades" +msgstr "%<nothing%>, %<need_device_ptr%> eller %<need_device_addr%> förväntades vid %C" #: fortran/openmp.cc:6782 fortran/openmp.cc:6900 fortran/openmp.cc:7055 -#, fuzzy, gcc-internal-format -#| msgid "Expected %<:%> at %C" +#, gcc-internal-format msgid "expected %<:%> at %C" msgstr "%<:%> förväntades vid %C" #: fortran/openmp.cc:6815 -#, fuzzy, gcc-internal-format -#| msgid "Expected %<:%> at %C" +#, gcc-internal-format msgid "unexpected %<:%> at %C" -msgstr "%<:%> förväntades vid %C" +msgstr "Oväntat %<:%> vid %C" #: fortran/openmp.cc:6862 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Expected integer expression at %C" +#, gcc-internal-format, gfc-internal-format msgid "expected constant integer expression at %C" -msgstr "Heltalsuttryck förväntades vid %C" +msgstr "ett konstant heltalsuttryck förväntades vid %C" #: fortran/openmp.cc:6884 -#, fuzzy, gcc-internal-format -#| msgid "ORDERED clause argument not constant positive integer at %C" +#, gcc-internal-format msgid "expected dummy parameter name, %<omp_num_args%> or constant positive integer at %C" -msgstr "ORDERED-klausulargument är inte ett konstant positivt heltal vid %C" +msgstr "ett attrapparameternamn, %<omp_num_args%> eller konstant positivt heltal förväntades vid %C" #: fortran/openmp.cc:6931 -#, fuzzy, gcc-internal-format -#| msgid "expected %<)%> at %C" +#, gcc-internal-format msgid "expected %<interop%> at %C" -msgstr "%<)%> förväntades vid %C" +msgstr "%<interop%> förväntades vid %C" #: fortran/openmp.cc:6981 -#, fuzzy, gcc-internal-format -#| msgid "expected %<at%>, %<severity%> or %<message%> clause" +#, gcc-internal-format msgid "expected %<match%>, %<adjust_args%> or %<append_args%> at %C" -msgstr "%<at%>-, %<severity%>- eller %<message%>-klausul förväntades" +msgstr "%<match%>-, %<adust_args%> eller %<append_args%> förväntades vid %C" #: fortran/openmp.cc:6987 #, gcc-internal-format @@ -77831,10 +77787,9 @@ msgid "the %qs clause at %L can only be specified if the %<dispatch%> selector o msgstr "klausulen %s vid %L kan endast anges om väljaren %<dispatch%> i konstruktionsväljarmängden förekommer i klausulen %<match%>" #: fortran/openmp.cc:7027 -#, fuzzy, gcc-internal-format -#| msgid "expected %<host%>, %<nohost%> or %<any%>" +#, gcc-internal-format msgid "expected %<when%>, %<otherwise%>, or %<default%> at %C" -msgstr "%<host%>, %<nohost%> eller %<any%> förväntades" +msgstr "%<when%>, %<otherwise%> eller %<default%> förväntades vid %C" #: fortran/openmp.cc:7034 #, gcc-internal-format @@ -77847,10 +77802,9 @@ msgid "%<otherwise%> or %<default%> clause must appear last in %<metadirective%> msgstr "en klausul %<otherwise%> eller %<default%> måste ligga sist i %<metadirective%> vid %C" #: fortran/openmp.cc:7069 -#, fuzzy, gcc-internal-format -#| msgid "destructor priorities are not supported" +#, gcc-internal-format msgid "declarative directive variants are not supported" -msgstr "destruerarprioriteter stödjs ej" +msgstr "deklarativa direktivvarianter stödjs ej" #: fortran/openmp.cc:7090 #, gcc-internal-format, gfc-internal-format @@ -77858,10 +77812,9 @@ msgid "variant directive used in OMP BEGIN METADIRECTIVE at %C must have a corre msgstr "variantdirektivet som används i OMP BEGIN METADIRECTIVE vid %C måste ha ett mostsvarande slutdirektiv" #: fortran/openmp.cc:7124 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Unexpected junk after OMP THREADPRIVATE at %C" +#, gcc-internal-format, gfc-internal-format msgid "Unexpected junk after OMP METADIRECTIVE at %C" -msgstr "Oväntat skräp efter OMP THREADPRIVATE vid %C" +msgstr "Oväntat skräp efter OMP METADIRECTIVE vid %C" #: fortran/openmp.cc:7183 #, gcc-internal-format, gfc-internal-format @@ -77879,10 +77832,9 @@ msgid "Syntax error in !$OMP THREADPRIVATE list at %C" msgstr "Syntaxfel i !$OMP THREADPRIVATE-lista vid %C" #: fortran/openmp.cc:7326 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Program unit at %L has OpenMP device constructs/routines but does not set !$OMP REQUIRES REVERSE_OFFLOAD but other program units do" +#, gcc-internal-format, gfc-internal-format msgid "Program unit at %L has OpenMP device constructs/routines but does not set !$OMP REQUIRES %s but other program units do" -msgstr "Programenheten vid %L har OpenMP device-konstruktioner/-rutiner men sätter inte !$OMP REQUIRES REVERSE_OFFLOAD men andra programenheter gör det" +msgstr "Programenheten vid %L har OpenMP device-konstruktioner/-rutiner men sätter inte !$OMP REQUIRES %s men andra programenheter gör det" #: fortran/openmp.cc:7369 #, gcc-internal-format @@ -77930,10 +77882,9 @@ msgid "Clause expected at %C" msgstr "Klausul förväntades vid %C" #: fortran/openmp.cc:7557 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Expected UNIFIED_ADDRESS, UNIFIED_SHARED_MEMORY, DYNAMIC_ALLOCATORS, REVERSE_OFFLOAD, or ATOMIC_DEFAULT_MEM_ORDER clause at %L" +#, gcc-internal-format, gfc-internal-format msgid "Expected UNIFIED_ADDRESS, UNIFIED_SHARED_MEMORY, SELF_MAPS, DYNAMIC_ALLOCATORS, REVERSE_OFFLOAD, or ATOMIC_DEFAULT_MEM_ORDER clause at %L" -msgstr "UNIFIED_ADDRESS-, UNIFIED_SHARED_MEMORY-, DYNAMIC_ALLOCATORS-, REVERSE_OFFLOAD- eller ATOMIC_DEFAULT_MEM_ORDER-klausul förväntades vid %L" +msgstr "UNIFIED_ADDRESS-, UNIFIED_SHARED_MEMORY-, SELF_MAPS-, DYNAMIC_ALLOCATORS-, REVERSE_OFFLOAD- eller ATOMIC_DEFAULT_MEM_ORDER-klausul förväntades vid %L" #: fortran/openmp.cc:7583 #, gcc-internal-format, gfc-internal-format @@ -78192,8 +78143,7 @@ msgstr "ORDERED-klausulparameter är mindre än COLLAPSE vid %L" # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107122 #: fortran/openmp.cc:8623 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "ORDER clause must not be used together ORDERED at %L" +#, gcc-internal-format, gfc-internal-format msgid "ORDER clause must not be used together with ORDERED at %L" msgstr "en ORDER-klausul får inte användas tillsammans med ORDERED vid %L" @@ -78224,16 +78174,14 @@ msgid "FINAL clause at %L requires a scalar LOGICAL expression" msgstr "FINAL-klausul vid %L kräver ett skalärt LOGICAL-uttryck" #: fortran/openmp.cc:8798 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "IF clause at %L requires a scalar LOGICAL expression" +#, gcc-internal-format, gfc-internal-format msgid "NOVARIANTS clause at %L requires a scalar LOGICAL expression" -msgstr "IF-klausul vid %L kräver ett skalärt LOGICAL-uttryck" +msgstr "NOVARIANTS-klausul vid %L kräver ett skalärt LOGICAL-uttryck" #: fortran/openmp.cc:8808 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "SELF clause at %L requires a scalar LOGICAL expression" +#, gcc-internal-format, gfc-internal-format msgid "NOCONTEXT clause at %L requires a scalar LOGICAL expression" -msgstr "SELF-klausulen vid %L kräver ett skalärt LOGICAL-uttryck" +msgstr "NOCONTEXT-klausulen vid %L kräver ett skalärt LOGICAL-uttryck" #: fortran/openmp.cc:8819 #, gcc-internal-format, gfc-internal-format @@ -78319,16 +78267,14 @@ msgid "DEPEND clause at %L requires %<targetsync%> interop-type, lacking it for msgstr "Klausulen DEPEND vid %L behöver interop-typen %<targetsync%>, den saknas för %qs vid %L" #: fortran/openmp.cc:9044 -#, fuzzy, gcc-internal-format -#| msgid "Allocator %qs at %L in USES_ALLOCATORS must be a scalar integer of kind %<omp_allocator_handle_kind%>" +#, gcc-internal-format msgid "%qs at %L in %qs clause must be a scalar integer variable of %<omp_interop_kind%> kind" -msgstr "Allokeraren %qs vid %L i USES_ALLOCATORS måste vara ett skalärt heltal av ssorten %<omp_allocator_handle_kind%>" +msgstr "%qs vid %L i klausulen %qs måste vara en skalär heltalsvariabel av sorten %<omp_interop_kind%>" #: fortran/openmp.cc:9049 -#, fuzzy, gcc-internal-format -#| msgid "%qs and %qs cannot both be enabled" +#, gcc-internal-format msgid "%qs at %L in %qs clause must be definable" -msgstr "%qs och %qs kan inte båda aktiveras" +msgstr "%qs vid %L i klausulen %qs måste vara definierbar" #: fortran/openmp.cc:9088 #, gcc-internal-format @@ -78560,7 +78506,7 @@ msgstr "Memspace %qs vid %L i USES_ALLOCATORS måste vara ett fördefinierat min #: fortran/openmp.cc:9878 #, gcc-internal-format msgid "Allocator %qs at %L in USES_ALLOCATORS must be a scalar integer of kind %<omp_allocator_handle_kind%>" -msgstr "Allokeraren %qs vid %L i USES_ALLOCATORS måste vara ett skalärt heltal av ssorten %<omp_allocator_handle_kind%>" +msgstr "Allokeraren %qs vid %L i USES_ALLOCATORS måste vara ett skalärt heltal av sorten %<omp_allocator_handle_kind%>" #: fortran/openmp.cc:9886 #, gcc-internal-format @@ -78614,16 +78560,14 @@ msgid "DETACH event handle %qs in %s clause at %L" msgstr "DETACH-händelsehandtag %qs i %s-klausul vid %L" #: fortran/openmp.cc:10016 -#, fuzzy, gcc-internal-format -#| msgid "List item %qs with allocatable components is not permitted in map clause at %L" +#, gcc-internal-format msgid "Sorry, list item %qs at %L with allocatable components is not yet supported in %s clause" -msgstr "Listposten %qs med allokerbara komponenter är inte tillåtet i map-klausulen vid %L" +msgstr "Ledsen, listposten %qs vid %L med allokerbara komponenter stödjs inte ännu i klausulen %s" #: fortran/openmp.cc:10022 -#, fuzzy, gcc-internal-format -#| msgid "comparison with string literal results in unspecified behavior" +#, gcc-internal-format msgid "Polymorphic list item %qs at %L in %s clause has unspecified behavior and unsupported" -msgstr "jämförelse med stränglitteral resulterar i odefinierat beteende" +msgstr "Det polymorfa listelementet %qs vid %L i klausulen %s har i odefinierat beteende och stödjs ej" #: fortran/openmp.cc:10054 #, gcc-internal-format, gfc-internal-format @@ -78686,22 +78630,19 @@ msgid "DIST_SCHEDULE clause's chunk_size at %L requires a scalar INTEGER express msgstr "DIST_SCHEDULE-klausulens chunk_size vid %L kräver ett skalärt INTEGER-uttryck" #: fortran/openmp.cc:10349 -#, fuzzy, gcc-internal-format -#| msgid "%<DETACH%> clause at %L must not be used together with %<MERGEABLE%> clause" +#, gcc-internal-format msgid "%<GRAINSIZE%> clause at %L must not be used together with %<NUM_TASKS%> clause" -msgstr "en %<DETACH%>-klausul vid %L får inte användas tillsammans med en %<MERGEABLE%>-klausul" +msgstr "en %<GRAINSIZE%>-klausul vid %L får inte användas tillsammans med en %<NUM_TASKS%>-klausul" #: fortran/openmp.cc:10352 -#, fuzzy, gcc-internal-format -#| msgid "%<DETACH%> clause at %L must not be used together with %<MERGEABLE%> clause" +#, gcc-internal-format msgid "%<REDUCTION%> clause at %L must not be used together with %<NOGROUP%> clause" -msgstr "en %<DETACH%>-klausul vid %L får inte användas tillsammans med en %<MERGEABLE%>-klausul" +msgstr "en %<REDUCTION%>-klausul vid %L får inte användas tillsammans med en %<NOGROUP%>-klausul" #: fortran/openmp.cc:10356 -#, fuzzy, gcc-internal-format -#| msgid "%<DETACH%> clause at %L must not be used together with %<MERGEABLE%> clause" +#, gcc-internal-format msgid "%<FULL%> clause at %C must not be used together with %<PARTIAL%> clause" -msgstr "en %<DETACH%>-klausul vid %L får inte användas tillsammans med en %<MERGEABLE%>-klausul" +msgstr "en %<FULL%>-klausul vid %C får inte användas tillsammans med en %<PARTIAL%>-klausul" #: fortran/openmp.cc:10379 #, gcc-internal-format, gfc-internal-format @@ -78719,10 +78660,9 @@ msgid "%s must contain at least one MAP clause at %L" msgstr "%s måste innehålla åtminstone en MAP-klausul vid %L" #: fortran/openmp.cc:10416 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "TILE requires constant expression at %L" +#, gcc-internal-format, gfc-internal-format msgid "SIZES requires constant expression at %L" -msgstr "TILE behöver ett konstant uttryck vid %L" +msgstr "SIZES behöver ett konstant uttryck vid %L" #: fortran/openmp.cc:10432 #, gcc-internal-format @@ -78825,8 +78765,7 @@ msgid "expr in !$OMP ATOMIC COMPARE assignment var = expr must be scalar and can msgstr "uttr i !$OMP ATOMIC COMPARE-tilldelning var = uttr måste vara skalär och får inte referera var vid %L" #: fortran/openmp.cc:10858 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "!$OMP ATOMIC UPDATE at %L with FAIL clause requiries either the COMPARE clause or using the intrinsic MIN/MAX procedure" +#, gcc-internal-format, gfc-internal-format msgid "!$OMP ATOMIC UPDATE at %L with FAIL clause requires either the COMPARE clause or using the intrinsic MIN/MAX procedure" msgstr "!$OMP ATOMIC UPDATE vid %L med en FAIL-klausul behöver antingen klausulen COMPARE eller användning av den inbyggda proceduren MIN/MAX" @@ -78916,10 +78855,9 @@ msgid "%s cannot contain OpenMP API call in intervening code at %L" msgstr "%s kan inte innehålla OpenMP-API-anrop i mellanliggande kod vid %L" #: fortran/openmp.cc:12052 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "LINEAR clause modifier used on DO or SIMD construct at %L" +#, gcc-internal-format, gfc-internal-format msgid "SIZES clause is required on !$OMP TILE construct at %L" -msgstr "LINEAR-klausulmodifierare använd på DO- eller SIMD-konstruktion vid %L" +msgstr "en klausul SIZES krävs på konstruktionen !$OMP TILE vid %L" #: fortran/openmp.cc:12079 #, gcc-internal-format, gfc-internal-format @@ -79038,10 +78976,9 @@ msgid "%s inner loops must be perfectly nested with REDUCTION INSCAN clause at % msgstr "%s intre slingor måste vara perfekt nästade med en REDUCTION INSCAN-klausul vid %L" #: fortran/openmp.cc:12284 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "%s inner loops must be perfectly nested with ORDERED clause at %L" +#, gcc-internal-format, gfc-internal-format msgid "%s inner loops must be perfectly nested at %L" -msgstr "%s inre slingor måste vara perfekt nästade med klausulen ORDERED vid %L" +msgstr "%s inre slingor måste vara perfekt nästade vid %L" #: fortran/openmp.cc:12538 fortran/openmp.cc:12551 #, gcc-internal-format, gfc-internal-format @@ -79144,10 +79081,9 @@ msgid "!$OMP DECLARE SIMD should refer to containing procedure %qs at %L" msgstr "!$OMP DECLARE SIMD skall referera till den inneslutande proceduren %qs vid %L" #: fortran/openmp.cc:13115 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "expected constant logical expression" +#, gcc-internal-format, gfc-internal-format msgid "Expected constant non-negative scalar integer offset expression at %L" -msgstr "ett konstant logiskt uttryck förväntades" +msgstr "Ett konstant icke-negativt skalärt heltalsavståndsuttryck förväntades vid %L" #: fortran/openmp.cc:13118 #, gcc-internal-format @@ -79155,10 +79091,9 @@ msgid "For range-based %<adjust_args%>, a constant positive scalar integer expre msgstr "För intervallbaserat %<adjust_args%> krävs ett konstant positivt skalärt heltalsuttryck vid %L" #: fortran/openmp.cc:13132 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Unexpected character in variable list at %C" +#, gcc-internal-format, gfc-internal-format msgid "Expected dummy parameter name or a positive integer at %L" -msgstr "Oväntat tecken i variabellista vid %C" +msgstr "Ett attrapparameternamn eller ettt positivt heltal förväntades vid %L" #: fortran/openmp.cc:13158 #, gcc-internal-format, gfc-internal-format @@ -79301,10 +79236,9 @@ msgid "The value of n in %<-finit-character=n%> must be between 0 and 127" msgstr "Värdet på n i %<-finit-character=n%> måste vara mellan 0 och 127" #: fortran/options.cc:889 -#, fuzzy, gcc-internal-format -#| msgid "command-line option %qs is valid for %s but not for %s" +#, gcc-internal-format msgid "command-line option %<-fno-builtin-%s%> is not valid for Fortran" -msgstr "kommandoradsflaggan %qs är giltig för %s men inte för %s" +msgstr "kommandoradsflaggan %<-fno-builtin-%s%> är inte giltig för Fortran" #: fortran/parse.cc:665 #, gcc-internal-format, gfc-internal-format @@ -79740,10 +79674,9 @@ msgstr "Namngivet DO-block vid %L kräver matchande ENDDO-namn" #. "begin metadirective" construct, or perhaps the #. "end metadirective" is missing entirely. #: fortran/parse.cc:5817 fortran/parse.cc:6314 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Unexpected junk after OMP THREADPRIVATE at %C" +#, gcc-internal-format, gfc-internal-format msgid "Expected OMP END METADIRECTIVE at %C" -msgstr "Oväntat skräp efter OMP THREADPRIVATE vid %C" +msgstr "OMP END METADIRECTIVE förväntades vid %C" #: fortran/parse.cc:5827 fortran/parse.cc:6330 fortran/parse.cc:6348 #, gcc-internal-format, gfc-internal-format @@ -79796,16 +79729,14 @@ msgid "%<OMP DISPATCH%> directive must be followed by a procedure call with opti msgstr "Direktivet %<OMP DISPATCH%> måste följas av ett proceduranrop med en möjlig tilldelning vid %C" #: fortran/parse.cc:6416 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Duplicated NOWAIT clause on %s and %s at %C" +#, gcc-internal-format, gfc-internal-format msgid "Duplicated NOWAIT clause on !$OMP DISPATCH and !$OMP END DISPATCH at %C" -msgstr "Dubblerad NOWAIT-klausul på %s och %s vid %C" +msgstr "Dubblerad NOWAIT-klausul på !$OMP DISPATCH och !$OMP END DISPATCH vid %C" #: fortran/parse.cc:6488 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Unexpected %s statement in WHERE block at %C" +#, gcc-internal-format, gfc-internal-format msgid "Unexpected %s statement in OMP METADIRECTIVE block at %C" -msgstr "Oväntad %s-sats i WHERE-block vid %C" +msgstr "Oväntad %s-sats i blocket OMP METADIRECTIVE vid %C" #: fortran/parse.cc:6529 #, gcc-internal-format, gfc-internal-format @@ -79931,10 +79862,9 @@ msgid "Integer too big for its kind at %C. This check can be disabled with the o msgstr "Heltal för stort för sin sort vid %C. Denna kontroll kan avaktiveras med flaggan %<-fno-range-check%>" #: fortran/primary.cc:388 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Integer kind %d at %C not available" +#, gcc-internal-format, gfc-internal-format msgid "Unsigned kind %d at %C not available" -msgstr "Heltalssort %d vid %C inte tillgänglig" +msgstr "Teckenlös sort %d vid %C inte tillgänglig" #: fortran/primary.cc:419 #, gcc-internal-format, gfc-internal-format @@ -80210,10 +80140,9 @@ msgid "Procedure pointer component %qs requires an argument list at %C" msgstr "Procedurpekarkomponent %qs kräver en argumentlista vid %C" #: fortran/primary.cc:2833 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Expected array subscript stride at %C" +#, gcc-internal-format, gfc-internal-format msgid "Unexpected array/substring ref at %C" -msgstr "Förväntade intervall av vektorindex vid %C" +msgstr "Oväntad vektor-/delsträngs-ref vid %C" #: fortran/primary.cc:2855 #, gcc-internal-format, gfc-internal-format @@ -80707,10 +80636,9 @@ msgid "The element in the structure constructor at %L, for pointer component %qs msgstr "Elementet i postkonstrueraren vid %L, för pekarkomponent %qs, borde vara en POINTER eller en TARGET" #: fortran/resolve.cc:1589 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Pointer assignment with vector subscript on rhs at %L" +#, gcc-internal-format, gfc-internal-format msgid "Pointer assignment target at %L has a vector subscript" -msgstr "Pekartilldelning med vektorindexering på högersidan vid %L" +msgstr "Pekartilldelningsmålet vid %L har en vektorindexering" #: fortran/resolve.cc:1601 #, gcc-internal-format @@ -80753,8 +80681,7 @@ msgid "The intrinsic %qs declared INTRINSIC at %L is not available in the curren msgstr "Den inbyggda %qs deklarerad INTRINSIC vid %L är inte tillgänglig i den aktuella standardinställningen utan i %s. Använd en lämplig flagga %<-std=*%> eller aktivera %<-fall-intrinsics%> för att använda den." #: fortran/resolve.cc:1989 -#, fuzzy, gcc-internal-format -#| msgid "Non-RECURSIVE procedure %qs from module %qs is possibly calling itself recursively in procedure %qs. Declare it RECURSIVE or use %<-frecursive%>" +#, gcc-internal-format msgid "Non-RECURSIVE procedure %qs from module %qs is possibly calling itself recursively in procedure %qs. Declare it RECURSIVE or use %<-frecursive%>" msgstr "Icke RECURSIVE procedur %qs från modulen %qs anropar kanske sig själv rekursivt i proceduren %qs. Deklarera den RECURSIVE eller använd %<-frecursive%>" @@ -80889,10 +80816,9 @@ msgid "Function %qs at %L has no IMPLICIT type" msgstr "Funktionen %qs vid %L har ingen IMPLICIT-typ" #: fortran/resolve.cc:3283 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Reference to impure function %qs at %L inside a DO CONCURRENT %s" +#, gcc-internal-format, gfc-internal-format msgid "Reference to impure function at %L inside a DO CONCURRENT" -msgstr "Referens till den orena funktionen %qs vid %L är inuti ett DO CONCURRENT-%s" +msgstr "Referens till en oren funktion vid %L inuti ett DO CONCURRENT" #: fortran/resolve.cc:3294 #, gcc-internal-format @@ -80936,10 +80862,9 @@ msgid "Function %qs is declared CHARACTER(*) and cannot be used at %L since it i msgstr "Funktionen %qs är deklarerad CHARACTER(*) och får inte användas vid %L eftersom det inte är ett attrappargument" #: fortran/resolve.cc:3470 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Missing argument list in function %qs at %C" +#, gcc-internal-format, gfc-internal-format msgid "Different argument lists in external dummy function %s at %L and %L" -msgstr "Argumentlista saknas i funktionen %qs vid %C" +msgstr "Olika argumentlistor i den externa atrappfunktionen %s vid %L och %L" #: fortran/resolve.cc:3509 #, gcc-internal-format @@ -80972,10 +80897,9 @@ msgid "Using function %qs at %L is deprecated" msgstr "Att använda funktionen %qs vid %L bör undvikas" #: fortran/resolve.cc:3701 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Subroutine call to %qs in DO CONCURRENT block at %L is not PURE" +#, gcc-internal-format, gfc-internal-format msgid "Subroutine call at %L in a DO CONCURRENT block is not PURE" -msgstr "Subrutinanrop till %qs i DO CONCURRENT-block vid %L är inte PURE" +msgstr "Subrutinanrop vid %L i ett block DO CONCURRENT är inte PURE" #: fortran/resolve.cc:3710 #, gcc-internal-format @@ -81068,10 +80992,9 @@ msgid "BOZ literal constant at %L cannot be an operand of unary operator %qs" msgstr "BOZ-litteralkonstanten vid %L får inte vara en operand till den unära operatorn %qs" #: fortran/resolve.cc:4368 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "comparison of unsigned expression in %<>= 0%> is always true" +#, gcc-internal-format, gfc-internal-format msgid "Negation of unsigned expression at %L not permitted " -msgstr "jämförelse med unsigned-uttryck %<>= 0%> är alltid sant" +msgstr "Negation av ett teckenlöst uttryck vid %L är inte tillåtet " #: fortran/resolve.cc:4389 #, gcc-internal-format @@ -81079,52 +81002,44 @@ msgid "Operands at %L and %L cannot appear as operands of binary operator %qs" msgstr "Operander vid %L och %L kan inte förekomma som operander av den binära operatorn %qs" #: fortran/resolve.cc:4399 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Invalid context for NULL() pointer at %%L" +#, gcc-internal-format, gfc-internal-format msgid "Invalid context for NULL() pointer at %L" -msgstr "Ogiltigt sammanhang för NULL()-pekare vid %%L" +msgstr "Ogiltigt sammanhang för NULL()-pekare vid %L" #: fortran/resolve.cc:4417 -#, fuzzy, gcc-internal-format -#| msgid "Operand of unary numeric operator %%<%s%%> at %%L is %s" +#, gcc-internal-format msgid "Operand of unary numeric operator %qs at %L is %s" -msgstr "Operand till unär numerisk operator %%<%s%%> vid %%L är %s" +msgstr "Operand till unär numerisk operator %qs vid %L är %s" #: fortran/resolve.cc:4432 fortran/resolve.cc:4466 -#, fuzzy, gcc-internal-format -#| msgid "Operands of binary numeric operator %%<%s%%> at %%L are %s/%s" +#, gcc-internal-format msgid "Operands of binary numeric operator %qs at %L are %s/%s" -msgstr "Operander till binär numerisk operator %%<%s%%> vid %%L är %s/%s" +msgstr "Operander till binär numerisk operator %qs vid %L är %s/%s" #: fortran/resolve.cc:4446 fortran/resolve.cc:4635 fortran/resolve.cc:4804 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Inconsistent ranks for operator at %%L and %%L" +#, gcc-internal-format, gfc-internal-format msgid "Inconsistent ranks for operator at %L and %L" -msgstr "Inkonsistenta ordningar för operator vid %%L och %%L" +msgstr "Inkonsistenta ordningar för operator vid %L och %L" #: fortran/resolve.cc:4458 -#, fuzzy, gcc-internal-format -#| msgid "Unexpected derived-type entities in binary intrinsic numeric operator %%<%s%%> at %%L" +#, gcc-internal-format msgid "Unexpected derived-type entities in binary intrinsic numeric operator %qs at %L" -msgstr "Oväntade entiteter av härledd typ i binär inbyggd numerisk operator %%<%s%%> vid %%L" +msgstr "Oväntade entiteter av härledd typ i binär inbyggd numerisk operator %qs vid %L" #: fortran/resolve.cc:4482 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Operands of string concatenation operator at %%L are %s/%s" +#, gcc-internal-format, gfc-internal-format msgid "Operands of string concatenation operator at %L are %s/%s" -msgstr "Operanderna till strängkonkateneringsoperatorn vid %%L är %s/%s" +msgstr "Operanderna till strängkonkateneringsoperatorn vid %L är %s/%s" #: fortran/resolve.cc:4525 -#, fuzzy, gcc-internal-format -#| msgid "Operands of logical operator %%<%s%%> at %%L are %s/%s" +#, gcc-internal-format msgid "Operands of logical operator %qs at %L are %s/%s" -msgstr "Operanderna till logiska operatorn %%<%s%%> vid %%L är %s/%s" +msgstr "Operanderna till logiska operatorn %qs vid %L är %s/%s" #: fortran/resolve.cc:4548 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Operand of .not. operator at %%L is %s" +#, gcc-internal-format, gfc-internal-format msgid "Operand of .not. operator at %L is %s" -msgstr "Operand till operatorn .not. vid %%L är %s" +msgstr "Operand till operatorn .not. vid %L är %s" #: fortran/resolve.cc:4563 #, gcc-internal-format, gfc-internal-format @@ -81137,10 +81052,9 @@ msgid "BOZ literal constant near %L cannot appear as an operand of a relational msgstr "BOZ-litteralkonstanten nära %L får inte förekomma som en operand till en relationsoperator" #: fortran/resolve.cc:4643 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Inconsistent ranks for operator at %%L and %%L" +#, gcc-internal-format, gfc-internal-format msgid "Inconsistent types for operator at %L and %L: %s and %s" -msgstr "Inkonsistenta ordningar för operator vid %%L och %%L" +msgstr "Inkonsistenta typer för operatorn vid %L och %L: %s och %s" #: fortran/resolve.cc:4667 #, gcc-internal-format, gfc-internal-format @@ -81153,40 +81067,34 @@ msgid "Inequality comparison for %s at %L" msgstr "Olikhetsjämförelse av %s vid %L" #: fortran/resolve.cc:4682 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Logicals at %%L must be compared with %s instead of %s" +#, gcc-internal-format, gfc-internal-format msgid "Logicals at %L must be compared with %s instead of %s" -msgstr "Logiska vid %%L måste jämföras med %s istället för %s" +msgstr "Logiska vid %L måste jämföras med %s istället för %s" #: fortran/resolve.cc:4690 -#, fuzzy, gcc-internal-format -#| msgid "Operands of comparison operator %%<%s%%> at %%L are %s/%s" +#, gcc-internal-format msgid "Operands of comparison operator %qs at %L are %s/%s" -msgstr "Operanderna till jämförelseoperatorn %%<%s%%> vid %%L är %s/%s" +msgstr "Operanderna till jämförelseoperatorn %qs vid %L är %s/%s" #: fortran/resolve.cc:4705 -#, fuzzy, gcc-internal-format -#| msgid "Unknown operator %%<%s%%> at %%L; did you mean %%<%s%%>?" +#, gcc-internal-format msgid "Unknown operator %qs at %L; did you mean %qs?" -msgstr "Okänd operator %%<%s%%> vid %%L; menade du %%<%s%%>?" +msgstr "Okänd operator %qs vid %L; menade du %qs?" #: fortran/resolve.cc:4708 -#, fuzzy, gcc-internal-format -#| msgid "Unknown operator %%<%s%%> at %%L" +#, gcc-internal-format msgid "Unknown operator %qs at %L" -msgstr "Okänd operator %%<%s%%> vid %%L" +msgstr "Okänd operator %qs vid %L" #: fortran/resolve.cc:4713 -#, fuzzy, gcc-internal-format -#| msgid "Operand of user operator %%<%s%%> at %%L is %s" +#, gcc-internal-format msgid "Operand of user operator %qs at %L is %s" -msgstr "Operanderna till användaroperatorn %%<%s%%> vid %%L är %s" +msgstr "Operanderna till användaroperatorn %qs vid %L är %s" #: fortran/resolve.cc:4720 -#, fuzzy, gcc-internal-format -#| msgid "Operands of user operator %%<%s%%> at %%L are %s/%s" +#, gcc-internal-format msgid "Operands of user operator %qs at %L are %s/%s" -msgstr "Operanderna till användaroperatorn %%<%s%%> vid %%L är %s/%s" +msgstr "Operanderna till användaroperatorn %qs vid %L är %s/%s" #: fortran/resolve.cc:4734 #, gcc-internal-format @@ -81194,10 +81102,9 @@ msgid "resolve_operator(): Bad intrinsic" msgstr "resolve_operator(): Felaktig inbyggd" #: fortran/resolve.cc:4832 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Inconsistent ranks for operator at %%L and %%L" +#, gcc-internal-format, gfc-internal-format msgid "Inconsistent coranks for operator at %L and %L" -msgstr "Inkonsistenta ordningar för operator vid %%L och %%L" +msgstr "Inkonsistenta co-ordningar för operator vid %L och %L" #: fortran/resolve.cc:5031 #, gcc-internal-format, gfc-internal-format @@ -81315,45 +81222,39 @@ msgid "Array index at %L is an array of rank %d" msgstr "Vektorindex vid %L är en vektor med ordning %d" #: fortran/resolve.cc:5506 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Argument dim at %L must be scalar" +#, gcc-internal-format, gfc-internal-format msgid "TEAM_NUMBER argument at %L must be scalar" -msgstr "Dim-argumentet vid %L måste vara skalärt" +msgstr "Argumentet till TEAM_NUMBER vid %L måste vara skalärt" #: fortran/resolve.cc:5513 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Expression at %L must be of INTEGER type, found %s" +#, gcc-internal-format, gfc-internal-format msgid "TEAM_NUMBER argument at %L must be of INTEGER type, found %s" -msgstr "Uttryck vid %L måste vara av INTEGER-typ, hittade %s" +msgstr "Argumentet till TEAM_NUMBER vid %L måste vara av INTEGER-typ, hittade %s" #: fortran/resolve.cc:5527 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Argument dim at %L must be scalar" +#, gcc-internal-format, gfc-internal-format msgid "TEAM argument at %L must be scalar" -msgstr "Dim-argumentet vid %L måste vara skalärt" +msgstr "Argumentet till TEAM vid %L måste vara skalärt" #: fortran/resolve.cc:5536 #, gcc-internal-format, gfc-internal-format msgid "TEAM argument at %L must be of TEAM_TYPE from the intrinsic module ISO_FORTRAN_ENV, found %s" -msgstr "Artument till TEAM vid %L master vara av TEAM_TYPE från den inbyggda modulen ISO_FORTRAN_ENV, fick %s" +msgstr "Argumentet till TEAM vid %L måste vara av TEAM_TYPE från den inbyggda modulen ISO_FORTRAN_ENV, hittade %s" #: fortran/resolve.cc:5550 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Argument dim at %L must be scalar" +#, gcc-internal-format, gfc-internal-format msgid "STAT argument at %L must be scalar" -msgstr "Dim-argumentet vid %L måste vara skalärt" +msgstr "Argumentet till STAT vid %L måste vara skalärt" #: fortran/resolve.cc:5557 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Expression at %L must be of INTEGER type, found %s" +#, gcc-internal-format, gfc-internal-format msgid "STAT argument at %L must be of INTEGER type, found %s" -msgstr "Uttryck vid %L måste vara av INTEGER-typ, hittade %s" +msgstr "Argumentet till STAT vid %L måste vara av INTEGER-typ, hittade %s" #: fortran/resolve.cc:5566 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Expression at %L must be scalar" +#, gcc-internal-format, gfc-internal-format msgid "STAT's expression at %L must be a variable" -msgstr "Uttryck vid %L måste vara skalärt" +msgstr "STATs uttryck vid %L måste vara en variabel" #: fortran/resolve.cc:5588 #, gcc-internal-format, gfc-internal-format @@ -81406,10 +81307,9 @@ msgid "gfc_expression_rank(): Two array specs" msgstr "gfc_expression_rank(): Två vektorspecifikationer" #: fortran/resolve.cc:6048 -#, fuzzy, gcc-internal-format -#| msgid "illegal operand " +#, gcc-internal-format msgid "Illegal coarray index" -msgstr "ogiltig operand " +msgstr "Otillåtet co-vektorindex" #: fortran/resolve.cc:6096 #, gcc-internal-format, gfc-internal-format @@ -81591,22 +81491,19 @@ msgid "Variable %qs at %L not specified in a locality spec of DO CONCURRENT at % msgstr "Variabeln %qs vid %L inte angiven i en lokalitetsspecifikation av DO CONCURRENT vid %L men behövs på grund av DEFAULT (NONE)" #: fortran/resolve.cc:8235 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Expected variable name at %C" +#, gcc-internal-format, gfc-internal-format msgid "Expected variable name in %s locality spec at %L" -msgstr "Variabelnamn förväntades vid %C" +msgstr "Variabelnamn förväntades i %s lokalitetsspecifikation vid %L" #: fortran/resolve.cc:8244 -#, fuzzy, gcc-internal-format -#| msgid "Variable %qs at %L has not been assigned a format label" +#, gcc-internal-format msgid "Variable %qs at %L has already been specified in a locality-spec" -msgstr "Variabeln %qs vid %L har inte tilldelats en formatetikett" +msgstr "Variabeln %qs vid %L har redan angivits i en lokalitetsspecifikation" #: fortran/resolve.cc:8254 -#, fuzzy, gcc-internal-format -#| msgid "SAVE attribute at %L cannot be specified in a PURE procedure" +#, gcc-internal-format msgid "Index variable %qs at %L cannot be specified in a locality-spec" -msgstr "SAVE-attribut vid %L kan inte anges i en PURE-procedur" +msgstr "Indexvariabeln %qs vid %L kan inte anges i en lokalitetsspecifikation" #: fortran/resolve.cc:8267 #, gcc-internal-format @@ -81614,16 +81511,14 @@ msgid "OPTIONAL attribute not permitted for %qs in %s locality-spec at %L" msgstr "Attributet OPTIONAL är inte tillåtet för %qs i lokalitetsspecifikationen %s vid %L" #: fortran/resolve.cc:8274 -#, fuzzy, gcc-internal-format -#| msgid "Assumed size array %qs in %s clause at %L" +#, gcc-internal-format msgid "Assumed-size array not permitted for %qs in %s locality-spec at %L" -msgstr "Vektor %qs med antagen storlek i %s-klausul vid %L" +msgstr "En vektor med antagen storlek är inte tillåten till %qs i lokalitetsspecifikationen %s vid %L" #: fortran/resolve.cc:8287 -#, fuzzy, gcc-internal-format -#| msgid "ALLOCATABLE object %qs in %s clause at %L" +#, gcc-internal-format msgid "ALLOCATABLE attribute not permitted for %qs in %s locality-spec at %L" -msgstr "ALLOCATABLE-objekt %qs i %s-klausul vid %L" +msgstr "Attributet ALLOCATABLE är inte tillåtet till %qs i lokalitetsspecifikationen %s vid %L" #: fortran/resolve.cc:8292 #, gcc-internal-format @@ -81631,10 +81526,9 @@ msgid "Nonpointer polymorphic dummy argument not permitted for %qs in %s localit msgstr "Polymorft attrappargument som inte är en pekare är inte tillåtet för %qs i lokalitetsspecifikationen %s vid %L" #: fortran/resolve.cc:8297 -#, fuzzy, gcc-internal-format -#| msgid "Cray pointer %qs in %s clause at %L" +#, gcc-internal-format msgid "Coarray not permitted for %qs in %s locality-spec at %L" -msgstr "Cray-pekare %qs i %s-klausul vid %L" +msgstr "En co-vektor är inte tillåten till %qs i lokalitetsspecifikationen %s vid %L" #: fortran/resolve.cc:8303 #, gcc-internal-format @@ -81642,10 +81536,9 @@ msgid "Finalizable type not permitted for %qs in %s locality-spec at %L" msgstr "en finalize:bar typ är inte tillåten för %qs i lokalitetsspecifikationen %s vid %L" #: fortran/resolve.cc:8308 -#, fuzzy, gcc-internal-format -#| msgid "List item %qs with allocatable components is not permitted in map clause at %L" +#, gcc-internal-format msgid "Type with ultimate allocatable component not permitted for %qs in %s locality-spec at %L" -msgstr "Listposten %qs med allokerbara komponenter är inte tillåtet i map-klausulen vid %L" +msgstr "Typen med en ytterst allokerbar komponent är inte är inte tillåten till %qs i lokalitetsspecifikationen %s vid %L" #: fortran/resolve.cc:8316 #, gcc-internal-format @@ -81658,16 +81551,14 @@ msgid "VOLATILE attribute not permitted for %qs in REDUCE locality-spec at %L" msgstr "Attributet VOLATILE är inte tillåtet för %qs i lokalitetsspecifikationen REDUCE vid %L" #: fortran/resolve.cc:8374 -#, fuzzy, gcc-internal-format -#| msgid "Unexpected intrinsic type %qs at %L" +#, gcc-internal-format msgid "Expected numeric type for %qs in REDUCE at %L, got %s" -msgstr "Oväntad inbyggd typ %qs vid %L" +msgstr "En numerisk typ förväntades till %qs i REDUCE vid %L, fick %s" #: fortran/resolve.cc:8383 -#, fuzzy, gcc-internal-format -#| msgid "Expected block name of %qs in %s statement at %L" +#, gcc-internal-format msgid "Expected logical type for %qs in REDUCE at %L, got %qs" -msgstr "Blocknamn på %qs i %s-sats förväntades vid %L" +msgstr "En logiskt typ förväntades till %qs i REDUCE vid %L, fick %s" #: fortran/resolve.cc:8401 #, gcc-internal-format @@ -81680,10 +81571,9 @@ msgid "Expected integer type for %qs in REDUCE with IAND/IOR/IEOR at %L, got %s" msgstr "En heltalstyp förväntades för %qs i REDUCE med IAND/IOR/IEOR vid %L, fick %s" #: fortran/resolve.cc:8448 -#, fuzzy, gcc-internal-format -#| msgid "variable %qD set but not used" +#, gcc-internal-format msgid "Variable %qs in locality-spec at %L is not used" -msgstr "variabeln %qD sätts men används inte" +msgstr "Variabeln %qs i lokalitetsspecifikationen vid %L används inte" #: fortran/resolve.cc:8479 #, gcc-internal-format, gfc-internal-format @@ -81736,10 +81626,9 @@ msgid "Source-expr at %L and allocate-object at %L must have the same shape" msgstr "Källuttryck vid %L och allokeringsobjekt vid %L måste ha samma form" #: fortran/resolve.cc:8943 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Only intrinsic operators can be used in expression at %L" +#, gcc-internal-format, gfc-internal-format msgid "The intrinsic NULL cannot be used as source-expr at %L" -msgstr "Endast inbyggda operatorer kan användas i uttryck vid %L" +msgstr "Den inbyggda NULL kan inte användas som källuttryck vid %L" #: fortran/resolve.cc:8951 #, gcc-internal-format, gfc-internal-format @@ -82216,10 +82105,9 @@ msgid "Variable in the ordinary assignment at %L is a procedure pointer componen msgstr "Variabeln i den ordinära tilldelningen vid %L är en procedurpekarkomponent" #: fortran/resolve.cc:12319 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Cannot convert %s to %s at %L" +#, gcc-internal-format, gfc-internal-format msgid "Cannot assign %s to %s at %L" -msgstr "Kan inte konvertera %s till %s vid %L" +msgstr "Kan inte tilldela %s till %s vid %L" #: fortran/resolve.cc:12367 #, gcc-internal-format @@ -82425,10 +82313,9 @@ msgid "Entity %qs at %L has a deferred type parameter and requires either the PO msgstr "Enheten %qs vid %L har en fördröjd typparameter och kräver antingen attributet POINTER eller ALLOCATABLE" #: fortran/resolve.cc:14579 -#, fuzzy, gcc-internal-format -#| msgid "CLASS variable %qs at %L cannot have the PARAMETER attribute" +#, gcc-internal-format msgid "Automatic object %qs at %L cannot have the SAVE attribute" -msgstr "CLASS-variabeln %qs vid %L får inte ha attributet PARAMETER" +msgstr "Det automatiska objektet %qs vid %L får inte ha attributet SAVE" #. F08:C541. The shape of an array defined in a main program or module #. * needs to be constant. @@ -83138,10 +83025,9 @@ msgid "Variable %qs at %L is a coarray and is not ALLOCATABLE, SAVE nor a dummy msgstr "Variabeln %qs vid %L är en co-vektor och är inte ALLOCATABLE, SAVE eller ett attrappargument" #: fortran/resolve.cc:17799 -#, fuzzy, gcc-internal-format -#| msgid "Coarray variable %qs at %L shall not have codimensions with deferred shape" +#, gcc-internal-format msgid "Coarray variable %qs at %L shall not have codimensions with deferred shape without allocatable" -msgstr "Co-vektorvariabeln %qs vid %L skall inte ha co-dimensioner med fördröjd form" +msgstr "Co-vektorvariabeln %qs vid %L skall inte ha co-dimensioner med fördröjd form utan allokerbarhet" #: fortran/resolve.cc:17807 #, gcc-internal-format @@ -83326,10 +83212,9 @@ msgid "Non-CHARACTER object %qs in default CHARACTER EQUIVALENCE statement at %L msgstr "Icke-CHARACTER-objektet %qs i standard-CHARACTER EQUIVALENCE-satsen vid %L" #: fortran/resolve.cc:18938 -#, fuzzy, gcc-internal-format -#| msgid "Syntax error in EQUIVALENCE statement at %L" +#, gcc-internal-format msgid "Non-NUMERIC object %qs in default NUMERIC EQUIVALENCE statement at %L" -msgstr "Syntaxfel i EQUIVALENCE-sats vid %L" +msgstr "Ett icke-numeriskt objektet %qs i satsen NUMERIC EQUIVALENCE vid %L" #: fortran/resolve.cc:18956 #, gcc-internal-format @@ -83422,10 +83307,9 @@ msgid "!$OMP at %C starts a commented line as it neither is followed by a space msgstr "!$OMP vid %C inleder en kommentarrad eftersom det varken följs av en blank eller en fortsättningsrad" #: fortran/scanner.cc:1011 -#, fuzzy, gcc-internal-format -#| msgid "Ignoring '!$omx' vendor-extension sentinel at %C" +#, gcc-internal-format msgid "Ignoring %<!$omx%> vendor-extension sentinel at %C" -msgstr "Ignorerar leverantörsutvidgningens vaktpost ”!$omx” vid %C" +msgstr "Ignorerar leverantörsutvidgningens vaktpost %<!$omx%> vid %C" #: fortran/scanner.cc:1323 fortran/scanner.cc:1526 #, gcc-internal-format, gfc-internal-format @@ -84027,10 +83911,9 @@ msgid "SAVE attribute at %L cannot be specified in a PURE procedure" msgstr "SAVE-attribut vid %L kan inte anges i en PURE-procedur" #: fortran/symbol.cc:1323 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Duplicate SAVE attribute specified at %L" +#, gcc-internal-format, gfc-internal-format msgid "Duplicate SAVE attribute specified near %C" -msgstr "Dubblerat SAVE-attribut angivet vid %L" +msgstr "Dubblerat SAVE-attribut angivet nära %C" #: fortran/symbol.cc:1327 #, gcc-internal-format, gfc-internal-format @@ -84234,10 +84117,9 @@ msgid "Derived type %qs declared at %L must have the BIND attribute to be C inte msgstr "Härledd typ %qs deklarerad vid %L måste ha attributet BIND för att vara ett C-interoperativ" #: fortran/symbol.cc:4640 -#, fuzzy, gcc-internal-format -#| msgid "Derived type %qs with BIND(C) attribute at %L is empty, and may be inaccessible by the C companion processor" +#, gcc-internal-format msgid "Derived type %qs with BIND(C) attribute at %L has no components" -msgstr "Härledd typ %qs med attributet BIND(C) vid %L är tom, och kan vara otillgängliga av C-följeslagarprocessorn" +msgstr "Den härledda typen %qs med attributet BIND(C) vid %L har inga komponenter" #. Generally emit warning, but not twice if -pedantic is given. #: fortran/symbol.cc:4646 @@ -84306,10 +84188,9 @@ msgid "Overlapping unequal initializers in EQUIVALENCE at %C" msgstr "Överlappande olika initierare i EQUIVALENCE vid %C" #: fortran/trans-array.cc:2466 fortran/trans-expr.cc:10439 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "The structure constructor at %C has been finalized. This feature was removed by f08/0011. Use -std=f2018 or -std=gnu to eliminate the finalization." +#, gcc-internal-format, gfc-internal-format msgid "The structure constructor at %L has been finalized. This feature was removed by f08/0011. Use -std=f2018 or -std=gnu to eliminate the finalization." -msgstr "Postkonstrueraren vid %C har avslutats. Denna funktion togs bart av f08/0011. Använd -std=f2018 eller -std=gnu för att eliminera avslutningen." +msgstr "Postkonstrueraren vid %L har avslutats. Denna funktion togs bart av f08/0011. Använd -std=f2018 eller -std=gnu för att eliminera avslutningen." #. Problems occur when we get something like #. integer :: a(lots) = (/(i, i=1, lots)/) @@ -84505,16 +84386,14 @@ msgid "Sorry, !$ACC DECLARE at %L is not allowed in BLOCK construct" msgstr "Ledsen, !$ACC DECLARE vid %L är inte tillåtet i BLOCK-konstruktion" #: fortran/trans-decl.cc:7199 fortran/trans-expr.cc:6117 -#, fuzzy, gcc-internal-format -#| msgid "Builtin not implemented" +#, gcc-internal-format msgid "Unsigned not yet implemented" -msgstr "Inbyggd inte implementerad" +msgstr "Teckenlöst är inte implementerat ännu" #: fortran/trans-decl.cc:8317 -#, fuzzy, gcc-internal-format -#| msgid "Symbol %qs at %C is already in a COMMON block" +#, gcc-internal-format msgid "Symbol %qs at %L is declared in a BLOCK DATA program unit but is not in a COMMON block" -msgstr "Symbolen %qs vid %C är redan i ett COMMON-block" +msgstr "Symbolen %qs vid %L är deklarerad i en programenhet BLOCK DATA men är inte i ett COMMON-block" #: fortran/trans-expr.cc:1211 #, gcc-internal-format, gfc-internal-format @@ -84593,16 +84472,14 @@ msgid "implicit mapping of assumed size array %qD" msgstr "implicit avbildning av vektorn %qD med antagen storlek" #: fortran/trans-openmp.cc:2149 -#, fuzzy, gcc-internal-format -#| msgid "comparison with string literal results in unspecified behavior" +#, gcc-internal-format msgid "Mapping of unlimited polymorphic list item %qD is unspecified behavior and unsupported" -msgstr "jämförelse med stränglitteral resulterar i odefinierat beteende" +msgstr "Avbildning av den obegränsade polymorfa listposten %qD är odefinierat beteende och stödjs ej" #: fortran/trans-openmp.cc:2154 -#, fuzzy, gcc-internal-format -#| msgid "comparison with string literal results in unspecified behavior" +#, gcc-internal-format msgid "Mapping of polymorphic list item %qD is unspecified behavior" -msgstr "jämförelse med stränglitteral resulterar i odefinierat beteende" +msgstr "Avbildningen av den polymorfa listposten %qD är odefinierat beteende" #: fortran/trans-openmp.cc:4176 #, gcc-internal-format @@ -84655,10 +84532,9 @@ msgid "gfc_trans_omp_workshare(): Bad statement code" msgstr "gfc_trans_omp_workshare(): Felaktig satskod" #: fortran/trans-openmp.cc:9631 -#, fuzzy, gcc-internal-format -#| msgid "The base name for 'declare variant' must be specified at %L " +#, gcc-internal-format msgid "The base name for %<declare variant%> must be specified at %L" -msgstr "Basnamnet för ”declare variant” måste anges vid %L" +msgstr "Basnamnet för %<declare variant%> måste anges vid %L" #: fortran/trans-openmp.cc:9642 #, gcc-internal-format, gfc-internal-format @@ -84726,58 +84602,49 @@ msgid "the %qs clause can only be specified if the %<dispatch%> selector of the msgstr "klausulen %qs kan endast anges om väljaren %<dispatch%> i konstruktionsväljarmängden förekommer i klausulen %<match%> vid %L" #: fortran/trans-openmp.cc:9912 fortran/trans-openmp.cc:9951 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Expected argument list at %C" +#, gcc-internal-format, gfc-internal-format msgid "Expected positive argument index at %L" -msgstr "Argumentlista förväntades vid %C" +msgstr "Ett positivt argumentindex förväntades vid %L" #: fortran/trans-openmp.cc:9923 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "attribute %qs positional argument %i value %wi exceeds number of function arguments %u" +#, gcc-internal-format, gfc-internal-format msgid "Argument index at %L exceeds number of arguments %d" -msgstr "värdet %3$wi på argument %2$i till attributet %1$qs överskrider antalet funktionsargument %4$u" +msgstr "Argumentindexet vid %L överskrider antalet argument %d" #: fortran/trans-openmp.cc:9961 -#, fuzzy, gcc-internal-format, gfc-internal-format -#| msgid "Upper cobound is less than lower cobound at %L" +#, gcc-internal-format, gfc-internal-format msgid "Upper argument index smaller than lower one at %L" -msgstr "Övre cobound är mindre än den lägre cobound vid %L" +msgstr "Det övre argumentindexet är mindre än det lägre vid %L" #: fortran/trans-openmp.cc:9987 -#, fuzzy, gcc-internal-format -#| msgid "Variable %qs is not a dummy argument at %L" +#, gcc-internal-format msgid "List item %qs at %L, declared at %L, is not a dummy argument" -msgstr "Variabeln %qs är inte ett attrappargument vid %L" +msgstr "Listposten %qs vid %L, deklarerad vid %L, är inte ett attrappargument" #: fortran/trans-openmp.cc:10001 -#, fuzzy, gcc-internal-format -#| msgid "List item %qs in %s clause at %L must be of TYPE(C_PTR)" +#, gcc-internal-format msgid "Argument %qs at %L to list item in %<need_device_ptr%> at %L must be a scalar of TYPE(C_PTR)" -msgstr "Listposten %qs i %s-klausul vid %L måste vara TYPE(C_PTR)" +msgstr "Argumentet %qs vid %L till listposten i %<need_device_ptr%> vid %L måste vara en skalär av TYPE(C_PTR)" #: fortran/trans-openmp.cc:10008 -#, fuzzy, gcc-internal-format -#| msgid "%qs is not valid for %qs" +#, gcc-internal-format msgid "Consider using %<need_device_addr%> instead" -msgstr "%qs är inte giltigt för %qs" +msgstr "Överväg att använda %<need_device_addr%> istället" #: fortran/trans-openmp.cc:10015 -#, fuzzy, gcc-internal-format -#| msgid "Argument %qs of elemental procedure at %L cannot have the ALLOCATABLE attribute" +#, gcc-internal-format msgid "Argument %qs at %L to list item in %<need_device_addr%> at %L must not have the VALUE attribute" -msgstr "Argumentet %qs av elementär procedur vid %L får inte ha attributet ALLOCATABLE" +msgstr "Argumentet %qs vid %L till listposten i %<need_device_addr%> vid %L får inte ha attributet VALUE" #: fortran/trans-openmp.cc:10024 -#, fuzzy, gcc-internal-format -#| msgid "%qs clause at %L specified more than once" +#, gcc-internal-format msgid "%qs at %L is specified more than once" -msgstr "Klausulen %qs vid %L angiven mer än en gång" +msgstr "%qs vid %L anges mer än en gång" #: fortran/trans-openmp.cc:10041 -#, fuzzy, gcc-internal-format -#| msgid "%qs is not valid for %qs" +#, gcc-internal-format msgid "%<need_device_addr%> not yet supported" -msgstr "%qs är inte giltigt för %qs" +msgstr "%<need_device_addr%> stödjs inte ännu" #: fortran/trans-stmt.cc:576 #, gcc-internal-format, gfc-internal-format @@ -84800,17 +84667,15 @@ msgid "gfc_trans_select(): Bad type for case expr." msgstr "gfc_trans_select(): Felaktig typ för Bad type for case-uttryck." #: fortran/trans-stmt.cc:5170 -#, fuzzy, gcc-internal-format -#| msgid "Sorry, the event component of derived type at %L is not yet supported" +#, gcc-internal-format msgid "Sorry, %s specifier at %L for assumed-size array %qs is not yet supported" -msgstr "Ledsen, händelsekomponenten hos härledd typ vid %L stödjs inte ännu" +msgstr "Ledsen, specificeraren %s vid %L för vektorn %qs med antagen storlek stödjs inte ännu" #. Cf. PR fortran/ #: fortran/trans-stmt.cc:5207 -#, fuzzy, gcc-internal-format -#| msgid "Sorry, the event component of derived type at %L is not yet supported" +#, gcc-internal-format msgid "Sorry, LOCAL specifier at %L for %qs of derived type with default initializer is not yet supported" -msgstr "Ledsen, händelsekomponenten hos härledd typ vid %L stödjs inte ännu" +msgstr "Ledsen, specificeraren LOCAL vid %L för %qs av härledd typp med standardinitierare stödjs inte ännu" #: fortran/trans-types.cc:619 #, gcc-internal-format @@ -84974,16 +84839,14 @@ msgid "unexpected EOF" msgstr "oväntat filslut" #: go/gofrontend/expressions.cc:985 -#, fuzzy, gcc-internal-format -#| msgid "invalid use of %qD" +#, gcc-internal-format msgid "invalid use of type" -msgstr "ogiltig användning av %qD" +msgstr "ogiltig användning av typen" #: go/gofrontend/statements.cc:2670 -#, fuzzy, gcc-internal-format -#| msgid "expected expression" +#, gcc-internal-format msgid "expected call expression" -msgstr "uttryck förväntades" +msgstr "ett anropsuttryck förväntades" #: lto/lto-common.cc:2041 #, gcc-internal-format @@ -86483,10 +86346,9 @@ msgid "label definition in %<constexpr%> function only available with %<-std=c++ msgstr "en etikettdefinition i en %<constexpr%>-funktion är endast tillgängligt med %<-std=c++2b%> eller %<-std=gnu++2b%>" #: rust/backend/rust-tree.cc:616 -#, fuzzy, gcc-internal-format -#| msgid "ignoring return value of %qD, that must be used: %<%s%>" +#, gcc-internal-format msgid "ignoring return value of %qD, that must be used: %qs" -msgstr "ignorerar returvärdet av %qD, som måste användas: %<%s%>" +msgstr "ignorerar returvärdet av %qD, som måste användas: %qs" #: rust/backend/rust-tree.cc:617 #, gcc-internal-format @@ -86494,10 +86356,9 @@ msgid "ignoring return value of %qD, that must be used" msgstr "ignorerar returvärdet av %qD, som måste användas" #: rust/backend/rust-tree.cc:633 -#, fuzzy, gcc-internal-format -#| msgid "ignoring returned value of type %qT, that must be used: %<%s%>" +#, gcc-internal-format msgid "ignoring returned value of type %qT, that must be used: %qs" -msgstr "ignorerar returnerat värde av typen %qT, som måste användas: %<%s%>" +msgstr "ignorerar returnerat värde av typen %qT, som måste användas: %qs" #: rust/backend/rust-tree.cc:634 #, gcc-internal-format @@ -86514,1163 +86375,3 @@ msgstr "oanvänt namn %qE" #, gcc-internal-format, gfc-internal-format msgid "are you trying to break %s? how dare you?" msgstr "försöker du göra sönder %s? hur vågar du?" - -#, gcc-internal-format -#~ msgid "%qF requires arch15 or higher" -#~ msgstr "%qF behöver arch15 eller högre" - -#, gcc-internal-format -#~ msgid "%qs matching variant requires arch15 or higher" -#~ msgstr "%qs-matchning kräver arch15 eller högre" - -#, gcc-internal-format -#~ msgid "Builtin %qF requires arch15 or higher" -#~ msgstr "Inbyggd %qF kräver arch15 eller högre" - -#, gcc-internal-format -#~ msgid "use of %<this%> in a constant expression" -#~ msgstr "%<this%> används i ett konstant uttryck" - -#, gcc-internal-format, gfc-internal-format -#~ msgid "FIRSTPRIVATE with polymorphic list item at %L is unspecified behavior" -#~ msgstr "FIRSTPRIVATE med ett polymorft listelement vid %L är ett ospecificerat beteeende" - -#, gcc-internal-format -#~ msgid "Sorry, LOCAL and LOCAL_INIT are not yet supported for %<do concurrent%> constructs at %L" -#~ msgstr "Ledsen, LOCAL och LOCAL_INIT stödjs inte ännu för konstruktioner %<do concurrent%> vid %L" - -#, fuzzy, gcc-internal-format -#~| msgid "comparison with string literal results in unspecified behavior" -#~ msgid "Implicit mapping of polymorphic variable %qD is unspecified behavior" -#~ msgstr "jämförelse med stränglitteral resulterar i odefinierat beteende" - -#, no-c-format -#~ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, and AVX10.1 built-in functions and code generation." -#~ msgstr "Stöd inbyggda MMX-, SSE-, SSE2-, SSE3-, SSSE3-, SSE4.1-, SSE4.2-, AVX-, AVX2- och AVX10.1-funktioner och -kodgenerering." - -#, no-c-format -#~ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX10.1 and AVX10.2 built-in functions and code generation." -#~ msgstr "Stöd inbyggda MMX-, SSE-, SSE2-, SSE3-, SSSE3-, SSE4.1-, SSE4.2-, AVX-, AVX2-, AVX10.1- och AVX10.2-funktioner och -kodgenerering." - -#, gcc-internal-format -#~ msgid "%<-mesa%> is deprecated and support for ESA/390 will be removed; use %<-mzarch%> instead" -#~ msgstr "%<-mesa%> bör undvikas och stöd för ESA/390 kommer tas bort; anvnd %<-march%> istället" - -#, gcc-internal-format -#~ msgid "%<append_args%> clause not yet supported for %qD, except when specifying all %d objects in the %<interop%> clause of the %<dispatch%> directive" -#~ msgstr "%<append_args%>-klausulen stödjs inte ännu för %qD, utom när alla %d objekt specificeras i %<interop%>-klausulen till %<dispatch%>-direktivet" - -#, gcc-internal-format -#~ msgid "required by %<dispatch%> construct" -#~ msgstr "krävs av konstruktionen %<dispatch%>" - -#, gcc-internal-format -#~ msgid "%<#pragma omp interop%> not yet supported" -#~ msgstr "%<#pragma omp interop%> stödjs inte ännu" - -#, gcc-internal-format -#~ msgid "%<init%> clause with modifier other than %<prefer_type%>, %<target%> or %<targetsync%>" -#~ msgstr "en klausul %<init%> med en annan modifierare än %<prefer_type%>, %<target%> eller %<targetsync%>" - -#, c-format -#~ msgid "bad I/O address 0x" -#~ msgstr "felaktig I/O-adress 0x" - -#, gcc-internal-format -#~ msgid "late or dynamic variant resolution required for call in a %<dispatch%> construct" -#~ msgstr "sen eller dynamisk variantupplösning krävs för anrop i en %<dispatch%>-konstruktion" - -#, gcc-internal-format -#~ msgid "unexpected %<interop%> clause as invoked procedure %qD is not variant substituted" -#~ msgstr "oväntad %<interop%>-klausul eftersom den anropade proceduren %qD inte är variantsubtituerad" - -#, gcc-internal-format, gfc-internal-format -#~ msgid "TEAM= attribute in %C misplaced" -#~ msgstr "attributet TEAM= i %C är felplacerat" - -#, gcc-internal-format, gfc-internal-format -#~ msgid "STAT= attribute in %C misplaced" -#~ msgstr "attributet STAT= i %C är felplacerat" - -#, gcc-internal-format, gfc-internal-format -#~ msgid "Sorry, not yet able to call a non-pure/non-elemental function %s in a coarray reference; use a temporary for the function's result instead" -#~ msgstr "Ledsen, kan inte ännu anropa en icke-ren/icke-elementär funktion %s i en co-vektor-referens; använd en temporär till funktionsresultatet istället" - -#~ msgid "You need a C startup file for -msys-crt0=" -#~ msgstr "Du behöver en C-uppstartsfil för -msys-crt0=" - -#, no-c-format -#~ msgid "Enable certain features present in the Concepts TS." -#~ msgstr "Aktivera vissa funktioner som finns i Concepts TS." - -#, no-c-format -#~ msgid "Conform to the ISO 2023 C++ draft standard (experimental and incomplete support)." -#~ msgstr "Följ standardutkastet ISO 2023 C++ (experimentellt och ofullständigt stöd)." - -#, no-c-format -#~ msgid "Conform to the ISO 2023 C standard draft (expected to be published in 2024) (experimental and incomplete support)." -#~ msgstr "Följ standardutkastet ISO 2023 C (förväntas publiceras under 2024) (experimentellt och ofullständigt stöd)." - -#, no-c-format -#~ msgid "Conform to the ISO 2023 C++ draft standard with GNU extensions (experimental and incomplete support)." -#~ msgstr "Följ standardutkastet ISO 2023 C++ med GNU-utökningar (experimentellt och ofullständigt stöd)." - -#, no-c-format -#~ msgid "Conform to the ISO 2023 C standard draft (expected to be published in 2024) with GNU extensions (experimental and incomplete support)." -#~ msgstr "Följ standardutkastet ISO 2023 C (förväntas publiceras under 2024) med GNU-utökningar (experimentellt och ofullständigt stöd)." - -#, no-c-format -#~ msgid "When generating -fpic code, allow the use of PLTs. Ignored for fno-pic." -#~ msgstr "Vid generering av -fpic-kod, tillåt användningen av PLT:er. Ignoreras för fno-pic." - -#, no-c-format -#~ msgid "Use LRA instead of reload." -#~ msgstr "Använd LRA istället för omladdning." - -#, no-c-format -#~ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation." -#~ msgstr "Stöd inbyggda MMX-, SSE-, SSE2-, SSE3-, SSSE3-, SSE4.1-, SSE4.2-, AVX-, AVX2- och AVX512F- och AVX512PF-funktioner och -kodgenerering." - -#, no-c-format -#~ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation." -#~ msgstr "Stöd inbyggda MMX-, SSE-, SSE2-, SSE3-, SSSE3-, SSE4.1-, SSE4.2-, AVX-, AVX2- och AVX512F- och AVX512ER-funktioner och -kodgenerering." - -#, no-c-format -#~ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation." -#~ msgstr "Stöd inbyggda MMX-, SSE-, SSE2-, SSE3-, SSSE3-, SSE4.1-, SSE4.2-, AVX-, AVX2-, AVX512F- och AVX5124FMAPS-funktioner och -kodgenerering." - -#, no-c-format -#~ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation." -#~ msgstr "Stöd inbyggda MMX-, SSE-, SSE2-, SSE3-, SSSE3-, SSE4.1-, SSE4.2-, AVX-, AVX2-, AVX512F- och AVX5124VNNIW-funktioner och -kodgenerering." - -#, no-c-format -#~ msgid "Support PREFETCHWT1 built-in functions and code generation." -#~ msgstr "Stöd inbyggda PREFETCHWT1-funktioner och -kodgenerering." - -#, no-c-format -#~ msgid "Link with a limited version of the C library." -#~ msgstr "Länka med en begränsad version av C-biblioteket." - -#, no-c-format -#~ msgid "Name of system library to link against." -#~ msgstr "Namn på systembiblioteket att länka mot." - -#, no-c-format -#~ msgid "Name of the startfile." -#~ msgstr "Namn på startfilen." - -#, no-c-format -#~ msgid "Link with HAL BSP." -#~ msgstr "Länka med HAL BSP." - -#, no-c-format -#~ msgid "Enable DIV, DIVU." -#~ msgstr "Aktivera DIV, DIVU." - -#, no-c-format -#~ msgid "Enable MUL instructions." -#~ msgstr "Använd MUL-instruktioner." - -#, no-c-format -#~ msgid "Enable MULX instructions, assume fast shifter." -#~ msgstr "Använd MULX-instruktioner, anta snabb skiftare." - -#, no-c-format -#~ msgid "Use table based fast divide (default at -O3)." -#~ msgstr "Använd tabellbaserad snabb division (standard för -O3)." - -#, no-c-format -#~ msgid "All memory accesses use I/O load/store instructions." -#~ msgstr "Alla minnesåtkomster använder I/O ladda-/lagrainstruktioner." - -#, no-c-format -#~ msgid "Volatile memory accesses use I/O load/store instructions." -#~ msgstr "Volatila minnesåtkomster använder I/O ladda-/lagrainstruktioner." - -#, no-c-format -#~ msgid "Volatile memory accesses do not use I/O load/store instructions." -#~ msgstr "Volatila minnesåtkomster använder inte I/O ladda-/lagrainstruktioner." - -#, no-c-format -#~ msgid "Enable/disable GP-relative addressing." -#~ msgstr "Aktivera/avaktivera GP-relativ adressering." - -#, no-c-format -#~ msgid "Valid options for GP-relative addressing (for -mgpopt):" -#~ msgstr "Giltiga flaggor för GP-relativ adressering (för -mgpopt):" - -#, no-c-format -#~ msgid "Equivalent to -mgpopt=none." -#~ msgstr "Ekvivalent med -mgpopt=none." - -#, no-c-format -#~ msgid "Floating point custom instruction configuration name." -#~ msgstr "Namn på anpassad instruktionskonfiguration för flyttal." - -#, no-c-format -#~ msgid "Do not use the ftruncds custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen ftruncds." - -#, no-c-format -#~ msgid "Integer id (N) of ftruncds custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion ftruncds." - -#, no-c-format -#~ msgid "Do not use the fextsd custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fextsd." - -#, no-c-format -#~ msgid "Integer id (N) of fextsd custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fextsd." - -#, no-c-format -#~ msgid "Do not use the fixdu custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fixdu." - -#, no-c-format -#~ msgid "Integer id (N) of fixdu custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fixdu." - -#, no-c-format -#~ msgid "Do not use the fixdi custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fixdi." - -#, no-c-format -#~ msgid "Integer id (N) of fixdi custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fixdi." - -#, no-c-format -#~ msgid "Do not use the fixsu custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fixsu." - -#, no-c-format -#~ msgid "Integer id (N) of fixsu custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fixsu." - -#, no-c-format -#~ msgid "Do not use the fixsi custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fixsi." - -#, no-c-format -#~ msgid "Integer id (N) of fixsi custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fixsi." - -#, no-c-format -#~ msgid "Do not use the floatud custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen floatud." - -#, no-c-format -#~ msgid "Integer id (N) of floatud custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion floatud." - -#, no-c-format -#~ msgid "Do not use the floatid custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen floatid." - -#, no-c-format -#~ msgid "Integer id (N) of floatid custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion floatid." - -#, no-c-format -#~ msgid "Do not use the floatus custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen floatus." - -#, no-c-format -#~ msgid "Integer id (N) of floatus custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion floatus." - -#, no-c-format -#~ msgid "Do not use the floatis custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen floatis." - -#, no-c-format -#~ msgid "Integer id (N) of floatis custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion floatis." - -#, no-c-format -#~ msgid "Do not use the fcmpned custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fcmpned." - -#, no-c-format -#~ msgid "Integer id (N) of fcmpned custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fcmpned." - -#, no-c-format -#~ msgid "Do not use the fcmpeqd custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fcmpeqd." - -#, no-c-format -#~ msgid "Integer id (N) of fcmpeqd custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fcmpeqd." - -#, no-c-format -#~ msgid "Do not use the fcmpged custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fcmpged." - -#, no-c-format -#~ msgid "Integer id (N) of fcmpged custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fcmpged." - -#, no-c-format -#~ msgid "Do not use the fcmpgtd custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fcmpgtd." - -#, no-c-format -#~ msgid "Integer id (N) of fcmpgtd custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fcmpgtd." - -#, no-c-format -#~ msgid "Do not use the fcmpled custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fcmpled." - -#, no-c-format -#~ msgid "Integer id (N) of fcmpled custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fcmpled." - -#, no-c-format -#~ msgid "Do not use the fcmpltd custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fcmpltd." - -#, no-c-format -#~ msgid "Integer id (N) of fcmpltd custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fcmpltd." - -#, no-c-format -#~ msgid "Do not use the flogd custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen flogd." - -#, no-c-format -#~ msgid "Integer id (N) of flogd custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion flogd." - -#, no-c-format -#~ msgid "Do not use the fexpd custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fexpd." - -#, no-c-format -#~ msgid "Integer id (N) of fexpd custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fexpd." - -#, no-c-format -#~ msgid "Do not use the fatand custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fatand." - -#, no-c-format -#~ msgid "Integer id (N) of fatand custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fatand." - -#, no-c-format -#~ msgid "Do not use the ftand custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen ftand." - -#, no-c-format -#~ msgid "Integer id (N) of ftand custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion ftand." - -#, no-c-format -#~ msgid "Do not use the fsind custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fsind." - -#, no-c-format -#~ msgid "Integer id (N) of fsind custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fsind." - -#, no-c-format -#~ msgid "Do not use the fcosd custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fcosd." - -#, no-c-format -#~ msgid "Integer id (N) of fcosd custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fcosd." - -#, no-c-format -#~ msgid "Do not use the fsqrtd custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fsqrtd." - -#, no-c-format -#~ msgid "Integer id (N) of fsqrtd custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fsqrtd." - -#, no-c-format -#~ msgid "Do not use the fabsd custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fabsd." - -#, no-c-format -#~ msgid "Integer id (N) of fabsd custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fabsd." - -#, no-c-format -#~ msgid "Do not use the fnegd custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fnegd." - -#, no-c-format -#~ msgid "Integer id (N) of fnegd custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fnegd." - -#, no-c-format -#~ msgid "Do not use the fmaxd custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fmaxd." - -#, no-c-format -#~ msgid "Integer id (N) of fmaxd custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fmaxd." - -#, no-c-format -#~ msgid "Do not use the fmind custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fmind." - -#, no-c-format -#~ msgid "Integer id (N) of fmind custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fmind." - -#, no-c-format -#~ msgid "Do not use the fdivd custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fdivd." - -#, no-c-format -#~ msgid "Integer id (N) of fdivd custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fdivd." - -#, no-c-format -#~ msgid "Do not use the fmuld custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fmuld." - -#, no-c-format -#~ msgid "Integer id (N) of fmuld custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fmuld." - -#, no-c-format -#~ msgid "Do not use the fsubd custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fsubd." - -#, no-c-format -#~ msgid "Integer id (N) of fsubd custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fsubd." - -#, no-c-format -#~ msgid "Do not use the faddd custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen faddd." - -#, no-c-format -#~ msgid "Integer id (N) of faddd custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion faddd." - -#, no-c-format -#~ msgid "Do not use the fcmpnes custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fcmpnes." - -#, no-c-format -#~ msgid "Integer id (N) of fcmpnes custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fcmpnes." - -#, no-c-format -#~ msgid "Do not use the fcmpeqs custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fcmpeqs." - -#, no-c-format -#~ msgid "Integer id (N) of fcmpeqs custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fcmpeqs." - -#, no-c-format -#~ msgid "Do not use the fcmpges custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fcmpges." - -#, no-c-format -#~ msgid "Integer id (N) of fcmpges custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fcmpges." - -#, no-c-format -#~ msgid "Do not use the fcmpgts custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fcmpgts." - -#, no-c-format -#~ msgid "Integer id (N) of fcmpgts custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fcmpgts." - -#, no-c-format -#~ msgid "Do not use the fcmples custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fcmples." - -#, no-c-format -#~ msgid "Integer id (N) of fcmples custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fcmples." - -#, no-c-format -#~ msgid "Do not use the fcmplts custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fcmplts." - -#, no-c-format -#~ msgid "Integer id (N) of fcmplts custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fcmplts." - -#, no-c-format -#~ msgid "Do not use the flogs custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen flogs." - -#, no-c-format -#~ msgid "Integer id (N) of flogs custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion flogs." - -#, no-c-format -#~ msgid "Do not use the fexps custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fexps." - -#, no-c-format -#~ msgid "Integer id (N) of fexps custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fexps." - -#, no-c-format -#~ msgid "Do not use the fatans custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fatans." - -#, no-c-format -#~ msgid "Integer id (N) of fatans custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fatans." - -#, no-c-format -#~ msgid "Do not use the ftans custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen ftans." - -#, no-c-format -#~ msgid "Integer id (N) of ftans custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion ftans." - -#, no-c-format -#~ msgid "Do not use the fsins custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fsins." - -#, no-c-format -#~ msgid "Integer id (N) of fsins custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fsins." - -#, no-c-format -#~ msgid "Do not use the fcoss custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fcoss." - -#, no-c-format -#~ msgid "Integer id (N) of fcoss custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fcoss." - -#, no-c-format -#~ msgid "Do not use the fsqrts custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fsqrts." - -#, no-c-format -#~ msgid "Integer id (N) of fsqrts custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fsqrts." - -#, no-c-format -#~ msgid "Do not use the fabss custom instr." -#~ msgstr "Använd inte den anpassade instruktionen fabss." - -#, no-c-format -#~ msgid "Integer id (N) of fabss custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fabss." - -#, no-c-format -#~ msgid "Do not use the fnegs custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fnegs." - -#, no-c-format -#~ msgid "Integer id (N) of fnegs custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fnegs." - -#, no-c-format -#~ msgid "Do not use the fmaxs custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fmaxs." - -#, no-c-format -#~ msgid "Integer id (N) of fmaxs custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fmaxs." - -#, no-c-format -#~ msgid "Do not use the fmins custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fmins." - -#, no-c-format -#~ msgid "Integer id (N) of fmins custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fmins." - -#, no-c-format -#~ msgid "Do not use the fdivs custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fdivs." - -#, no-c-format -#~ msgid "Integer id (N) of fdivs custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fdivs." - -#, no-c-format -#~ msgid "Do not use the fmuls custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fmuls." - -#, no-c-format -#~ msgid "Integer id (N) of fmuls custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fmuls." - -#, no-c-format -#~ msgid "Do not use the fsubs custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fsubs." - -#, no-c-format -#~ msgid "Integer id (N) of fsubs custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fsubs." - -#, no-c-format -#~ msgid "Do not use the fadds custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fadds." - -#, no-c-format -#~ msgid "Integer id (N) of fadds custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fadds." - -#, no-c-format -#~ msgid "Do not use the frdy custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen frdy." - -#, no-c-format -#~ msgid "Integer id (N) of frdy custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion frdy." - -#, no-c-format -#~ msgid "Do not use the frdxhi custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen frdxhi." - -#, no-c-format -#~ msgid "Integer id (N) of frdxhi custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion frdxhi." - -#, no-c-format -#~ msgid "Do not use the frdxlo custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen frdxlo." - -#, no-c-format -#~ msgid "Integer id (N) of frdxlo custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion frdxlo." - -#, no-c-format -#~ msgid "Do not use the fwry custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fwry." - -#, no-c-format -#~ msgid "Integer id (N) of fwry custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fwry." - -#, no-c-format -#~ msgid "Do not use the fwrx custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen fwrx." - -#, no-c-format -#~ msgid "Integer id (N) of fwrx custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion fwrx." - -#, no-c-format -#~ msgid "Do not use the round custom instruction." -#~ msgstr "Använd inte den anpassade instruktionen round." - -#, no-c-format -#~ msgid "Integer id (N) of round custom instruction." -#~ msgstr "Heltals-id (N) för anpassad instruktion round." - -#, no-c-format -#~ msgid "Valid Nios II ISA levels (for -march):" -#~ msgstr "Giltiga Nios II ISA-nivåer (för -march):" - -#, no-c-format -#~ msgid "Enable generation of R2 BMX instructions." -#~ msgstr "Aktivera generering av R2 BMX-instruktioner." - -#, no-c-format -#~ msgid "Enable generation of R2 CDX instructions." -#~ msgstr "Använd generering av R2 CDX-instruktioner." - -#, no-c-format -#~ msgid "Regular expression matching additional GP-addressible section names." -#~ msgstr "Reguljärt uttryck som matchar ytterligare GP-adresserbara sektionsnamn." - -#, no-c-format -#~ msgid "Regular expression matching section names for r0-relative addressing." -#~ msgstr "Reguljärt uttryck som matchar sektionsnamn för r0-relativ adressering." - -#, no-c-format -#~ msgid "Target DFLOAT double precision code." -#~ msgstr "Sikta på DFLOAT-dubbelprecisionskod." - -#, no-c-format -#~ msgid "Improve GCC's ability to track column numbers in large source files, at the expense of slower compilation." -#~ msgstr "Förbättra GCC:s förmåga att följa kolumnnummer i stora källkodsfiler, på bekostnad av långsammare kompilering." - -#~ msgid "bad address, not an I/O address:" -#~ msgstr "felaktig adress, inte en I/O-adress:" - -#~ msgid "candidate:" -#~ msgstr "kandidat:" - -#~ msgid "%r%s:%d:%d:%R [ skipping %d instantiation contexts, use -ftemplate-backtrace-limit=0 to disable ]\n" -#~ msgstr "%r%s:%d:%d:%R [ hoppar över %d instansieringskontexter, använd -ftemplate-backtrace-limit=0 för att avaktivera ]\n" - -#~ msgid "%r%s:%d:%d:%R in %<constexpr%> expansion of %qs" -#~ msgstr "%r%s:%d:%d:%R i expansion av %<constexpr%> i %qs" - -#, gcc-internal-format -#~ msgid "AVX512PF support will be removed in GCC 15" -#~ msgstr "stöd för AVX512PF kommer tas bort i GCC 15" - -#, gcc-internal-format -#~ msgid "AVX512ER support will be removed in GCC 15" -#~ msgstr "stöd för AVX512ER kommer tas bort i GCC 15" - -#, gcc-internal-format -#~ msgid "AVX5124FMAPS support will be removed in GCC 15" -#~ msgstr "stöd för AVX5124FMAPS kommer tas bort i GCC 15" - -#, gcc-internal-format -#~ msgid "AVX5124VNNIW support will be removed in GCC 15" -#~ msgstr "stöd för AVX5124VNNIW kommer tas bort i GCC 15" - -#, gcc-internal-format -#~ msgid "PREFETCHWT1 support will be removed in GCC 15" -#~ msgstr "stöd för PREFETCHWT1 kommer tas bort i GCC 15" - -#, gcc-internal-format -#~ msgid "%<or%> of unmatched not-equal tests is always 1" -#~ msgstr "%<or%> mellan omatchade olikhetstester är alltid 1" - -#, gcc-internal-format -#~ msgid "%<and%> of mutually exclusive equal-tests is always 0" -#~ msgstr "%<and%> mellan ömsesidigt uteslutande likhetstester är alltid 0" - -#, gcc-internal-format -#~ msgid "%+qD causes a section type conflict" -#~ msgstr "%+qD orsakar en sektionstypkonflikt" - -#, gcc-internal-format -#~ msgid "section type conflict" -#~ msgstr "sektionstypskonflikt" - -#, gcc-internal-format -#~ msgid "%s %<%s%.*s%> expects argument of type %<%T%s%>, but argument %d has type %qT" -#~ msgstr "%s %<%s%.*s%> förväntar sig argument av typen %<%T%s%>, men argument %d har typen %qT" - -#, gcc-internal-format -#~ msgid "%s %<%s%.*s%> expects a matching %<%T%s%> argument" -#~ msgstr "%s %<%s%.*s%> förväntar sig ett matchande %<%T%s%>-argument" - -#, gcc-internal-format -#~ msgid "adding %<-flarge-source-files%> will allow for more column-tracking support, at the expense of compilation time and memory" -#~ msgstr "att lägga till %<-flarge-source-files%> kommer tillåta mer kolumnspårningstöd, på bekostnad av kompileringstid och minne" - -#, gcc-internal-format -#~ msgid "%<-fconcepts-ts%> is deprecated and will be removed in GCC 15; please convert your code to C++20 concepts" -#~ msgstr "%<-fconcepts-ts%> undanbedes och kommer tas bort i GCC 15; konvertera din kod till C++20-koncept" - -#, gcc-internal-format -#~ msgid "previously declared as %s with bound %<%s%>" -#~ msgstr "tidigare deklaration som %s med gränsen %<%s%>" - -#, gcc-internal-format -#~ msgid "bad value %<%s%> for %<-mtls-size=%> switch" -#~ msgstr "felaktigt värde %<%s%> till flaggan %<-mtls-size=%>" - -#, gcc-internal-format -#~ msgid "invalid argument %<%s%> for %<%s%>" -#~ msgstr "ogiltigt argument %<%s%> till %<%s%>" - -#, gcc-internal-format -#~ msgid "nested function trampolines not supported on GCN5 due to non-executable stacks" -#~ msgstr "nästade funktionstrampoliner stödjs inte på GCN5 på grund av icke exekverbar stack" - -#, gcc-internal-format -#~ msgid "cannot open intermediate gcn obj file" -#~ msgstr "kan inte öppna intermediär gcn-obj-fil" - -#, gcc-internal-format -#~ msgid "the forth argument must be scale 1, 2, 4, 8" -#~ msgstr "det fjärde argumentet ha skala 1, 2, 4, 8" - -#, gcc-internal-format -#~ msgid "incorrect hint operand" -#~ msgstr "felaktig tipsoperand" - -#, gcc-internal-format -#~ msgid "%<-mtune=knl%> support will be removed in GCC 15" -#~ msgstr "stödet för %<-mtune=knl%> kommer tas bort i GCC 15" - -#, gcc-internal-format -#~ msgid "%<target(\"tune=knl\")%> support will be removed in GCC 15" -#~ msgstr "stödet för %<target(\"tune=knl\")%> kommer tas bort i GCC 15" - -#, gcc-internal-format -#~ msgid "%<-mtune=knm%> support will be removed in GCC 15" -#~ msgstr "stödet för %<-mtune=knm%> kommer tas bort i GCC 15" - -#, gcc-internal-format -#~ msgid "%<target(\"tune=knm\")%> support will be removed in GCC 15" -#~ msgstr "stödet för %<target(\"tune=knm\")%> kommer tas bort i GCC 15" - -#, gcc-internal-format -#~ msgid "%<-march=knl%> support will be removed in GCC 15" -#~ msgstr "stödet för %<-march=knl%> kommer tas bort i GCC 15" - -#, gcc-internal-format -#~ msgid "%<target(\"arch=knl\")%> support will be removed in GCC 15" -#~ msgstr "stödet för %<target(\"arch=knl\")%> kommer tas bort i GCC 15" - -#, gcc-internal-format -#~ msgid "%<-march=knm%> support will be removed in GCC 15" -#~ msgstr "stödet för %<-march=knm%> kommer tas bort i GCC 15" - -#, gcc-internal-format -#~ msgid "%<target(\"arch=knm\")%> support will be removed in GCC 15" -#~ msgstr "stödet för %<target(\"arch=knm\")%> kommer tas bort i GCC 15" - -#, gcc-internal-format -#~ msgid "%<-mfpxx%> requires %<-mlra%>" -#~ msgstr "%<-mfpxx%> kräver %<-mlra%>" - -#, gcc-internal-format -#~ msgid "Unknown form for stack limit expression" -#~ msgstr "Okänd form på stackgränsuttryck" - -#, gcc-internal-format -#~ msgid "switch %<-mcustom-%s%> is required for double-precision floating-point" -#~ msgstr "flaggan %<-mcustom-%s%> behövs för dubbel precisions flyttal" - -#, gcc-internal-format -#~ msgid "conflicting use of %<-mcustom%> switches, target attributes, and/or %<__builtin_custom_%> functions" -#~ msgstr "motstridig användning av %<-mcustom%>-flaggor, målattribut, och/eller %<__builtin_custom_%>-funktioner" - -#, gcc-internal-format -#~ msgid "ignoring unrecognized switch %<-mcustom-fpu-cfg%> value %<%s%>" -#~ msgstr "ignorerar okänt värde %<%s%> till flaggan %<-mcustom-fpu-cfg%>" - -#, gcc-internal-format -#~ msgid "switch %<-mcustom-%s%> value %d must be between 0 and 255" -#~ msgstr "värdet %2$d till flaggan %<-mcustom-%1$s%> måste vara mellan 0 och 255" - -#, gcc-internal-format -#~ msgid "position-independent code requires the Linux ABI" -#~ msgstr "positionsoberoende kod behöver Linux-ABI:et" - -#, gcc-internal-format -#~ msgid "PIC support for %<-fstack-limit-symbol%>" -#~ msgstr "PIC-stöd för %<-fstack-limit-symbol%>" - -#, gcc-internal-format -#~ msgid "%<-mgpopt%> not supported with PIC" -#~ msgstr "%<-mgpopt%> stödjs inte med PIC" - -#, gcc-internal-format -#~ msgid "%<-mgprel-sec=%> not supported with PIC" -#~ msgstr "%<-mgprel-sec=%> stödjs inte med PIC" - -#, gcc-internal-format -#~ msgid "%<-mr0rel-sec=%> not supported with PIC" -#~ msgstr "%<-mr0rel-sec=%> stödjs inte med PIC" - -#, gcc-internal-format -#~ msgid "%<-mgprel-sec=%> argument is not a valid regular expression" -#~ msgstr "argumentet till %<-mgprel-sec=%> är inte ett giltigt reguljärt uttryck" - -#, gcc-internal-format -#~ msgid "%<-mr0rel-sec=%> argument is not a valid regular expression" -#~ msgstr "argumentet till %<-mr0rel-sec=%> är inte ett giltigt reguljärt uttryck" - -#, gcc-internal-format -#~ msgid "BMX instructions are only supported with R2 architecture" -#~ msgstr "BMX-instruktioner stödjs endast med R2-arkitekturen" - -#, gcc-internal-format -#~ msgid "CDX instructions are only supported with R2 architecture" -#~ msgstr "CDX-instruktioner stödjs endast med R2-arkitekturer" - -#, gcc-internal-format -#~ msgid "R2 architecture is little-endian only" -#~ msgstr "R2-arkitekturen har endast omvänd byteordning" - -#, gcc-internal-format -#~ msgid "cannot call %<__builtin_custom_%s%> without specifying switch %<-mcustom-%s%>" -#~ msgstr "det går inte att anropa %<__builtin_custom_%s%> utan att ange flaggan %<-mcustom-%s%>" - -#, gcc-internal-format -#~ msgid "custom instruction opcode must be a compile-time constant in the range 0-255 for %<__builtin_custom_%s%>" -#~ msgstr "anpassade instruktions-opkoder måste vara kompileringstillfälleskonstanter i intervallet 0-255 för %<__builtin_custom_%s%>" - -#, gcc-internal-format, gfc-internal-format -#~ msgid "control register number must be in range 0-31 for %s" -#~ msgstr "styrregisternummer måste vara i intervallet 0-31 för %s" - -#, gcc-internal-format, gfc-internal-format -#~ msgid "register number must be in range 0-31 for %s" -#~ msgstr "registernummer måste vara i intervallet 0-31 för %s" - -#, gcc-internal-format, gfc-internal-format -#~ msgid "immediate value must fit into a %d-bit integer for %s" -#~ msgstr "ett omedelbart värde måste passa i ett %d-bitars heltal för %s" - -#, gcc-internal-format -#~ msgid "the ENI instruction operand must be either 0 or 1" -#~ msgstr "operanden till instruktionen ENI måste vara antingen 0 eller 1" - -#, gcc-internal-format, gfc-internal-format -#~ msgid "built-in function %s requires Nios II R%d" -#~ msgstr "den inbyggda funktionen %s behöver Nios II R%d" - -#, gcc-internal-format -#~ msgid "switch %<-mcustom-%s%> conflicts with switch %<-mcustom-%s%>" -#~ msgstr "flaggan %<-mcustom-%s%> står i konflikt med flaggan %<-mcustom-%s%>" - -#, gcc-internal-format -#~ msgid "call to %<__builtin_custom_%s%> conflicts with switch %<-mcustom-%s%>" -#~ msgstr "anrop till %<__builtin_custom_%s%> står i konflikt med flaggan %<-mcustom-%s%>" - -#, gcc-internal-format -#~ msgid "%<custom-fpu-cfg%> option does not support %<no-%>" -#~ msgstr "flaggan %<custom-fpu-cfg%> stödjer inte %<no-%>" - -#, gcc-internal-format -#~ msgid "%<custom-fpu-cfg%> option requires configuration argument" -#~ msgstr "flaggan %<custom-fpu-cfg%> behöver konfigurationsargument" - -#, gcc-internal-format -#~ msgid "%<no-custom-%s%> does not accept arguments" -#~ msgstr "%<no-custom-%s%> tar inte argument" - -#, gcc-internal-format -#~ msgid "%<custom-%s=%> requires argument" -#~ msgstr "%<custom-%s=%> behöver argument" - -#, gcc-internal-format -#~ msgid "%<custom-%s=%> argument should be a non-negative integer" -#~ msgstr "argumentet till %<custom-%s=%> skall vara ett ickenegativt heltal" - -#, gcc-internal-format -#~ msgid "%<custom-%s=%> is not recognized as FPU instruction" -#~ msgstr "%<custom-%s=%> är inte känt som en FPU-instruktion" - -#, gcc-internal-format -#~ msgid "invalid custom instruction option %qs" -#~ msgstr "ogiltig flagga för anpassad instruktion %qs" - -#, gcc-internal-format -#~ msgid "parameter %u (%q+D) has void type" -#~ msgstr "parameter %u (%q+D) har void-typ" - -#, gcc-internal-format, gfc-internal-format -#~ msgid "parameter %u has void type" -#~ msgstr "parameter %u har void-typ" - -#, gcc-internal-format -#~ msgid "%<_Generic%> association has function type" -#~ msgstr "%<_Generic%>-association har funktionstyp" - -#, gcc-internal-format -#~ msgid "%<#pragma omp allocate%> for static variables like %qD not yet supported" -#~ msgstr "%<#pragma omp allocate%> för statiska variabler som %qD stödjs inte ännu" - -#, gcc-internal-format -#~ msgid "expected %<match%>" -#~ msgstr "%<match%> förväntades" - -#, gcc-internal-format -#~ msgid "%qs attribute cannot be applied to a function that does not take variable arguments" -#~ msgstr "attributet %qs kan användas på en funktion som inte tar variabla argument" - -#, gcc-internal-format -#~ msgid " passing %qT as %<this%> argument discards qualifiers" -#~ msgstr " att skicka %qT som %<this%>-argument kastar kvalificerare" - -#, gcc-internal-format -#~ msgid "the temporary was destroyed at the end of the full expression %qE" -#~ msgstr "den temporära destruerades vid slutet av det fullständiga uttrycket %qE" - -#, gcc-internal-format -#~ msgid "cast from %qT is not allowed in a constant expression because %qE does not point to an object" -#~ msgstr "typkonvertering från %qT är inte tillåtet i ett konstant uttryck eftersom %qE inte pekar på ett objekt" - -#, gcc-internal-format -#~ msgid "unexpected template-id %qE" -#~ msgstr "oväntat mall-id %qE" - -#, gcc-internal-format -#~ msgid "function concept must be called" -#~ msgstr "funktionskoncept måste anropas" - -#, gcc-internal-format -#~ msgid "function call of variable concept %qE" -#~ msgstr "funktionsanrop av variabelkonceptet %qE" - -#, gcc-internal-format -#~ msgid "no matching concepts for %qE" -#~ msgstr "inga matchande koncept för %qE" - -#, gcc-internal-format -#~ msgid "%qE cannot be introduced with an ellipsis %<...%>" -#~ msgstr "%qE kan inte introduceras med en ellips %<...%>" - -#, gcc-internal-format -#~ msgid "prototype declared here" -#~ msgstr "prototypen deklarerad här" - -#, gcc-internal-format -#~ msgid "all template parameters of %qD must be introduced" -#~ msgstr "alla mallparametrar till %qD måste introduceras" - -#, gcc-internal-format -#~ msgid "cannot deduce template parameters from introduction list" -#~ msgstr "kan inte härleda mallargument från introduktionslistan" - -#, gcc-internal-format -#~ msgid "definition of concept %qD is empty" -#~ msgstr "definitionen av konceptet %qD är tom" - -#, gcc-internal-format -#~ msgid "definition of concept %qD has multiple statements" -#~ msgstr "definitionen av konceptet %qD har flera satser" - -#, gcc-internal-format -#~ msgid "cannot initialize a return object of type %qT with an rvalue of type %<void%>" -#~ msgstr "det går inte att initiera ett returobjekt av typen %qT med ett r-värde av typen %<void%>" - -#, gcc-internal-format -#~ msgid "ignoring return value of %qD, declared with attribute %<nodiscard%>: %<%s%>" -#~ msgstr "ignorerar returvärdet av %qD, deklarerad med attributet %<nodiscard%>: %<%s%>" - -#, gcc-internal-format -#~ msgid "ignoring returned value of type %qT, declared with attribute %<nodiscard%>: %<%s%>" -#~ msgstr "ignorerar returnerat värde av typen %qT, deklarerat med attributet %<nodiscard%>: %<%s%>" - -#, gcc-internal-format -#~ msgid "cannot specialize concept %q#D" -#~ msgstr "kan inte specialisera konceptet %q#D" - -#, gcc-internal-format -#~ msgid "variable concept has no initializer" -#~ msgstr "variabelkoncept har ingen initierare" - -#, gcc-internal-format -#~ msgid "concept %q#D declared with function parameters" -#~ msgstr "konceptet %q#D deklarerad med funktionsparametrar" - -#, gcc-internal-format -#~ msgid "concept %q#D declared with a deduced return type" -#~ msgstr "konceptet %q#D deklarerat med en härledd returtyp" - -#, gcc-internal-format -#~ msgid "concept %q#D with non-%<bool%> return type %qT" -#~ msgstr "koncept %q#D med icke-%<bool%>-returtyp %qT" - -#, gcc-internal-format -#~ msgid "concept %qD has no definition" -#~ msgstr "konceptet %qD har ingen definition" - -#, gcc-internal-format -#~ msgid "a function concept cannot be constrained" -#~ msgstr "ett funktionskoncept kan inte begränsas" - -#, gcc-internal-format -#~ msgid "concept must have type %<bool%>" -#~ msgstr "koncept måste ha typen %<bool%>" - -#, gcc-internal-format -#~ msgid "a variable concept cannot be constrained" -#~ msgstr "ett variabelkoncept kan inte begränsas" - -#, gcc-internal-format -#~ msgid "%<long%> and %<short%> specified together" -#~ msgstr "%<long%> och %<short%> angivna tillsammans" - -#, gcc-internal-format -#~ msgid "defaulted declaration %q+D does not match the expected signature" -#~ msgstr "standarddeklaration %q+D stämmer inte med den förväntade signaturen" - -#, gcc-internal-format -#~ msgid "%q#D references internal linkage entity %q#D" -#~ msgstr "%q#D refererar entiteten %q#D med intern länkning" - -#, gcc-internal-format -#~ msgid "macro debug output may be incomplete with modules" -#~ msgstr "makrofelsökningsutdata kan vara ofullständig med moduler" - -#, gcc-internal-format -#~ msgid "module dependencies require preprocessing" -#~ msgstr "modulberoenden kräver preprocessning" - -#, gcc-internal-format -#~ msgid "you should use the %<-%s%> option" -#~ msgstr "du behöver använda flaggan %<-%s%>" - -#, gcc-internal-format -#~ msgid "%<%T::%D%> names the constructor, not the type" -#~ msgstr "%<%T::%D%> namnger konstrueraren, inte typen" - -#, gcc-internal-format -#~ msgid "import cannot appear directly in a linkage-specification" -#~ msgstr "import får inte förekomma direkt i en länkningsspecifikation" - -#, gcc-internal-format -#~ msgid "extra %<;%>" -#~ msgstr "extra %<;%>" - -#, gcc-internal-format -#~ msgid "use of %<auto%> in template argument only available with %<-fconcepts-ts%>" -#~ msgstr "användning av %<auto%> i mallargument är endast tillgängligt med %<-fconcepts-ts%>" - -#, gcc-internal-format -#~ msgid "template-introductions are not part of C++20 concepts; use %qs to enable" -#~ msgstr "mallintroduktioner är inte en del av C++20 koncept; använd %qs för att aktivera" - -#, gcc-internal-format -#~ msgid "no matching concept for template-introduction" -#~ msgstr "det finns inget matchande koncept för mallintroduktionen" - -#, gcc-internal-format -#~ msgid "explicit specialization of function concept %qD" -#~ msgstr "explicit specialisering av funktionskonceptet %qD" - -#, gcc-internal-format -#~ msgid "specialization of variable concept %q#D" -#~ msgstr "specialisering av variabelkonceptet %q#D" - -#, gcc-internal-format -#~ msgid "explicit instantiation of variable concept %q#D" -#~ msgstr "explicit instansiering av variabelkonceptet %q#D" - -#, gcc-internal-format -#~ msgid "explicit instantiation of function concept %q#D" -#~ msgstr "explicit instansiering av funktionskonceptet %q#D" - -#, gcc-internal-format -#~ msgid "invalid use of %qT in template argument" -#~ msgstr "felaktig användning av %qT i mallargument" - -#, gcc-internal-format -#~ msgid "non-pointer argument to %<__builtin_launder%>" -#~ msgstr "icke-pekar-argument till %<__builtin_launder%>" - -#, gcc-internal-format -#~ msgid "statement-expression in a constant expression" -#~ msgstr "satsuttryck i ett konstant uttryck" - -#, gcc-internal-format, gfc-internal-format -#~ msgid " Included at %s:%d:" -#~ msgstr " Inkluderad vid %s:%d:" - -#, gcc-internal-format -#~ msgid "<During initialization>\n" -#~ msgstr "<Under initiering>\n" - -#, gcc-internal-format, gfc-internal-format -#~ msgid "Program unit at %L has OpenMP device constructs/routines but does not set !$OMP REQUIRES UNIFIED_ADDRESS but other program units do" -#~ msgstr "Programenheten vid %L har OpenMP device-konstruktioner/-rutiner men sätter inte !$OMP REQUIRES UNIFIED_ADDRESS men andra programenheter gör det" - -#, gcc-internal-format, gfc-internal-format -#~ msgid "Program unit at %L has OpenMP device constructs/routines but does not set !$OMP REQUIRES UNIFIED_SHARED_MEMORY but other program units do" -#~ msgstr "Programenheten vid %L har OpenMP device-konstruktioner/-rutiner men sätter inte !$OMP REQUIRES UNIFIED_SHARED_MEMORY men andra programenheter gör det" - -#, gcc-internal-format -#~ msgid "Sorry, !$OMP allocate for variable %qs at %L with SAVE attribute not yet implemented" -#~ msgstr "Ledsen, !$OMP allokering för variabeln %qs vid %L med attributet SAVE stödjs inte ännu" - -#, gcc-internal-format -#~ msgid "%qs specified in 'allocate' clause at %L but not in an explicit privatization clause" -#~ msgstr "%qs angivet i en ”allocate”-klausul vid %L men inte i en explicit privatiseringsklausul" diff --git a/gcc/range-op-float.cc b/gcc/range-op-float.cc index 4719829..dafd9c0 100644 --- a/gcc/range-op-float.cc +++ b/gcc/range-op-float.cc @@ -2899,6 +2899,37 @@ private: } } fop_div; +// Implement fold for a cast from float to an int. +bool +operator_cast::fold_range (irange &, tree, const frange &, + const irange &, relation_trio) const +{ + return false; +} + +// Implement op1_range for a cast from float to an int. +bool +operator_cast::op1_range (frange &, tree, const irange &, + const irange &, relation_trio) const +{ + return false; +} + +// Implement fold for a cast from int to a float. +bool +operator_cast::fold_range (frange &, tree, const irange &, + const frange &, relation_trio) const +{ + return false; +} + +// Implement op1_range for a cast from int to a float. +bool +operator_cast::op1_range (irange &, tree, const frange &, + const frange &, relation_trio) const +{ + return false; +} // Initialize any float operators to the primary table diff --git a/gcc/range-op-mixed.h b/gcc/range-op-mixed.h index bb8e90a..3fb7bff 100644 --- a/gcc/range-op-mixed.h +++ b/gcc/range-op-mixed.h @@ -473,6 +473,15 @@ public: bool fold_range (prange &r, tree type, const irange &op1, const prange &op2, relation_trio rel = TRIO_VARYING) const final override; + bool fold_range (irange &r, tree type, + const frange &lh, + const irange &rh, + relation_trio = TRIO_VARYING) const; + bool fold_range (frange &r, tree type, + const irange &lh, + const frange &rh, + relation_trio = TRIO_VARYING) const; + bool op1_range (irange &r, tree type, const irange &lhs, const irange &op2, relation_trio rel = TRIO_VARYING) const final override; @@ -485,6 +494,15 @@ public: bool op1_range (prange &r, tree type, const irange &lhs, const prange &op2, relation_trio rel = TRIO_VARYING) const final override; + bool op1_range (frange &r, tree type, + const irange &lhs, + const irange &op2, + relation_trio = TRIO_VARYING) const; + bool op1_range (irange &r, tree type, + const frange &lhs, + const frange &op2, + relation_trio = TRIO_VARYING) const; + relation_kind lhs_op1_relation (const irange &lhs, const irange &op1, const irange &op2, relation_kind) const final override; diff --git a/gcc/range-op.cc b/gcc/range-op.cc index 35b3e18..06d357f 100644 --- a/gcc/range-op.cc +++ b/gcc/range-op.cc @@ -164,6 +164,8 @@ dispatch_trio (unsigned lhs, unsigned op1, unsigned op2) // These are the supported dispatch patterns. These map to the parameter list // of the routines in range_operator. Note the last 3 characters are // shorthand for the LHS, OP1, and OP2 range discriminator class. +// Reminder, single operand instructions use the LHS type for op2, even if +// unused. so FLOAT = INT would be RO_FIF. const unsigned RO_III = dispatch_trio (VR_IRANGE, VR_IRANGE, VR_IRANGE); const unsigned RO_IFI = dispatch_trio (VR_IRANGE, VR_FRANGE, VR_IRANGE); @@ -246,6 +248,10 @@ range_op_handler::fold_range (vrange &r, tree type, return m_operator->fold_range (as_a <frange> (r), type, as_a <irange> (lh), as_a <irange> (rh), rel); + case RO_FIF: + return m_operator->fold_range (as_a <frange> (r), type, + as_a <irange> (lh), + as_a <frange> (rh), rel); case RO_PPP: return m_operator->fold_range (as_a <prange> (r), type, as_a <prange> (lh), @@ -292,6 +298,10 @@ range_op_handler::op1_range (vrange &r, tree type, return m_operator->op1_range (as_a <irange> (r), type, as_a <irange> (lhs), as_a <irange> (op2), rel); + case RO_IFF: + return m_operator->op1_range (as_a <irange> (r), type, + as_a <frange> (lhs), + as_a <frange> (op2), rel); case RO_PPP: return m_operator->op1_range (as_a <prange> (r), type, as_a <prange> (lhs), @@ -312,6 +322,10 @@ range_op_handler::op1_range (vrange &r, tree type, return m_operator->op1_range (as_a <frange> (r), type, as_a <irange> (lhs), as_a <frange> (op2), rel); + case RO_FII: + return m_operator->op1_range (as_a <frange> (r), type, + as_a <irange> (lhs), + as_a <irange> (op2), rel); case RO_FFF: return m_operator->op1_range (as_a <frange> (r), type, as_a <frange> (lhs), @@ -761,6 +775,30 @@ range_operator::fold_range (irange &r, tree type, return true; } + +bool +range_operator::fold_range (frange &, tree, const irange &, + const frange &, relation_trio) const +{ + return false; +} + +bool +range_operator::op1_range (irange &, tree, const frange &, + const frange &, relation_trio) const +{ + return false; +} + +bool +range_operator::op1_range (frange &, tree, const irange &, + const irange &, relation_trio) const +{ + return false; +} + + + // The default for op1_range is to return false. bool diff --git a/gcc/range-op.h b/gcc/range-op.h index 594e678..1075786 100644 --- a/gcc/range-op.h +++ b/gcc/range-op.h @@ -86,6 +86,10 @@ public: const irange &lh, const irange &rh, relation_trio = TRIO_VARYING) const; + virtual bool fold_range (frange &r, tree type, + const irange &lh, + const frange &rh, + relation_trio = TRIO_VARYING) const; virtual bool fold_range (prange &r, tree type, const prange &lh, const prange &rh, @@ -146,7 +150,14 @@ public: const irange &lhs, const frange &op2, relation_trio = TRIO_VARYING) const; - + virtual bool op1_range (irange &r, tree type, + const frange &lhs, + const frange &op2, + relation_trio = TRIO_VARYING) const; + virtual bool op1_range (frange &r, tree type, + const irange &lhs, + const irange &op2, + relation_trio = TRIO_VARYING) const; virtual bool op2_range (irange &r, tree type, const irange &lhs, diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b9e39f2..b7e62e8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,106 @@ +2025-05-13 Andrew MacLeod <amacleod@redhat.com> + + * gcc.dg/tree-ssa/vrp124.c: New. + +2025-05-12 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: Add test helper macros. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c: New test. + +2025-05-12 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/sat/sat_arith.h: Add test helper macros. + * gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c: New test. + * gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c: New test. + * gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c: New test. + * gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c: New test. + +2025-05-12 Jason Merrill <jason@redhat.com> + + PR c++/120012 + * g++.dg/abi/base-defaulted2.C: New test. + +2025-05-12 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/120188 + * lib/gm2-dg.exp (gm2-dg-frontend-configure-check): New function. + (gm2-dg-runtest): Add -O2 to the option_list. + * gm2.dg/doc/examples/plugin/fail/assignvalue.mod: New test. + * gm2.dg/doc/examples/plugin/fail/doc-examples-plugin-fail.exp: New test. + +2025-05-12 Thomas Schwinge <tschwinge@baylibre.com> + + * gcc.target/nvptx/march-map=sm_61.c: Adjust. + * gcc.target/nvptx/march-map=sm_62.c: Likewise. + * gcc.target/nvptx/march=sm_61.c: New. + +2025-05-12 Thomas Schwinge <tschwinge@baylibre.com> + + * gcc.target/nvptx/mptx=5.0.c: New. + +2025-05-12 Christophe Lyon <christophe.lyon@linaro.org> + + PR target/116445 + * gcc.target/arm/unsigned-extend-2.c: Fix dg directives. + +2025-05-12 Dongyan Chen <chendongyan@isrc.iscas.ac.cn> + + * gcc.target/riscv/arch-ss-1.c: New test. + * gcc.target/riscv/arch-ss-2.c: New test. + +2025-05-12 Dongyan Chen <chendongyan@isrc.iscas.ac.cn> + + * gcc.target/riscv/arch-zilsd-1.c: New. + * gcc.target/riscv/arch-zilsd-2.c: New. + * gcc.target/riscv/arch-zilsd-3.c: New. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * gcc.target/arm/ivopts.c: Remove test for iwmmxt + * lib/target-supports.exp + (check_effective_target_arm_iwmmxt_ok): Delete. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * gcc.target/arm/mmx-1.c: Removed. + * gcc.target/arm/mmx-2.c: Removed. + * gcc.target/arm/pr64208.c: Removed. + * gcc.target/arm/pr79145.c: Removed. + * gcc.target/arm/pr99724.c: Removed. + * gcc.target/arm/pr99786.c: Removed. + +2025-05-12 Richard Biener <rguenther@suse.de> + + PR testsuite/120222 + * gcc.dg/tree-ssa/gen-vect-28.c: Use noipa on main_1. + +2025-05-12 Jiawei <jiawei@iscas.ac.cn> + + * gcc.target/riscv/arch-52.c: Fix regular expression. + +2025-05-12 Chao-ying Fu <cfu@wavecomp.com> + + * gcc.target/mips/pr54240.c: Scan phiopt2. + 2025-05-11 Jan Hubicka <hubicka@ucw.cz> * gcc.target/i386/pr91446.c: xfail. diff --git a/gcc/testsuite/g++.dg/abi/base-defaulted2.C b/gcc/testsuite/g++.dg/abi/base-defaulted2.C new file mode 100644 index 0000000..9652ae6 --- /dev/null +++ b/gcc/testsuite/g++.dg/abi/base-defaulted2.C @@ -0,0 +1,12 @@ +// { dg-do compile { target c++11 } } +// { dg-additional-options "-fabi-version=20 -Wabi" } + +struct Base { +protected: + Base() = default; + ~Base() = default; +}; + +struct Derived : Base { + void* ptr; // { dg-bogus "offset" } +}; diff --git a/gcc/testsuite/gcc.dg/html-output/missing-semicolon.py b/gcc/testsuite/gcc.dg/html-output/missing-semicolon.py index 8687168..8ac1f14 100644 --- a/gcc/testsuite/gcc.dg/html-output/missing-semicolon.py +++ b/gcc/testsuite/gcc.dg/html-output/missing-semicolon.py @@ -60,7 +60,8 @@ def test_basics(html_tree): pre = diag.find('xhtml:pre', ns) assert pre is not None - assert pre.attrib['class'] == 'gcc-annotated-source' + assert pre.attrib['class'] == 'gcc-generated-patch' + assert pre.text.startswith('--- ') # For reference, here's the generated HTML: """ @@ -76,7 +77,9 @@ def test_basics(html_tree): <div class="gcc-diagnostic-list"> <div class="gcc-diagnostic"> <span class="gcc-message">expected '<span class="gcc-quoted-text">;</span>' before '<span class="gcc-quoted-text">}</span>' token</span> - <pre class="gcc-annotated-source"></pre> + <pre class="gcc-generated-patch"> + [...snip...] + </pre> </div> </div> </body> diff --git a/gcc/testsuite/gcc.dg/plugin/diagnostic-test-metadata-html.c b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-metadata-html.c new file mode 100644 index 0000000..2499e8d --- /dev/null +++ b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-metadata-html.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-fdiagnostics-set-output=experimental-html" } */ +/* { dg-additional-options "-fdiagnostics-show-caret" } */ + +extern char *gets (char *s); + +void test_cwe (void) +{ + char buf[1024]; + gets (buf); +} + +/* Use a Python script to verify various properties about the generated + HTML file: + { dg-final { run-html-pytest diagnostic-test-metadata-html.c "diagnostic-test-metadata-html.py" } } */ diff --git a/gcc/testsuite/gcc.dg/plugin/diagnostic-test-metadata-html.py b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-metadata-html.py new file mode 100644 index 0000000..e475e95 --- /dev/null +++ b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-metadata-html.py @@ -0,0 +1,68 @@ +# Verify that metadata works in HTML output. + +from htmltest import * + +import pytest + +@pytest.fixture(scope='function', autouse=True) +def html_tree(): + return html_tree_from_env() + +XHTML = 'http://www.w3.org/1999/xhtml' +ns = {'xhtml': XHTML} + +def make_tag(local_name): + return f'{{{XHTML}}}' + local_name + +def test_metadata(html_tree): + root = html_tree.getroot () + assert root.tag == make_tag('html') + + body = root.find('xhtml:body', ns) + assert body is not None + + diag_list = body.find('xhtml:div', ns) + assert diag_list is not None + assert diag_list.attrib['class'] == 'gcc-diagnostic-list' + + diag = diag_list.find('xhtml:div', ns) + assert diag is not None + assert diag.attrib['class'] == 'gcc-diagnostic' + + spans = diag.findall('xhtml:span', ns) + metadata = spans[1] + assert metadata.attrib['class'] == 'gcc-metadata' + assert metadata[0].tag == make_tag('span') + assert metadata[0].attrib['class'] == 'gcc-metadata-item' + assert metadata[0].text == '[' + assert metadata[0][0].tag == make_tag('a') + assert metadata[0][0].attrib['href'] == 'https://cwe.mitre.org/data/definitions/242.html' + assert metadata[0][0].text == 'CWE-242' + assert metadata[0][0].tail == ']' + + assert metadata[1].tag == make_tag('span') + assert metadata[1].attrib['class'] == 'gcc-metadata-item' + assert metadata[1].text == '[' + assert metadata[1][0].tag == make_tag('a') + assert metadata[1][0].attrib['href'] == 'https://example.com/' + assert metadata[1][0].text == 'STR34-C' + assert metadata[1][0].tail == ']' + + src = diag.find('xhtml:pre', ns) + assert src.attrib['class'] == 'gcc-annotated-source' + assert src.text == ( + ' gets (buf);\n' + ' ^~~~~~~~~~\n') + +# For reference, here's the generated HTML: +""" + <body> + <div class="gcc-diagnostic-list"> + <div class="gcc-diagnostic"> + <span class="gcc-message">never use '<span class="gcc-quoted-text">gets</span>'</span> + <span class="gcc-metadata"><span class="gcc-metadata-item">[<a href="https://cwe.mitre.org/data/definitions/242.html">CWE-242</a>]</span><span class="gcc-metadata-item">[<a href="https://example.com/">STR34-C</a>]</span></span> + ...etc... + </div> + </div> + </body> +""" diff --git a/gcc/testsuite/gcc.dg/plugin/diagnostic-test-paths-2.c b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-paths-2.c index b8134ae..26605f7 100644 --- a/gcc/testsuite/gcc.dg/plugin/diagnostic-test-paths-2.c +++ b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-paths-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-fdiagnostics-show-caret -fdiagnostics-show-line-numbers -fdiagnostics-path-format=inline-events" } */ +/* { dg-options "-fdiagnostics-show-caret -fdiagnostics-show-line-numbers -fdiagnostics-path-format=inline-events -fdiagnostics-add-output=experimental-html" } */ #include <stddef.h> #include <stdlib.h> @@ -52,3 +52,7 @@ make_a_list_of_random_ints_badly(PyObject *self, | (3) when calling 'PyList_Append', passing NULL from (1) as argument 1 { dg-end-multiline-output "" } */ } + +/* Use a Python script to verify various properties about the generated + HTML file: + { dg-final { run-html-pytest diagnostic-test-paths-2.c "diagnostic-test-paths-2.py" } } */ diff --git a/gcc/testsuite/gcc.dg/plugin/diagnostic-test-paths-2.py b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-paths-2.py new file mode 100644 index 0000000..c212e49 --- /dev/null +++ b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-paths-2.py @@ -0,0 +1,35 @@ +# Verify that execution paths work in HTML output. + +from htmltest import * + +import pytest + +@pytest.fixture(scope='function', autouse=True) +def html_tree(): + return html_tree_from_env() + +XHTML = 'http://www.w3.org/1999/xhtml' +ns = {'xhtml': XHTML} + +def make_tag(local_name): + return f'{{{XHTML}}}' + local_name + +def test_paths(html_tree): + root = html_tree.getroot () + assert root.tag == make_tag('html') + + body = root.find('xhtml:body', ns) + assert body is not None + + diag_list = body.find('xhtml:div', ns) + assert diag_list is not None + assert diag_list.attrib['class'] == 'gcc-diagnostic-list' + + diag = diag_list.find('xhtml:div', ns) + assert diag is not None + assert diag.attrib['class'] == 'gcc-diagnostic' + + pre = diag.findall('xhtml:pre', ns) + assert pre[0].attrib['class'] == 'gcc-annotated-source' + assert pre[1].attrib['class'] == 'gcc-execution-path' + assert pre[1].text.startswith(" 'make_a_list_of_random_ints_badly': events 1-3") diff --git a/gcc/testsuite/gcc.dg/plugin/plugin.exp b/gcc/testsuite/gcc.dg/plugin/plugin.exp index a84fbae..a066b67 100644 --- a/gcc/testsuite/gcc.dg/plugin/plugin.exp +++ b/gcc/testsuite/gcc.dg/plugin/plugin.exp @@ -105,6 +105,7 @@ set plugin_test_list [list \ diagnostic-test-inlining-4.c } \ { diagnostic_plugin_test_metadata.cc diagnostic-test-metadata.c \ + diagnostic-test-metadata-html.c \ diagnostic-test-metadata-sarif.c } \ { diagnostic_plugin_test_nesting.cc \ diagnostic-test-nesting-text-plain.c \ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-28.c b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-28.c index 5c0ea58..4b3ce4e 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-28.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-28.c @@ -9,7 +9,8 @@ /* unaligned store. */ -int main_1 (int off) +int __attribute__((noipa)) +main_1 (int off) { int i; char ia[N+OFF]; diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vrp124.c b/gcc/testsuite/gcc.dg/tree-ssa/vrp124.c new file mode 100644 index 0000000..789b550 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/vrp124.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-evrp" } */ + +/* Test removal of trailing zero mask ranges from signed values. */ +/* Mask off the lower 4 bits of an integer. */ +#define MASK 0XF + +void dead (int c); +void keep(); + +/* A signed character should have a range something like : */ +/* int [-INF, -16][0, 0][16, 2147483632] MASK 0xfffffff0 VALUE 0x0 */ + +int +foo2 (int c) +{ + c = c & ~MASK; + if (c == 0) + return 0; + if (c > -16) + { + keep (); + if (c < 16) + dead (c); + } + if (c > (__INT_MAX__ & ~MASK)) + dead (c); + return 0; +} + +/* { dg-final { scan-tree-dump-not "dead" "evrp" } } */ diff --git a/gcc/testsuite/gcc.target/arm/ivopts.c b/gcc/testsuite/gcc.target/arm/ivopts.c index 582fdab..6e3e74c 100644 --- a/gcc/testsuite/gcc.target/arm/ivopts.c +++ b/gcc/testsuite/gcc.target/arm/ivopts.c @@ -12,5 +12,4 @@ tr5 (short array[], int n) /* { dg-final { scan-tree-dump-times "PHI <" 1 "ivopts"} } */ /* { dg-final { object-size text <= 20 { target { arm_thumb2_no_arm_v8_1m_lob } } } } */ -/* { dg-final { object-size text <= 32 { target { arm_nothumb && { ! arm_iwmmxt_ok } } } } } */ -/* { dg-final { object-size text <= 36 { target { arm_nothumb && arm_iwmmxt_ok } } } } */ +/* { dg-final { object-size text <= 32 { target { arm_nothumb } } } } */ diff --git a/gcc/testsuite/gcc.target/arm/mmx-1.c b/gcc/testsuite/gcc.target/arm/mmx-1.c deleted file mode 100644 index 8060dbd..0000000 --- a/gcc/testsuite/gcc.target/arm/mmx-1.c +++ /dev/null @@ -1,26 +0,0 @@ -/* Verify that if IP is saved to ensure stack alignment, we don't load - it into sp. */ -/* { dg-do compile } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ -/* { dg-options "-O -mno-apcs-frame -mcpu=iwmmxt -mabi=iwmmxt" } */ -/* { dg-require-effective-target arm32 } */ -/* { dg-require-effective-target arm_iwmmxt_ok } */ -/* { dg-final { scan-assembler "push.*ip,\[ ]*pc" } } */ -/* { dg-skip-if "r9 is reserved in FDPIC" { arm*-*-uclinuxfdpiceabi } "*" "" } */ - -/* This function uses all the call-saved registers, namely r4, r5, r6, - r7, r8, r9, sl, fp. Since we also save lr, that leaves an odd - number of registers, and the compiler will push ip to align the - stack. Make sure that we restore ip into ip, not into sp as is - done when using a frame pointer. The -mno-apcs-frame option - permits the frame pointer to be used as an ordinary register. */ - -void -foo(void) -{ - __asm volatile ("" : : : - "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "lr"); -} diff --git a/gcc/testsuite/gcc.target/arm/mmx-2.c b/gcc/testsuite/gcc.target/arm/mmx-2.c deleted file mode 100644 index 0540f65..0000000 --- a/gcc/testsuite/gcc.target/arm/mmx-2.c +++ /dev/null @@ -1,166 +0,0 @@ -/* { dg-do compile } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ -/* { dg-require-effective-target arm32 } */ -/* { dg-require-effective-target arm_iwmmxt_ok } */ -/* { dg-options "-mcpu=iwmmxt -flax-vector-conversions -std=gnu99" } */ - -/* Internal data types for implementing the intrinsics. */ -typedef int __v2si __attribute__ ((vector_size (8))); -typedef short __v4hi __attribute__ ((vector_size (8))); -typedef signed char __v8qi __attribute__ ((vector_size (8))); - -void -foo(void) -{ - volatile int isink; - volatile long long llsink; - volatile __v8qi v8sink; - volatile __v4hi v4sink; - volatile __v2si v2sink; - - isink = __builtin_arm_getwcgr0 (); - __builtin_arm_setwcgr0 (isink); - isink = __builtin_arm_getwcgr1 (); - __builtin_arm_setwcgr1 (isink); - isink = __builtin_arm_getwcgr2 (); - __builtin_arm_setwcgr2 (isink); - isink = __builtin_arm_getwcgr3 (); - __builtin_arm_setwcgr3 (isink); - - isink = __builtin_arm_textrmsb (v8sink, 0); - isink = __builtin_arm_textrmsh (v4sink, 0); - isink = __builtin_arm_textrmsw (v2sink, 0); - isink = __builtin_arm_textrmub (v8sink, 0); - isink = __builtin_arm_textrmuh (v4sink, 0); - isink = __builtin_arm_textrmuw (v2sink, 0); - v8sink = __builtin_arm_tinsrb (v8sink, isink, 0); - v4sink = __builtin_arm_tinsrh (v4sink, isink, 0); - v2sink = __builtin_arm_tinsrw (v2sink, isink, 0); - llsink = __builtin_arm_tmia (llsink, isink, isink); - llsink = __builtin_arm_tmiabb (llsink, isink, isink); - llsink = __builtin_arm_tmiabt (llsink, isink, isink); - llsink = __builtin_arm_tmiaph (llsink, isink, isink); - llsink = __builtin_arm_tmiatb (llsink, isink, isink); - llsink = __builtin_arm_tmiatt (llsink, isink, isink); - isink = __builtin_arm_tmovmskb (v8sink); - isink = __builtin_arm_tmovmskh (v4sink); - isink = __builtin_arm_tmovmskw (v2sink); - llsink = __builtin_arm_waccb (v8sink); - llsink = __builtin_arm_wacch (v4sink); - llsink = __builtin_arm_waccw (v2sink); - v8sink = __builtin_arm_waddb (v8sink, v8sink); - v8sink = __builtin_arm_waddbss (v8sink, v8sink); - v8sink = __builtin_arm_waddbus (v8sink, v8sink); - v4sink = __builtin_arm_waddh (v4sink, v4sink); - v4sink = __builtin_arm_waddhss (v4sink, v4sink); - v4sink = __builtin_arm_waddhus (v4sink, v4sink); - v2sink = __builtin_arm_waddw (v2sink, v2sink); - v2sink = __builtin_arm_waddwss (v2sink, v2sink); - v2sink = __builtin_arm_waddwus (v2sink, v2sink); - v8sink = __builtin_arm_walign (v8sink, v8sink, 0); /* waligni: 3-bit immediate. */ - v8sink = __builtin_arm_walign (v8sink, v8sink, isink); /* walignr: GP register. */ - llsink = __builtin_arm_wand(llsink, llsink); - llsink = __builtin_arm_wandn (llsink, llsink); - v8sink = __builtin_arm_wavg2b (v8sink, v8sink); - v8sink = __builtin_arm_wavg2br (v8sink, v8sink); - v4sink = __builtin_arm_wavg2h (v4sink, v4sink); - v4sink = __builtin_arm_wavg2hr (v4sink, v4sink); - v8sink = __builtin_arm_wcmpeqb (v8sink, v8sink); - v4sink = __builtin_arm_wcmpeqh (v4sink, v4sink); - v2sink = __builtin_arm_wcmpeqw (v2sink, v2sink); - v8sink = __builtin_arm_wcmpgtsb (v8sink, v8sink); - v4sink = __builtin_arm_wcmpgtsh (v4sink, v4sink); - v2sink = __builtin_arm_wcmpgtsw (v2sink, v2sink); - v8sink = __builtin_arm_wcmpgtub (v8sink, v8sink); - v4sink = __builtin_arm_wcmpgtuh (v4sink, v4sink); - v2sink = __builtin_arm_wcmpgtuw (v2sink, v2sink); - llsink = __builtin_arm_wmacs (llsink, v4sink, v4sink); - llsink = __builtin_arm_wmacsz (v4sink, v4sink); - llsink = __builtin_arm_wmacu (llsink, v4sink, v4sink); - llsink = __builtin_arm_wmacuz (v4sink, v4sink); - v4sink = __builtin_arm_wmadds (v4sink, v4sink); - v4sink = __builtin_arm_wmaddu (v4sink, v4sink); - v8sink = __builtin_arm_wmaxsb (v8sink, v8sink); - v4sink = __builtin_arm_wmaxsh (v4sink, v4sink); - v2sink = __builtin_arm_wmaxsw (v2sink, v2sink); - v8sink = __builtin_arm_wmaxub (v8sink, v8sink); - v4sink = __builtin_arm_wmaxuh (v4sink, v4sink); - v2sink = __builtin_arm_wmaxuw (v2sink, v2sink); - v8sink = __builtin_arm_wminsb (v8sink, v8sink); - v4sink = __builtin_arm_wminsh (v4sink, v4sink); - v2sink = __builtin_arm_wminsw (v2sink, v2sink); - v8sink = __builtin_arm_wminub (v8sink, v8sink); - v4sink = __builtin_arm_wminuh (v4sink, v4sink); - v2sink = __builtin_arm_wminuw (v2sink, v2sink); - v4sink = __builtin_arm_wmulsm (v4sink, v4sink); - v4sink = __builtin_arm_wmulul (v4sink, v4sink); - v4sink = __builtin_arm_wmulum (v4sink, v4sink); - llsink = __builtin_arm_wor (llsink, llsink); - v2sink = __builtin_arm_wpackdss (llsink, llsink); - v2sink = __builtin_arm_wpackdus (llsink, llsink); - v8sink = __builtin_arm_wpackhss (v4sink, v4sink); - v8sink = __builtin_arm_wpackhus (v4sink, v4sink); - v4sink = __builtin_arm_wpackwss (v2sink, v2sink); - v4sink = __builtin_arm_wpackwus (v2sink, v2sink); - llsink = __builtin_arm_wrord (llsink, llsink); - llsink = __builtin_arm_wrordi (llsink, isink); - v4sink = __builtin_arm_wrorh (v4sink, llsink); - v4sink = __builtin_arm_wrorhi (v4sink, isink); - v2sink = __builtin_arm_wrorw (v2sink, llsink); - v2sink = __builtin_arm_wrorwi (v2sink, isink); - v2sink = __builtin_arm_wsadb (v2sink, v8sink, v8sink); - v2sink = __builtin_arm_wsadbz (v8sink, v8sink); - v2sink = __builtin_arm_wsadh (v2sink, v4sink, v4sink); - v2sink = __builtin_arm_wsadhz (v4sink, v4sink); - v4sink = __builtin_arm_wshufh (v4sink, 0); - llsink = __builtin_arm_wslld (llsink, llsink); - llsink = __builtin_arm_wslldi (llsink, 0); - v4sink = __builtin_arm_wsllh (v4sink, llsink); - v4sink = __builtin_arm_wsllhi (v4sink, isink); - v2sink = __builtin_arm_wsllw (v2sink, llsink); - v2sink = __builtin_arm_wsllwi (v2sink, isink); - llsink = __builtin_arm_wsrad (llsink, llsink); - llsink = __builtin_arm_wsradi (llsink, isink); - v4sink = __builtin_arm_wsrah (v4sink, llsink); - v4sink = __builtin_arm_wsrahi (v4sink, isink); - v2sink = __builtin_arm_wsraw (v2sink, llsink); - v2sink = __builtin_arm_wsrawi (v2sink, isink); - llsink = __builtin_arm_wsrld (llsink, llsink); - llsink = __builtin_arm_wsrldi (llsink, isink); - v4sink = __builtin_arm_wsrlh (v4sink, llsink); - v4sink = __builtin_arm_wsrlhi (v4sink, isink); - v2sink = __builtin_arm_wsrlw (v2sink, llsink); - v2sink = __builtin_arm_wsrlwi (v2sink, isink); - v8sink = __builtin_arm_wsubb (v8sink, v8sink); - v8sink = __builtin_arm_wsubbss (v8sink, v8sink); - v8sink = __builtin_arm_wsubbus (v8sink, v8sink); - v4sink = __builtin_arm_wsubh (v4sink, v4sink); - v4sink = __builtin_arm_wsubhss (v4sink, v4sink); - v4sink = __builtin_arm_wsubhus (v4sink, v4sink); - v2sink = __builtin_arm_wsubw (v2sink, v2sink); - v2sink = __builtin_arm_wsubwss (v2sink, v2sink); - v2sink = __builtin_arm_wsubwus (v2sink, v2sink); - v4sink = __builtin_arm_wunpckehsb (v8sink); - v2sink = __builtin_arm_wunpckehsh (v4sink); - llsink = __builtin_arm_wunpckehsw (v2sink); - v4sink = __builtin_arm_wunpckehub (v8sink); - v2sink = __builtin_arm_wunpckehuh (v4sink); - llsink = __builtin_arm_wunpckehuw (v2sink); - v4sink = __builtin_arm_wunpckelsb (v8sink); - v2sink = __builtin_arm_wunpckelsh (v4sink); - llsink = __builtin_arm_wunpckelsw (v2sink); - v4sink = __builtin_arm_wunpckelub (v8sink); - v2sink = __builtin_arm_wunpckeluh (v4sink); - llsink = __builtin_arm_wunpckeluw (v2sink); - v8sink = __builtin_arm_wunpckihb (v8sink, v8sink); - v4sink = __builtin_arm_wunpckihh (v4sink, v4sink); - v2sink = __builtin_arm_wunpckihw (v2sink, v2sink); - v8sink = __builtin_arm_wunpckilb (v8sink, v8sink); - v4sink = __builtin_arm_wunpckilh (v4sink, v4sink); - v2sink = __builtin_arm_wunpckilw (v2sink, v2sink); - llsink = __builtin_arm_wxor (llsink, llsink); - llsink = __builtin_arm_wzero (); -} diff --git a/gcc/testsuite/gcc.target/arm/pr64208.c b/gcc/testsuite/gcc.target/arm/pr64208.c deleted file mode 100644 index 96fd56d..0000000 --- a/gcc/testsuite/gcc.target/arm/pr64208.c +++ /dev/null @@ -1,25 +0,0 @@ -/* { dg-do compile } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ -/* { dg-require-effective-target arm32 } */ -/* { dg-require-effective-target arm_iwmmxt_ok } */ -/* { dg-options "-O1 -mcpu=iwmmxt" } */ - -long long x6(void); -void x7(long long, long long); -void x8(long long); - -int x0; -long long *x1; - -void x2(void) { - long long *x3 = x1; - while (x1) { - long long x4 = x0, x5 = x6(); - x7(x4, x5); - x8(x5); - *x3 = 0; - } -} diff --git a/gcc/testsuite/gcc.target/arm/pr79145.c b/gcc/testsuite/gcc.target/arm/pr79145.c deleted file mode 100644 index 6678244..0000000 --- a/gcc/testsuite/gcc.target/arm/pr79145.c +++ /dev/null @@ -1,16 +0,0 @@ -/* { dg-do compile } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ -/* { dg-require-effective-target arm32 } */ -/* { dg-require-effective-target arm_iwmmxt_ok } */ -/* { dg-options "-mcpu=iwmmxt" } */ - -int -main (void) -{ - volatile long long t1; - t1 ^= 0x55; - return 0; -} diff --git a/gcc/testsuite/gcc.target/arm/pr99724.c b/gcc/testsuite/gcc.target/arm/pr99724.c deleted file mode 100644 index 5411078..0000000 --- a/gcc/testsuite/gcc.target/arm/pr99724.c +++ /dev/null @@ -1,31 +0,0 @@ -/* PR target/99724 */ -/* { dg-do compile } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ -/* { dg-require-effective-target arm32 } */ -/* { dg-require-effective-target arm_iwmmxt_ok } */ -/* { dg-options "-O1 -mcpu=iwmmxt" } */ - -typedef int V __attribute__((vector_size (8))); -struct __attribute__((packed)) S { char a; V b; char c[7]; }; - -void -foo (V *x) -{ - *x = ~*x; -} - -void -bar (V *x) -{ - *x = -*x; -} - -void -baz (V *x, struct S *p) -{ - V y = p->b; - *x = y; -} diff --git a/gcc/testsuite/gcc.target/arm/pr99786.c b/gcc/testsuite/gcc.target/arm/pr99786.c deleted file mode 100644 index 11d86f0..0000000 --- a/gcc/testsuite/gcc.target/arm/pr99786.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ -/* { dg-require-effective-target arm32 } */ -/* { dg-require-effective-target arm_iwmmxt_ok } */ -/* { dg-options "-O3 -mcpu=iwmmxt" } */ - -typedef signed char V __attribute__((vector_size (8))); - -void -foo (V *a) -{ - *a = *a * 3; -} - -typedef signed short Vshort __attribute__((vector_size (8))); -void -foo_short (Vshort *a) -{ - *a = *a * 3; -} - -typedef signed int Vint __attribute__((vector_size (8))); -void -foo_int (Vint *a) -{ - *a = *a * 3; -} diff --git a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c index 41ee994..d9f95a1 100644 --- a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c +++ b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c @@ -1,6 +1,31 @@ /* { dg-do compile } */ -/* { dg-require-effective-target arm_thumb2_ok_no_arm_v8_1m_lob } */ -/* { dg-options "-O" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-O2 -mthumb" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** foo: +** movs (r[0-9]+), #8 +** ( +** subs \1, \1, #1 +** ands \1, \1, #255 +** and r0, r1, r0, lsr #1 +** bne .L[0-9]+ +** bx lr +** | +** subs \1, \1, #1 +** and r0, r1, r0, lsr #1 +** ands \1, \1, #255 +** bne .L[0-9]+ +** bx lr +** | +** push {lr} +** dls lr, \1 +** and r0, r1, r0, lsr #1 +** le lr, .L[0-9]+ +** pop {pc} +** ) +*/ unsigned short foo (unsigned short x, unsigned short c) { @@ -12,7 +37,3 @@ unsigned short foo (unsigned short x, unsigned short c) } return x; } - -/* { dg-final { scan-assembler "ands" } } */ -/* { dg-final { scan-assembler-not "uxtb" } } */ -/* { dg-final { scan-assembler-not "cmp" } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_61.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_61.c index 742e25d..d6e8ce9 100644 --- a/gcc/testsuite/gcc.target/nvptx/march-map=sm_61.c +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_61.c @@ -2,7 +2,7 @@ /* { dg-options {-march-map=sm_61 -mptx=_} } */ /* { dg-additional-options -save-temps } */ /* { dg-final { scan-assembler-times {(?n)^ \.version 7\.3$} 1 } } */ -/* { dg-final { scan-assembler-times {(?n)^ \.target sm_53$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_61$} 1 } } */ #if __PTX_ISA_VERSION_MAJOR__ != 7 #error wrong value for __PTX_ISA_VERSION_MAJOR__ @@ -12,7 +12,7 @@ #error wrong value for __PTX_ISA_VERSION_MINOR__ #endif -#if __PTX_SM__ != 530 +#if __PTX_SM__ != 610 #error wrong value for __PTX_SM__ #endif diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_62.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_62.c index 02ced4c..ccce6f7 100644 --- a/gcc/testsuite/gcc.target/nvptx/march-map=sm_62.c +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_62.c @@ -2,7 +2,7 @@ /* { dg-options {-march-map=sm_62 -mptx=_} } */ /* { dg-additional-options -save-temps } */ /* { dg-final { scan-assembler-times {(?n)^ \.version 7\.3$} 1 } } */ -/* { dg-final { scan-assembler-times {(?n)^ \.target sm_53$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_61$} 1 } } */ #if __PTX_ISA_VERSION_MAJOR__ != 7 #error wrong value for __PTX_ISA_VERSION_MAJOR__ @@ -12,7 +12,7 @@ #error wrong value for __PTX_ISA_VERSION_MINOR__ #endif -#if __PTX_SM__ != 530 +#if __PTX_SM__ != 610 #error wrong value for __PTX_SM__ #endif diff --git a/gcc/testsuite/gcc.target/nvptx/march=sm_61.c b/gcc/testsuite/gcc.target/nvptx/march=sm_61.c new file mode 100644 index 0000000..d8bccb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march=sm_61.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march=sm_61 -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.3$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_61$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 3 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 610 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/mptx=5.0.c b/gcc/testsuite/gcc.target/nvptx/mptx=5.0.c new file mode 100644 index 0000000..5d6163e --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/mptx=5.0.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march=sm_30 -mptx=5.0} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 5\.0$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_30$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 5 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 0 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 300 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/riscv/arch-ss-1.c b/gcc/testsuite/gcc.target/riscv/arch-ss-1.c new file mode 100644 index 0000000..8f95737 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-ss-1.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_ssnpm_smnpm_smmpm_sspm_supm -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-ss-2.c b/gcc/testsuite/gcc.target/riscv/arch-ss-2.c new file mode 100644 index 0000000..f1d7724 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-ss-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm -mabi=ilp32d" } */ +int foo() +{ +} +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-1.c b/gcc/testsuite/gcc.target/riscv/arch-zilsd-1.c new file mode 100644 index 0000000..452c04e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-1.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zilsd_zclsd -mabi=ilp32d" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c b/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c new file mode 100644 index 0000000..5d6185d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zilsd -mabi=ilp32d" } */ +int foo() +{ +} +/* { dg-error "'-march=rv64gc_zilsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c b/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c new file mode 100644 index 0000000..3cda120 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zclsd -mabi=ilp32d" } */ +int foo() +{ +} +/* { dg-error "'-march=rv64gc_zclsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64gc_zclsd': zclsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd_zclsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd_zclsd': zclsd extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h index 7db892c..983c9b4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h @@ -123,6 +123,22 @@ vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_ADD_FMT_9(WT, T) \ +void __attribute__((noinline)) \ +vec_sat_u_add_##WT##_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + T max = -1; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + WT val = (WT)x + (WT)y; \ + out[i] = val > max ? max : (T)val; \ + } \ +} +#define DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) DEF_VEC_SAT_U_ADD_FMT_9(WT, T) + #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N) @@ -147,6 +163,21 @@ vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_ADD_FMT_8(T, out, op_1, op_2, N) \ vec_sat_u_add_##T##_fmt_8(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16(T, out, op_1, op_2, N) \ + vec_sat_u_add_uint16_t_##T##_fmt_9(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16(T, out, op_1, op_2, N) + +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32(T, out, op_1, op_2, N) \ + vec_sat_u_add_uint32_t_##T##_fmt_9(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32(T, out, op_1, op_2, N) + +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64(T, out, op_1, op_2, N) \ + vec_sat_u_add_uint64_t_##T##_fmt_9(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64(T, out, op_1, op_2, N) + #define DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM) \ T __attribute__((noinline)) \ vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c new file mode 100644 index 0000000..6e9cbd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint32_t, uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c new file mode 100644 index 0000000..3ab4641 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint64_t, uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c new file mode 100644 index 0000000..57aa772 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint64_t, uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c new file mode 100644 index 0000000..d14fe00 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint16_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c new file mode 100644 index 0000000..240af94 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint32_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c new file mode 100644 index 0000000..706d4f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint64_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c new file mode 100644 index 0000000..06d3ba0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define WT uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 65534, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 9, + }, + { + 0, 1, 2, 65534, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c new file mode 100644 index 0000000..64dbde7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define WT uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 65534, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 9, + }, + { + 0, 1, 2, 65534, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c new file mode 100644 index 0000000..2523126 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint32_t +#define WT uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 9, + }, + { + 0, 1, 1, 4294967294, + 4294967294, 4294967294, 4294967294, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 9, + }, + { + 0, 1, 2, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c new file mode 100644 index 0000000..4cd4817 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define WT uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 254, 255, 9, + }, + { + 0, 1, 1, 254, + 254, 254, 254, 255, + 255, 255, 255, 255, + 255, 255, 255, 9, + }, + { + 0, 1, 2, 254, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c new file mode 100644 index 0000000..6b46465 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define WT uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 254, 255, 9, + }, + { + 0, 1, 1, 254, + 254, 254, 254, 255, + 255, 255, 255, 255, + 255, 255, 255, 9, + }, + { + 0, 1, 2, 254, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c new file mode 100644 index 0000000..4cd4817 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define WT uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 254, 255, 9, + }, + { + 0, 1, 1, 254, + 254, 254, 254, 255, + 255, 255, 255, 255, + 255, 255, 255, 9, + }, + { + 0, 1, 2, 254, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h index c8a135a..2225d30 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h @@ -53,12 +53,34 @@ sat_u_add_##T##_fmt_6 (T x, T y) \ return (T)(x + y) < x ? -1 : (x + y); \ } +#define DEF_SAT_U_ADD_FMT_7(WT, T) \ +T __attribute__((noinline)) \ +sat_u_add_##WT##_##T##_fmt_7(T x, T y) \ +{ \ + T max = -1; \ + WT val = (WT)x + (WT)y; \ + return val > max ? max : (T)val; \ +} +#define DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) DEF_SAT_U_ADD_FMT_7(WT, T) + #define RUN_SAT_U_ADD_FMT_1(T, x, y) sat_u_add_##T##_fmt_1(x, y) #define RUN_SAT_U_ADD_FMT_2(T, x, y) sat_u_add_##T##_fmt_2(x, y) #define RUN_SAT_U_ADD_FMT_3(T, x, y) sat_u_add_##T##_fmt_3(x, y) #define RUN_SAT_U_ADD_FMT_4(T, x, y) sat_u_add_##T##_fmt_4(x, y) #define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y) #define RUN_SAT_U_ADD_FMT_6(T, x, y) sat_u_add_##T##_fmt_6(x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U16(T, x, y) \ + sat_u_add_uint16_t_##T##_fmt_7(x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP(T, x, y) \ + RUN_SAT_U_ADD_FMT_7_FROM_U16(T, x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U32(T, x, y) \ + sat_u_add_uint32_t_##T##_fmt_7(x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP(T, x, y) \ + RUN_SAT_U_ADD_FMT_7_FROM_U32(T, x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U64(T, x, y) \ + sat_u_add_uint64_t_##T##_fmt_7(x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T, x, y) \ + RUN_SAT_U_ADD_FMT_7_FROM_U64(T, x, y) #define DEF_SAT_U_ADD_IMM_FMT_1(T, IMM) \ T __attribute__((noinline)) \ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c new file mode 100644 index 0000000..527f8de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint32_t_uint16_t_fmt_7: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_ADD_FMT_7(uint32_t, uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c new file mode 100644 index 0000000..e9031de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint64_t_uint16_t_fmt_7: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_ADD_FMT_7(uint64_t, uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c new file mode 100644 index 0000000..a71bd2f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint64_t_uint32_t_fmt_7: +** slli\s+[atx][0-9]+,\s*a0,\s*32 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] +** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** sext.w\s+a0,\s*a0 +** ret +*/ +DEF_SAT_U_ADD_FMT_7(uint64_t, uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c new file mode 100644 index 0000000..5892986 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint16_t_uint8_t_fmt_7: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_ADD_FMT_7(uint16_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c new file mode 100644 index 0000000..a42a712 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint32_t_uint8_t_fmt_7: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_ADD_FMT_7(uint32_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c new file mode 100644 index 0000000..f37ef1c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint64_t_uint8_t_fmt_7: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_ADD_FMT_7(uint64_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c new file mode 100644 index 0000000..25dc1d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint16_t +#define WT uint32_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP + +DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 65534, 65534, }, + { 1, 65534, 65535, }, + { 2, 65534, 65535, }, + { 0, 65535, 65535, }, + { 1, 65535, 65535, }, + { 2, 65535, 65535, }, + { 65535, 65535, 65535, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c new file mode 100644 index 0000000..565b108 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint16_t +#define WT uint64_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP + +DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 65534, 65534, }, + { 1, 65534, 65535, }, + { 2, 65534, 65535, }, + { 0, 65535, 65535, }, + { 1, 65535, 65535, }, + { 2, 65535, 65535, }, + { 65535, 65535, 65535, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c new file mode 100644 index 0000000..6ff34fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint32_t +#define WT uint64_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP + +DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 4294967294, 4294967294, }, + { 1, 4294967294, 4294967295, }, + { 2, 4294967294, 4294967295, }, + { 0, 4294967295, 4294967295, }, + { 1, 4294967295, 4294967295, }, + { 2, 4294967295, 4294967295, }, + { 4294967295, 4294967295, 4294967295, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c new file mode 100644 index 0000000..9e6e70a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint8_t +#define WT uint16_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP + +DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 254, 254, }, + { 1, 254, 255, }, + { 2, 254, 255, }, + { 0, 255, 255, }, + { 1, 255, 255, }, + { 2, 255, 255, }, + { 255, 255, 255, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c new file mode 100644 index 0000000..a1134ed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint8_t +#define WT uint32_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP + +DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 254, 254, }, + { 1, 254, 255, }, + { 2, 254, 255, }, + { 0, 255, 255, }, + { 1, 255, 255, }, + { 2, 255, 255, }, + { 255, 255, 255, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c new file mode 100644 index 0000000..ef9f7aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint8_t +#define WT uint64_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP + +DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 254, 254, }, + { 1, 254, 255, }, + { 2, 254, 255, }, + { 0, 255, 255, }, + { 1, 255, 255, }, + { 2, 255, 255, }, + { 255, 255, 255, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gm2.dg/doc/examples/plugin/fail/assignvalue.mod b/gcc/testsuite/gm2.dg/doc/examples/plugin/fail/assignvalue.mod new file mode 100644 index 0000000..56eb0bb --- /dev/null +++ b/gcc/testsuite/gm2.dg/doc/examples/plugin/fail/assignvalue.mod @@ -0,0 +1,25 @@ +(* { dg-do compile } *) +(* { dg-options "-fsoft-check-all -fm2-plugin" } *) +(* { dg-skip-if "" { *-*-* } { "*" } { "-O2" } } *) + +MODULE assignvalue ; (*!m2iso+gm2*) + +PROCEDURE bad () : INTEGER ; +VAR + i: INTEGER ; +BEGIN + i := -1 ; + RETURN i +END bad ; + +VAR + foo: CARDINAL ; +BEGIN + (* The m2rte plugin will detect this as an error, post + optimization. *) + foo := bad () (* { dg-error "error: In program module assignvalue" } *) + (* { dg-begin-multiline-output "" } +runtime error will occur, assignment will cause a range error, as the runtime instance value of 'CARDINAL' does not overlap with the type 'INTEGER' + { dg-end-multiline-output "" } *) + +END assignvalue. diff --git a/gcc/testsuite/gm2.dg/doc/examples/plugin/fail/doc-examples-plugin-fail.exp b/gcc/testsuite/gm2.dg/doc/examples/plugin/fail/doc-examples-plugin-fail.exp new file mode 100644 index 0000000..8a41ff8 --- /dev/null +++ b/gcc/testsuite/gm2.dg/doc/examples/plugin/fail/doc-examples-plugin-fail.exp @@ -0,0 +1,25 @@ +# Compile tests, no torture testing. +# +# These tests should all generate errors if the plugin is available. + +# Load support procs. +load_lib gm2-dg.exp + +gm2_init_pim4 $srcdir/$subdir + +# Initialize `dg'. +dg-init + +# If the --enable-plugin has not been enabled during configure, bail. +if { ![gm2-dg-frontend-configure-check "enable-plugin" ] } { + return +} + +# Main loop. + +set tests [lsort [glob -nocomplain $srcdir/$subdir/*.mod]] + +gm2-dg-runtest $tests "" "" + +# All done. +dg-finish diff --git a/gcc/testsuite/lib/gm2-dg.exp b/gcc/testsuite/lib/gm2-dg.exp index eaed554..5a36507 100644 --- a/gcc/testsuite/lib/gm2-dg.exp +++ b/gcc/testsuite/lib/gm2-dg.exp @@ -65,7 +65,7 @@ proc gm2-dg-runtest { testcases flags default-extra-flags } { if [expr [search_for $test "dg-do run"]] { set option_list $TORTURE_OPTIONS } else { - set option_list [list { -O } ] + set option_list [list { -O -O2 } ] } set nshort [file tail [file dirname $test]]/[file tail $test] @@ -77,3 +77,38 @@ proc gm2-dg-runtest { testcases flags default-extra-flags } { } } + +# Check if frontend has been configured with option. +# This checks a configure build option was used and not +# the availability of a compiler command line option. + +proc gm2-dg-frontend-configure-check { option } { + global GCC_UNDER_TEST + + # ignore any arguments after the command + set compiler [lindex $GCC_UNDER_TEST 0] + + if ![is_remote host] { + set compiler_name [which $compiler] + } else { + set compiler_name $compiler + } + + # verify that the compiler exists + if { $compiler_name != 0 } then { + set tmp [remote_exec host "$compiler -v"] + set status [lindex $tmp 0] + set output [lindex $tmp 1] + regexp "Configured with.*\[\n\r\]" $output config + set option "*${option}*" + if { [string match $option $config] } { + return 1 + } else { + return 0 + } + } else { + # compiler does not exist (this should have already been detected) + warning "$compiler does not exist" + return 0 + } +} diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 24d0b3d..e0495d8 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -7436,19 +7436,6 @@ proc check_effective_target_arm_softfloat { } { }] } -# Return 1 if this is an ARM target supporting -mcpu=iwmmxt. -# Some multilibs may be incompatible with this option. - -proc check_effective_target_arm_iwmmxt_ok { } { - if { [check_effective_target_arm32] } { - return [check_no_compiler_messages arm_iwmmxt_ok object { - int dummy; - } "-mcpu=iwmmxt"] - } else { - return 0 - } -} - # Return true if LDRD/STRD instructions are prefered over LDM/STM instructions # for an ARM target. proc check_effective_target_arm_prefer_ldrd_strd { } { diff --git a/gcc/tree-ssanames.cc b/gcc/tree-ssanames.cc index de7b9b7..fd2abfe 100644 --- a/gcc/tree-ssanames.cc +++ b/gcc/tree-ssanames.cc @@ -488,7 +488,7 @@ set_bitmask (tree name, const wide_int &value, const wide_int &mask) { gcc_assert (!POINTER_TYPE_P (TREE_TYPE (name))); - int_range<2> r (TREE_TYPE (name)); + int_range_max r (TREE_TYPE (name)); r.update_bitmask (irange_bitmask (value, mask)); set_range_info (name, r); } diff --git a/gcc/value-range.cc b/gcc/value-range.cc index a770b41..d2c14e7 100644 --- a/gcc/value-range.cc +++ b/gcc/value-range.cc @@ -2286,7 +2286,7 @@ irange::set_range_from_bitmask () if (has_zero) { int_range<2> zero; - zero.set_zero (type ()); + zero.set_zero (m_type); union_ (zero); } if (flag_checking) @@ -2295,31 +2295,58 @@ irange::set_range_from_bitmask () } else if (popcount == 0) { - set_zero (type ()); + set_zero (m_type); return true; } - // If the mask doesn't have any trailing zero, return. + // If the mask doesn't have a trailing zero, theres nothing to filter. int z = wi::ctz (m_bitmask.mask ()); if (!z) return false; - // Remove trailing ranges that this bitmask indicates can't exist. - int_range_max mask_range; - int prec = TYPE_PRECISION (type ()); - wide_int ub = (wi::one (prec) << z) - 1; - mask_range = int_range<2> (type (), wi::zero (prec), ub); + int prec = TYPE_PRECISION (m_type); + wide_int value = m_bitmask.value (); + wide_int mask = m_bitmask.mask (); - // Then remove the specific value these bits contain from the range. - wide_int value = m_bitmask.value () & ub; - mask_range.intersect (int_range<2> (type (), value, value, VR_ANTI_RANGE)); + // Remove the [0, X] values which the trailing-zero mask rules out. + // For example, if z == 4, the mask is 0xFFF0, and the lowest 4 bits + // define the range [0, 15]. Only one of which (value & low_mask) is allowed. + wide_int ub = (wi::one (prec) << z) - 1; // Upper bound of affected range. + int_range_max mask_range (m_type, wi::zero (prec), ub); - // Inverting produces a list of ranges which can be valid. + // Remove the one valid value from the excluded range and form an anti-range. + wide_int allow = value & ub; + mask_range.intersect (int_range<2> (m_type, allow, allow, VR_ANTI_RANGE)); + + // Invert it to get the allowed values and intersect it with the main range. mask_range.invert (); + bool changed = intersect (mask_range); - // And finally select R from only those valid values. - intersect (mask_range); - return true; + // Now handle the rest of the domain — the upper side for positive values, + // or [-X, -1] for signed negatives. + // Compute the maximum value representable under the mask/value constraint. + ub = mask | value; + + // If value is non-negative, adjust the upper limit to remove values above + // UB that conflict with known fixed bits. + if (TYPE_SIGN (m_type) == UNSIGNED || wi::clz (ub) > 0) + mask_range = int_range<1> (m_type, wi::zero (prec), ub); + else + { + // For signed negative values, find the lowest value with trailing zeros. + // This forms a range such as [-512, -1] for z=9. + wide_int lb = -(wi::one (prec) << z); + mask_range = int_range<2> (m_type, lb, wi::minus_one (prec)); + + // Remove the one allowed value from that set. + allow = value | lb; + mask_range.intersect (int_range<2> (m_type, allow, allow, VR_ANTI_RANGE)); + mask_range.invert (); + } + + // Make sure we call intersect, so do it first. + changed = intersect (mask_range) | changed; + return changed; } void |