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-rw-r--r--gcc/ChangeLog122
-rw-r--r--gcc/DATESTAMP2
-rw-r--r--gcc/Makefile.in1
-rw-r--r--gcc/c/ChangeLog11
-rw-r--r--gcc/config/sol2.h6
-rw-r--r--gcc/cp/ChangeLog25
-rw-r--r--gcc/doc/tm.texi5
-rw-r--r--gcc/doc/tm.texi.in5
-rw-r--r--gcc/testsuite/ChangeLog110
-rw-r--r--gcc/testsuite/g++.dg/lookup/extern-c-redecl3.C8
-rw-r--r--gcc/testsuite/g++.dg/pid_t-1.C3
-rw-r--r--gcc/testsuite/g++.target/riscv/rvv/autovec/pr123074.C (renamed from gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123074.C)0
-rw-r--r--gcc/testsuite/gcc.dg/pid_t-1.c19
-rw-r--r--gcc/testsuite/gcc.target/riscv/rvv/rvv.exp2
14 files changed, 309 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e6da5b8..d4ef4f9 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,125 @@
+2025-12-09 John Ericson <git@JohnEricson.me>
+
+ * Makefile.in: No longer include TARGET_SYSTEM_ROOT in
+ libgcc.mvars.
+
+2025-12-09 John Ericson <git@JohnEricson.me>
+
+ * Makefile.in:: Remove NO_PIE_CFLAGS logic, since it is now in
+ libgcc.
+ * configure: Regenerate.
+ * configure.ac: Remove the enable_default_pie substitution, since
+ libgcc now has its own logic.
+
+2025-12-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR tree-optimization/123074
+ * tree-vect-loop.cc: Reset LOOP_VINFO_USING_SELECT_VL_P.
+
+2025-12-09 Pan Li <pan2.li@intel.com>
+
+ * config/riscv/predicates.md: Append operator lt to
+ the comparison_swappable_operator.
+ * config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Add
+ swappable operator lt handing.
+
+2025-12-09 Richard Biener <rguenther@suse.de>
+
+ PR target/121230
+ * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
+ With FP mode and 387 math cost spill/reload.
+
+2025-12-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ * config/riscv/riscv.opt.urls: Regenerate.
+
+2025-12-09 Andrew Stubbs <ams@baylibre.com>
+
+ * config/gcn/gcn.cc (gcn_init_cumulative_args): Only warn once.
+ Use "required" instead of "enabled" in the warning.
+ * config/gcn/mkoffload.cc (process_asm): Warn, don't error.
+ Use "required" instead of "on" in the warning.
+
+2025-12-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR tree-optimization/122635
+ * gimple-fold.cc (enum mask_load_store_state): New enum.
+ (gimple_fold_partial_load_store_mem_ref): Only fold
+ "all active" loads/stores.
+ (partial_load_store_mask_state): New function to compute mask
+ state.
+ (gimple_fold_partial_load): Remove.
+ (gimple_fold_partial_load_store): New function.
+ (gimple_fold_partial_store): Remove.
+ (gimple_fold_call): Use new function.
+
+2025-12-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ * config/rs6000/predicates.md (lxvl_else_operand): New
+ predicate.
+ * config/rs6000/vsx.md: Add else operand.
+ * config/s390/predicates.md (vll_else_operand): New predicate.
+ * config/s390/vector.md: Add else operand.
+ * doc/md.texi: Document else operand.
+ * internal-fn.cc (internal_fn_len_index): Adjust IFN_LEN_LOAD.
+ (internal_fn_else_index): Add IFN_LEN_LOAD.
+ * optabs-tree.cc (target_supports_len_load_store_p): Get else
+ value for len_load.
+ * tree-vect-stmts.cc (vectorizable_load): Pun the else value
+ type.
+
+2025-12-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::handle_max_vect):
+ New parser entry.
+ (riscv_target_attr_parser::update_settings): Set max-vect
+ option.
+ (riscv_process_one_target_attr): Change null-arg handling.
+ * config/riscv/riscv.cc (riscv_override_options_internal): Set
+ max-vect option.
+ * config/riscv/riscv.opt: Add -mmax-vectorization option.
+ * doc/extend.texi: Document new option.
+ * doc/invoke.texi: Ditto.
+
+2025-12-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/123022
+ * config/riscv/vector.md: Add mode_idx attribute.
+
+2025-12-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/115325
+ * config/riscv/riscv-c.cc (riscv_pragma_target_parse): New
+ function.
+ (riscv_register_pragmas): Register riscv_pragma_target_parse.
+ * config/riscv/riscv-protos.h (riscv_process_target_attr_for_pragma):
+ Declare.
+ (riscv_reset_previous_fndecl): Ditto.
+ * config/riscv/riscv-target-attr.cc (riscv_process_target_attr_for_pragma):
+ New function.
+ * config/riscv/riscv.cc (riscv_reset_previous_fndecl): Reset.
+ (riscv_option_save): New function.
+ (riscv_option_print): Ditto.
+ (riscv_get_interrupt_type): Adjust docs.
+ (TARGET_OPTION_SAVE): Implement.
+ (TARGET_OPTION_PRINT): Ditto.
+ * doc/extend.texi: Document that riscv can do target pragams.
+
+2025-12-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ * config/riscv/autovec.md (reduc_sbool_and_scal_<mode>): New
+ expander.
+ (reduc_sbool_ior_scal_<mode>): Ditto.
+ (reduc_sbool_xor_scal_<mode>): Ditto.
+ * config/riscv/riscv-protos.h (expand_mask_reduction): Declare.
+ * config/riscv/riscv-v.cc (expand_mask_reduction): New function.
+
+2025-12-09 Richard Biener <rguenther@suse.de>
+
+ PR target/123027
+ * config/i386/i386-expand.cc (ix86_expand_sse_fp_minmax):
+ With !HONOR_NANS we can handle LE by swapping and inverting.
+
2025-12-08 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/46555
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4568345..4d0208f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20251209
+20251210
diff --git a/gcc/Makefile.in b/gcc/Makefile.in
index a9264bd..d623145 100644
--- a/gcc/Makefile.in
+++ b/gcc/Makefile.in
@@ -2503,7 +2503,6 @@ libgcc.mvars: config.status Makefile specs xgcc$(exeext)
: > tmp-libgcc.mvars
echo GCC_CFLAGS = '$(GCC_CFLAGS)' >> tmp-libgcc.mvars
echo INHIBIT_LIBC_CFLAGS = '$(INHIBIT_LIBC_CFLAGS)' >> tmp-libgcc.mvars
- echo TARGET_SYSTEM_ROOT = '$(TARGET_SYSTEM_ROOT)' >> tmp-libgcc.mvars
mv tmp-libgcc.mvars libgcc.mvars
diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog
index 5589389..8d3084e 100644
--- a/gcc/c/ChangeLog
+++ b/gcc/c/ChangeLog
@@ -1,3 +1,14 @@
+2025-12-09 Qing Zhao <qing.zhao@oracle.com>
+
+ PR c/122982
+ * c-typeck.cc (build_access_with_size_for_counted_by): Call
+ c_fully_fold on the first parameter.
+
+2025-12-09 Jakub Jelinek <jakub@redhat.com>
+
+ PR c/123018
+ * c-decl.cc (finish_struct): Diagnose bit-fields with vector type.
+
2025-12-05 Richard Biener <rguenther@suse.de>
* gimple-parser.cc (c_parser_gimple_postfix_expression):
diff --git a/gcc/config/sol2.h b/gcc/config/sol2.h
index 4e3199d..026d363 100644
--- a/gcc/config/sol2.h
+++ b/gcc/config/sol2.h
@@ -41,6 +41,12 @@ along with GCC; see the file COPYING3. If not see
#undef WINT_TYPE_SIZE
#define WINT_TYPE_SIZE 32
+/* Same for pid_t. See SCD 2.4.2, p. 6P-12, Figure 6-59 (64-bit). There's
+ no corresponding 32-bit definition, but this is what Solaris 8
+ <sys/types.h> uses. */
+
+#define PID_TYPE (TARGET_64BIT ? "int" : "long int")
+
#define SIG_ATOMIC_TYPE "int"
/* ??? This definition of int8_t follows the system header but does
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index b4c2b70..bc8bb88 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,28 @@
+2025-12-09 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ Revert:
+ 2025-12-09 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ PR c++/122819
+ * decl.cc (start_preparsed_function): Use
+ DECL_TEMPLOID_INSTANTIATION instead of
+ DECL_TEMPLATE_INSTANTIATION to check vague linkage.
+ * decl2.cc (vague_linkage_p): Likewise.
+ (c_parse_final_cleanups): Simplify condition.
+ * semantics.cc (expand_or_defer_fn_1): Also check for temploid
+ friend functions.
+
+2025-12-09 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ PR c++/122819
+ * decl.cc (start_preparsed_function): Use
+ DECL_TEMPLOID_INSTANTIATION instead of
+ DECL_TEMPLATE_INSTANTIATION to check vague linkage.
+ * decl2.cc (vague_linkage_p): Likewise.
+ (c_parse_final_cleanups): Simplify condition.
+ * semantics.cc (expand_or_defer_fn_1): Also check for temploid
+ friend functions.
+
2025-12-08 Egas Ribeiro <egas.g.ribeiro@tecnico.ulisboa.pt>
* pt.cc (tsubst_expr): Add TARGET_EXPR case with explanatory
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 25aad2e..bbb1182 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -1825,6 +1825,7 @@ int}.
@defmacx UINT_FAST64_TYPE
@defmacx INTPTR_TYPE
@defmacx UINTPTR_TYPE
+@defmacx PID_TYPE
C expressions for the standard types @code{sig_atomic_t},
@code{int8_t}, @code{int16_t}, @code{int32_t}, @code{int64_t},
@code{uint8_t}, @code{uint16_t}, @code{uint32_t}, @code{uint64_t},
@@ -1833,8 +1834,8 @@ C expressions for the standard types @code{sig_atomic_t},
@code{uint_least32_t}, @code{uint_least64_t}, @code{int_fast8_t},
@code{int_fast16_t}, @code{int_fast32_t}, @code{int_fast64_t},
@code{uint_fast8_t}, @code{uint_fast16_t}, @code{uint_fast32_t},
-@code{uint_fast64_t}, @code{intptr_t}, and @code{uintptr_t}. See
-@code{SIZE_TYPE} above for more information.
+@code{uint_fast64_t}, @code{intptr_t}, and @code{uintptr_t} and the
+built-in type @code{pid_t}. See @code{SIZE_TYPE} above for more information.
If any of these macros evaluates to a null pointer, the corresponding
type is not supported; if GCC is configured to provide
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 24d47b1..253965b 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -1553,6 +1553,7 @@ int}.
@defmacx UINT_FAST64_TYPE
@defmacx INTPTR_TYPE
@defmacx UINTPTR_TYPE
+@defmacx PID_TYPE
C expressions for the standard types @code{sig_atomic_t},
@code{int8_t}, @code{int16_t}, @code{int32_t}, @code{int64_t},
@code{uint8_t}, @code{uint16_t}, @code{uint32_t}, @code{uint64_t},
@@ -1561,8 +1562,8 @@ C expressions for the standard types @code{sig_atomic_t},
@code{uint_least32_t}, @code{uint_least64_t}, @code{int_fast8_t},
@code{int_fast16_t}, @code{int_fast32_t}, @code{int_fast64_t},
@code{uint_fast8_t}, @code{uint_fast16_t}, @code{uint_fast32_t},
-@code{uint_fast64_t}, @code{intptr_t}, and @code{uintptr_t}. See
-@code{SIZE_TYPE} above for more information.
+@code{uint_fast64_t}, @code{intptr_t}, and @code{uintptr_t} and the
+built-in type @code{pid_t}. See @code{SIZE_TYPE} above for more information.
If any of these macros evaluates to a null pointer, the corresponding
type is not supported; if GCC is configured to provide
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f8a8fba..e80759b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,113 @@
+2025-12-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR tree-optimization/123074
+ * gcc.target/riscv/rvv/rvv.exp: Include *.C.
+ * gcc.target/riscv/rvv/autovec/pr123074.C: New test.
+
+2025-12-09 Qing Zhao <qing.zhao@oracle.com>
+
+ PR c/122982
+ * gcc.dg/pointer-counted-by-pr122982.c: New test.
+
+2025-12-09 Pan Li <pan2.li@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
+ for vmslt.vx.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
+ helper macros.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
+ data for run test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i16.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i32.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i64.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i8.c: New test.
+
+2025-12-09 Richard Biener <rguenther@suse.de>
+
+ PR target/121230
+ * gcc.target/i386/pr121230.c: New testcase.
+
+2025-12-09 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ Revert:
+ 2025-12-09 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ PR c++/122819
+ * g++.dg/modules/tpl-friend-22.C: New test.
+
+2025-12-09 Jakub Jelinek <jakub@redhat.com>
+
+ PR c/123018
+ * gcc.dg/pr123018.c: New test.
+
+2025-12-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR tree-optimization/122635
+ * gcc.target/aarch64/sve/pfalse-store.c: Expect more elided
+ stores.
+ * gcc.target/riscv/rvv/autovec/pr122635-1.c: New test.
+ * gcc.target/riscv/rvv/autovec/pr122635-2.c: New test.
+ * gcc.target/powerpc/p9-vec-length-epil-8.c: Expect two lxvl
+ less.
+
+2025-12-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ * gcc.target/riscv/rvv/autovec/max-vect-1.c: New test.
+ * gcc.target/riscv/rvv/autovec/max-vect-2.c: New test.
+
+2025-12-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/123022
+ * gcc.target/riscv/rvv/autovec/pr123022-2.c: New test.
+ * gcc.target/riscv/rvv/autovec/pr123022.c: New test.
+
+2025-12-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/115325
+ * gcc.target/riscv/pragma-target-1.c: New test.
+ * gcc.target/riscv/pragma-target-2.c: New test.
+
+2025-12-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8.c: New test.
+
+2025-12-09 Richard Biener <rguenther@suse.de>
+
+ PR target/123027
+ * gcc.target/i386/pr123027.c: New testcase.
+ * gcc.dg/torture/pr123027.c: Likewise.
+
+2025-12-09 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ PR c++/122819
+ * g++.dg/modules/tpl-friend-22.C: New test.
+
2025-12-08 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/46555
diff --git a/gcc/testsuite/g++.dg/lookup/extern-c-redecl3.C b/gcc/testsuite/g++.dg/lookup/extern-c-redecl3.C
index 56dcefa..c9c9bd5 100644
--- a/gcc/testsuite/g++.dg/lookup/extern-c-redecl3.C
+++ b/gcc/testsuite/g++.dg/lookup/extern-c-redecl3.C
@@ -5,17 +5,19 @@
// { dg-final { scan-assembler-not "call\[\t \]+\[^\$\]*?_Z4forkv" { target i?86-*-* x86_64-*-* } } }
// { dg-final { scan-assembler "call\[\t \]+_?fork" { target i?86-*-* x86_64-*-* } } }
-extern "C" int fork (void);
+typedef __typeof (__builtin_fork ()) pid_t;
+
+extern "C" pid_t fork (void);
void
foo ()
{
- extern int fork (void);
+ extern pid_t fork (void);
fork ();
}
extern "C"
-int
+pid_t
fork (void)
{
return 0;
diff --git a/gcc/testsuite/g++.dg/pid_t-1.C b/gcc/testsuite/g++.dg/pid_t-1.C
new file mode 100644
index 0000000..cb32eb4
--- /dev/null
+++ b/gcc/testsuite/g++.dg/pid_t-1.C
@@ -0,0 +1,3 @@
+/* { dg-options "-Wall" } */
+
+extern "C" int fork (void); // { dg-warning "conflicts with built-in declaration" "" { target { *-*-solaris2* && ilp32 } } }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123074.C b/gcc/testsuite/g++.target/riscv/rvv/autovec/pr123074.C
index d203477..d203477 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123074.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/autovec/pr123074.C
diff --git a/gcc/testsuite/gcc.dg/pid_t-1.c b/gcc/testsuite/gcc.dg/pid_t-1.c
new file mode 100644
index 0000000..f4f3f68
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pid_t-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-Wall" } */
+/* { dg-require-fork "" } */
+
+/* Compile with -Wall to get a warning if built-in and system pid_t don't
+ match. */
+
+#include <sys/types.h>
+
+typedef __typeof (__builtin_fork ()) __builtin_pid_t;
+
+__builtin_pid_t __p_t__;
+pid_t *p_t_p;
+
+void
+pt (void)
+{
+ p_t_p = &__p_t__;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index e128b17..877cc55 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -47,7 +47,7 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xandesvector/*.\[cS\]]] \
"" $CFLAGS
gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
"" $CFLAGS
-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cCS\]]] \
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \
"-O3 -ftree-vectorize" $CFLAGS
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls/*.\[cS\]]] \
"-O3 -ftree-vectorize -mrvv-vector-bits=scalable" $CFLAGS
generated by cgit v1.1 at 2025-12-10 22:34:24 +0000