diff options
Diffstat (limited to 'gcc')
70 files changed, 886 insertions, 92 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1181667..407faa7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,169 @@ +2025-07-07 Qing Zhao <qing.zhao@oracle.com> + + Revert: + 2025-07-07 Qing Zhao <qing.zhao@oracle.com> + + * doc/extend.texi: Extend counted_by attribute to pointer fields in + structures. Add one more requirement to pointers with counted_by + attribute. + +2025-07-07 Qing Zhao <qing.zhao@oracle.com> + + Revert: + 2025-07-01 Qing Zhao <qing.zhao@oracle.com> + + * tree-object-size.cc (access_with_size_object_size): Update comments + for pointers with .ACCESS_WITH_SIZE. + (collect_object_sizes_for): Propagate size info through GIMPLE_ASSIGN + for pointers with .ACCESS_WITH_SIZE. + +2025-07-07 Martin Jambor <mjambor@suse.cz> + + * value-range.h (class irange): Mark member function verify_range + with override. + (class prange): Mark member function verify_range with final override. + (class frange): Mark member function verify_range with override. + +2025-07-07 H.J. Lu <hjl.tools@gmail.com> + + PR target/120888 + * config/xtensa/xtensa.cc (xtensa_promote_function_mode): New. + (TARGET_PROMOTE_FUNCTION_MODE): Use. + (TARGET_PROMOTE_PROTOTYPES): Removed. + +2025-07-07 Juergen Christ <jchrist@linux.ibm.com> + + * config/s390/s390.md: Update UNSPECs + * config/s390/vector.md (fmax<mode>3): New expander. + (fmin<mode>3): New expander. + * config/s390/vx-builtins.md (*fmin<mode>): New insn. + (vfmin<mode>): Redefined to use new insn. + (*fmax<mode>): New insn. + (vfmax<mode>): Redefined to use new insn. + +2025-07-07 Jason Merrill <jason@redhat.com> + + PR c++/120917 + * doc/invoke.texi: Add -Wno-abbreviated-auto-in-template-arg. + +2025-07-07 Kyrylo Tkachov <ktkachov@nvidia.com> + + * config/aarch64/aarch64.md (popcountti2): Add TARGET_SVE path. + +2025-07-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/120817 + * tree-ssa-dse.cc (initialize_ao_ref_for_dse): Use + ao_ref_init_from_ptr_and_range with unknown size for + .MASK_STORE and .MASK_LEN_STORE. + +2025-07-07 Pan Li <pan2.li@intel.com> + + * config/riscv/riscv-protos.h (riscv_expand_usmul): Add new func + decl. + * config/riscv/riscv.cc (riscv_expand_xmode_usmul): Add new func + to expand Xmode SAT_MUL. + (riscv_expand_non_xmode_usmul): Ditto but for non-Xmode. + (riscv_expand_usmul): Add new func to implment SAT_MUL. + * config/riscv/riscv.md (usmul<mode>3): Add new pattern to match + standard name usmul. + +2025-07-07 Pan Li <pan2.li@intel.com> + + * match.pd: Add new match pattern for unsigned SAT_MUL. + * tree-ssa-math-opts.cc (gimple_unsigned_integer_sat_mul): + new decl for pattern match func. + (match_unsigned_saturation_mul): Add new func to match unsigned + SAT_MUL. + (math_opts_dom_walker::after_dom_children): Try to match + unsigned SAT_MUL on NOP. + +2025-07-07 Pan Li <pan2.li@intel.com> + + * internal-fn.cc (commutative_binary_fn_p): Add new case + for SAT_MUL. + * internal-fn.def (SAT_MUL): Add new IFN_SAT_MUL. + * optabs.def (OPTAB_NL): Remove fixed point limitation. + +2025-07-07 Juergen Christ <jchrist@linux.ibm.com> + + * config/s390/s390.md: Removed unused unspecs. + * config/s390/vector.md (avg<mode>3_ceil): New expander. + (uavg<mode>3_ceil): New expander. + (smul<mode>3_highpart): New expander. + (umul<mode>3_highpart): New expander. + * config/s390/vx-builtins.md (vec_umulh<mode>): Remove unspec. + (vec_smulh<mode>): Remove unspec. + +2025-07-07 Spencer Abson <spencer.abson@arm.com> + + * config/aarch64/aarch64-sve.md (vec_cmp<mode><vpred>): Extend + to handle partial FP modes. + (@aarch64_pred_fcm<cmp_op><mode>): Likewise. + (@aarch64_pred_fcmuo<mode>): Likewise. + (*one_cmpl<mode>3): Rename to... + (@aarch64_pred_one_cmpl<mode>_z): ... this. + * config/aarch64/aarch64.cc (aarch64_emit_sve_fp_cond): Allow the + target and governing predicates to have different modes. + (aarch64_emit_sve_or_fp_conds): Likewise. + (aarch64_emit_sve_invert_fp_cond): Likewise. + (aarch64_expand_sve_vec_cmp_float): Likewise. + +2025-07-07 Richard Sandiford <richard.sandiford@arm.com> + + PR tree-optimization/118891 + * tree-vect-stmts.cc (supportable_widening_operation): Swap the + hi and lo internal functions on big-endian targets. + +2025-07-07 Richard Sandiford <richard.sandiford@arm.com> + + * ext-dce.cc (ext_dce_process_uses): Apply is_constant directly + to the subreg_lsb. + +2025-07-07 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve.md (@aarch64_sve_set_neonq_<mode>): + Use %Z instead of lowpart_subreg. Tweak formatting. + +2025-07-07 Richard Sandiford <richard.sandiford@arm.com> + + PR target/118891 + * config/aarch64/aarch64.cc (aarch64_expand_vector_init): Fix the + ZIP1 operand order for big-endian targets. + +2025-07-07 Jan Hubicka <hubicka@ucw.cz> + + * tree-ssa-live.cc (dump_scope_block): Print discriminators + of inlined functions. + +2025-07-07 H.J. Lu <hjl.tools@gmail.com> + + PR target/120670 + PR target/120683 + * config/i386/i386-expand.cc (expand_set_or_cpymem_via_loop): + Don't generate the loop if the loop count is 1. + (expand_cpymem_epilogue): Use move_by_pieces. + (setmem_epilogue_gen_val): New. + (expand_setmem_epilogue): Use store_by_pieces. + (expand_small_cpymem_or_setmem): Choose cpymem mode from MOVE_MAX. + For memset with vector and the size is smaller than the vector + size, first try the narrower vector, otherwise, use the scalar + value. + (promote_duplicated_reg): Duplicate the scalar value for vector. + (ix86_expand_set_or_cpymem): Always expand vector-version of + memset for vector_loop. Use misaligned prologue if alignment + isn't needed and destination isn't aligned. Always initialize + vec_promoted_val from the promoted scalar value for vector_loop. + +2025-07-07 Andrew Pinski <quic_apinski@quicinc.com> + + PR middle-end/120709 + * builtins.cc (expand_builtin_crc_table_based): Error out + instead of asserting the 3rd argument is an integer constant. + * internal-fn.cc (expand_crc_optab_fn): Likewise. + * doc/extend.texi (crc): Document requirement of the poly argument + being a constant. + 2025-07-06 Georg-Johann Lay <avr@gjlay.de> * config/avr/avr-mcus.def: -mmcu= takes lower case MCU names. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index d4353d1..7475f8c 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20250707 +20250708 diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index bef9a0e..54dcb52 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,37 @@ +2025-07-07 Qing Zhao <qing.zhao@oracle.com> + + Revert: + 2025-07-01 Qing Zhao <qing.zhao@oracle.com> + + * c-attribs.cc (handle_counted_by_attribute): Accept counted_by + attribute for pointer fields. + +2025-07-07 Qing Zhao <qing.zhao@oracle.com> + + Revert: + 2025-07-01 Qing Zhao <qing.zhao@oracle.com> + + * c-gimplify.cc (is_address_with_access_with_size): New function. + (ubsan_walk_array_refs_r): Instrument an INDIRECT_REF whose base + address is .ACCESS_WITH_SIZE or an address computation whose base + address is .ACCESS_WITH_SIZE. + * c-ubsan.cc (ubsan_instrument_bounds_pointer_address): New function. + (struct factor_t): New structure. + (get_factors_from_mul_expr): New function. + (get_index_from_offset): New function. + (get_index_from_pointer_addr_expr): New function. + (is_instrumentable_pointer_array_address): New function. + (ubsan_array_ref_instrumented_p): Change prototype. + Handle MEM_REF in addtional to ARRAY_REF. + (ubsan_maybe_instrument_array_ref): Handle MEM_REF in addtional + to ARRAY_REF. + +2025-07-07 Jason Merrill <jason@redhat.com> + + PR c++/120917 + * c.opt: Add -Wno-abbreviated-auto-in-template-arg. + * c.opt.urls: Regenerate. + 2025-07-04 Jakub Jelinek <jakub@redhat.com> PR c/120837 diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index cb69b8c..dcef284 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,20 @@ +2025-07-07 Qing Zhao <qing.zhao@oracle.com> + + Revert: + 2025-07-07 Qing Zhao <qing.zhao@oracle.com> + + * c-decl.cc (verify_counted_by_attribute): Change the 2nd argument + to a vector of fields with counted_by attribute. Verify all fields + in this vector. + (finish_struct): Collect all the fields with counted_by attribute + to a vector and pass this vector to verify_counted_by_attribute. + * c-typeck.cc (build_counted_by_ref): Handle pointers with counted_by. + Add one more argument, issue error when the pointee type is a structure + or union including a flexible array member. + (build_access_with_size_for_counted_by): Handle pointers with counted_by. + (handle_counted_by_for_component_ref): Call build_counted_by_ref + with the new prototype. + 2025-07-01 Qing Zhao <qing.zhao@oracle.com> * c-decl.cc (verify_counted_by_attribute): Change the 2nd argument diff --git a/gcc/config.gcc b/gcc/config.gcc index a6f6efe..5953ace 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -5894,7 +5894,7 @@ esac # distinguish VxWorks variants such as VxWorks 7 or 64). case ${target} in -arm*-*-* | i[34567]86-*-* | mips*-*-* | powerpc*-*-* | sh*-*-* \ +aarch64*-*-* | arm*-*-* | i[34567]86-*-* | mips*-*-* | powerpc*-*-* | sh*-*-* \ | sparc*-*-* | x86_64-*-*) tm_file="vxworks-dummy.h ${tm_file}" ;; diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index b64175d..ad7360e 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -6526,7 +6526,7 @@ output_set_got (rtx dest, rtx label) xops[0] = dest; - if (TARGET_VXWORKS_RTP && flag_pic) + if (TARGET_VXWORKS_GOTTPIC && TARGET_VXWORKS_RTP && flag_pic) { /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */ xops[2] = gen_rtx_MEM (Pmode, @@ -12245,7 +12245,7 @@ legitimize_pic_address (rtx orig, rtx reg) else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0) /* We can't always use @GOTOFF for text labels on VxWorks, see gotoff_operand. */ - || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF)) + || (TARGET_VXWORKS_VAROFF && GET_CODE (addr) == LABEL_REF)) { #if TARGET_PECOFF rtx tmp = legitimize_pe_coff_symbol (addr, true); @@ -13472,7 +13472,7 @@ ix86_delegitimize_address_1 (rtx x, bool base_term_p) else if (base_term_p && pic_offset_table_rtx && !TARGET_MACHO - && !TARGET_VXWORKS_RTP) + && !TARGET_VXWORKS_VAROFF) { rtx tmp = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME); tmp = gen_rtx_MINUS (Pmode, copy_rtx (addend), tmp); @@ -15872,7 +15872,7 @@ ix86_output_addr_diff_elt (FILE *file, int value, int rel) gcc_assert (!TARGET_64BIT); #endif /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */ - if (TARGET_64BIT || TARGET_VXWORKS_RTP) + if (TARGET_64BIT || TARGET_VXWORKS_VAROFF) fprintf (file, "%s%s%d-%s%d\n", directive, LPREFIX, value, LPREFIX, rel); #if TARGET_MACHO @@ -26295,6 +26295,65 @@ ix86_vector_costs::finish_cost (const vector_costs *scalar_costs) && LOOP_VINFO_VECT_FACTOR (loop_vinfo).to_constant () >= 16) m_suggested_epilogue_mode = V8QImode; + /* When X86_TUNE_AVX512_MASKED_EPILOGUES is enabled try to use + a masked epilogue if that doesn't seem detrimental. */ + if (loop_vinfo + && !LOOP_VINFO_EPILOGUE_P (loop_vinfo) + && LOOP_VINFO_VECT_FACTOR (loop_vinfo).to_constant () > 2 + && ix86_tune_features[X86_TUNE_AVX512_MASKED_EPILOGUES] + && !OPTION_SET_P (param_vect_partial_vector_usage)) + { + bool avoid = false; + if (LOOP_VINFO_NITERS_KNOWN_P (loop_vinfo) + && LOOP_VINFO_PEELING_FOR_ALIGNMENT (loop_vinfo) >= 0) + { + unsigned int peel_niter + = LOOP_VINFO_PEELING_FOR_ALIGNMENT (loop_vinfo); + if (LOOP_VINFO_PEELING_FOR_GAPS (loop_vinfo)) + peel_niter += 1; + /* When we know the number of scalar iterations of the epilogue, + avoid masking when a single vector epilog iteration handles + it in full. */ + if (pow2p_hwi ((LOOP_VINFO_INT_NITERS (loop_vinfo) - peel_niter) + % LOOP_VINFO_VECT_FACTOR (loop_vinfo).to_constant ())) + avoid = true; + } + if (!avoid && loop_outer (loop_outer (LOOP_VINFO_LOOP (loop_vinfo)))) + for (auto ddr : LOOP_VINFO_DDRS (loop_vinfo)) + { + if (DDR_ARE_DEPENDENT (ddr) == chrec_known) + ; + else if (DDR_ARE_DEPENDENT (ddr) == chrec_dont_know) + ; + else + { + int loop_depth + = index_in_loop_nest (LOOP_VINFO_LOOP (loop_vinfo)->num, + DDR_LOOP_NEST (ddr)); + if (DDR_NUM_DIST_VECTS (ddr) == 1 + && DDR_DIST_VECTS (ddr)[0][loop_depth] == 0) + { + /* Avoid the case when there's an outer loop that might + traverse a multi-dimensional array with the inner + loop just executing the masked epilogue with a + read-write where the next outer iteration might + read from the masked part of the previous write, + 'n' filling half a vector. + for (j = 0; j < m; ++j) + for (i = 0; i < n; ++i) + a[j][i] = c * a[j][i]; */ + avoid = true; + break; + } + } + } + if (!avoid) + { + m_suggested_epilogue_mode = loop_vinfo->vector_mode; + m_masked_epilogue = 1; + } + } + vector_costs::finish_cost (scalar_costs); } diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 21b9f5c..5825aca 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -20102,7 +20102,7 @@ /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */ - if (TARGET_64BIT || TARGET_VXWORKS_RTP) + if (TARGET_64BIT || TARGET_VXWORKS_VAROFF) { code = PLUS; op0 = operands[0]; @@ -20970,7 +20970,7 @@ (clobber (reg:CC FLAGS_REG))])] "!TARGET_64BIT" { - if (flag_pic && !TARGET_VXWORKS_RTP) + if (flag_pic && !TARGET_VXWORKS_GOTTPIC) ix86_pc_thunk_call_expanded = true; }) @@ -20991,7 +20991,7 @@ (clobber (reg:CC FLAGS_REG))])] "!TARGET_64BIT" { - if (flag_pic && !TARGET_VXWORKS_RTP) + if (flag_pic && !TARGET_VXWORKS_GOTTPIC) ix86_pc_thunk_call_expanded = true; }) diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 1bd63b2..3afaf83 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -664,8 +664,9 @@ ;; same segment as the GOT. Unfortunately, the flexibility of linker ;; scripts means that we can't be sure of that in general, so assume ;; @GOTOFF is not valid on VxWorks, except with the large code model. +;; The comments above seem to apply only to VxWorks releases before 7. (define_predicate "gotoff_operand" - (and (ior (not (match_test "TARGET_VXWORKS_RTP")) + (and (ior (not (match_test "TARGET_VXWORKS_VAROFF")) (match_test "ix86_cmodel == CM_LARGE") (match_test "ix86_cmodel == CM_LARGE_PIC")) (match_operand 0 "local_symbolic_operand"))) diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 91cdca7..4773e5d 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -639,6 +639,11 @@ DEF_TUNE (X86_TUNE_AVX512_STORE_BY_PIECES, "avx512_store_by_pieces", DEF_TUNE (X86_TUNE_AVX512_TWO_EPILOGUES, "avx512_two_epilogues", m_ZNVER4 | m_ZNVER5) +/* X86_TUNE_AVX512_MAKED_EPILOGUES: Use two masked vector epilogues + when fit. */ +DEF_TUNE (X86_TUNE_AVX512_MASKED_EPILOGUES, "avx512_masked_epilogues", + m_ZNVER4 | m_ZNVER5) + /*****************************************************************************/ /*****************************************************************************/ /* Historical relics: tuning flags that helps a specific old CPU designs */ diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index a5ab8dd..22d1949 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -408,7 +408,7 @@ emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) gcc_assert (!can_create_pseudo_p ()); machine_mode mode = GET_MODE (ops[0]); - if (imm_avl_p (mode)) + if (imm_avl_p (mode) && !TARGET_XTHEADVECTOR) { /* Even though VL is a real hardreg already allocated since it is post-RA now, we still gain benefits that we emit diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index f652a12..8810af0 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -4977,6 +4977,12 @@ registered_function::overloaded_hash () const for (unsigned int i = 0; i < argument_types.length (); i++) { type = argument_types[i]; + + /* If we're passed something entirely unreasonable, just ignore here. + We'll warn later anyway. */ + if (TREE_CODE_CLASS (TREE_CODE (type)) != tcc_type) + continue; + unsigned_p = POINTER_TYPE_P (type) ? TYPE_UNSIGNED (TREE_TYPE (type)) : TYPE_UNSIGNED (type); mode_p = POINTER_TYPE_P (type) ? TYPE_MODE (TREE_TYPE (type)) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index a75ea68..50ec8b3 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -627,7 +627,7 @@ (match_operand:SHORT 1 "memory_operand" "+A")) ;; memory (set (match_dup 1) (unspec_volatile:SHORT [(match_operand:SHORT 2 "register_operand" "0") ;; expected_val - (match_operand:SHORT 3 "register_operand" "rJ") ;; desired_val + (match_operand:SHORT 3 "reg_or_0_operand" "rJ") ;; desired_val (match_operand:SI 4 "const_int_operand") ;; mod_s (match_operand:SI 5 "const_int_operand")] ;; mod_f UNSPEC_COMPARE_AND_SWAP))] diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index f6db36e..02bc149 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -308,6 +308,9 @@ UNSPECV_SPLIT_STACK_CALL UNSPECV_OSC_BREAK + + ; Stack Protector + UNSPECV_SP_GET_TP ]) ;; @@ -365,6 +368,9 @@ (VR23_REGNUM 45) (VR24_REGNUM 46) (VR31_REGNUM 53) + ; Access registers + (AR0_REGNUM 36) + (AR1_REGNUM 37) ]) ; Rounding modes for binary floating point numbers @@ -11924,15 +11930,43 @@ ; Stack Protector Patterns ; +; Insns stack_protect_get_tp{si,di} are similar to *get_tp_{31,64} but still +; distinct in the sense that they force recomputation of the thread pointer +; instead of potentially reloading it from stack. + +(define_insn_and_split "stack_protect_get_tpsi" + [(set (match_operand:SI 0 "register_operand" "=d") + (unspec_volatile:SI [(const_int 0)] UNSPECV_SP_GET_TP))] + "" + "#" + "&& reload_completed" + [(set (match_dup 0) (reg:SI AR0_REGNUM))]) + +(define_insn_and_split "stack_protect_get_tpdi" + [(set (match_operand:DI 0 "register_operand" "=d") + (unspec_volatile:DI [(const_int 0)] UNSPECV_SP_GET_TP))] + "" + "#" + "&& reload_completed" + [(set (match_dup 1) (reg:SI AR0_REGNUM)) + (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) + (set (strict_low_part (match_dup 1)) (reg:SI AR1_REGNUM))] + "operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]));") + (define_expand "stack_protect_set" [(set (match_operand 0 "memory_operand" "") (match_operand 1 "memory_operand" ""))] "" { #ifdef TARGET_THREAD_SSP_OFFSET + rtx tp = gen_reg_rtx (Pmode); + if (TARGET_64BIT) + emit_insn (gen_stack_protect_get_tpdi (tp)); + else + emit_insn (gen_stack_protect_get_tpsi (tp)); operands[1] - = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), - GEN_INT (TARGET_THREAD_SSP_OFFSET))); + = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tp, + GEN_INT (TARGET_THREAD_SSP_OFFSET))); #endif if (TARGET_64BIT) emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); @@ -11958,9 +11992,14 @@ { rtx cc_reg, test; #ifdef TARGET_THREAD_SSP_OFFSET + rtx tp = gen_reg_rtx (Pmode); + if (TARGET_64BIT) + emit_insn (gen_stack_protect_get_tpdi (tp)); + else + emit_insn (gen_stack_protect_get_tpsi (tp)); operands[1] - = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), - GEN_INT (TARGET_THREAD_SSP_OFFSET))); + = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tp, + GEN_INT (TARGET_THREAD_SSP_OFFSET))); #endif if (TARGET_64BIT) emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); diff --git a/gcc/config/vxworks-dummy.h b/gcc/config/vxworks-dummy.h index 494799d..516728c 100644 --- a/gcc/config/vxworks-dummy.h +++ b/gcc/config/vxworks-dummy.h @@ -40,9 +40,21 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_VXWORKS_RTP false #endif +/* True if offsets between different segments may vary, so we must avoid + cross-segment GOT- and PC-relative address computations. */ +#ifndef TARGET_VXWORKS_VAROFF +#define TARGET_VXWORKS_VAROFF false +#endif + /* The symbol that points to an RTP's table of GOTs. */ #define VXWORKS_GOTT_BASE (gcc_unreachable (), "") /* The symbol that holds the index of the current module's GOT in VXWORKS_GOTT_BASE. */ #define VXWORKS_GOTT_INDEX (gcc_unreachable (), "") + +/* True if PIC relies on the GOTT_* symbols above. As of VxWorks7, they are no + longer used. */ +#ifndef TARGET_VXWORKS_GOTTPIC +#define TARGET_VXWORKS_GOTTPIC false +#endif diff --git a/gcc/config/vxworks.h b/gcc/config/vxworks.h index 204a8e0..d2b6025 100644 --- a/gcc/config/vxworks.h +++ b/gcc/config/vxworks.h @@ -159,6 +159,18 @@ extern void vxworks_driver_init (unsigned int *, struct cl_decoded_option **); Earlier versions did not, not even for RTPS. */ #define VXWORKS_HAVE_TLS TARGET_VXWORKS7 +/* RTP segments could be loaded with varying offsets, so cross-segment offsets + could not be assumed to be constant. This rules out some PC- and + GOT-relative addressing. */ +#undef TARGET_VXWORKS_VAROFF +#define TARGET_VXWORKS_VAROFF (!TARGET_VXWORKS7 && TARGET_VXWORKS_RTP) + +/* GOTT_BASE and GOTT_INDEX symbols are only used by some ports up to VxWorks6. + This macro is only used by i386 so far. Other ports seem to keep on using + GOTTPIC from VxWorks7 on, but they don't test this macro. */ +#undef TARGET_VXWORKS_GOTTPIC +#define TARGET_VXWORKS_GOTTPIC (!TARGET_VXWORKS7) + /* On Vx6 and previous, the libraries to pick up depends on the architecture, so cannot be defined for all archs at once. On Vx7, a VSB is always needed and its structure is fixed and does not depend on the arch. We can thus diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 23511a0..38a2d68 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,26 @@ +2025-07-07 Alfie Richards <alfie.richards@arm.com> + + PR c++/119498 + * decl.cc (duplicate_decls): Change logic to not always exclude FMV + annotated functions in cases of return type non-ambiguation. + +2025-07-07 Jason Merrill <jason@redhat.com> + + PR c++/120917 + * parser.cc (cp_parser_simple_type_specifier): Attach + auto in targ in parameter to -Wabbreviated-auto-in-template-arg. + (cp_parser_placeholder_type_specifier): Diagnose constrained auto in + template arg. + +2025-07-07 Jakub Jelinek <jakub@redhat.com> + + PR c++/84009 + * parser.cc (cp_parser_decomposition_declaration): Pedwarn + on thread_local, __thread or static in decl_specifiers for + for-range-declaration. + (cp_parser_init_declarator): Likewise, and also for extern + or register. + 2025-07-04 Jason Merrill <jason@redhat.com> PR c++/120575 diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index ea366b1..49eef94 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,8 @@ +2025-07-07 Mikael Morin <mikael@gcc.gnu.org> + + * trans-intrinsic.cc (conv_intrinsic_move_alloc): Add pre and + post code for the FROM and TO arguments. + 2025-07-04 Martin Jambor <mjambor@suse.cz> * io.cc (format_asterisk): Add a brace around static initialization diff --git a/gcc/fortran/class.cc b/gcc/fortran/class.cc index df18601..a1c6faf 100644 --- a/gcc/fortran/class.cc +++ b/gcc/fortran/class.cc @@ -1034,7 +1034,7 @@ comp_is_finalizable (gfc_component *comp) of calling the appropriate finalizers, coarray deregistering, and deallocation of allocatable subcomponents. */ -static void +static bool finalize_component (gfc_expr *expr, gfc_symbol *derived, gfc_component *comp, gfc_symbol *stat, gfc_symbol *fini_coarray, gfc_code **code, gfc_namespace *sub_ns) @@ -1044,14 +1044,14 @@ finalize_component (gfc_expr *expr, gfc_symbol *derived, gfc_component *comp, gfc_was_finalized *f; if (!comp_is_finalizable (comp)) - return; + return false; /* If this expression with this component has been finalized already in this namespace, there is nothing to do. */ for (f = sub_ns->was_finalized; f; f = f->next) { if (f->e == expr && f->c == comp) - return; + return false; } e = gfc_copy_expr (expr); @@ -1208,8 +1208,6 @@ finalize_component (gfc_expr *expr, gfc_symbol *derived, gfc_component *comp, final_wrap->ext.actual->next->next = gfc_get_actual_arglist (); final_wrap->ext.actual->next->next->expr = fini_coarray_expr; - - if (*code) { (*code)->next = final_wrap; @@ -1221,11 +1219,14 @@ finalize_component (gfc_expr *expr, gfc_symbol *derived, gfc_component *comp, else { gfc_component *c; + bool ret = false; for (c = comp->ts.u.derived->components; c; c = c->next) - finalize_component (e, comp->ts.u.derived, c, stat, fini_coarray, code, - sub_ns); - gfc_free_expr (e); + ret |= finalize_component (e, comp->ts.u.derived, c, stat, fini_coarray, + code, sub_ns); + /* Only free the expression, if it has never been used. */ + if (!ret) + gfc_free_expr (e); } /* Record that this was finalized already in this namespace. */ @@ -1234,6 +1235,7 @@ finalize_component (gfc_expr *expr, gfc_symbol *derived, gfc_component *comp, sub_ns->was_finalized->e = expr; sub_ns->was_finalized->c = comp; sub_ns->was_finalized->next = f; + return true; } @@ -2314,6 +2316,7 @@ finish_assumed_rank: { gfc_symbol *stat; gfc_code *block = NULL; + gfc_expr *ptr_expr; if (!ptr) { @@ -2359,14 +2362,15 @@ finish_assumed_rank: sub_ns); block = block->next; + ptr_expr = gfc_lval_expr_from_sym (ptr); for (comp = derived->components; comp; comp = comp->next) { if (comp == derived->components && derived->attr.extension && ancestor_wrapper && ancestor_wrapper->expr_type != EXPR_NULL) continue; - finalize_component (gfc_lval_expr_from_sym (ptr), derived, comp, - stat, fini_coarray, &block, sub_ns); + finalize_component (ptr_expr, derived, comp, stat, fini_coarray, + &block, sub_ns); if (!last_code->block->next) last_code->block->next = block; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6ad847d..3923bb7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,183 @@ +2025-07-07 Qing Zhao <qing.zhao@oracle.com> + + Revert: + 2025-07-07 Qing Zhao <qing.zhao@oracle.com> + + * gcc.dg/flex-array-counted-by.c: Update test. + * gcc.dg/pointer-counted-by-1.c: New test. + * gcc.dg/pointer-counted-by-2.c: New test. + * gcc.dg/pointer-counted-by-3.c: New test. + * gcc.dg/pointer-counted-by.c: New test. + +2025-07-07 Qing Zhao <qing.zhao@oracle.com> + + Revert: + 2025-07-07 Qing Zhao <qing.zhao@oracle.com> + + * gcc.dg/pointer-counted-by-4-char.c: New test. + * gcc.dg/pointer-counted-by-4-float.c: New test. + * gcc.dg/pointer-counted-by-4-struct.c: New test. + * gcc.dg/pointer-counted-by-4-union.c: New test. + * gcc.dg/pointer-counted-by-4.c: New test. + * gcc.dg/pointer-counted-by-5.c: New test. + * gcc.dg/pointer-counted-by-6.c: New test. + * gcc.dg/pointer-counted-by-7.c: New test. + +2025-07-07 Qing Zhao <qing.zhao@oracle.com> + + Revert: + 2025-07-07 Qing Zhao <qing.zhao@oracle.com> + + * gcc.dg/ubsan/pointer-counted-by-bounds-2.c: New test. + * gcc.dg/ubsan/pointer-counted-by-bounds-3.c: New test. + * gcc.dg/ubsan/pointer-counted-by-bounds-4.c: New test. + * gcc.dg/ubsan/pointer-counted-by-bounds-5.c: New test. + * gcc.dg/ubsan/pointer-counted-by-bounds.c: New test. + +2025-07-07 H.J. Lu <hjl.tools@gmail.com> + + PR testsuite/120881 + * lib/scanasm.exp (check-function-bodies): Allow "^[0-9]+:". + +2025-07-07 H.J. Lu <hjl.tools@gmail.com> + + PR target/120888 + * gcc.target/xtensa/pr120888-1.c: New test. + * gcc.target/xtensa/pr120888-2.c: Likewise. + +2025-07-07 Juergen Christ <jchrist@linux.ibm.com> + + * gcc.target/s390/fminmax-1.c: New test. + * gcc.target/s390/fminmax-2.c: New test. + +2025-07-07 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/120817 + * gcc.dg/vect/pr120817.c: Add SVE HW check. + +2025-07-07 Alfie Richards <alfie.richards@arm.com> + + PR c++/119498 + * g++.target/aarch64/pr119498.C: New test. + +2025-07-07 Jason Merrill <jason@redhat.com> + + PR c++/120917 + * g++.dg/concepts/auto7a.C: Add diagnostic. + * g++.dg/concepts/auto7b.C: New test. + * g++.dg/concepts/auto7c.C: New test. + * g++.dg/cpp1y/pr85076.C: Expect 'auto' error. + * g++.dg/concepts/pr67249.C: Likewise. + * g++.dg/cpp1y/lambda-generic-variadic.C: Likewise. + * g++.dg/cpp2a/concepts-pr67210.C: Likewise. + * g++.dg/concepts/pr67249a.C: New test. + * g++.dg/cpp1y/lambda-generic-variadic-a.C: New test. + * g++.dg/cpp2a/concepts-pr67210a.C: New test. + +2025-07-07 Kyrylo Tkachov <ktkachov@nvidia.com> + + * gcc.target/aarch64/popcnt9.c: Add +nosve to target pragma. + * gcc.target/aarch64/popcnt13.c: New test. + +2025-07-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/120817 + * gcc.dg/vect/pr120817.c: New testcase. + +2025-07-07 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/sat/sat_arith.h: Add test helper macros. + * gcc.target/riscv/sat/sat_arith_data.h: Add test data for + run test. + * gcc.target/riscv/sat/sat_u_mul-1-u16-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-1-u32-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-1-u8-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c: New test. + +2025-07-07 Eric Botcazou <ebotcazou@adacore.com> + + * ada/acats-3/tests/c9/c94001c.ada: Tweak delay statements. + * ada/acats-4/tests/c9/c94001c.ada: Likewise. + * ada/acats-4/tests/c9/c94006a.ada: Likewise. + * ada/acats-4/tests/c9/c94008c.ada: Likewise. + * ada/acats-4/tests/c9/c951002.a: Likewise. + * ada/acats-4/tests/c9/c954a01.a: Likewise. + * ada/acats-4/tests/c9/c940005.a: Tweak duration constants. + * ada/acats-4/tests/c9/c940007.a: Likewise. + * ada/acats-4/tests/c9/c96001a.ada: Likewise. + +2025-07-07 Juergen Christ <jchrist@linux.ibm.com> + + * gcc.target/s390/vector/pattern-avg-1.c: New test. + * gcc.target/s390/vector/pattern-mulh-1.c: New test. + +2025-07-07 Spencer Abson <spencer.abson@arm.com> + + * gcc.target/aarch64/sve/unpacked_fcm_1.c: New test. + * gcc.target/aarch64/sve/unpacked_fcm_2.c: Likewise. + +2025-07-07 H.J. Lu <hjl.tools@gmail.com> + + PR target/120670 + PR target/120683 + * gcc.target/i386/auto-init-padding-9.c: Updated. + * gcc.target/i386/memcpy-strategy-12.c: Likewise. + * gcc.target/i386/memset-strategy-25.c: Likewise. + * gcc.target/i386/memset-strategy-29.c: Likewise. + * gcc.target/i386/memset-strategy-30.c: Likewise. + * gcc.target/i386/memset-strategy-31.c: Likewise. + * gcc.target/i386/memcpy-pr120683-1.c: New test. + * gcc.target/i386/memcpy-pr120683-2.c: Likewise. + * gcc.target/i386/memcpy-pr120683-3.c: Likewise. + * gcc.target/i386/memcpy-pr120683-4.c: Likewise. + * gcc.target/i386/memcpy-pr120683-5.c: Likewise. + * gcc.target/i386/memcpy-pr120683-6.c: Likewise. + * gcc.target/i386/memcpy-pr120683-7.c: Likewise. + * gcc.target/i386/memset-pr120683-1.c: Likewise. + * gcc.target/i386/memset-pr120683-2.c: Likewise. + * gcc.target/i386/memset-pr120683-3.c: Likewise. + * gcc.target/i386/memset-pr120683-4.c: Likewise. + * gcc.target/i386/memset-pr120683-5.c: Likewise. + * gcc.target/i386/memset-pr120683-6.c: Likewise. + * gcc.target/i386/memset-pr120683-7.c: Likewise. + * gcc.target/i386/memset-pr120683-8.c: Likewise. + * gcc.target/i386/memset-pr120683-9.c: Likewise. + * gcc.target/i386/memset-pr120683-10.c: Likewise. + * gcc.target/i386/memset-pr120683-11.c: Likewise. + * gcc.target/i386/memset-pr120683-12.c: Likewise. + * gcc.target/i386/memset-pr120683-13.c: Likewise. + * gcc.target/i386/memset-pr120683-14.c: Likewise. + * gcc.target/i386/memset-pr120683-15.c: Likewise. + * gcc.target/i386/memset-pr120683-16.c: Likewise. + * gcc.target/i386/memset-pr120683-17.c: Likewise. + * gcc.target/i386/memset-pr120683-18.c: Likewise. + * gcc.target/i386/memset-pr120683-19.c: Likewise. + * gcc.target/i386/memset-pr120683-20.c: Likewise. + * gcc.target/i386/memset-pr120683-21.c: Likewise. + * gcc.target/i386/memset-pr120683-22.c: Likewise. + * gcc.target/i386/memset-pr120683-23.c: Likewise. + +2025-07-07 Jakub Jelinek <jakub@redhat.com> + + PR c++/84009 + * g++.dg/cpp0x/range-for40.C: New test. + * g++.dg/cpp0x/range-for41.C: New test. + * g++.dg/cpp0x/range-for42.C: New test. + * g++.dg/cpp0x/range-for43.C: New test. + +2025-07-07 Mikael Morin <mikael@gcc.gnu.org> + + * gfortran.dg/move_alloc_20.f03: New test. + +2025-07-07 Andrew Pinski <quic_apinski@quicinc.com> + + PR middle-end/120709 + * gcc.dg/crc-non-cst-poly-1.c: New test. + 2025-07-06 Andrew Pinski <quic_apinski@quicinc.com> PR tree-optimization/120951 diff --git a/gcc/testsuite/g++.dg/cpp1y/lambda-generic-variadic.C b/gcc/testsuite/g++.dg/cpp1y/lambda-generic-variadic.C index 971f58f..6ef8652 100644 --- a/gcc/testsuite/g++.dg/cpp1y/lambda-generic-variadic.C +++ b/gcc/testsuite/g++.dg/cpp1y/lambda-generic-variadic.C @@ -1,5 +1,5 @@ // Basic generic lambda test -// { dg-do run { target c++14 } } +// { dg-do compile { target c++14 } } template <typename T, typename U> struct pair {}; template <typename... T> struct tuple {}; diff --git a/gcc/testsuite/gcc.dg/guality/guality.h b/gcc/testsuite/gcc.dg/guality/guality.h index d41327c..48b59d2e 100644 --- a/gcc/testsuite/gcc.dg/guality/guality.h +++ b/gcc/testsuite/gcc.dg/guality/guality.h @@ -204,9 +204,10 @@ int volatile guality_attached; of this wrapping, guality_main may not have an empty argument list. */ -extern int guality_main (int argc, char *argv[]); +extern int __attribute__((noipa)) +guality_main (int argc, char *argv[]); -static void __attribute__((noinline)) +static void __attribute__((noipa)) guality_check (const char *name, gualchk_t value, int unknown_ok); /* Set things up, run guality_main, then print a summary and quit. */ diff --git a/gcc/testsuite/gcc.dg/torture/pr120654.c b/gcc/testsuite/gcc.dg/torture/pr120654.c index 3819b78..aacfeea 100644 --- a/gcc/testsuite/gcc.dg/torture/pr120654.c +++ b/gcc/testsuite/gcc.dg/torture/pr120654.c @@ -2,8 +2,6 @@ int a, c, e, f, h, j; long g, k; -void *malloc(long); -void free(void *); int b(int m) { if (m || a) return 1; @@ -16,9 +14,9 @@ int i() { } void n() { long o; - int *p = malloc(sizeof(int)); + int *p = __builtin_malloc(sizeof(int)); k = 1 % j; for (; i() + f + h; o++) if (p[d(j + 6, (int)k + 1992695866) + h + f + j + (int)k - 1 + o]) - free(p); + __builtin_free(p); } diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-1.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-1.c index 753238e..b1f6678 100644 --- a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-1.c +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mno-sse -mmemcpy-strategy=unrolled_loop:256:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mno-sse -mmemcpy-strategy=unrolled_loop:256:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-2.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-2.c index 9b0fb06..0d0e348 100644 --- a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-2.c +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-3.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-3.c index 600459b..e5aca32 100644 --- a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-3.c +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-4.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-4.c index 14833ff..27f7bed 100644 --- a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-4.c +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v3 -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64-v3 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-5.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-5.c index 15ffed9..34a7408 100644 --- a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-5.c +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v3 -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64-v3 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-6.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-6.c index d57dcc1..aa5d90d 100644 --- a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-6.c +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v4 -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64-v4 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-7.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-7.c index d9eb77d..63d8a15 100644 --- a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-7.c +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v4 -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64-v4 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-strategy-12.c b/gcc/testsuite/gcc.target/i386/memcpy-strategy-12.c index 4716086..c60cef0 100644 --- a/gcc/testsuite/gcc.target/i386/memcpy-strategy-12.c +++ b/gcc/testsuite/gcc.target/i386/memcpy-strategy-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mtune=generic -mno-sse" } */ +/* { dg-options "-O2 -mtune=generic -mno-sse -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-1.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-1.c index 90e544d..06e3892 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-1.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-10.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-10.c index 6d3d9e7..36a924d 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-10.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mno-sse -mmemset-strategy=unrolled_loop:256:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -mno-sse -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=unrolled_loop:256:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-11.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-11.c index 30b0cad..4868e56 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-11.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mno-sse -mmemset-strategy=unrolled_loop:256:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -mno-sse -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=unrolled_loop:256:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-12.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-12.c index 15987a6..9112897 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-12.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mno-sse -mmemset-strategy=unrolled_loop:256:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -mno-sse -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=unrolled_loop:256:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-13.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-13.c index 3da6ca7..69ec6c6 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-13.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-14.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-14.c index 7ec9b3f..209cd67 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-14.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-15.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-15.c index e754405..d19188f 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-15.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v3 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* { dg-options "-O2 -march=x86-64-v3 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-16.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-16.c index c519bf3..539714c 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-16.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v4 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* { dg-options "-O2 -march=x86-64-v4 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-17.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-17.c index 744184c..f58cb28 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-17.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-18.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-18.c index 32f8981..a127028 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-18.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-19.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-19.c index 04f9171..8dd5ae6 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-19.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-2.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-2.c index f7834c0..3b84b29 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-2.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v3 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64-v3 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-20.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-20.c index edece12..b8b9cb7 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-20.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-20.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-21.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-21.c index a88e109..3c7bb7c 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-21.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-21.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-22.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-22.c index f2bd698..96a21c8 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-22.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-22.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O2 -march=x86-64 -mmemset-strategy=rep_8byte:8192:align,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=rep_8byte:8192:align,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-23.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-23.c index 784f8dc..f3f5d80 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-23.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-23.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -minline-all-stringops -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -minline-all-stringops -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-3.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-3.c index 621baf7..faa47ca 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-3.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v4 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* { dg-options "-O2 -march=x86-64-v4 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-4.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-4.c index 712404b..dc3aa57b 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-4.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-5.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-5.c index f597395..a324f8e 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-5.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v3 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* { dg-options "-O2 -march=x86-64-v3 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-6.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-6.c index 7ba1b742..64e7589 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-6.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v4 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* { dg-options "-O2 -march=x86-64-v4 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-7.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-7.c index 62f61c5..022f6f9 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-7.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-8.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-8.c index d12ab15..5254e21 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-8.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v3 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* { dg-options "-O2 -march=x86-64-v3 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-9.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-9.c index 1a0abe6..1719de6 100644 --- a/gcc/testsuite/gcc.target/i386/memset-pr120683-9.c +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v4 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* { dg-options "-O2 -march=x86-64-v4 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-epilogues-3.c b/gcc/testsuite/gcc.target/i386/vect-epilogues-3.c index 0ee610f..e88ab30 100644 --- a/gcc/testsuite/gcc.target/i386/vect-epilogues-3.c +++ b/gcc/testsuite/gcc.target/i386/vect-epilogues-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -mavx512bw -mtune=znver4 -fdump-tree-vect-optimized" } */ +/* { dg-options "-O3 -mavx512bw -mtune=znver4 --param vect-partial-vector-usage=0 -fdump-tree-vect-optimized" } */ int test (signed char *data, int n) { diff --git a/gcc/testsuite/gcc.target/i386/vect-mask-epilogue-1.c b/gcc/testsuite/gcc.target/i386/vect-mask-epilogue-1.c new file mode 100644 index 0000000..55519aa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-mask-epilogue-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=znver5 -fdump-tree-vect-optimized" } */ + +void bar (double *a, double *b, double c, int n, int m) +{ + for (int j = 0; j < m; ++j) + for (int i = 0; i < n; ++i) + a[j*n + i] = b[j*n + i] + c; +} + +/* { dg-final { scan-tree-dump "epilogue loop vectorized using masked 64 byte vectors" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-mask-epilogue-2.c b/gcc/testsuite/gcc.target/i386/vect-mask-epilogue-2.c new file mode 100644 index 0000000..3dc28b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-mask-epilogue-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=znver5 -fdump-tree-vect-optimized" } */ + +void foo (double *a, double b, double c, int n, int m) +{ + for (int j = 0; j < m; ++j) + for (int i = 0; i < n; ++i) + a[j*n + i] = a[j*n + i] * b + c; +} + +/* We do not want to use a masked epilogue for the inner loop as the next + outer iteration will possibly immediately read from elements masked of + the previous inner loop epilogue and that never forwards. */ +/* { dg-final { scan-tree-dump "epilogue loop vectorized using 32 byte vectors" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c new file mode 100644 index 0000000..d3d84fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* PR target/120995 ICE unrecognized subword atomic cas */ +/* { dg-options "-O" } */ +/* { dg-add-options riscv_zacas } */ +/* { dg-add-options riscv_zabha } */ + +_Bool b; +void atomic_bool_cmpxchg() +{ + __sync_bool_compare_and_swap(&b, 1, 0); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c index 4cf617d..0dfe816 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c +++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c @@ -9,7 +9,7 @@ /* ** atomic_add_fetch_int_relaxed: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -23,7 +23,7 @@ void atomic_add_fetch_int_relaxed (int* bar, int baz) /* ** atomic_add_fetch_int_acquire: -** 1: +**... ** lr.w.aq\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -37,7 +37,7 @@ void atomic_add_fetch_int_acquire (int* bar, int baz) /* ** atomic_add_fetch_int_release: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -51,7 +51,7 @@ void atomic_add_fetch_int_release (int* bar, int baz) /* ** atomic_add_fetch_int_acq_rel: -** 1: +**... ** lr.w.aq\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -65,7 +65,7 @@ void atomic_add_fetch_int_acq_rel (int* bar, int baz) /* ** atomic_add_fetch_int_seq_cst: -** 1: +**... ** lr.w.aqrl\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c index 3fb16c0..658b040 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c +++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c @@ -9,7 +9,7 @@ /* ** atomic_add_fetch_int_relaxed: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -23,7 +23,7 @@ void atomic_add_fetch_int_relaxed (int* bar, int baz) /* ** atomic_add_fetch_int_acquire: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -37,7 +37,7 @@ void atomic_add_fetch_int_acquire (int* bar, int baz) /* ** atomic_add_fetch_int_release: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -51,7 +51,7 @@ void atomic_add_fetch_int_release (int* bar, int baz) /* ** atomic_add_fetch_int_acq_rel: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -65,7 +65,7 @@ void atomic_add_fetch_int_acq_rel (int* bar, int baz) /* ** atomic_add_fetch_int_seq_cst: -** 1: +**... ** lr.w.aqrl\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113829.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113829.c new file mode 100644 index 0000000..48c291a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113829.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gcv -mabi=lp64d" } */ + +#pragma riscv intrinsic "vector" +void +foo (void) +{ + __riscv_vfredosum_tu (X); /* { dg-error "undeclared" } */ + /* { dg-error "too many arguments" "" { target *-*-* } .-1 } */ +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c new file mode 100644 index 0000000..6939157 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=xt-c920 -mrvv-vector-bits=zvl -fzero-call-used-regs=all" */ + +void +foo () +{} diff --git a/gcc/testsuite/gcc.target/s390/stack-protector-guard-tls-1.c b/gcc/testsuite/gcc.target/s390/stack-protector-guard-tls-1.c new file mode 100644 index 0000000..1efd245 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/stack-protector-guard-tls-1.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fstack-protector-all" } */ +/* { dg-final { scan-assembler-times {\tear\t%r[0-9]+,%a[01]} 8 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\tsllg\t%r[0-9]+,%r[0-9]+,32} 4 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\tear\t%r[0-9]+,%a[01]} 3 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times {\tmvc\t160\(8,%r15\),40\(%r[0-9]+\)} 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\tmvc\t100\(4,%r15\),20\(%r[0-9]+\)} 2 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times {\tclc\t160\(8,%r15\),40\(%r[0-9]+\)} 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\tclc\t100\(4,%r15\),20\(%r[0-9]+\)} 2 { target { ! lp64 } } } } */ + +/* Computing the address of the thread pointer on s390 involves multiple + instructions and therefore bears the risk that the address of the canary or + intermediate values of it are spilled and reloaded. Therefore, as a + precaution compute the address always twice, i.e., one time for the prologue + and one time for the epilogue. */ + +void test_0 (void) { } + +void test_1 (void) +{ + __asm__ __volatile ("" ::: + "r0", + "r1", + "r2", + "r3", + "r4", + "r5", + "r6", + "r7", + "r8", + "r9", + "r10", + "r11", +#ifndef __PIC__ + "r12", +#endif + "r13", + "r14"); +} diff --git a/gcc/testsuite/gcc.target/s390/vector/pattern-avg-1.c b/gcc/testsuite/gcc.target/s390/vector/pattern-avg-1.c index a15301a..30c6ed4 100644 --- a/gcc/testsuite/gcc.target/s390/vector/pattern-avg-1.c +++ b/gcc/testsuite/gcc.target/s390/vector/pattern-avg-1.c @@ -21,6 +21,5 @@ TEST(char,short,16) TEST(short,int,8) TEST(int,long,4) -TEST(long,__int128,2) -/* { dg-final { scan-tree-dump-times "\.AVG_CEIL" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.AVG_CEIL" 6 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/pattern-avg-2.c b/gcc/testsuite/gcc.target/s390/vector/pattern-avg-2.c new file mode 100644 index 0000000..1cc614e --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/pattern-avg-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O3 -mzarch -march=z16 -ftree-vectorize -fdump-tree-optimized" } */ + +#define TEST(T1,T2,N) \ + void \ + avg##T1 (signed T1 *__restrict res, signed T1 *__restrict a, \ + signed T1 *__restrict b) \ + { \ + for (int i = 0; i < N; ++i) \ + res[i] = ((signed T2)a[i] + b[i] + 1) >> 1; \ + } \ + \ + void \ + uavg##T1 (unsigned T1 *__restrict res, unsigned T1 *__restrict a, \ + unsigned T1 *__restrict b) \ + { \ + for (int i = 0; i < N; ++i) \ + res[i] = ((unsigned T2)a[i] + b[i] + 1) >> 1; \ + } + +TEST(long,__int128,2) + +/* { dg-final { scan-tree-dump-times "\.AVG_CEIL" 2 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/pattern-mulh-1.c b/gcc/testsuite/gcc.target/s390/vector/pattern-mulh-1.c index cd8e4e7d..f71ef06 100644 --- a/gcc/testsuite/gcc.target/s390/vector/pattern-mulh-1.c +++ b/gcc/testsuite/gcc.target/s390/vector/pattern-mulh-1.c @@ -24,6 +24,5 @@ TEST(char,short,16,8) TEST(short,int,8,16) TEST(int,long,4,32) -TEST(long,__int128,2,64) -/* { dg-final { scan-tree-dump-times "\.MULH" 8 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.MULH" 6 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/pattern-mulh-2.c b/gcc/testsuite/gcc.target/s390/vector/pattern-mulh-2.c new file mode 100644 index 0000000..6ac6855 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/pattern-mulh-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O3 -mzarch -march=arch15 -ftree-vectorize -fdump-tree-optimized" } */ + +#define TEST(T1,T2,N,S) \ + void \ + mulh##T1 (signed T1 *__restrict res, \ + signed T1 *__restrict l, \ + signed T1 *__restrict r) \ + { \ + for (int i = 0; i < N; ++i) \ + res[i] = (signed T1) (((signed T2)l[i] * (signed T2)r[i]) >> S); \ + } \ + \ + void \ + umulh##T1 (unsigned T1 *__restrict res, \ + unsigned T1 *__restrict l, \ + unsigned T1 *__restrict r) \ + { \ + for (int i = 0; i < N; ++i) \ + res[i] = (unsigned T1) \ + (((unsigned T2)l[i] * (unsigned T2)r[i]) >> S); \ + } + +TEST(long,__int128,2,64) + +/* { dg-final { scan-tree-dump-times "\.MULH" 2 "optimized" } } */ diff --git a/gcc/testsuite/gfortran.dg/asan/finalize_1.f90 b/gcc/testsuite/gfortran.dg/asan/finalize_1.f90 new file mode 100644 index 0000000..ab53a9e --- /dev/null +++ b/gcc/testsuite/gfortran.dg/asan/finalize_1.f90 @@ -0,0 +1,67 @@ +!{ dg-do run } + +! PR fortran/120637 + +! Contributed by Antony Lewis <antony@cosmologist.info> +! The unused module is needed to trigger the issue of not freeing the +! memory of second module. + + module MiscUtils + implicit none + + contains + + logical function isFloat0(R) + class(*), intent(in) :: R + + select type(R) + type is (real) + isFloat0 = .true. + end select + end function isFloat0 + + end module MiscUtils + + module results3 + implicit none + public + + Type ClTransferData2 + real, dimension(:,:,:), allocatable :: Delta_p_l_k + end type ClTransferData2 + + type TCLdata2 + Type(ClTransferData2) :: CTransScal, CTransTens, CTransVec + end type TCLdata2 + + type :: CAMBdata2 + Type(TClData2) :: CLdata2 + end type + + end module results3 + +program driver + use results3 + integer i + do i=1, 2 + call test() + end do + + contains + + subroutine test + implicit none + class(CAMBdata2), pointer :: Data + + allocate(CAMBdata2::Data) + + allocate(Data%ClData2%CTransScal%Delta_p_l_k(3, 1000, 1000)) + allocate(Data%ClData2%CTransVec%Delta_p_l_k(3, 1000, 1000)) + deallocate(Data) + + end subroutine test + + end program driver + +!{ dg-final { cleanup-modules "miscutils results3" } } + diff --git a/gcc/tree-ssa-structalias.cc b/gcc/tree-ssa-structalias.cc index deca44a..0215243 100644 --- a/gcc/tree-ssa-structalias.cc +++ b/gcc/tree-ssa-structalias.cc @@ -3690,7 +3690,10 @@ get_constraint_for_1 (tree t, vec<ce_s> *results, bool address_p, size = -1; for (; curr; curr = vi_next (curr)) { - if (curr->offset - vi->offset < size) + /* The start of the access might happen anywhere + within vi, so conservatively assume it was + at its end. */ + if (curr->offset - (vi->offset + vi->size - 1) < size) { cs.var = curr->id; results->safe_push (cs); diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc index 2782d61..d5044d5 100644 --- a/gcc/tree-vect-loop.cc +++ b/gcc/tree-vect-loop.cc @@ -58,6 +58,7 @@ along with GCC; see the file COPYING3. If not see #include "tree-eh.h" #include "case-cfn-macros.h" #include "langhooks.h" +#include "opts.h" /* Loop Vectorization Pass. @@ -3400,8 +3401,10 @@ vect_joust_loop_vinfos (loop_vec_info new_loop_vinfo, } /* Analyze LOOP with VECTOR_MODES[MODE_I] and as epilogue if ORIG_LOOP_VINFO is - not NULL. Set AUTODETECTED_VECTOR_MODE if VOIDmode and advance - MODE_I to the next mode useful to analyze. + not NULL. When MASKED_P is not -1 override the default + LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P with it. + Set AUTODETECTED_VECTOR_MODE if VOIDmode and advance MODE_I to the next + mode useful to analyze. Return the loop_vinfo on success and wrapped null on failure. */ static opt_loop_vec_info @@ -3409,6 +3412,7 @@ vect_analyze_loop_1 (class loop *loop, vec_info_shared *shared, const vect_loop_form_info *loop_form_info, loop_vec_info orig_loop_vinfo, const vector_modes &vector_modes, unsigned &mode_i, + int masked_p, machine_mode &autodetected_vector_mode, bool &fatal) { @@ -3417,6 +3421,8 @@ vect_analyze_loop_1 (class loop *loop, vec_info_shared *shared, machine_mode vector_mode = vector_modes[mode_i]; loop_vinfo->vector_mode = vector_mode; + if (masked_p != -1) + loop_vinfo->can_use_partial_vectors_p = masked_p; unsigned int suggested_unroll_factor = 1; unsigned slp_done_for_suggested_uf = 0; @@ -3600,7 +3606,7 @@ vect_analyze_loop (class loop *loop, gimple *loop_vectorized_call, cached_vf_per_mode[last_mode_i] = -1; opt_loop_vec_info loop_vinfo = vect_analyze_loop_1 (loop, shared, &loop_form_info, - NULL, vector_modes, mode_i, + NULL, vector_modes, mode_i, -1, autodetected_vector_mode, fatal); if (fatal) break; @@ -3685,18 +3691,21 @@ vect_analyze_loop (class loop *loop, gimple *loop_vectorized_call, array may contain length-agnostic and length-specific modes. Their ordering is not guaranteed, so we could end up picking a mode for the main loop that is after the epilogue's optimal mode. */ + int masked_p = -1; if (!unlimited_cost_model (loop) - && first_loop_vinfo->vector_costs->suggested_epilogue_mode () != VOIDmode) + && (first_loop_vinfo->vector_costs->suggested_epilogue_mode (masked_p) + != VOIDmode)) { vector_modes[0] - = first_loop_vinfo->vector_costs->suggested_epilogue_mode (); + = first_loop_vinfo->vector_costs->suggested_epilogue_mode (masked_p); cached_vf_per_mode[0] = 0; } else vector_modes[0] = autodetected_vector_mode; mode_i = 0; - bool supports_partial_vectors = param_vect_partial_vector_usage != 0; + bool supports_partial_vectors = (param_vect_partial_vector_usage != 0 + || masked_p == 1); machine_mode mask_mode; if (supports_partial_vectors && !partial_vectors_supported_p () @@ -3710,6 +3719,10 @@ vect_analyze_loop (class loop *loop, gimple *loop_vectorized_call, loop_vec_info orig_loop_vinfo = first_loop_vinfo; do { + /* Let the user override what the target suggests. */ + if (OPTION_SET_P (param_vect_partial_vector_usage)) + masked_p = -1; + while (1) { /* If the target does not support partial vectors we can shorten the @@ -3750,7 +3763,7 @@ vect_analyze_loop (class loop *loop, gimple *loop_vectorized_call, opt_loop_vec_info loop_vinfo = vect_analyze_loop_1 (loop, shared, &loop_form_info, orig_loop_vinfo, - vector_modes, mode_i, + vector_modes, mode_i, masked_p, autodetected_vector_mode, fatal); if (fatal) break; @@ -3781,6 +3794,9 @@ vect_analyze_loop (class loop *loop, gimple *loop_vectorized_call, break; } + /* Revert back to the default from the suggested prefered + epilogue vectorization mode. */ + masked_p = -1; if (mode_i == vector_modes.length ()) break; } @@ -3791,13 +3807,14 @@ vect_analyze_loop (class loop *loop, gimple *loop_vectorized_call, /* When we selected a first vectorized epilogue, see if the target suggests to have another one. */ + masked_p = -1; if (!unlimited_cost_model (loop) && !LOOP_VINFO_USING_PARTIAL_VECTORS_P (orig_loop_vinfo) - && (orig_loop_vinfo->vector_costs->suggested_epilogue_mode () + && (orig_loop_vinfo->vector_costs->suggested_epilogue_mode (masked_p) != VOIDmode)) { vector_modes[0] - = orig_loop_vinfo->vector_costs->suggested_epilogue_mode (); + = orig_loop_vinfo->vector_costs->suggested_epilogue_mode (masked_p); cached_vf_per_mode[0] = 0; mode_i = 0; } diff --git a/gcc/tree-vectorizer.h b/gcc/tree-vectorizer.h index 66a2964..ba06c5d 100644 --- a/gcc/tree-vectorizer.h +++ b/gcc/tree-vectorizer.h @@ -1714,7 +1714,7 @@ public: unsigned int outside_cost () const; unsigned int total_cost () const; unsigned int suggested_unroll_factor () const; - machine_mode suggested_epilogue_mode () const; + machine_mode suggested_epilogue_mode (int &masked) const; protected: unsigned int record_stmt_cost (stmt_vec_info, vect_cost_model_location, @@ -1738,8 +1738,13 @@ protected: unsigned int m_suggested_unroll_factor; /* The suggested mode to be used for a vectorized epilogue or VOIDmode, - determined at finish_cost. */ + determined at finish_cost. m_masked_epilogue specifies whether the + epilogue should use masked vectorization, regardless of the + --param vect-partial-vector-usage default. If -1 then the + --param setting takes precedence. If the user explicitly specified + --param vect-partial-vector-usage then that takes precedence. */ machine_mode m_suggested_epilogue_mode; + int m_masked_epilogue; /* True if finish_cost has been called. */ bool m_finished; @@ -1755,6 +1760,7 @@ vector_costs::vector_costs (vec_info *vinfo, bool costing_for_scalar) m_costs (), m_suggested_unroll_factor(1), m_suggested_epilogue_mode(VOIDmode), + m_masked_epilogue (-1), m_finished (false) { } @@ -1815,9 +1821,10 @@ vector_costs::suggested_unroll_factor () const /* Return the suggested epilogue mode. */ inline machine_mode -vector_costs::suggested_epilogue_mode () const +vector_costs::suggested_epilogue_mode (int &masked_p) const { gcc_checking_assert (m_finished); + masked_p = m_masked_epilogue; return m_suggested_epilogue_mode; } |