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-rw-r--r--gcc/ChangeLog27
-rw-r--r--gcc/DATESTAMP2
-rw-r--r--gcc/config/i386/i386.cc3
-rw-r--r--gcc/config/i386/i386.md8
-rw-r--r--gcc/config/riscv/riscv-v.cc2
-rw-r--r--gcc/testsuite/ChangeLog18
-rw-r--r--gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c2
-rw-r--r--gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c2
-rw-r--r--gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c2
-rw-r--r--gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c2
-rw-r--r--gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c2
-rw-r--r--gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c2
-rw-r--r--gcc/testsuite/gcc.target/riscv/pr118241.c2
-rw-r--r--gcc/testsuite/gcc.target/riscv/pr120223.c2
-rw-r--r--gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c26
-rw-r--r--gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c2
-rw-r--r--gcc/tree-vect-loop.cc1
17 files changed, 90 insertions, 15 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9004d1c..94cb5ae 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,30 @@
+2025-07-02 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/120908
+ * config/i386/i386.cc (legitimize_tls_address): Pass RDI to
+ gen_tls_global_dynamic_64.
+ * config/i386/i386.md (*tls_global_dynamic_64_<mode>): Add RDI
+ clobber and use it to generate LEA.
+ (@tls_global_dynamic_64_<mode>): Add a clobber.
+
+2025-07-02 Alexey Merzlyakov <alexey.merzlyakov@samsung.com>
+
+ PR target/120356
+ * config/riscv/riscv-v.cc
+ (expand_const_vector_interleaved_stepped_npatterns):
+ Fix ASHIFT to LSHIFTRT insn.
+
+2025-07-02 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/120927
+ * tree-vect-loop.cc (vect_analyze_loop): Stop querying
+ further epilogues after one with partial vectors.
+
+2025-07-02 Haochen Jiang <haochen.jiang@intel.com>
+
+ * config/i386/driver-i386.cc (host_detect_local_cpu): Change
+ to AMX-FP8 for Diamond Rapids.
+
2025-07-01 Qing Zhao <qing.zhao@oracle.com>
* tree-object-size.cc (access_with_size_object_size): Update comments
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 46e9463..6952979 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250702
+20250703
diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 44763c8..9657c6a 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -12562,11 +12562,12 @@ legitimize_tls_address (rtx x, enum tls_model model, bool for_mov)
if (TARGET_64BIT)
{
rtx rax = gen_rtx_REG (Pmode, AX_REG);
+ rtx rdi = gen_rtx_REG (Pmode, DI_REG);
rtx_insn *insns;
start_sequence ();
emit_call_insn
- (gen_tls_global_dynamic_64 (Pmode, rax, x, caddr));
+ (gen_tls_global_dynamic_64 (Pmode, rax, x, caddr, rdi));
insns = end_sequence ();
if (GET_MODE (x) != Pmode)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index adff2af..370e79b 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -23201,7 +23201,8 @@
(match_operand 3)))
(unspec:P [(match_operand 1 "tls_symbolic_operand")
(reg:P SP_REG)]
- UNSPEC_TLS_GD)]
+ UNSPEC_TLS_GD)
+ (clobber (match_operand:P 4 "register_operand" "=D"))]
"TARGET_64BIT"
{
if (!TARGET_X32)
@@ -23218,7 +23219,7 @@
Use data16 prefix instead, which doesn't have this problem. */
fputs ("\tdata16", asm_out_file);
output_asm_insn
- ("lea{q}\t{%E1@tlsgd(%%rip), %%rdi|rdi, %E1@tlsgd[rip]}", operands);
+ ("lea{q}\t{%E1@tlsgd(%%rip), %q4|%q4, %E1@tlsgd[rip]}", operands);
if (TARGET_SUN_TLS || flag_plt || !HAVE_AS_IX86_TLS_GET_ADDR_GOT)
fputs (ASM_SHORT "0x6666\n", asm_out_file);
else
@@ -23265,7 +23266,8 @@
(const_int 0)))
(unspec:P [(match_operand 1 "tls_symbolic_operand")
(reg:P SP_REG)]
- UNSPEC_TLS_GD)])]
+ UNSPEC_TLS_GD)
+ (clobber (match_operand:P 3 "register_operand"))])]
"TARGET_64BIT"
"ix86_tls_descriptor_calls_expanded_in_cfun = true;")
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 69f2a1ec..ce1633c 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx target, rtx src,
shifted_vid = gen_reg_rtx (mode);
rtx shift = gen_int_mode (1, Xmode);
rtx shift_ops[] = {shifted_vid, vid, shift};
- emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+ emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
shift_ops);
}
else
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index eaa08db..ab15e88 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,21 @@
+2025-07-02 Dimitar Dimitrov <dimitar@dinux.eu>
+
+ * gcc.target/riscv/mcpu-xt-c908.c: Disable for E ABI variants.
+ * gcc.target/riscv/mcpu-xt-c908v.c: Ditto.
+ * gcc.target/riscv/mcpu-xt-c910.c: Ditto.
+ * gcc.target/riscv/mcpu-xt-c910v2.c: Ditto.
+ * gcc.target/riscv/mcpu-xt-c920.c: Ditto.
+ * gcc.target/riscv/mcpu-xt-c920v2.c: Ditto.
+ * gcc.target/riscv/pr118241.c: Ditto.
+ * gcc.target/riscv/pr120223.c: Ditto.
+ * gcc.target/riscv/rvv/base/pr119164.c: Disable for E ABI variants
+ and for 32-bit ISA.
+
+2025-07-02 Alexey Merzlyakov <alexey.merzlyakov@samsung.com>
+
+ PR target/120356
+ * gcc.target/riscv/rvv/autovec/pr120356.c: New test.
+
2025-07-01 Qing Zhao <qing.zhao@oracle.com>
* gcc.dg/ubsan/pointer-counted-by-bounds-2.c: New test.
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
index cb28baf..4ad82a8 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
/* { dg-options "-mcpu=xt-c908" { target { rv64 } } } */
/* XuanTie C908 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
index 1b1ee18..bb9e310 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
/* { dg-options "-mcpu=xt-c908v" { target { rv64 } } } */
/* XuanTie C908v => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
index 1e27665..397e7b1 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
/* { dg-options "-mcpu=xt-c910" { target { rv64 } } } */
/* XuanTie C910 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_xtheadba_
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
index 6a54f09..9e39c9f 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
/* { dg-options "-mcpu=xt-c910v2" { target { rv64 } } } */
/* XuanTie C910v2 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
index 6bcd687..4cce90a 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
/* { dg-options "-mcpu=xt-c920" { target { rv64 } } } */
/* XuanTie c920 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync_xtheadvector */
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
index 36a6267..1f21d07 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
/* { dg-options "-mcpu=xt-c920v2" { target { rv64 } } } */
/* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync_xtheadvdot */
diff --git a/gcc/testsuite/gcc.target/riscv/pr118241.c b/gcc/testsuite/gcc.target/riscv/pr118241.c
index f1dc44b..768ea05 100644
--- a/gcc/testsuite/gcc.target/riscv/pr118241.c
+++ b/gcc/testsuite/gcc.target/riscv/pr118241.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-options "-march=rv64gc_zicbop" { target { rv64 } } } */
/* { dg-options "-march=rv32gc_zicbop" { target { rv32 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/pr120223.c b/gcc/testsuite/gcc.target/riscv/pr120223.c
index fae21b6..d6afd86 100644
--- a/gcc/testsuite/gcc.target/riscv/pr120223.c
+++ b/gcc/testsuite/gcc.target/riscv/pr120223.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-options "-mcpu=thead-c906" } */
long foo(long x) { return x ^ 0x80000000; }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
new file mode 100644
index 0000000..2913f04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target rvv_zvl256b_ok } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -O2" } */
+
+unsigned char a = 5;
+long long c[18];
+
+static void d ()
+{
+ for (short i = 0; i < 60; i += 65413)
+ for (char j = 0; j < 18; j++)
+ {
+ for (char k = 0; k < 18; k++)
+ a *= 143;
+ for (char k = 0; k < 6; k++)
+ for (char l = 0; l < 18; l++)
+ c[l] = 0;
+ }
+}
+
+int main ()
+{
+ d ();
+ if (a + c[0] != 69)
+ __builtin_abort ();
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c
index a39a7f1..266e948 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c
@@ -1,7 +1,7 @@
/* Reduced from SPEC2017 blender: node_texture_util.c.
The conditional function call was tripping mode switching state machine */
-/* { dg-do compile } */
+/* { dg-do compile { target { rv64 && { ! riscv_abi_e } } } } */
/* { dg-options " -Ofast -march=rv64gcv_zvl256b -ftree-vectorize -mrvv-vector-bits=zvl" } */
void *a;
diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index 575987e..2782d61 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -3792,6 +3792,7 @@ vect_analyze_loop (class loop *loop, gimple *loop_vectorized_call,
/* When we selected a first vectorized epilogue, see if the target
suggests to have another one. */
if (!unlimited_cost_model (loop)
+ && !LOOP_VINFO_USING_PARTIAL_VECTORS_P (orig_loop_vinfo)
&& (orig_loop_vinfo->vector_costs->suggested_epilogue_mode ()
!= VOIDmode))
{
generated by cgit v1.1 at 2025-07-03 07:17:49 +0000