diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 25 | ||||
| -rw-r--r-- | gcc/DATESTAMP | 2 | ||||
| -rw-r--r-- | gcc/ada/ChangeLog | 126 | ||||
| -rw-r--r-- | gcc/ada/sem_ch12.adb | 2 | ||||
| -rw-r--r-- | gcc/config/loongarch/genopts/loongarch.opt.in | 4 | ||||
| -rw-r--r-- | gcc/config/loongarch/lasx.md | 53 | ||||
| -rw-r--r-- | gcc/config/loongarch/loongarch.cc | 78 | ||||
| -rw-r--r-- | gcc/config/loongarch/loongarch.md | 14 | ||||
| -rw-r--r-- | gcc/config/loongarch/loongarch.opt | 4 | ||||
| -rw-r--r-- | gcc/config/loongarch/loongarch.opt.urls | 3 | ||||
| -rw-r--r-- | gcc/config/loongarch/lsx.md | 53 | ||||
| -rw-r--r-- | gcc/config/loongarch/simd.md | 71 | ||||
| -rw-r--r-- | gcc/cp/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/cp/decl.cc | 8 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 13 | ||||
| -rw-r--r-- | gcc/fortran/ChangeLog | 12 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 26 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/loongarch/pr122097.c | 271 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/loongarch/trap-1.c | 9 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/loongarch/trap-default.c | 9 |
20 files changed, 664 insertions, 125 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1ae78b4..f05b25b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,28 @@ +2025-10-28 Richard Biener <rguenther@suse.de> + + * tree-vect-loop-manip.cc (vect_update_ivs_after_vectorizer): + Avoid explicit LOOP_VINFO_IV_EXIT reference. + +2025-10-28 Artemiy Volkov <artemiy.volkov@arm.com> + + * match.pd: Add pattern to simplify view_convert (BIT_FIELD_REF). + +2025-10-28 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/riscv.cc (riscv_get_vls_cc_attr): Fix error message + parameter order and add check_only condition. Improve diagnostic + message formatting with proper quoting. + (riscv_handle_rvv_vls_cc_attribute): Anonymize unused node parameter. + +2025-10-28 Avinash Jayakar <avinashd@linux.ibm.com> + + PR tree-optimization/122065 + * tree-vect-generic.cc (add_rshift): Update name and add code parameter. + (add_shift): Update name. + (expand_vector_mult): New lowering for MULT_EXPR. + (expand_vector_divmod): Use updated function name. + (expand_vector_operation): Use updated function name. + 2025-10-27 Andrew Pinski <andrew.pinski@oss.qualcomm.com> * expr.cc (expr_has_boolean_range): New function. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 0bfc1e9..aa425f4 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20251028 +20251029 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index bd1e2ae..fc58e04 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,129 @@ +2025-10-28 Eric Botcazou <ebotcazou@adacore.com> + + PR ada/48039 + * sem_ch12.adb (Analyze_Subprogram_Instantiation): Call + Remove_Homonym to remove the enclosing package from visibility. + +2025-10-28 Eric Botcazou <ebotcazou@adacore.com> + + * exp_util.adb (Remove_Side_Effects): Use separately the Etype of + the expression to build new nodes and its Underlying_Type to drive + part of the processing. + +2025-10-28 Johannes Kliemann <kliemann@adacore.com> + + * adaint.c: Remove __gnat_enable_signals, __gnat_disable_signals + and related code for QNX. + * libgnarl/s-taprop__qnx.adb: Disable and enable + signals in Ada. + +2025-10-28 Alexandre Oliva <oliva@adacore.com> + + * sem_ch13.adb (Analyze_Aspect_Export_Import): Skip + Set_Is_Imported on E_Exception. + * sem_prag.adb (Process_Import_Or_Interface): Explain + why not Set_Is_Imported. + +2025-10-28 Denis Mazzucato <mazzucato@adacore.com> + + * sem_util.adb (Collect_Primitive_Operations): Avoid setting + Is_Primitive for noninherited and nonoverriding subprograms not + declared immediately within a package specification. + * sem_ch13.adb (Check_Nonoverridable_Aspect_Subprograms): Better + error posting to allow multiple errors on same type but different + aggregate subprogram. + +2025-10-28 Ronan Desplanques <desplanques@adacore.com> + + * table.ads (Clear, Is_Empty): New subprograms. + * table.adb (Clear, Is_Empty): Likewise. + (Init): Use new subprogram. + * atree.adb (Traverse_Func_With_Parent): Use new subprograms. + * fmap.adb (Empty_Tables): Use new subprogram. + * par_sco.adb (Process_Pending_Decisions): Likewise. + * sem_elab.adb (Check_Elab_Call): Likewise. + * sem_ch12.adb (Build_Local_Package, Analyze_Package_Instantiation, + Analyze_Subprogram_Instantiation): Likewise. + (Save_And_Reset): Use Table.Table.First. + +2025-10-28 Eric Botcazou <ebotcazou@adacore.com> + + PR ada/122063 + * exp_fixd.adb (Build_Double_Divide_Code): Convert the result of the + multiply. + (Build_Multiply): Use base types of operands to size the operation. + (Build_Rem): Likewise. + (Build_Scaled_Divide_Code): Convert the result of the multiply. + +2025-10-28 Tonu Naks <naks@adacore.com> + + * doc/gnat_rm/obsolescent_features.rst: typo + * gnat_rm.texi: Regenerate. + +2025-10-28 Javier Miranda <miranda@adacore.com> + + * aspects.adb (Get_Aspect_Id): Enable aspect Unsigned_Base_Range + using -gnatd.u + * debug.adb (Debug_Flag_Dot_U): Document this switch. + * einfo-utils.adb (Is_Modular_Integer_Type): Return True if + the entity is a modular integer type and its base type does + not have the attribute has_unsigned_base_range_aspect. + (Is_Signed_Integer_Type): Return True if the entity is a signed + integer type, or it is a modular integer type and its base type + has the attribute has_unsigned_base_range_aspect. + * einfo.ads (E_Modular_Integer_Type): Add documentation of + Has_Unsigned_Base_Range_Aspect. + * par-ch4.adb (Scan_Apostrophe): Enable attribute Unsigned_Base_Range + using -gnatd.u + * sem_ch13.adb (Analyze_One_Aspect): Check general language + restrictions on aspect Unsigned_Base_Range. For Unsigned_Base_Range + aspect, do not delay the generation of the pragma becase we need + to process it before any type or subtype derivation is analyzed. + * sem_ch3.adb (Build_Scalar_Bound): Disable code analyzing the + bound with the base type of the parent type because, for unsigned + base range types, their base type is a modular type but their + type is a signed integer type. + * sem_prag.adb (Analyze_Pragma): Enable pragma Unsigned_Base_Range + using -gnatd.u. Check more errors on Unsigned_Base_Range pragma, + and create the new base type only when required. + +2025-10-28 Ronan Desplanques <desplanques@adacore.com> + + * sem_ch12.adb (Build_Local_Package) + (Analyze_Package_Instantiation, Analyze_Subprogram_Instantiation): + Fix Set_Last calls. + (Set_Instance_Of): Use Table.Table.Append. + (Save_And_Reset): Remove useless call. Remove defensive code. + (Restore): Remove incorrect Set_Last call and adapt to + Set_Instance_Of change. + +2025-10-28 Denis Mazzucato <mazzucato@adacore.com> + + * sem_prag.adb (Analyze_Pragma): Add enclosing quotation when the + invalid switch ends with a space. + +2025-10-28 Eric Botcazou <ebotcazou@adacore.com> + + PR ada/59234 + * sem_ch12.adb (Analyze_Formal_Package_Declaration): Mark the + special name built for the formal in the parent of a child unit + as internal. + +2025-10-28 Eric Botcazou <ebotcazou@adacore.com> + + PR ada/34511 + * sem_ch12.adb (Analyze_Associations): Add Parent_Installed formal + parameter and pass it in call to Analyze_One_Association. + (Analyze_One_Association): Add Parent_Installed formal parameter + and pass it in call to Instantiate_Formal_Subprogram. + (Analyze_Formal_Package_Declaration): Pass Parent_Installed in call + to Analyze_Associations. + (Analyze_Package_Instantiation): Likewise. + (Analyze_Subprogram_Instantiation): Likewise. + (Instantiate_Formal_Subprogram): Add Parent_Installed formal + parameter and prune references to the parent unit(s) only if + it is true. + 2025-10-27 Eric Botcazou <ebotcazou@adacore.com> PR ada/29958 diff --git a/gcc/ada/sem_ch12.adb b/gcc/ada/sem_ch12.adb index b5c276a..cbb0deb 100644 --- a/gcc/ada/sem_ch12.adb +++ b/gcc/ada/sem_ch12.adb @@ -6735,7 +6735,7 @@ package body Sem_Ch12 is -- Remove package itself from visibility, so it does not -- conflict with subprogram. - Set_Name_Entity_Id (Chars (Pack_Id), Homonym (Pack_Id)); + Remove_Homonym (Pack_Id); -- Set name and scope of internal subprogram so that the proper -- external name will be generated. The proper scope is the scope diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index 39c1545..f0c089a 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -205,6 +205,10 @@ mmax-inline-memcpy-size= Target Joined RejectNegative UInteger Var(la_max_inline_memcpy_size) Init(1024) Save -mmax-inline-memcpy-size=SIZE Set the max size of memcpy to inline, default is 1024. +mbreak-code= +Target Joined UInteger Var(la_break_code) Init(-1) Save +-mbreak-code=CODE Use 'break CODE' for traps supposed to be unrecoverable, or an 'amswap.w' instruction leading to INE if CODE is out of range. + Enum Name(explicit_relocs) Type(int) The code model option names for -mexplicit-relocs: diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index eed4d2b..3048c48 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -834,59 +834,6 @@ [(set_attr "type" "simd_div") (set_attr "mode" "<MODE>")]) -(define_insn "xor<mode>3" - [(set (match_operand:LASX 0 "register_operand" "=f,f,f") - (xor:LASX - (match_operand:LASX 1 "register_operand" "f,f,f") - (match_operand:LASX 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))] - "ISA_HAS_LASX" - "@ - xvxor.v\t%u0,%u1,%u2 - xvbitrevi.%v0\t%u0,%u1,%V2 - xvxori.b\t%u0,%u1,%B2" - [(set_attr "type" "simd_logic,simd_bit,simd_logic") - (set_attr "mode" "<MODE>")]) - -(define_insn "ior<mode>3" - [(set (match_operand:LASX 0 "register_operand" "=f,f,f") - (ior:LASX - (match_operand:LASX 1 "register_operand" "f,f,f") - (match_operand:LASX 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))] - "ISA_HAS_LASX" - "@ - xvor.v\t%u0,%u1,%u2 - xvbitseti.%v0\t%u0,%u1,%V2 - xvori.b\t%u0,%u1,%B2" - [(set_attr "type" "simd_logic,simd_bit,simd_logic") - (set_attr "mode" "<MODE>")]) - -(define_insn "and<mode>3" - [(set (match_operand:LASX 0 "register_operand" "=f,f,f") - (and:LASX - (match_operand:LASX 1 "register_operand" "f,f,f") - (match_operand:LASX 2 "reg_or_vector_same_val_operand" "f,YZ,Urv8")))] - "ISA_HAS_LASX" -{ - switch (which_alternative) - { - case 0: - return "xvand.v\t%u0,%u1,%u2"; - case 1: - { - rtx elt0 = CONST_VECTOR_ELT (operands[2], 0); - unsigned HOST_WIDE_INT val = ~UINTVAL (elt0); - operands[2] = loongarch_gen_const_int_vector (<MODE>mode, val & (-val)); - return "xvbitclri.%v0\t%u0,%u1,%V2"; - } - case 2: - return "xvandi.b\t%u0,%u1,%B2"; - default: - gcc_unreachable (); - } -} - [(set_attr "type" "simd_logic,simd_bit,simd_logic") - (set_attr "mode" "<MODE>")]) - (define_insn "one_cmpl<mode>2" [(set (match_operand:ILASX 0 "register_operand" "=f") (not:ILASX (match_operand:ILASX 1 "register_operand" "f")))] diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 5c2a9eb..bdf2906 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -1718,14 +1718,36 @@ loongarch_symbol_binds_local_p (const_rtx x) bool loongarch_const_vector_bitimm_set_p (rtx op, machine_mode mode) { - if (GET_CODE (op) == CONST_VECTOR && op != CONST0_RTX (mode)) + if (GET_CODE (op) == CONST_VECTOR + && (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT + || GET_MODE_CLASS (mode) == MODE_VECTOR_INT)) { - unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (op, 0)); + unsigned HOST_WIDE_INT val; + + if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) + { + rtx val_s = CONST_VECTOR_ELT (op, 0); + const REAL_VALUE_TYPE *x = CONST_DOUBLE_REAL_VALUE (val_s); + if (GET_MODE (val_s) == DFmode) + { + long tmp[2]; + REAL_VALUE_TO_TARGET_DOUBLE (*x, tmp); + val = (unsigned HOST_WIDE_INT) tmp[1] << 32 | tmp[0]; + } + else + { + long tmp; + REAL_VALUE_TO_TARGET_SINGLE (*x, tmp); + val = (unsigned HOST_WIDE_INT) tmp; + } + } + else + val = UINTVAL (CONST_VECTOR_ELT (op, 0)); + int vlog2 = exact_log2 (val & GET_MODE_MASK (GET_MODE_INNER (mode))); if (vlog2 != -1) { - gcc_assert (GET_MODE_CLASS (mode) == MODE_VECTOR_INT); gcc_assert (vlog2 >= 0 && vlog2 <= GET_MODE_UNIT_BITSIZE (mode) - 1); return loongarch_const_vector_same_val_p (op, mode); } @@ -1740,14 +1762,35 @@ loongarch_const_vector_bitimm_set_p (rtx op, machine_mode mode) bool loongarch_const_vector_bitimm_clr_p (rtx op, machine_mode mode) { - if (GET_CODE (op) == CONST_VECTOR && op != CONSTM1_RTX (mode)) + if (GET_CODE (op) == CONST_VECTOR + && (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT + || GET_MODE_CLASS (mode) == MODE_VECTOR_INT)) { - unsigned HOST_WIDE_INT val = ~UINTVAL (CONST_VECTOR_ELT (op, 0)); + unsigned HOST_WIDE_INT val; + if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) + { + rtx val_s = CONST_VECTOR_ELT (op, 0); + const REAL_VALUE_TYPE *x = CONST_DOUBLE_REAL_VALUE (val_s); + if (GET_MODE (val_s) == DFmode) + { + long tmp[2]; + REAL_VALUE_TO_TARGET_DOUBLE (*x, tmp); + val = ~((unsigned HOST_WIDE_INT) tmp[1] << 32 | tmp[0]); + } + else + { + long tmp; + REAL_VALUE_TO_TARGET_SINGLE (*x, tmp); + val = ~((unsigned HOST_WIDE_INT) tmp); + } + } + else + val = ~UINTVAL (CONST_VECTOR_ELT (op, 0)); + int vlog2 = exact_log2 (val & GET_MODE_MASK (GET_MODE_INNER (mode))); if (vlog2 != -1) { - gcc_assert (GET_MODE_CLASS (mode) == MODE_VECTOR_INT); gcc_assert (vlog2 >= 0 && vlog2 <= GET_MODE_UNIT_BITSIZE (mode) - 1); return loongarch_const_vector_same_val_p (op, mode); } @@ -6450,7 +6493,28 @@ loongarch_print_operand (FILE *file, rtx op, int letter) if (CONST_VECTOR_P (op)) { machine_mode mode = GET_MODE_INNER (GET_MODE (op)); - unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (op, 0)); + rtx val_s = CONST_VECTOR_ELT (op, 0); + unsigned HOST_WIDE_INT val; + + if (GET_MODE_CLASS (mode) == MODE_FLOAT) + { + const REAL_VALUE_TYPE *x = CONST_DOUBLE_REAL_VALUE (val_s); + if (GET_MODE (val_s) == DFmode) + { + long tmp[2]; + REAL_VALUE_TO_TARGET_DOUBLE (*x, tmp); + val = (unsigned HOST_WIDE_INT) (tmp[1] << 32 | tmp[0]); + } + else + { + long tmp; + REAL_VALUE_TO_TARGET_SINGLE (*x, tmp); + val = (unsigned HOST_WIDE_INT) tmp; + } + } + else + val = UINTVAL (val_s); + int vlog2 = exact_log2 (val & GET_MODE_MASK (mode)); if (vlog2 != -1) fprintf (file, "%d", vlog2); diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index be9a235..625f30c 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -679,14 +679,22 @@ ;; .................... ;; -(define_insn "trap" - [(trap_if (const_int 1) (const_int 0))] +(define_insn "*trap" + [(trap_if (const_int 1) (match_operand 0 "const_int_operand"))] "" { - return "break\t0"; + return (const_uimm15_operand (operands[0], VOIDmode) + ? "break\t%0" + : "amswap.w\t$r0,$r1,$r0"); } [(set_attr "type" "trap")]) +(define_expand "trap" + [(trap_if (const_int 1) (match_dup 0))] + "" +{ + operands[0] = GEN_INT (la_break_code); +}) ;; diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index fbe61c0..628eabe 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -213,6 +213,10 @@ mmax-inline-memcpy-size= Target Joined RejectNegative UInteger Var(la_max_inline_memcpy_size) Init(1024) Save -mmax-inline-memcpy-size=SIZE Set the max size of memcpy to inline, default is 1024. +mbreak-code= +Target Joined UInteger Var(la_break_code) Init(-1) Save +-mbreak-code=CODE Use 'break CODE' for traps supposed to be unrecoverable, or an 'amswap.w' instruction leading to INE if CODE is out of range. + Enum Name(explicit_relocs) Type(int) The code model option names for -mexplicit-relocs: diff --git a/gcc/config/loongarch/loongarch.opt.urls b/gcc/config/loongarch/loongarch.opt.urls index 606a211..c93f046 100644 --- a/gcc/config/loongarch/loongarch.opt.urls +++ b/gcc/config/loongarch/loongarch.opt.urls @@ -48,6 +48,9 @@ UrlSuffix(gcc/LoongArch-Options.html#index-mstrict-align-1) mmax-inline-memcpy-size= UrlSuffix(gcc/LoongArch-Options.html#index-mmax-inline-memcpy-size) +mbreak-code= +UrlSuffix(gcc/LoongArch-Options.html#index-mbreak-code) + mexplicit-relocs= UrlSuffix(gcc/LoongArch-Options.html#index-mexplicit-relocs-1) diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index fb0236b..7131a53 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -654,59 +654,6 @@ [(set_attr "type" "simd_div") (set_attr "mode" "<MODE>")]) -(define_insn "xor<mode>3" - [(set (match_operand:LSX 0 "register_operand" "=f,f,f") - (xor:LSX - (match_operand:LSX 1 "register_operand" "f,f,f") - (match_operand:LSX 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))] - "ISA_HAS_LSX" - "@ - vxor.v\t%w0,%w1,%w2 - vbitrevi.%v0\t%w0,%w1,%V2 - vxori.b\t%w0,%w1,%B2" - [(set_attr "type" "simd_logic,simd_bit,simd_logic") - (set_attr "mode" "<MODE>")]) - -(define_insn "ior<mode>3" - [(set (match_operand:LSX 0 "register_operand" "=f,f,f") - (ior:LSX - (match_operand:LSX 1 "register_operand" "f,f,f") - (match_operand:LSX 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))] - "ISA_HAS_LSX" - "@ - vor.v\t%w0,%w1,%w2 - vbitseti.%v0\t%w0,%w1,%V2 - vori.b\t%w0,%w1,%B2" - [(set_attr "type" "simd_logic,simd_bit,simd_logic") - (set_attr "mode" "<MODE>")]) - -(define_insn "and<mode>3" - [(set (match_operand:LSX 0 "register_operand" "=f,f,f") - (and:LSX - (match_operand:LSX 1 "register_operand" "f,f,f") - (match_operand:LSX 2 "reg_or_vector_same_val_operand" "f,YZ,Urv8")))] - "ISA_HAS_LSX" -{ - switch (which_alternative) - { - case 0: - return "vand.v\t%w0,%w1,%w2"; - case 1: - { - rtx elt0 = CONST_VECTOR_ELT (operands[2], 0); - unsigned HOST_WIDE_INT val = ~UINTVAL (elt0); - operands[2] = loongarch_gen_const_int_vector (<MODE>mode, val & (-val)); - return "vbitclri.%v0\t%w0,%w1,%V2"; - } - case 2: - return "vandi.b\t%w0,%w1,%B2"; - default: - gcc_unreachable (); - } -} - [(set_attr "type" "simd_logic,simd_bit,simd_logic") - (set_attr "mode" "<MODE>")]) - (define_insn "one_cmpl<mode>2" [(set (match_operand:ILSX 0 "register_operand" "=f") (not:ILSX (match_operand:ILSX 1 "register_operand" "f")))] diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index 4156b26..9f4525a 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -972,6 +972,77 @@ DONE; }) +(define_insn "xor<mode>3" + [(set (match_operand:ALLVEC 0 "register_operand" "=f,f,f") + (xor:ALLVEC + (match_operand:ALLVEC 1 "register_operand" "f,f,f") + (match_operand:ALLVEC 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))] + "" + "@ + <x>vxor.v\t%<wu>0,%<wu>1,%<wu>2 + <x>vbitrevi.%v0\t%<wu>0,%<wu>1,%V2 + <x>vxori.b\t%<wu>0,%<wu>1,%B2" + [(set_attr "type" "simd_logic,simd_bit,simd_logic") + (set_attr "mode" "<MODE>")]) + +(define_insn "ior<mode>3" + [(set (match_operand:ALLVEC 0 "register_operand" "=f,f,f") + (ior:ALLVEC + (match_operand:ALLVEC 1 "register_operand" "f,f,f") + (match_operand:ALLVEC 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))] + "" + "@ + <x>vor.v\t%<wu>0,%<wu>1,%<wu>2 + <x>vbitseti.%v0\t%<wu>0,%<wu>1,%V2 + <x>vori.b\t%<wu>0,%<wu>1,%B2" + [(set_attr "type" "simd_logic,simd_bit,simd_logic") + (set_attr "mode" "<MODE>")]) + +(define_insn "and<mode>3" + [(set (match_operand:ALLVEC 0 "register_operand" "=f,f,f") + (and:ALLVEC + (match_operand:ALLVEC 1 "register_operand" "f,f,f") + (match_operand:ALLVEC 2 "reg_or_vector_same_val_operand" "f,YZ,Urv8")))] + "" +{ + switch (which_alternative) + { + case 0: + return "<x>vand.v\t%<wu>0,%<wu>1,%<wu>2"; + case 1: + { + rtx elt0 = CONST_VECTOR_ELT (operands[2], 0); + unsigned HOST_WIDE_INT val; + if (GET_MODE_CLASS (<MODE>mode) == MODE_VECTOR_FLOAT) + { + const REAL_VALUE_TYPE *x = CONST_DOUBLE_REAL_VALUE (elt0); + if (GET_MODE (elt0) == DFmode) + { + long tmp[2]; + REAL_VALUE_TO_TARGET_DOUBLE (*x, tmp); + val = ~((unsigned HOST_WIDE_INT) tmp[1] << 32 | tmp[0]); + } + else + { + long tmp; + REAL_VALUE_TO_TARGET_SINGLE (*x, tmp); + val = ~((unsigned HOST_WIDE_INT) tmp); + } + } + else + val = ~UINTVAL (elt0); + operands[2] = loongarch_gen_const_int_vector (<VIMODE>mode, val & (-val)); + return "<x>vbitclri.%v0\t%<wu>0,%<wu>1,%V2"; + } + case 2: + return "<x>vandi.b\t%<wu>0,%<wu>1,%B2"; + default: + gcc_unreachable (); + } +} + [(set_attr "type" "simd_logic,simd_bit,simd_logic") + (set_attr "mode" "<MODE>")]) + ; The LoongArch SX Instructions. (include "lsx.md") diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index e03b69c..ae4581a 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2025-10-28 Marek Polacek <polacek@redhat.com> + Jakub Jelinek <jakub@redhat.com> + + * decl.cc (finish_enum_value_list): Use fold_convert instead of + copy_node. + 2025-10-27 Nathaniel Shead <nathanieloshead@gmail.com> PR c++/122422 diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc index e2c20a3..751ba40 100644 --- a/gcc/cp/decl.cc +++ b/gcc/cp/decl.cc @@ -18958,13 +18958,9 @@ finish_enum_value_list (tree enumtype) value = perform_implicit_conversion (underlying_type, DECL_INITIAL (decl), tf_warning_or_error); - /* Do not clobber shared ints. */ - if (value != error_mark_node) - { - value = copy_node (value); + /* Do not clobber shared ints. But do share identical enumerators. */ + value = fold_convert (enumtype, value); - TREE_TYPE (value) = enumtype; - } DECL_INITIAL (decl) = value; if (export_p) DECL_MODULE_EXPORT_P (decl) = true; diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b40fc89..32b9c48 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1097,7 +1097,7 @@ Objective-C and Objective-C++ Dialects}. -mfpu=@var{fpu-type} -msimd=@var{simd-type} -msoft-float -msingle-float -mdouble-float -mlsx -mno-lsx -mlasx -mno-lasx -mbranch-cost=@var{n} -maddr-reg-reg-cost=@var{n} -mcheck-zero-division --mno-check-zero-division +-mno-check-zero-division -mbreak-code=@var{code} -mcond-move-int -mno-cond-move-int -mcond-move-float -mno-cond-move-float -memcpy -mno-memcpy -mstrict-align -mno-strict-align -G @var{num} @@ -28457,6 +28457,17 @@ Trap (do not trap) on integer division by zero. The default is @option{-mcheck-zero-division} for @option{-O0} or @option{-Og}, and @option{-mno-check-zero-division} for other optimization levels. +@opindex mbreak-code +@item -mbreak-code=@var{code} +Emit a @code{break} @var{code} instruction for irrecoverable traps +from @code{__builtin_trap} or inserted by the compiler (for example +an erroneous path isolated with +@option{-fisolate-erroneous-paths-dereference}), or an +@code{amswap.w $r0, $r1, $r0} instruction which will cause the hardware +to trigger an Instruction Not-defined Exception if @var{code} is negative +or greater than 32767. The default is -1, meaning to use the +@code{amswap.w} instruction. + @opindex mcond-move-int @item -mcond-move-int @itemx -mno-cond-move-int diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index c0a5710..cee5ef4 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,15 @@ +2025-10-28 Yuao Ma <c8ef@outlook.com> + + PR fortran/122342 + * trans-const.cc (gfc_conv_constant): Create a variable for the + non-char pointer. + +2025-10-28 Paul-Antoine Arras <parras@baylibre.com> + + PR fortran/122439 + * openmp.cc (gfc_resolve_omp_context_selector): Skip selectors that have + OMP_TRAIT_INVALID. + 2025-10-27 Paul Thomas <pault@gcc.gnu.org> PR fortran/922290 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 40f1582..e13b07d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,29 @@ +2025-10-28 Yuao Ma <c8ef@outlook.com> + + PR fortran/122342 + * gfortran.dg/coarray_atomic_5.f90: Update testcase. + * gfortran.dg/team_form_3.f90: Likewise. + +2025-10-28 Artemiy Volkov <artemiy.volkov@arm.com> + + * gcc.dg/tree-ssa/forwprop-42.c: New test. + +2025-10-28 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/specs/generic_inst5.ads: New test. + * gnat.dg/specs/generic_inst5_pkg1.ads: New helper. + * gnat.dg/specs/generic_inst5_pkg2.ads: Likewise. + +2025-10-28 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/specs/generic_inst4-child2.ads: New test. + * gnat.dg/specs/generic_inst4.ads: New helper. + * gnat.dg/specs/generic_inst4-child1.ads: Likewise. + +2025-10-28 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/specs/generic_inst3.ads: Add dg-do directive. + 2025-10-27 Nathaniel Shead <nathanieloshead@gmail.com> PR c++/122422 diff --git a/gcc/testsuite/gcc.target/loongarch/pr122097.c b/gcc/testsuite/gcc.target/loongarch/pr122097.c new file mode 100644 index 0000000..5d32b19 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr122097.c @@ -0,0 +1,271 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mabi=lp64d -mlsx" } */ +/* { dg-final { scan-assembler "vbitseti\.d\t\\\$vr\[0-9\]+,\\\$vr\[0-9\]+,63" } } */ + +typedef long unsigned int size_t; +typedef unsigned char simde__mmask8; +typedef long simde__m128i __attribute__ ((__aligned__ ((16)))) +__attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__)); +typedef union +{ + + __attribute__ ((__aligned__ ((16)))) long i64 + __attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__)); +} simde__m128i_private; +typedef double simde_float64; +typedef simde_float64 simde__m128d __attribute__ ((__aligned__ ((16)))) +__attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__)); +typedef long int int_fast32_t; +typedef union +{ + + __attribute__ ((__aligned__ ((16)))) int_fast32_t i32f + __attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__)); + __attribute__ ((__aligned__ ((16)))) long i64 + __attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__)); + __attribute__ ((__aligned__ ((16)))) simde_float64 f64 + __attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__)); +} simde__m128d_private; +__attribute__ ((__always_inline__)) inline static simde__m128d +simde__m128d_from_private (simde__m128d_private v) +{ + simde__m128d r; + __builtin_memcpy (&r, &v, sizeof (r)); + return r; +} + +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_mm_set_pd (simde_float64 e1, simde_float64 e0) +{ + + simde__m128d_private r_; + r_.f64[0] = e0; + r_.f64[1] = e1; + + return simde__m128d_from_private (r_); +} +__attribute__ ((__always_inline__)) inline static simde__m128i +simde_mm_castpd_si128 (simde__m128d a) +{ + simde__m128i r; + __builtin_memcpy (&r, &a, sizeof (a)); + return r; +} + +__attribute__ ((__always_inline__)) inline static simde__m128i +simde__m128i_from_private (simde__m128i_private v) +{ + simde__m128i r; + __builtin_memcpy (&r, &v, sizeof (r)); + return r; +} + +__attribute__ ((__always_inline__)) inline static simde__m128i_private +simde__m128i_to_private (simde__m128i v) +{ + simde__m128i_private r; + __builtin_memcpy (&r, &v, sizeof (r)); + return r; +} +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_mm_castsi128_pd (simde__m128i a) +{ + simde__m128d r; + __builtin_memcpy (&r, &a, sizeof (a)); + return r; +} + +__attribute__ ((__always_inline__)) inline static simde__m128i +simde_mm_mask_mov_epi64 (simde__m128i src, simde__mmask8 k, simde__m128i a) +{ + + simde__m128i_private src_ = simde__m128i_to_private (src), + a_ = simde__m128i_to_private (a), r_; + + for (size_t i = 0; i < (sizeof (r_.i64) / sizeof (r_.i64[0])); i++) + { + r_.i64[i] = ((k >> i) & 1) ? a_.i64[i] : src_.i64[i]; + } + + return simde__m128i_from_private (r_); +} + +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_mm_mask_mov_pd (simde__m128d src, simde__mmask8 k, simde__m128d a) +{ + return simde_mm_castsi128_pd (simde_mm_mask_mov_epi64 ( + simde_mm_castpd_si128 (src), k, simde_mm_castpd_si128 (a))); +} + +static double +simde_test_f64_precision_to_slop (int precision) +{ + return __builtin_expect (!!(precision == 0x7fffffff), 0) + ? 0.0 + : __builtin_pow (10.0, -((double)(precision))); +} +__attribute__ ((__always_inline__)) inline static void +simde_mm_storeu_pd (simde_float64 *mem_addr, simde__m128d a) +{ + + __builtin_memcpy (mem_addr, &a, sizeof (a)); +} +int simde_test_equal_f64 (simde_float64 a, simde_float64 b, + simde_float64 slop); +void simde_test_debug_printf_ (const char *format, ...); +static int +simde_assert_equal_vf64_ (size_t vec_len, simde_float64 const a[(vec_len)], + simde_float64 const b[(vec_len)], simde_float64 slop, + const char *filename, int line, const char *astr, + const char *bstr) +{ + for (size_t i = 0; i < vec_len; i++) + { + if (__builtin_expect (!!(!simde_test_equal_f64 (a[i], b[i], slop)), 0)) + { + simde_test_debug_printf_ ( + "%s:%d: assertion failed: %s[%zu] ~= %s[%zu] (%f ~= %f)\n", + filename, line, astr, i, bstr, i, ((double)(a[i])), + ((double)(b[i]))); + return 1; + } + } + return 0; +} +static int +simde_test_x86_assert_equal_f64x2_ (simde__m128d a, simde__m128d b, + simde_float64 slop, const char *filename, + int line, const char *astr, + const char *bstr) +{ + simde_float64 a_[sizeof (a) / sizeof (simde_float64)], + b_[sizeof (a) / sizeof (simde_float64)]; + simde_mm_storeu_pd (a_, a); + simde_mm_storeu_pd (b_, b); + return simde_assert_equal_vf64_ (sizeof (a_) / sizeof (a_[0]), a_, b_, slop, + filename, line, astr, bstr); +} +__attribute__ ((__always_inline__)) inline static simde__m128d_private +simde__m128d_to_private (simde__m128d v) +{ + simde__m128d_private r; + __builtin_memcpy (&r, &v, sizeof (r)); + return r; +} +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_mm_min_pd (simde__m128d a, simde__m128d b) +{ + + simde__m128d_private r_, a_ = simde__m128d_to_private (a), + b_ = simde__m128d_to_private (b); + + for (size_t i = 0; i < (sizeof (r_.f64) / sizeof (r_.f64[0])); i++) + { + r_.f64[i] = (a_.f64[i] < b_.f64[i]) ? a_.f64[i] : b_.f64[i]; + } + + return simde__m128d_from_private (r_); +} + +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_mm_max_pd (simde__m128d a, simde__m128d b) +{ + + simde__m128d_private r_, a_ = simde__m128d_to_private (a), + b_ = simde__m128d_to_private (b); + + for (size_t i = 0; i < (sizeof (r_.f64) / sizeof (r_.f64[0])); i++) + { + r_.f64[i] = (a_.f64[i] > b_.f64[i]) ? a_.f64[i] : b_.f64[i]; + } + + return simde__m128d_from_private (r_); +} + +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_x_mm_abs_pd (simde__m128d a) +{ + + simde__m128d_private r_, a_ = simde__m128d_to_private (a); + for (size_t i = 0; i < (sizeof (r_.f64) / sizeof (r_.f64[0])); i++) + { + r_.f64[i] = __builtin_fabs (a_.f64[i]); + } + + return simde__m128d_from_private (r_); +} +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_mm_cmple_pd (simde__m128d a, simde__m128d b) +{ + + simde__m128d_private r_, a_ = simde__m128d_to_private (a), + b_ = simde__m128d_to_private (b); + + r_.i64 = ((__typeof__ (r_.i64))((a_.f64 <= b_.f64))); + return simde__m128d_from_private (r_); +} + +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_x_mm_select_pd (simde__m128d a, simde__m128d b, simde__m128d mask) +{ + simde__m128d_private r_, a_ = simde__m128d_to_private (a), + b_ = simde__m128d_to_private (b), + mask_ = simde__m128d_to_private (mask); + + r_.i64 = a_.i64 ^ ((a_.i64 ^ b_.i64) & mask_.i64); + return simde__m128d_from_private (r_); +} +simde__m128d simde_mm_cmpge_pd (simde__m128d a, simde__m128d b); + +simde__m128d +simde_x_mm_copysign_pd (simde__m128d dest, simde__m128d src) +{ + simde__m128d_private r_, dest_ = simde__m128d_to_private (dest), + src_ = simde__m128d_to_private (src); + for (size_t i = 0; i < (sizeof (r_.f64) / sizeof (r_.f64[0])); i++) + { + r_.f64[i] = __builtin_copysign (dest_.f64[i], src_.f64[i]); + } + + return simde__m128d_from_private (r_); +} +simde__m128d simde_mm_or_pd (simde__m128d a, simde__m128d b); + +simde__m128d simde_mm_set1_pd (simde_float64 a); + +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_mm_range_pd (simde__m128d a, simde__m128d b, int imm8) +{ + simde__m128d r; + + r = simde_x_mm_select_pd ( + b, a, simde_mm_cmple_pd (simde_x_mm_abs_pd (a), simde_x_mm_abs_pd (b))); + + r = simde_x_mm_copysign_pd (r, a); + + return r; +} +int +test_simde_mm_mask_range_pd (void) +{ + + simde__m128d src, a, b, e, r; + + src = simde_mm_set_pd (-2.92, -85.39); + a = simde_mm_set_pd (-47.59, -122.31); + b = simde_mm_set_pd (877.42, 69.15); + e = simde_mm_set_pd (-47.59, -69.15); + r = simde_mm_mask_mov_pd (src, 143, simde_mm_range_pd (a, b, 2)); + do + { + if (simde_test_x86_assert_equal_f64x2_ ( + r, e, simde_test_f64_precision_to_slop (1), + "../test/x86/avx512/range.c", 1454, "r", "e")) + { + return 1; + } + } + while (0); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/loongarch/trap-1.c b/gcc/testsuite/gcc.target/loongarch/trap-1.c new file mode 100644 index 0000000..8936f60 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/trap-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -w -fisolate-erroneous-paths-dereference -mbreak-code=1" } */ +/* { dg-final { scan-assembler "break\\t1" } } */ + +int +bug (void) +{ + return *(int *)0; +} diff --git a/gcc/testsuite/gcc.target/loongarch/trap-default.c b/gcc/testsuite/gcc.target/loongarch/trap-default.c new file mode 100644 index 0000000..32948d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/trap-default.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -w -fisolate-erroneous-paths-dereference" } */ +/* { dg-final { scan-assembler "amswap\\.w\\t\\\$r0,\\\$r1,\\\$r0" } } */ + +int +bug (void) +{ + return *(int *)0; +} |