diff options
Diffstat (limited to 'gcc/testsuite')
282 files changed, 8043 insertions, 86 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e13b07d..452c9c9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,537 @@ +2025-11-02 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/122499 + * gm2.dg/spell/iso/fail/badimport2.mod: New test. + * gm2.dg/spell/iso/fail/badimport3.mod: New test. + * gm2.dg/spell/iso/fail/badimport4.mod: New test. + +2025-11-02 Eric Botcazou <ebotcazou@adacore.com> + + * gcc.target/sparc/small-struct-1.c: Run only on Solaris. + +2025-11-02 Eric Botcazou <ebotcazou@adacore.com> + + * gcc.target/sparc/cbcond-1.c: Accept reverse branches. + * gcc.target/sparc/cbcond-2.c: Likewise. + * gcc.target/sparc/overflow-3.c: Likewise. + * gcc.target/sparc/overflow-4.c: Likewise. + * gcc.target/sparc/overflow-5.c: Likewise. + +2025-11-02 Uros Bizjak <ubizjak@gmail.com> + + PR target/122518 + * gcc.target/i386/pr122518.c: New test. + +2025-11-02 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/specs/unknown_discr1.ads: New test. + * gnat.dg/specs/unknown_discr1_pkg.ads: New helper. + * gnat.dg/specs/unknown_discr1_pkg-child.ads: Likewise. + * gnat.dg/specs/unknown_discr1_pkg-g.ads: Likewise. + * gnat.dg/specs/unknown_discr1_pkg-inst.ads: Likewise. + +2025-11-02 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/use_type4.adb: New test. + +2025-11-02 Georg-Johann Lay <avr@gjlay.de> + + * gcc.target/avr/torture/pr84211-fuse-move-1.c: Add -fno-lto. + +2025-11-02 Nathaniel Shead <nathanieloshead@gmail.com> + + PR c++/122421 + * g++.dg/modules/inst-6_a.C: New test. + * g++.dg/modules/inst-6_b.C: New test. + +2025-11-01 Shreya Munnangi <smunnangi1@ventanamicro.com> + + PR target/67731 + * gcc.target/riscv/pr67731.c: New test. + * gcc.target/sh/pr67731.c: New test. + +2025-11-01 Jeff Law <jlaw@ventanamicro.com> + + PR rtl-optimization/122321 + * gcc.target/riscv/rvv/autovec/pr122321.c: New test. + +2025-11-01 Harald Anlauf <anlauf@gmx.de> + + PR fortran/78640 + * gfortran.dg/pure_result.f90: New test. + +2025-11-01 Nathaniel Shead <nathanieloshead@gmail.com> + + PR c++/122381 + * g++.dg/modules/convop-2_a.H: New test. + * g++.dg/modules/convop-2_b.C: New test. + +2025-11-01 Martin Uecker <uecker@tugraz.at> + + * gcc.dg/gnu-compoundlit-1.c: New test. + * gcc.dg/gnu-compoundlit-2.c: New test. + * gcc.dg/pr68090.c: Adapt. + * gcc.dg/vla-init-4.c: Adapt. + * gcc.dg/vla-init-5.c: Adapt. + +2025-11-01 Martin Uecker <uecker@tugraz.at> + + PR c/97986 + * gcc.dg/pr97986-1.c: New test. + * gcc.dg/pr97986-2.c: New test. + +2025-11-01 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * gcc.dg/fold-vecperm-1.c: Test at forwprop3. + +2025-10-31 Tamar Christina <tamar.christina@arm.com> + + PR target/121853 + * gcc.target/aarch64/pr121853_1.c: New test. + * gcc.target/aarch64/pr121853_2.c: New test. + +2025-10-31 Paul Thomas <pault@gcc.gnu.org> + + PR fortran/122452 + * gfortran.dg/pdt_65.f03: New test. + +2025-10-31 Richard Biener <rguenther@suse.de> + + PR tree-optimization/122502 + * gcc.dg/torture/pr122502.c: New testcase. + +2025-10-31 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * gcc.dg/tree-ssa/pr122478.c: Swap `1` and `"optimized"`. + +2025-10-31 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/122497 + * gcc.dg/torture/pr122497-1.c: New test. + +2025-10-31 Lulu Cheng <chenglulu@loongson.cn> + + * gcc.dg/vect/slp-widen-mult-half.c: Remove '-mlasx'. + * gcc.dg/vect/tree-vect.h: Check whether the runtime + environment supports LSX instructions. + * gcc.dg/vect/vect-widen-mult-const-s16.c: Dito. + * gcc.dg/vect/vect-widen-mult-const-u16.c: Dito. + * gcc.dg/vect/vect-widen-mult-half-u8.c: Dito. + * gcc.dg/vect/vect-widen-mult-half.c: Dito. + * gcc.dg/vect/vect-widen-mult-u16.c: Dito. + * gcc.dg/vect/vect-widen-mult-u8-s16-s32.c: Dito. + * gcc.dg/vect/vect-widen-mult-u8-u32.c: Dito. + * gcc.dg/vect/vect-widen-mult-u8.c: Dito. + +2025-10-30 Yap Zhi Heng <yapzhhg@gmail.com> + + * rust/compile/tuplepattern-restpattern-typecheck-err.rs: New file. + +2025-10-30 Ryo Yoshida <low.ryoshida@gmail.com> + + * rust/compile/match-tuplestructpattern-non-variant.rs: New test. + +2025-10-30 Yap Zhi Heng <yapzhhg@gmail.com> + + * rust/compile/issue-4231.rs: New file. + +2025-10-30 Lucas Ly Ba <lucas.ly-ba@outlook.fr> + + * rust/compile/issue-4212.rs: New test. + +2025-10-30 lishin <lishin1008@gmail.com> + + * rust/compile/issue-3556.rs: New test. + +2025-10-30 Ryo Yoshida <low.ryoshida@gmail.com> + + * rust/compile/tuple_index_on_non_tuple.rs: New test. + +2025-10-30 0xllx0 <github+elle@weathered-steel.dev> + + * rust/compile/issue-4145.rs: New test. + +2025-10-30 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/attr_malformed_doc.rs: New test. + +2025-10-30 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/attr_malformed_path.rs: New test. + +2025-10-30 Yap Zhi Heng <yapzhhg@gmail.com> + + * rust/compile/match-tuplestructpattern-err.rs: New file. + +2025-10-30 Yap Zhi Heng <yapzhhg@gmail.com> + + * rust/compile/match-tuplestructpattern-rest.rs: New file. + * rust/execute/torture/match-tuplestructpattern-rest-1.rs: New file. + * rust/execute/torture/match-tuplestructpattern-rest-2.rs: New file. + +2025-10-30 0xllx0 <github+elle@weathered-steel.dev> + + * rust/compile/issue-4148.rs: New test. + +2025-10-30 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/core/core.exp: New test. + +2025-10-30 Yap Zhi Heng <yapzhhg@gmail.com> + + * rust/compile/issue-3929-1.rs: New file. + * rust/compile/issue-3929-2.rs: New file. + +2025-10-30 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/execute/torture/link-name.rs: New test. + +2025-10-30 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/macros/mbe/macro58.rs: New test. + +2025-10-30 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/issue-3538.rs: New test. + +2025-10-30 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/issue-3592.rs: New test. + +2025-10-30 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/issue-4165.rs: New test. + +2025-10-30 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/issue-4090-1.rs: New test. + * rust/compile/issue-4090-2.rs: New test. + +2025-10-30 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/issue-4168.rs: New test. + +2025-10-30 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/issue-2394.rs: Update test case + * rust/compile/issue-4146.rs: New test. + +2025-10-30 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/issue-4139.rs: New test. + +2025-10-30 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/issue-4155.rs: New test. + +2025-10-30 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/issue-3922.rs: New test. + +2025-10-30 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/issue-3924.rs: New test. + +2025-10-30 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/issue-3969.rs: New test. + +2025-10-30 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/issue-3965-1.rs: New test. + * rust/compile/issue-3965-2.rs: New test. + +2025-10-30 Yap Zhi Heng <yapzhhg@gmail.com> + + * rust/compile/tuplepattern-rest-readonly.rs: New file. + +2025-10-30 Yap Zhi Heng <yapzhhg@gmail.com> + + * rust/compile/issue-3930.rs: New file. + +2025-10-30 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/issue-1725-2.rs: remove bad error message + +2025-10-30 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/use_self_alone_in_list.rs: New test. + +2025-10-30 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/use_self_alone.rs: New test. + +2025-10-30 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/primitive-import.rs: New test. + +2025-10-30 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/parse_float_dot.rs: New test. + +2025-10-30 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/format_args_concat.rs: New test. + +2025-10-30 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/global-path-array.rs: New test. + +2025-10-30 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/impl_fnptr.rs: New test. + +2025-10-30 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/parse_closure_bind.rs: New test. + +2025-10-30 lishin <lishin1008@gmail.com> + + * rust/compile/issue-3645.rs: New test. + +2025-10-30 Yap Zhi Heng <yapzhhg@gmail.com> + + * rust/compile/slice_rest_pattern.rs: Removed -fsyntax-only. + * rust/execute/torture/match-slicepattern-array-2.rs: New file. + * rust/execute/torture/match-slicepattern-slice-2.rs: New file. + +2025-10-30 Yap Zhi Heng <yapzhhg@gmail.com> + + * rust/execute/torture/let-identifierpattern-subpattern.rs: New file. + +2025-10-30 lishin <lishin1008@gmail.com> + + * rust/compile/issue-3958.rs: New test. + +2025-10-30 lishin <lishin1008@gmail.com> + + * rust/compile/issue-3947.rs: New test. + +2025-10-30 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/issue-3966.rs: New test. + +2025-10-30 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/use_3.rs: New test. + +2025-10-30 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/issue-3974.rs: New test. + +2025-10-30 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/compile/issue-3726.rs: New test. + * rust/compile/issue-3898.rs: New test. + +2025-10-30 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/macros/mbe/macro-issue4054.rs: New test. + +2025-10-30 Ryutaro Okada <1015ryu88@gmail.com> + + * rust/compile/enum_discriminant3.rs: New test. + +2025-10-30 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/cfg-test.rs: New test. + +2025-10-30 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/import_wildcards.rs: New test. + +2025-10-30 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/macros/mbe/macro49.rs: Add missing lang items. + +2025-10-30 lishin <lishin1008@gmail.com> + + * rust/compile/issue-3928.rs: New test. + +2025-10-30 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/execute/inline_asm_inout_ident.rs: Add arch filter on test. + * rust/execute/inline_asm_inout_var.rs: Likewise. + +2025-10-30 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/attr-macro.rs: New test. + +2025-10-30 David Faust <david.faust@oracle.com> + + PR debug/122248 + * gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-4.c: New. + * gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-5.c: New. + * gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-6.c: New. + +2025-10-30 David Faust <david.faust@oracle.com> + + * gcc.dg/debug/btf/btf-prune-4.c: New. + +2025-10-30 Eric Botcazou <ebotcazou@adacore.com> + + * gcc.dg/cpp/escape-3.i: Remove parentheses in dg-scan directive. + +2025-10-30 Qing Zhao <qing.zhao@oracle.com> + + * gcc.dg/pointer-counted-by.c: Update for void pointers. + * gcc.dg/pointer-counted-by-10.c: New test. + * gcc.dg/pointer-counted-by-4-void.c: New test. + +2025-10-30 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR target/116075 + * gcc.target/aarch64/sve/dup-insr-1.c: New test. + * gcc.target/aarch64/sve/dup-insr-2.c: New test. + +2025-10-30 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/122247 + * g++.dg/tree-ssa/copy-prop-aggregate-sra-2.C: New test. + +2025-10-30 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/122247 + * g++.dg/tree-ssa/copy-prop-aggregate-sra-1.C: New test. + +2025-10-30 Robin Dapp <rdapp@ventanamicro.com> + + * gcc.dg/tree-ssa/ctz-char.c: Remove -fno-tree-ch. + * gcc.dg/tree-ssa/ctz-complement-char.c: Ditto. + * gcc.dg/tree-ssa/ctz-complement-int.c: Ditto. + * gcc.dg/tree-ssa/ctz-complement-long-long.c: Ditto. + * gcc.dg/tree-ssa/ctz-complement-long.c: Ditto. + * gcc.dg/tree-ssa/ctz-int.c: Ditto. + * gcc.dg/tree-ssa/ctz-long-long.c: Ditto. + * gcc.dg/tree-ssa/ctz-long.c: Ditto. + * gcc.dg/tree-ssa/ctz-ch.c: New test. + * gcc.dg/pr41488.c: Add -fno-tree-scev-cprop. + +2025-10-30 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/specs/generic_inst7.ads: New test. + * gnat.dg/specs/generic_inst8.ads: New test. + +2025-10-30 Robin Dapp <rdapp.gcc@gmail.com> + + PR target/122445 + * gcc.target/riscv/rvv/autovec/pr122445.c: New test. + +2025-10-30 Artemiy Volkov <artemiy.volkov@arm.com> + + PR tree-optimization/122478 + * gcc.dg/tree-ssa/pr122478.c: New test. + +2025-10-30 Richard Biener <rguenther@suse.de> + + * gcc.dg/tree-ssa/pr92834.c: Scan phiopt1 instead of optimized. + +2025-10-30 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + PR rtl-optimization/121198 + * gcc.target/avr/pr121198.c: New test. + +2025-10-30 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/122485 + * gm2.dg/spell/iso/fail/badimport.mod: New test. + +2025-10-30 Richard Biener <rguenther@suse.de> + Eric Botcazou <ebotcazou@adacore.com> + + * gcc.dg/vect/slp-reduc-13.c: New testcase. + +2025-10-30 Uros Bizjak <ubizjak@gmail.com> + + PR target/116815 + * gcc.dg/pr116815.c: New test. + * gcc.target/i386/pr116815.c: New test. + +2025-10-30 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * c-c++-common/ubsan/align-5.c: Xfail. + * gcc.dg/pr107389.c: Move to... + * gcc.dg/torture/pr107389.c: ...here. Skip for lto. + * gcc.dg/builtin-assume-aligned-1.c: Instead of + testing for deleting of assume-align, test for + the alignment/misalignment. Also disable the + vectorizer. + +2025-10-30 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + Revert: + 2025-10-30 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR middle-end/107389 + PR tree-optimization/122086 + * gcc.dg/pr107389.c: Move to... + * gcc.dg/torture/pr107389.c: ...here. Skip for lto. + Use dg-additional-options rather than dg-options. + * c-c++-common/ubsan/align-5.c: xfail. + +2025-10-30 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/pr122457.c: New test. + +2025-10-30 Guo Jie <guojie@loongson.cn> + + * gcc.target/loongarch/fnmam4-vec.c: New test. + +2025-10-30 Jinyang He <hejinyang@loongson.cn> + Peng Fan <fanpeng@loongson.cn> + + * gcc.target/loongarch/conditional-move-opt-1.c: Remove mul. + * gcc.target/loongarch/conditional-move-opt-2.c: Remove and. + * gcc.target/loongarch/conditional-move-opt-3.c: New test. + +2025-10-30 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/aggr32.adb: New test. + * gnat.dg/aggr32_pkg.ads: New helper. + * gnat.dg/aggr32_pkg-child.ads: Likewise. + +2025-10-30 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/specs/generic_inst6.ads: New test. + * gnat.dg/specs/generic_inst6_pkg1-child.ads: New helper. + * gnat.dg/specs/generic_inst6_pkg1-child-grand1.ads: Likewise. + * gnat.dg/specs/generic_inst6_pkg1-child-grand2.ads: Likewise. + * gnat.dg/specs/generic_inst6_pkg1.ads: Likewise. + * gnat.dg/specs/generic_inst6_pkg2.ads: Likewise. + * gnat.dg/specs/generic_inst6_pkg3.ads: Likewise. + +2025-10-29 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/91191 + * gcc.dg/pr91191.c: New. + +2025-10-29 Paul Thomas <pault@gcc.gnu.org> + + PR fortran/122165 + * gfortran.dg/pdt_64.f03: New test. + +2025-10-29 Richard Biener <rguenther@suse.de> + + PR tree-optimization/70102 + * gfortran.dg/vect/pr70102.f: New testcase. + +2025-10-29 Paul Thomas <pault@gcc.gnu.org> + + PR fortran/122433 + PR fortran/122434 + * gfortran.dg/pdt_62.f03: New test. + * gfortran.dg/pdt_63.f03: New test. + +2025-10-29 Lulu Cheng <chenglulu@loongson.cn> + + PR target/122097 + * gcc.target/loongarch/pr122097.c: New test. + +2025-10-29 Xi Ruoyao <xry111@xry111.site> + + * gcc.target/loongarch/trap-default.c: New test. + * gcc.target/loongarch/trap-1.c: New test. + 2025-10-28 Yuao Ma <c8ef@outlook.com> PR fortran/122342 diff --git a/gcc/testsuite/g++.dg/abi/param2.C b/gcc/testsuite/g++.dg/abi/param2.C index d28387a..4752717 100644 --- a/gcc/testsuite/g++.dg/abi/param2.C +++ b/gcc/testsuite/g++.dg/abi/param2.C @@ -1,7 +1,7 @@ // PR target/20795 // Test passing aligned empty aggregate // { dg-do compile } -// { dg-options "-Wno-psabi" { target { { i?86-*-* x86_64-*-* } && ilp32 } } } +// { dg-options "-Wno-psabi" { target { { { i?86-*-* x86_64-*-* } && ilp32 } || { riscv*-*-* } } } } struct S { union {} a; } __attribute__((aligned)); diff --git a/gcc/testsuite/g++.dg/lookup/koenig16.C b/gcc/testsuite/g++.dg/lookup/koenig16.C new file mode 100644 index 0000000..1d6e4e3 --- /dev/null +++ b/gcc/testsuite/g++.dg/lookup/koenig16.C @@ -0,0 +1,22 @@ +// Before P1787 (C++20), only hidden friends are included in ADL. +// After P1787, all friends are included. + +namespace N { + namespace NN { + struct A; + } + using NN::A; + void fn (A); + namespace NN { + struct A { + friend void N::fn (A); + }; + } + void fn (A) { } +} + +int main() +{ + N::A a; + fn(a); // { dg-error "not declared" "" { target c++17_down } } +} diff --git a/gcc/testsuite/g++.dg/modules/adl-11_a.C b/gcc/testsuite/g++.dg/modules/adl-11_a.C new file mode 100644 index 0000000..063dd89 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/adl-11_a.C @@ -0,0 +1,21 @@ +// Before P1787 (C++20), only hidden friends are included in ADL. +// After P1787, all friends are included. + +// { dg-additional-options "-fmodules -Wno-global-module" } + +export module M; + +namespace N { + namespace NN { + export struct A; + } + export using NN::A; + + export void fn (A); + + namespace NN { + struct A { + friend void N::fn (A); + }; + } +} diff --git a/gcc/testsuite/g++.dg/modules/adl-11_b.C b/gcc/testsuite/g++.dg/modules/adl-11_b.C new file mode 100644 index 0000000..f178915 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/adl-11_b.C @@ -0,0 +1,12 @@ +// Before P1787 (C++20), only hidden friends are included in ADL. +// After P1787, all friends are included. + +// { dg-additional-options -fmodules } + +import M; + +int main() +{ + N::A a; + fn(a); // { dg-error "not declared" "" { target c++17_down } } +} diff --git a/gcc/testsuite/g++.dg/modules/builtin-9_a.C b/gcc/testsuite/g++.dg/modules/builtin-9_a.C new file mode 100644 index 0000000..69b0e37 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/builtin-9_a.C @@ -0,0 +1,16 @@ +// Test that the built-in clog doesn't interfere with redeclaring the import. + +// { dg-additional-options "-fmodules -Wno-global-module" } + +module; + +namespace std { + class ostream; + extern ostream clog; +} + +export module M; + +namespace std { + export using std::clog; +} diff --git a/gcc/testsuite/g++.dg/modules/builtin-9_b.C b/gcc/testsuite/g++.dg/modules/builtin-9_b.C new file mode 100644 index 0000000..30ea013 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/builtin-9_b.C @@ -0,0 +1,8 @@ +// { dg-additional-options -fmodules } + +import M; + +namespace std { + class ostream; + extern ostream clog; +} diff --git a/gcc/testsuite/g++.dg/modules/clone-5_a.C b/gcc/testsuite/g++.dg/modules/clone-5_a.C new file mode 100644 index 0000000..4a72e8f --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/clone-5_a.C @@ -0,0 +1,25 @@ +// Test that a random instantiation of a constructor template doesn't end up in +// the overload set for other arguments. + +// { dg-do compile { target c++20 } } +// { dg-additional-options "-fmodules" } + +export module M; + +export { + inline int i; + + template <class T> + struct A { + A(const T* p, unsigned long len) { ++i; } + template <class B, class E> + requires (!__is_convertible(E,unsigned long)) + A(B,E) { ++i; } + }; + + inline void f() + { + const char *const p = nullptr; + A<char> a (p, p); // instantiate A<const char *, const char *> + } +} diff --git a/gcc/testsuite/g++.dg/modules/clone-5_b.C b/gcc/testsuite/g++.dg/modules/clone-5_b.C new file mode 100644 index 0000000..f66b465 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/clone-5_b.C @@ -0,0 +1,9 @@ +// { dg-additional-options -fmodules } + +import M; + +int main() +{ + const char *const p = nullptr; + A<char> (p, 0); +} diff --git a/gcc/testsuite/g++.dg/modules/convop-2_a.H b/gcc/testsuite/g++.dg/modules/convop-2_a.H new file mode 100644 index 0000000..62bb210 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/convop-2_a.H @@ -0,0 +1,10 @@ +// PR c++/122381 +// { dg-additional-options "-fmodule-header" } +// { dg-module-cmi {} } + +template <typename T> struct color_ref { + operator int() const { return 0; } + int foo(color_ref x) { + return x.operator int(); + } +}; diff --git a/gcc/testsuite/g++.dg/modules/convop-2_b.C b/gcc/testsuite/g++.dg/modules/convop-2_b.C new file mode 100644 index 0000000..d1e829e --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/convop-2_b.C @@ -0,0 +1,5 @@ +// PR c++/122381 +// { dg-additional-options "-fmodules" } + +import "convop-2_a.H"; +template struct color_ref<int>; diff --git a/gcc/testsuite/g++.dg/modules/inst-6_a.C b/gcc/testsuite/g++.dg/modules/inst-6_a.C new file mode 100644 index 0000000..7f35cc1 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/inst-6_a.C @@ -0,0 +1,14 @@ +// PR c++/122421 +// { dg-additional-options "-fmodules" } +// { dg-module-cmi M } + +export module M; + +export template <typename T> struct Type { + static const int arr[3]; +}; + +extern template const int Type<double>::arr[3]; +template <typename T> const int Type<T>::arr[] = { 42, 43, 44 }; + +export Type<int> ti; diff --git a/gcc/testsuite/g++.dg/modules/inst-6_b.C b/gcc/testsuite/g++.dg/modules/inst-6_b.C new file mode 100644 index 0000000..5a8092c --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/inst-6_b.C @@ -0,0 +1,12 @@ +// PR c++/122421 +// { dg-additional-options "-fmodules" } + +import M; + +int main() { + const int& a = Type<int>::arr[0]; + const int& b = Type<double>::arr[0]; +} + +// { dg-final { scan-assembler {_ZNW1M4TypeIiE3arrE:} } } +// { dg-final { scan-assembler-not {_ZNW1M4TypeIdE3arrE:} } } diff --git a/gcc/testsuite/g++.dg/modules/namespace-15_a.C b/gcc/testsuite/g++.dg/modules/namespace-15_a.C new file mode 100644 index 0000000..7c0c0e6 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/namespace-15_a.C @@ -0,0 +1,9 @@ +// Test that namespace deprecation is represented in the gcm. + +// { dg-additional-options "-fmodules" } + +export module M; + +export { + namespace [[deprecated]] N { } +} diff --git a/gcc/testsuite/g++.dg/modules/namespace-15_b.C b/gcc/testsuite/g++.dg/modules/namespace-15_b.C new file mode 100644 index 0000000..5128e82 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/namespace-15_b.C @@ -0,0 +1,5 @@ +// { dg-additional-options -fmodules } + +import M; + +using namespace N; // { dg-warning "deprecated" } diff --git a/gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-1.C b/gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-1.C new file mode 100644 index 0000000..52f1779 --- /dev/null +++ b/gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-1.C @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -fdump-tree-forwprop1-details -fdump-tree-esra-details -fexceptions" } */ + +/* PR tree-optimization/122247 */ + +struct s1 +{ + int t[1024]; +}; + +struct s1 f(void); + +void g(int a, int b, int ); +void p(struct s1); +void h(struct s1 outer) +{ + { + struct s1 inner = outer; + p(inner); + } + g(outer.t[0], outer.t[1], outer.t[2]); +} +/* Forwprop should be able to copy prop the copy of `inner = outer` to the call of p. + Also remove this copy. */ + +/* { dg-final { scan-tree-dump-times "after previous" 1 "forwprop1" } } */ +/* { dg-final { scan-tree-dump-times "Removing dead store stmt inner = outer" 1 "forwprop1" } } */ + +/* The extra copy that was done by inlining is removed so SRA should not decide to cause + inner nor outer to be scalarized even for the 3 elements accessed afterwards. */ +/* { dg-final { scan-tree-dump-times "Disqualifying inner" 1 "esra" } } */ +/* { dg-final { scan-tree-dump-times "Disqualifying outer" 1 "esra" } } */ + diff --git a/gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-2.C b/gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-2.C new file mode 100644 index 0000000..0b05d5d --- /dev/null +++ b/gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-2.C @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-forwprop1-details -fdump-tree-esra-details -fexceptions" } */ + +/* PR tree-optimization/122247 */ + +struct s1 +{ + int t[1024]; +}; + +struct s1 f(void); + +void g(int a, int b, int ); +void p(struct s1); +void h(struct s1 outer) +{ + struct s1 inner = outer; + p(inner); + g(outer.t[0], outer.t[1], outer.t[2]); +} +/* Forwprop should be able to copy prop the copy of `inner = outer` to the call of p. + Also remove this copy. */ + +/* { dg-final { scan-tree-dump-times "after previous" 1 "forwprop1" } } */ +/* { dg-final { scan-tree-dump-times "Removing dead store stmt inner = outer" 1 "forwprop1" } } */ + +/* The extra copy that was done by inlining is removed so SRA should not decide to cause + inner nor outer to be scalarized even for the 3 elements accessed afterwards. */ +/* { dg-final { scan-tree-dump-times "Disqualifying inner" 1 "esra" } } */ +/* { dg-final { scan-tree-dump-times "Disqualifying outer" 1 "esra" } } */ + diff --git a/gcc/testsuite/g++.target/aarch64/mv-cpu-features.C b/gcc/testsuite/g++.target/aarch64/mv-cpu-features.C index ad6accd..56e2916 100644 --- a/gcc/testsuite/g++.target/aarch64/mv-cpu-features.C +++ b/gcc/testsuite/g++.target/aarch64/mv-cpu-features.C @@ -41,6 +41,14 @@ int impl () #define _IFUNC_ARG_HWCAP (1ULL << 62) #endif +#ifndef HWCAP_ATOMICS +#define HWCAP_ATOMICS (1 << 8) +#endif + +#ifndef HWCAP2_RNG +#define HWCAP2_RNG (1 << 16) +#endif + extern "C" void __init_cpu_features_resolver (unsigned long hwcap, const ifunc_arg_t *arg); diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct+union-1.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct+union-1.cc new file mode 100644 index 0000000..69a1350 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct+union-1.cc @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Su2e_1f { + union { + struct { + } e1, e2; + } u; + float f; +}; +struct Su2e_1f echo_Su2e_1f(int i, float f, struct Su2e_1f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct+union-2.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct+union-2.cc new file mode 100644 index 0000000..763477c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct+union-2.cc @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Su2e_2f { + union { + struct { + } e1, e2; + } u; + float f; + float g; +}; +struct Su2e_2f echo_Su2e_2f(int i, float f, struct Su2e_2f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+8 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+8 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct+union-3.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct+union-3.cc new file mode 100644 index 0000000..5c9ce31 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct+union-3.cc @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Smu2e_1f { + union { + struct { + } e1, e2; + } u1; + struct { + float f; + union { + struct { + } e1, e2; + } u; + } ue; + union { + struct { + } e1, e2; + } u2; +}; +struct Smu2e_1f echo_Smu2e_1f(int i, float f, struct Smu2e_1f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct+union-4.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct+union-4.cc new file mode 100644 index 0000000..ecefc94 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct+union-4.cc @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Smu2e_2f { + union { + struct { + } e1, e2; + } u1; + struct { + float f; + float g; + union { + struct { + } e1, e2; + } u; + } ue; + union { + struct { + } e1, e2; + } u2; +}; +struct Smu2e_2f echo_Smu2e_2f(int i, float f, struct Smu2e_2f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+8 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+8 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct-1.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct-1.cc new file mode 100644 index 0000000..81f563e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct-1.cc @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Se_1f { + struct { + } e1; + float f; +}; +struct Se_1f echo_Se_1f(int i, float f, struct Se_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct-10.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct-10.cc new file mode 100644 index 0000000..167f54c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct-10.cc @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct S1ae_2f { + struct { + } e1[1]; + float f; + float g; +}; +struct S1ae_2f echo_S1ae_2f(int i, float f, struct S1ae_2f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(mem.*:DI .*\[.* s\+0 .*\]\)[[:space:]]+\(reg.*:DI \d+ a1\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(mem.*:DI .*\[.* s\+8 .*\]\)[[:space:]]+\(reg.*:DI \d+ a2\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0 .*\)[[:space:]]+\(subreg:DI \(reg.*:TI \d+ \[ <retval> \]\) 0\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 .*\)[[:space:]]+\(subreg:DI \(reg.*:TI \d+ \[ <retval> \]\) 8\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct-11.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct-11.cc new file mode 100644 index 0000000..057994d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct-11.cc @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Sm1ae_1f { + struct { + } e1[1]; + struct { + float f; + struct { + } e[1]; + } fe; + struct { + } e2[1]; +}; +struct Sm1ae_1f echo_Sm1ae_1f(int i, float f, struct Sm1ae_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(mem.*:DI .*\[.* s\+0 .*\]\)[[:space:]]+\(reg.*:DI \d+ a1\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(mem.*:DI .*\[.* s\+8 .*\]\)[[:space:]]+\(reg.*:DI \d+ a2\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0 .*\)[[:space:]]+\(subreg:DI \(reg.*:TI \d+ \[ <retval> \]\) 0\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 .*\)[[:space:]]+\(subreg:DI \(reg.*:TI \d+ \[ <retval> \]\) 8\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct-12.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct-12.cc new file mode 100644 index 0000000..d8f0154 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct-12.cc @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Sm1ae_2f { + struct { + } e1[1]; + struct { + float f; + float g; + struct { + } e[1]; + } fe; + struct { + } e2[1]; +}; +struct Sm1ae_2f echo_Sm1ae_2f(int i, float f, struct Sm1ae_2f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\[.* \.result_ptr\+0 .*\]} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct-2.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct-2.cc new file mode 100644 index 0000000..9d5669c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct-2.cc @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Se_2f { + struct { + } e1; + float f; + float g; +}; +struct Se_2f echo_Se_2f(int i, float f, struct Se_2f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+8 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+8 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct-3.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct-3.cc new file mode 100644 index 0000000..7b9e71a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct-3.cc @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Sme_1f { + struct { + } e1; + struct { + float f; + struct { + } e; + } fe; + struct { + } e2; +}; +struct Sme_1f echo_Sme_1f(int i, float f, struct Sme_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct-4.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct-4.cc new file mode 100644 index 0000000..aaec892 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct-4.cc @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Sme_2f { + struct { + } e1; + struct { + float f; + float g; + struct { + } e; + } fe; + struct { + } e2; +}; +struct Sme_2f echo_Sme_2f(int i, float f, struct Sme_2f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+8 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+8 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct-5.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct-5.cc new file mode 100644 index 0000000..0ae1e41 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct-5.cc @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct S0ae_1f { + struct { + } e1[0]; + float f; +}; +struct S0ae_1f echo_S0ae_1f(int i, float f, struct S0ae_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct-6.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct-6.cc new file mode 100644 index 0000000..d3d0b65 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct-6.cc @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct S0ae_2f { + struct { + } e1[0]; + float f; + float g; +}; +struct S0ae_2f echo_S0ae_2f(int i, float f, struct S0ae_2f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct-7.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct-7.cc new file mode 100644 index 0000000..9eae13d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct-7.cc @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Sm0ae_1f { + struct { + } e1[0]; + struct { + float f; + struct { + } e[0]; + } fe; + struct { + } e2[0]; +}; +struct Sm0ae_1f echo_Sm0ae_1f(int i, float f, struct Sm0ae_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct-8.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct-8.cc new file mode 100644 index 0000000..e7c81f4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct-8.cc @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Sm0ae_2f { + struct { + } e1[0]; + struct { + float f; + float g; + struct { + } e[0]; + } fe; + struct { + } e2[0]; +}; +struct Sm0ae_2f echo_Sm0ae_2f(int i, float f, struct Sm0ae_2f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-struct-9.cc b/gcc/testsuite/g++.target/riscv/abi/empty-struct-9.cc new file mode 100644 index 0000000..d36d50b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-struct-9.cc @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct S1ae_1f { + struct { + } e1[1]; + float f; +}; +struct S1ae_1f echo_S1ae_1f(int i, float f, struct S1ae_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(mem.*:DI .*\[.* s\+0 .*\]\)[[:space:]]+\(reg.*:DI \d+ a1\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\)[[:space:]]+\(reg.*:DI \d+ \[ <retval> \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-union-1.cc b/gcc/testsuite/g++.target/riscv/abi/empty-union-1.cc new file mode 100644 index 0000000..e3c2376 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-union-1.cc @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Seu_1f { + union { + } e1; + float f; +}; +struct Seu_1f echo_Seu_1f(int i, float f, struct Seu_1f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-union-2.cc b/gcc/testsuite/g++.target/riscv/abi/empty-union-2.cc new file mode 100644 index 0000000..d7b7d05 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-union-2.cc @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct S2eu_2f { + union { + } e1; + float f; + float g; +}; +struct S2eu_2f echo_S2eu_2f(int i, float f, struct S2eu_2f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+8 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+8 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-union-3.cc b/gcc/testsuite/g++.target/riscv/abi/empty-union-3.cc new file mode 100644 index 0000000..f12af7a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-union-3.cc @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Smeu_1f { + union { + } e1; + struct { + float f; + union { + } e; + } fe; + union { + } e2; +}; +struct Smeu_1f echo_Smeu_1f(int i, float f, struct Smeu_1f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/abi/empty-union-4.cc b/gcc/testsuite/g++.target/riscv/abi/empty-union-4.cc new file mode 100644 index 0000000..ab8c56e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/abi/empty-union-4.cc @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Smeu_2f { + union { + } e1; + struct { + float f; + float g; + union { + } e; + } fe; + union { + } e2; +}; +struct Smeu_2f echo_Smeu_2f(int i, float f, struct Smeu_2f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+8 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+8 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/g++.target/riscv/riscv.exp b/gcc/testsuite/g++.target/riscv/riscv.exp index f58e688..e268bd8 100644 --- a/gcc/testsuite/g++.target/riscv/riscv.exp +++ b/gcc/testsuite/g++.target/riscv/riscv.exp @@ -29,6 +29,7 @@ dg-init # Main loop. dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.C]] "" "" +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi/*.cc]] "" "" # All done. dg-finish diff --git a/gcc/testsuite/gcc.dg/builtin-assume-aligned-1.c b/gcc/testsuite/gcc.dg/builtin-assume-aligned-1.c index a74ecce..01aa884 100644 --- a/gcc/testsuite/gcc.dg/builtin-assume-aligned-1.c +++ b/gcc/testsuite/gcc.dg/builtin-assume-aligned-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -fdump-tree-optimized" } */ +/* { dg-options "-O3 -fno-tree-vectorize -fdump-tree-optimized-alias" } */ void test1 (double *out1, double *out2, double *out3, double *in1, @@ -19,6 +19,8 @@ test1 (double *out1, double *out2, double *out3, double *in1, } } +/* { dg-final { scan-tree-dump-times " ALIGN = 16, MISALIGN = 0" 5 "optimized" } } */ + void test2 (double *out1, double *out2, double *out3, double *in1, double *in2, int len) @@ -37,4 +39,8 @@ test2 (double *out1, double *out2, double *out3, double *in1, } } -/* { dg-final { scan-tree-dump-not "__builtin_assume_aligned" "optimized" } } */ + +/* { dg-final { scan-tree-dump-times " ALIGN = 32" 5 "optimized" } } */ +/* { dg-final { scan-tree-dump-times " ALIGN = 32, MISALIGN = 16" 4 "optimized" } } */ +/* { dg-final { scan-tree-dump-times " ALIGN = 32, MISALIGN = 0" 1 "optimized" } } */ + diff --git a/gcc/testsuite/gcc.dg/compat/pr83487-1_x.c b/gcc/testsuite/gcc.dg/compat/pr83487-1_x.c index b5b208f..22b71cf 100644 --- a/gcc/testsuite/gcc.dg/compat/pr83487-1_x.c +++ b/gcc/testsuite/gcc.dg/compat/pr83487-1_x.c @@ -1,4 +1,5 @@ /* { dg-options "-fno-common" { target { hppa*-*-hpux* } } } */ +/* { dg-options "-Wno-psabi" { target { riscv*-*-* } } } */ #include "pr83487-1.h" extern diff --git a/gcc/testsuite/gcc.dg/compat/pr83487-1_y.c b/gcc/testsuite/gcc.dg/compat/pr83487-1_y.c index ad336dd..cf275d8 100644 --- a/gcc/testsuite/gcc.dg/compat/pr83487-1_y.c +++ b/gcc/testsuite/gcc.dg/compat/pr83487-1_y.c @@ -1,4 +1,5 @@ /* { dg-options "-fno-common" { target { hppa*-*-hpux* } } } */ +/* { dg-options "-Wno-psabi" { target { riscv*-*-* } } } */ #include "pr83487-1.h" struct A a; diff --git a/gcc/testsuite/gcc.dg/compat/pr83487-2_x.c b/gcc/testsuite/gcc.dg/compat/pr83487-2_x.c index 7103194..399ac86 100644 --- a/gcc/testsuite/gcc.dg/compat/pr83487-2_x.c +++ b/gcc/testsuite/gcc.dg/compat/pr83487-2_x.c @@ -1,3 +1,4 @@ /* { dg-options "-fno-common" { target { hppa*-*-hpux* } } } */ +/* { dg-options "-Wno-psabi" { target { riscv*-*-* } } } */ #define PR83487_LARGE #include "pr83487-1_x.c" diff --git a/gcc/testsuite/gcc.dg/compat/pr83487-2_y.c b/gcc/testsuite/gcc.dg/compat/pr83487-2_y.c index e176783..dc6c1f8 100644 --- a/gcc/testsuite/gcc.dg/compat/pr83487-2_y.c +++ b/gcc/testsuite/gcc.dg/compat/pr83487-2_y.c @@ -1,3 +1,4 @@ /* { dg-options "-fno-common" { target { hppa*-*-hpux* } } } */ +/* { dg-options "-Wno-psabi" { target { riscv*-*-* } } } */ #define PR83487_LARGE #include "pr83487-1_y.c" diff --git a/gcc/testsuite/gcc.dg/cpp/escape-3.i b/gcc/testsuite/gcc.dg/cpp/escape-3.i index 6eb7dc4..cb47581 100644 --- a/gcc/testsuite/gcc.dg/cpp/escape-3.i +++ b/gcc/testsuite/gcc.dg/cpp/escape-3.i @@ -13,4 +13,4 @@ int foo (int a, int b) } /* Test for "/some\\directory" instead of "/some\\\\directory" */ -/* { dg-final { scan-assembler { "/some\\\\directory" } } } */ +/* { dg-final { scan-assembler "/some\\\\\\\\directory" } } */ diff --git a/gcc/testsuite/gcc.dg/debug/btf/btf-prune-4.c b/gcc/testsuite/gcc.dg/debug/btf/btf-prune-4.c new file mode 100644 index 0000000..3f19559 --- /dev/null +++ b/gcc/testsuite/gcc.dg/debug/btf/btf-prune-4.c @@ -0,0 +1,61 @@ +/* Test that -gprune-btf does not prune at typedefs. */ + +/* { dg-do compile } */ +/* { dg-options "-gbtf -gprune-btf -dA" } */ + +/* We must have the full definitions of td1 and td3. Neither are pruned. + td2 will be skipped entirely, only because the only reference to + it is through struct inner, which is pruned because inner itself + is only used as a pointer member. + + In general, we must never get an anonymous FWD; the only FWD in this + case will be for 'inner' */ + +/* Exactly 1 FWD for inner and no anonymous FWD. */ +/* { dg-final { scan-assembler-times "TYPE \[0-9\]+ BTF_KIND_FWD" 1 } } */ +/* { dg-final { scan-assembler-not "TYPE \[0-9\]+ BTF_KIND_FWD ''" } } */ +/* { dg-final { scan-assembler " BTF_KIND_FWD 'inner'" } } */ + +/* One anonymous struct for td1 and one anonymous union for td3. */ +/* { dg-final { scan-assembler-times "TYPE \[0-9\]+ BTF_KIND_STRUCT ''" 1 } } */ +/* { dg-final { scan-assembler-times "TYPE \[0-9\]+ BTF_KIND_UNION ''" 1 } } */ + +/* The two remaining typedefs. */ +/* { dg-final { scan-assembler " BTF_KIND_TYPEDEF 'td1'" } } */ +/* { dg-final { scan-assembler " BTF_KIND_TYPEDEF 'td3'" } } */ + +typedef struct { + int x; + char c; +} td1; + +typedef struct { + long l; + char b[4]; +} td2; + +typedef union { + long l; + unsigned short s[2]; +} td3; + +struct inner { + char a; + td2 *ptd; + long z; +}; + +struct A { + td1 *pt; + struct inner *in; + unsigned long l[4]; +}; + +struct A foo; + +struct B { + int x; + td3 **ppptd3; +}; + +struct B bar; diff --git a/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-4.c b/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-4.c new file mode 100644 index 0000000..6fdcdc6 --- /dev/null +++ b/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-4.c @@ -0,0 +1,28 @@ +/* Test DWARF generation for decl_tags on global decls appearing multiple + times with different decl_tags. PR122248. */ +/* { dg-do compile } */ +/* { dg-options "-gdwarf -dA" } */ + +#define __tag1 __attribute__((btf_decl_tag ("tag1"))) +#define __tag2 __attribute__((btf_decl_tag ("tag2"))) +#define __tag3 __attribute__((btf_decl_tag ("tag3"))) +#define __tag4 __attribute__((btf_decl_tag ("tag4"))) + +int foo __tag1; +int foo __tag2; + +/* Result: foo has __tag1 and __tag2. */ + +int bar __tag3; +int bar; + +/* Result: bar has __tag3. */ + +int baz; +int baz __tag4; + +/* Result: baz has __tag4. */ + +/* { dg-final { scan-assembler-times "DIE \\(\[^\n\]*\\) DW_TAG_GNU_annotation" 4 } } */ +/* { dg-final { scan-assembler-times " DW_AT_GNU_annotation" 4 } } */ + diff --git a/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-5.c b/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-5.c new file mode 100644 index 0000000..c7cb60c --- /dev/null +++ b/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-5.c @@ -0,0 +1,35 @@ +/* Test DWARF generation for decl_tags on global decls appearing multiple + times with different decl_tags. PR122248. */ +/* { dg-do compile } */ +/* { dg-options "-gdwarf -dA" } */ + +#define __tag1 __attribute__((btf_decl_tag ("tag1"))) +#define __tag2 __attribute__((btf_decl_tag ("tag2"))) +#define __tag3 __attribute__((btf_decl_tag ("tag3"))) + +struct S +{ + int x; + char c; +}; + +extern struct S foo __tag1; +struct S foo __tag2; + +/* Result: non-completing variable DIE for 'foo' has tag1, and the + completing DIE (with AT_specification) for 'foo' has tag2 -> tag1. */ + +extern int a __tag3; +int a; + +/* Result: non-completing variable DIE for a has tag3, and the + completing DIE (with AT_specification) for 'a' also refers to tag3. */ + +/* { dg-final { scan-assembler-times "DIE \\(\[^\n\]*\\) DW_TAG_GNU_annotation" 3 } } */ + +/* 5 AT_GNU annotations: + - foo -> tag1 + - foo -> tag2 -> tag1 + - a -> tag3 + - a -> tag3 */ +/* { dg-final { scan-assembler-times " DW_AT_GNU_annotation" 5 } } */ diff --git a/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-6.c b/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-6.c new file mode 100644 index 0000000..dd89d11 --- /dev/null +++ b/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-6.c @@ -0,0 +1,24 @@ +/* Test DWARF generation for decl_tags on global decls appearing multiple + times with different decl_tags. PR122248. */ +/* { dg-do compile } */ +/* { dg-options "-gdwarf -dA" } */ + +#define __tag1 __attribute__((btf_decl_tag ("tag1"))) +#define __tag2 __attribute__((btf_decl_tag ("tag2"))) +#define __tag3 __attribute__((btf_decl_tag ("tag3"))) + +__tag1 +extern int +do_thing (int); + +__tag2 +__tag3 +int +do_thing (int x) +{ + return x * x; +} + +/* Result: do_thing has all 3 tags. */ +/* { dg-final { scan-assembler-times "DIE \\(\[^\n\]*\\) DW_TAG_GNU_annotation" 3 } } */ +/* { dg-final { scan-assembler-times " DW_AT_GNU_annotation" 3 } } */ diff --git a/gcc/testsuite/gcc.dg/fold-vecperm-1.c b/gcc/testsuite/gcc.dg/fold-vecperm-1.c index 5d4456b..878d392 100644 --- a/gcc/testsuite/gcc.dg/fold-vecperm-1.c +++ b/gcc/testsuite/gcc.dg/fold-vecperm-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* { dg-options "-O2 -fdump-tree-forwprop3" } */ typedef int v4si __attribute__((vector_size(16))); typedef short v8hi __attribute__((vector_size(16))); @@ -20,4 +20,4 @@ int128 concat (int128 a, int128 b) { return res; } -/* { dg-final { scan-tree-dump-times "VEC_PERM_EXPR" 1 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "VEC_PERM_EXPR" 1 "forwprop3" } } */ diff --git a/gcc/testsuite/gcc.dg/gnu-compoundlit-1.c b/gcc/testsuite/gcc.dg/gnu-compoundlit-1.c new file mode 100644 index 0000000..a7f3496 --- /dev/null +++ b/gcc/testsuite/gcc.dg/gnu-compoundlit-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-std=gnu23" } */ + +int g(int n, int (*p)[n]); +int f(int n) +{ + return g(n, &(int[n]){ }); +} + +void h(int n) +{ + (int[n]){ 1 }; /* { dg-error "empty initializer" } */ +} + +void i(int n) +{ + (static int[3]){ }; + (static int[n]){ }; /* { dg-error "storage size" } */ + (constexpr int[3]){ }; + (constexpr int[n]){ }; /* { dg-error "storage size" } */ + (register int[3]){ }; /* { dg-error "register" } */ + (register int[n]){ }; /* { dg-error "register" } */ + (_Thread_local int[3]){ }; /* { dg-error "_Thread_local" } */ + (_Thread_local int[n]){ }; /* { dg-error "_Thread_local" } */ +} + diff --git a/gcc/testsuite/gcc.dg/gnu-compoundlit-2.c b/gcc/testsuite/gcc.dg/gnu-compoundlit-2.c new file mode 100644 index 0000000..dcc5775 --- /dev/null +++ b/gcc/testsuite/gcc.dg/gnu-compoundlit-2.c @@ -0,0 +1,20 @@ +/* { dg-do run } */ +/* { dg-options "-std=gnu23 -Wall" } */ + +[[gnu::noinline,gnu::noipa]] +static bool f(int n) +{ + struct foo { char a[n]; }; + struct foo x = { }; + + return 0 == __builtin_memcmp(&x, &(struct foo){ }, sizeof x); +} + +int main() +{ + if (!f(7)) + __builtin_abort(); + + return 0; +} + diff --git a/gcc/testsuite/gcc.dg/pointer-counted-by-10.c b/gcc/testsuite/gcc.dg/pointer-counted-by-10.c new file mode 100644 index 0000000..e2bd018 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pointer-counted-by-10.c @@ -0,0 +1,8 @@ +/* Testing the correct usage of attribute counted_by for pointer to void. */ +/* { dg-do compile } */ +/* { dg-options "-O0 -Wpointer-arith" } */ + +struct pointer_array { + int count; + void *array __attribute__ ((counted_by (count))); /* { dg-warning "attribute is used for a pointer to void" } */ +}; diff --git a/gcc/testsuite/gcc.dg/pointer-counted-by-4-void.c b/gcc/testsuite/gcc.dg/pointer-counted-by-4-void.c new file mode 100644 index 0000000..71bac95 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pointer-counted-by-4-void.c @@ -0,0 +1,6 @@ +/* Test the attribute counted_by for pointer field and its usage in + * __builtin_dynamic_object_size. */ +/* { dg-do run } */ +/* { dg-options "-O2" } */ +#define PTR_TYPE void +#include "pointer-counted-by-4.c" diff --git a/gcc/testsuite/gcc.dg/pointer-counted-by.c b/gcc/testsuite/gcc.dg/pointer-counted-by.c index 0f18828..5e9ebef 100644 --- a/gcc/testsuite/gcc.dg/pointer-counted-by.c +++ b/gcc/testsuite/gcc.dg/pointer-counted-by.c @@ -49,9 +49,10 @@ struct pointer_array_6 { int *array_6 __attribute__ ((counted_by (days))); }; +/* counted_by is allowed for pointer to void when GNU extension is enabled. */ struct pointer_array_7 { int count; - void *array_7 __attribute__ ((counted_by (count))); /* { dg-error "attribute is not allowed for a pointer to void" } */ + void *array_7 __attribute__ ((counted_by (count))); }; struct pointer_array_8 { diff --git a/gcc/testsuite/gcc.dg/pr116815.c b/gcc/testsuite/gcc.dg/pr116815.c new file mode 100644 index 0000000..b5f1330 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr116815.c @@ -0,0 +1,57 @@ +/* PR target/116815 */ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +[[gnu::always_inline]] +inline unsigned min (unsigned a, unsigned b) +{ + return (a < b) ? a : b; +} + +[[gnu::always_inline]] +inline unsigned max (unsigned a, unsigned b) +{ + return (a > b) ? a : b; +} + +[[gnu::noipa]] unsigned +umaxadd (unsigned a, unsigned b) +{ + return max (a + b, a); +} + +[[gnu::noipa]] unsigned +umaxsub (unsigned a, unsigned b) +{ + return max (a - b, a); +} + +[[gnu::noipa]] unsigned +uminadd (unsigned a, unsigned b) +{ + return min (a + b, a); +} + +[[gnu::noipa]] unsigned +uminsub (unsigned a, unsigned b) +{ + return min (a - b, a); +} + +int +main () +{ + /* Overflows to 0x30000000. */ + if (umaxadd (0x90000000, 0xa0000000) != 0x90000000) + __builtin_abort (); + + if (uminadd (0x90000000, 0xa0000000) != 0x30000000) + __builtin_abort (); + + /* Underflows to 0x60000000. */ + if (umaxsub (0x00000000, 0xa0000000) != 0x60000000) + __builtin_abort (); + + if (uminsub (0x00000000, 0xa0000000) != 0x00000000) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.dg/pr41488.c b/gcc/testsuite/gcc.dg/pr41488.c index 1e4bf19..a7ba367 100644 --- a/gcc/testsuite/gcc.dg/pr41488.c +++ b/gcc/testsuite/gcc.dg/pr41488.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -fdump-tree-ivcanon-scev" } */ +/* { dg-options "-O2 -fno-tree-scev-cprop -fdump-tree-ivcanon-scev" } */ struct struct_t { diff --git a/gcc/testsuite/gcc.dg/pr68090.c b/gcc/testsuite/gcc.dg/pr68090.c index 87b3b93..84e0ca4 100644 --- a/gcc/testsuite/gcc.dg/pr68090.c +++ b/gcc/testsuite/gcc.dg/pr68090.c @@ -1,13 +1,18 @@ /* PR c/68090 */ /* { dg-do compile } */ -/* { dg-options "" } */ +/* { dg-options "--pedantic-error" } */ void fn (int i) { (int[(0, 1)]) { 0 }; /* { dg-error "compound literal has variable size" } */ + /* { dg-error "variable-size" "" { target *-*-* } .-1 } */ (int[i]) { 0 }; /* { dg-error "compound literal has variable size" } */ + /* { dg-error "variable-size" "" { target *-*-* } .-1 } */ (int[(0, i)]) { 0 }; /* { dg-error "compound literal has variable size" } */ + /* { dg-error "variable-size" "" { target *-*-* } .-1 } */ (int [][i]){ 0 }; /* { dg-error "compound literal has variable size" } */ + /* { dg-error "variable-size" "" { target *-*-* } .-1 } */ (int [][(1, 2)]){ 0 }; /* { dg-error "compound literal has variable size" } */ + /* { dg-error "variable-size" "" { target *-*-* } .-1 } */ } diff --git a/gcc/testsuite/gcc.dg/pr97986-1.c b/gcc/testsuite/gcc.dg/pr97986-1.c new file mode 100644 index 0000000..87ee3d8 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr97986-1.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-options "-std=gnu23" } */ + +#include <stdarg.h> + +int f(int n, ...) +{ + __label__ b, d; + va_list ap; + va_start(ap, n); + _Static_assert(5 == sizeof(va_arg(ap, char[5]))); /* { dg-warning "array type" } */ + void g(void) { n++; goto b; } + int *a = va_arg((g(), ap), int[n]); /* { dg-warning "array type" } */ +b: + void h(void) { n++; goto d; } + typeof(va_arg(ap, int[(h(), n)])) c; /* { dg-warning "array type" } */ +d: + return n; +} + +int main() +{ + if (9 != f(7)) + __builtin_abort(); + return 0; +} + diff --git a/gcc/testsuite/gcc.dg/pr97986-2.c b/gcc/testsuite/gcc.dg/pr97986-2.c new file mode 100644 index 0000000..fc23a57 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr97986-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-std=c90" } */ + +#include <stdarg.h> + + +int f(int n, ...) +{ + va_list ap; + va_start(ap, n); + _Static_assert(5 == sizeof(va_arg(ap, char[5]))); + va_arg(ap, int[n]); /* { dg-error "array type" } */ + int * a = va_arg(ap, int[3]); /* { dg-error "invalid use of non-lvalue array" } */ +} + diff --git a/gcc/testsuite/gcc.dg/torture/pr122497-1.c b/gcc/testsuite/gcc.dg/torture/pr122497-1.c new file mode 100644 index 0000000..8b027ca --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr122497-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* PR tree-optimization/122497 */ + +/* This was ICEing during SCCP + trying to simplify a reference back to the phi + which was removed. */ + +char g_2[1][2]; +int g_4, g_5; +void main() { + for (; g_4; g_4 -= 1) + g_5 = g_2[g_4 + 2][g_4]; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr122502.c b/gcc/testsuite/gcc.dg/torture/pr122502.c new file mode 100644 index 0000000..5e2cb2e --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr122502.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ + +short int *ts; + +void +c2 (unsigned long long int s4, int ns) +{ + short int *b2 = (short int *)&ns; + + while (ns != 0) + { + int xn; + + for (xn = 0; xn < 3; ++xn) + for (*b2 = 0; *b2 < 2; ++*b2) + s4 += xn; + if (s4 != 0) + b2 = ts; + ++ns; + } +} diff --git a/gcc/testsuite/gcc.dg/torture/pr28814.c b/gcc/testsuite/gcc.dg/torture/pr28814.c index cf641ca..e835ff5 100644 --- a/gcc/testsuite/gcc.dg/torture/pr28814.c +++ b/gcc/testsuite/gcc.dg/torture/pr28814.c @@ -1,4 +1,5 @@ /* { dg-do compile { target { ilp32 || lp64 } } } */ +/* { dg-options "-Wno-psabi" { target { riscv*-*-* } } } */ struct w49 { diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ctz-ch.c b/gcc/testsuite/gcc.dg/tree-ssa/ctz-ch.c new file mode 100644 index 0000000..5d72597 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/ctz-ch.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ + +typedef unsigned long BITMAP_WORD; + +bool +bmp_iter_set (BITMAP_WORD bits, unsigned *bit_no) +{ + /* If our current word is nonzero, it contains the bit we want. */ + if (bits) + { + while (!(bits & 1)) + { + bits >>= 1; + *bit_no += 1; + } + return true; + } + + return false; +} + +/* { dg-final { scan-tree-dump-times "__builtin_ctz|\\.CTZ" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ctz-char.c b/gcc/testsuite/gcc.dg/tree-ssa/ctz-char.c index 3cd166a..fa8b7f3 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ctz-char.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ctz-char.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target ctz } */ -/* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ #define PREC (__CHAR_BIT__) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-char.c b/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-char.c index b9afe88..5ebc321 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-char.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-char.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target ctz } */ -/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */ #define PREC (__CHAR_BIT__) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-int.c b/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-int.c index d2702a6..0ce4b6b 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-int.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-int.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target ctz } */ -/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */ #define PREC (__CHAR_BIT__ * __SIZEOF_INT__) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long-long.c b/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long-long.c index 1ea0d5d..f98bec0 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long-long.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long-long.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target ctzll } */ -/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */ #define PREC (__CHAR_BIT__ * __SIZEOF_LONG_LONG__) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long.c b/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long.c index 80fb02d..8edb372 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target ctzl } */ -/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */ #define PREC (__CHAR_BIT__ * __SIZEOF_LONG__) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ctz-int.c b/gcc/testsuite/gcc.dg/tree-ssa/ctz-int.c index 7f63493..2bf3ae6 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ctz-int.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ctz-int.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target ctz } */ -/* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ #define PREC (__CHAR_BIT__ * __SIZEOF_INT__) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ctz-long-long.c b/gcc/testsuite/gcc.dg/tree-ssa/ctz-long-long.c index 924f61b..2e15948 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ctz-long-long.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ctz-long-long.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target ctzll } */ -/* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ #define PREC (__CHAR_BIT__ * __SIZEOF_LONG_LONG__) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ctz-long.c b/gcc/testsuite/gcc.dg/tree-ssa/ctz-long.c index 178945d..2e3be65 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ctz-long.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ctz-long.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target ctzl } */ -/* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ #define PREC (__CHAR_BIT__ * __SIZEOF_LONG__) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr122478.c b/gcc/testsuite/gcc.dg/tree-ssa/pr122478.c new file mode 100644 index 0000000..a39c91b --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr122478.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* { dg-additional-options "-fgimple" } */ + +unsigned char __GIMPLE (ssa) +foo (unsigned short mask__701) +{ + _Bool _19; + unsigned char _180; + +__BB(2): + _19 = __BIT_FIELD_REF <_Bool> (mask__701, 1, 12); + _180 = __VIEW_CONVERT<unsigned char>(_19); + return _180; +} + +/* { dg-final { scan-tree-dump-times "VIEW_CONVERT_EXPR" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr92834.c b/gcc/testsuite/gcc.dg/tree-ssa/pr92834.c index 889048d..70acf74 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr92834.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr92834.c @@ -1,8 +1,8 @@ /* PR tree-optimization/92834 */ /* { dg-do compile } */ -/* { dg-options "-O2 -fdump-tree-optimized" } */ -/* { dg-final { scan-tree-dump-times "MIN_EXPR <" 8 "optimized" } } */ -/* { dg-final { scan-tree-dump-times "MAX_EXPR <" 8 "optimized" } } */ +/* { dg-options "-O2 -fdump-tree-phiopt1" } */ +/* { dg-final { scan-tree-dump-times "MIN_EXPR <" 16 "phiopt1" } } */ +/* { dg-final { scan-tree-dump-times "MAX_EXPR <" 16 "phiopt1" } } */ static inline unsigned umax1 (unsigned a, unsigned b) diff --git a/gcc/testsuite/gcc.dg/vect/pr122475.c b/gcc/testsuite/gcc.dg/vect/pr122475.c new file mode 100644 index 0000000..ed229c5 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr122475.c @@ -0,0 +1,13 @@ +/* { dg-additional-options "-march=armv8-a+sve" { target aarch64*-*-* } } */ +/* Check that we don't ICE. */ +int a; +int b; +int main() { + for (char t = 0; t < 14; t += 2) + for (int u = 0; u < 242; u += 4) { + a = a < 0 ? a : 0; + b = b < 0 ? b : 0; + } +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 1 "vect" { target aarch64*-*-* } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/slp-reduc-13.c b/gcc/testsuite/gcc.dg/vect/slp-reduc-13.c new file mode 100644 index 0000000..00e91fc --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/slp-reduc-13.c @@ -0,0 +1,66 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-fgimple" } */ + +int q[2]; + +void __GIMPLE (ssa,guessed_local(16535624),startwith("loop")) +foo (int * r) +{ + int i; + int sum2; + int sum1; + int _1; + long unsigned int _2; + long unsigned int _3; + int * _4; + int _24; + __SIZETYPE__ _6; + __SIZETYPE__ _7; + int * _8; + int _9; + int _13; + unsigned int _30; + unsigned int _31; + + __BB(2,guessed_local(16535624)): + goto __BB3(precise(134217728)); + + __BB(3,loop_header(1),guessed_local(1057206200)): + sum1_5 = __PHI (__BB5: sum1_18, __BB2: 0); + sum2_26 = __PHI (__BB5: sum2_19, __BB2: 0); + i_28 = __PHI (__BB5: i_20, __BB2: 0); + _31 = __PHI (__BB5: _30, __BB2: 64u); + _1 = i_28 * 2; + _2 = (long unsigned int) _1; + _3 = _2 * 4ul; + _4 = r_17(D) + _3; + _24 = __MEM <int> (_4); + /* Deliberately have swapped operands here */ + sum1_18 = sum1_5 + _24; + _13 = _1 + 1; + _6 = (__SIZETYPE__) _13; + _7 = _6 * 4ul; + _8 = r_17(D) + _7; + _9 = __MEM <int> (_8); + /* versus here. */ + sum2_19 = _9 + sum2_26; + i_20 = i_28 + 1; + _30 = _31 - 1u; + if (_30 != 0u) + goto __BB5(guessed(132118446)); + else + goto __BB4(guessed(2099282)); + + __BB(5,guessed_local(1040670576)): + goto __BB3(precise(134217728)); + + __BB(4,guessed_local(16535624)): + sum1_33 = __PHI (__BB3: sum1_18); + sum2_32 = __PHI (__BB3: sum2_19); + q[0] = sum1_33; + q[1] = sum2_32; + return; +} + +/* { dg-final { scan-tree-dump "SLP discovery of size 2 reduction group succeeded" "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c b/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c index b69ade3..72811eb 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c +++ b/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c @@ -1,7 +1,6 @@ /* Disabling epilogues until we find a better way to deal with scans. */ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ -/* { dg-additional-options "-mlasx" { target loongarch*-*-* } } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/tree-vect.h b/gcc/testsuite/gcc.dg/vect/tree-vect.h index 1e4b56e..37908c9 100644 --- a/gcc/testsuite/gcc.dg/vect/tree-vect.h +++ b/gcc/testsuite/gcc.dg/vect/tree-vect.h @@ -76,6 +76,8 @@ check_vect (void) } #elif defined(__mips_msa) asm volatile ("or.v $w0,$w0,$w0"); +#elif defined(__loongarch__) + asm volatile ("vor.v\t$vr0,$vr0,$vr0"); #endif signal (SIGILL, SIG_DFL); } diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c index 53c9b84..dfbb217 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c @@ -2,7 +2,6 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ /* { dg-additional-options "-fno-ipa-icf" } */ -/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c index e9db828..c2ad58f 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c @@ -2,7 +2,6 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ /* { dg-additional-options "-fno-ipa-icf" } */ -/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c index 607f317..bfdcbaa 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c @@ -2,7 +2,6 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ /* { dg-additional-options "-fno-ipa-icf" } */ -/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c index cd13d82..e46b0cc 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c @@ -1,7 +1,6 @@ /* Disabling epilogues until we find a better way to deal with scans. */ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ -/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c index 258d253..14411ef 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c @@ -1,7 +1,6 @@ /* Disabling epilogues until we find a better way to deal with scans. */ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ -/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include <stdarg.h> #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c index 3baafca..f40def5 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c @@ -1,7 +1,6 @@ /* Disabling epilogues until we find a better way to deal with scans. */ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ -/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include <stdarg.h> #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c index bcfbe19..6386639 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c @@ -1,6 +1,5 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ -/* { dg-additional-options "-mlasx" { target loongarch*-*-* } } */ #include <stdarg.h> #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c index e3bf13b..78ad74b 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c @@ -1,6 +1,5 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ -/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include <stdarg.h> #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vla-init-4.c b/gcc/testsuite/gcc.dg/vla-init-4.c index 06351d0..7d1aa5b 100644 --- a/gcc/testsuite/gcc.dg/vla-init-4.c +++ b/gcc/testsuite/gcc.dg/vla-init-4.c @@ -4,4 +4,4 @@ /* { dg-options "" } */ const int i = 1; -void foo() { char *p = (char [i]){ "" }; } /* { dg-error "compound literal has variable size" } */ +void foo() { char *p = (char [i]){ "" }; } /* { dg-error "variable-sized object" } */ diff --git a/gcc/testsuite/gcc.dg/vla-init-5.c b/gcc/testsuite/gcc.dg/vla-init-5.c index aa9f491..2c249ec 100644 --- a/gcc/testsuite/gcc.dg/vla-init-5.c +++ b/gcc/testsuite/gcc.dg/vla-init-5.c @@ -4,4 +4,4 @@ /* { dg-options "" } */ const int i = 1; -void foo() { void *p = (char [][i]){ "" }; } /* { dg-error "compound literal has variable size" } */ +void foo() { void *p = (char [][i]){ "" }; } /* { dg-error "variable-sized object" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fmv_priority.in b/gcc/testsuite/gcc.target/aarch64/fmv_priority.in index 93209bc..4637369 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmv_priority.in +++ b/gcc/testsuite/gcc.target/aarch64/fmv_priority.in @@ -30,10 +30,12 @@ int fn [[gnu::target_version("fp16")]] (int) { return 1; } int fn_fp16(int) asm("fn._Mfp16"); int fn [[gnu::target_version("fp16fml")]] (int) { return 1; } int fn_fp16fml(int) asm("fn._Mfp16fml"); -/* TODO: These FMV features are not yet supported in GCC. */ -// int fn [[gnu::target_version("dit")]] (int) { return 1; } -// int fn [[gnu::target_version("dpb")]] (int) { return 1; } -// int fn [[gnu::target_version("dpb2")]] (int) { return 1; } +int fn [[gnu::target_version("dit")]] (int) { return 1; } +int fn_dit(int) asm("fn._Mdit"); +int fn [[gnu::target_version("dpb")]] (int) { return 1; } +int fn_dpb(int) asm("fn._Mdpb"); +int fn [[gnu::target_version("dpb2")]] (int) { return 1; } +int fn_dpb2(int) asm("fn._Mdpb2"); int fn [[gnu::target_version("jscvt")]] (int) { return 1; } int fn_jscvt(int) asm("fn._Mjscvt"); int fn [[gnu::target_version("fcma")]] (int) { return 1; } @@ -68,15 +70,14 @@ int fn [[gnu::target_version("sve2-sm4")]] (int) { return 1; } int fn_sve2_sm4(int) asm("fn._Msve2_sm4"); int fn [[gnu::target_version("sve2+sme")]] (int) { return 1; } int fn_sve2_sme(int) asm("fn._Msve2Msme"); -/* TODO: This FMV features is not yet supported in GCC. */ -// int fn [[gnu::target_version("memtag")]] (int) { return 1; } +int fn [[gnu::target_version("memtag")]] (int) { return 1; } +int fn_memtag(int) asm("fn._Mmemtag"); int fn [[gnu::target_version("sb")]] (int) { return 1; } int fn_sb(int) asm("fn._Msb"); -/* TODO: This FMV feature is not yet supported in GCC. */ -// int fn [[gnu::target_version("ssbs")]] (int) { return 1; } -// int fn_ssbs(int) asm("fn._Mssbs"); -/* TODO: This FMV feature is not yet supported in GCC. */ -// int fn [[gnu::target_version("bti")]] (int) { return 1; } +int fn [[gnu::target_version("ssbs")]] (int) { return 1; } +int fn_ssbs(int) asm("fn._Mssbs"); +int fn [[gnu::target_version("bti")]] (int) { return 1; } +int fn_bti(int) asm("fn._Mbti"); int fn [[gnu::target_version("wfxt")]] (int) { return 1; } int fn_wfxt(int) asm("fn._Mwfxt"); int fn [[gnu::target_version("sve2+sme-f64f64")]] (int) { return 1; } diff --git a/gcc/testsuite/gcc.target/aarch64/fmv_priority1.c b/gcc/testsuite/gcc.target/aarch64/fmv_priority1.c index 942b7a7..6075ccf 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmv_priority1.c +++ b/gcc/testsuite/gcc.target/aarch64/fmv_priority1.c @@ -81,14 +81,14 @@ int main () { if(resolver() != &fn_fp16fml) return 1; setCPUFeature (FEAT_DIT); - // if(resolver() != &fn_dit) return 1; - // + if(resolver() != &fn_dit) return 1; + setCPUFeature (FEAT_DPB); - // if(resolver() != &fn_dpb) return 1; - // + if(resolver() != &fn_dpb) return 1; + setCPUFeature (FEAT_DPB2); - // if(resolver() != &fn_dpb2) return 1; - // + if(resolver() != &fn_dpb2) return 1; + setCPUFeature (FEAT_JSCVT); if (resolver () != &fn_jscvt) return 1; @@ -102,8 +102,8 @@ int main () { if (resolver () != &fn_rcpc2) return 1; setCPUFeature (FEAT_RCPC3); - // if(resolver() != &fn_rcpc3) return 1; - // + if(resolver() != &fn_rcpc3) return 1; + setCPUFeature (FEAT_FRINTTS); if (resolver () != &fn_frintts) return 1; @@ -141,16 +141,16 @@ int main () { if (resolver () != &fn_sve2_sme) return 1; setCPUFeature(FEAT_MEMTAG2); - // if(resolver() != &fn_memtag) return 1; + if(resolver() != &fn_memtag) return 1; setCPUFeature (FEAT_SB); if (resolver () != &fn_sb) return 1; setCPUFeature(FEAT_SSBS2); - // if(resolver() != &fn_ssbs) return 1; + if(resolver() != &fn_ssbs) return 1; setCPUFeature(FEAT_BTI); - // if(resolver() != &fn_bti) return 1; + if(resolver() != &fn_bti) return 1; setCPUFeature (FEAT_WFXT); if (resolver () != &fn_wfxt) return 1; diff --git a/gcc/testsuite/gcc.target/aarch64/fmv_priority2.c b/gcc/testsuite/gcc.target/aarch64/fmv_priority2.c index dbeb15e..9464015 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmv_priority2.c +++ b/gcc/testsuite/gcc.target/aarch64/fmv_priority2.c @@ -14,7 +14,9 @@ /* { dg-final { scan-ipa-dump-times "fn\._Msm4/\[0-9\]+\\nfn\._MrdmaMrdm/\[0-9\]+\\nfn\._Mcrc/\[0-9\]+\\n" 1 "targetclone1" } } */ /* { dg-final { scan-ipa-dump-times "fn\._Mcrc/\[0-9\]+\\nfn\._Msha2/\[0-9\]+\\nfn\._Msha3/\[0-9\]+\\n" 1 "targetclone1" } } */ /* { dg-final { scan-ipa-dump-times "fn\._Msha3/\[0-9\]+\\nfn\._Maes/\[0-9\]+\\nfn\._Mfp16/\[0-9\]+\\n" 1 "targetclone1" } } */ -/* { dg-final { scan-ipa-dump-times "fn\._Mfp16/\[0-9\]+\\nfn\._Mfp16fml/\[0-9\]+\\nfn\._Mjscvt/\[0-9\]+\\n" 1 "targetclone1" } } */ +/* { dg-final { scan-ipa-dump-times "fn\._Mfp16/\[0-9\]+\\nfn\._Mfp16fml/\[0-9\]+\\nfn\._Mdit/\[0-9\]+\\n" 1 "targetclone1" } } */ +/* { dg-final { scan-ipa-dump-times "fn\._Mdit/\[0-9\]+\\nfn\._Mdpb/\[0-9\]+\\nfn\._Mdpb2/\[0-9\]+\\n" 1 "targetclone1" } } */ +/* { dg-final { scan-ipa-dump-times "fn\._Mdpb2/\[0-9\]+\\nfn\._Mjscvt/\[0-9\]+\\n" 1 "targetclone1" } } */ /* { dg-final { scan-ipa-dump-times "fn\._Mjscvt/\[0-9\]+\\nfn\._Mfcma/\[0-9\]+\\nfn\._Mrcpc/\[0-9\]+\\n" 1 "targetclone1" } } */ /* { dg-final { scan-ipa-dump-times "fn\._Mrcpc/\[0-9\]+\\nfn\._Mrcpc2/\[0-9\]+\\nfn\._Mrcpc3/\[0-9\]+\\n" 1 "targetclone1" } } */ /* { dg-final { scan-ipa-dump-times "fn\._Mrcpc3/\[0-9\]+\\nfn\._Mfrintts/\[0-9\]+\\nfn\._Mi8mm/\[0-9\]+\\n" 1 "targetclone1" } } */ @@ -23,7 +25,9 @@ /* { dg-final { scan-ipa-dump-times "fn\._Mf64mm/\[0-9\]+\\nfn\._Msve2/\[0-9\]+\\nfn\._Msve2_aes/\[0-9\]+\\n" 1 "targetclone1" } } */ /* { dg-final { scan-ipa-dump-times "fn\._Msve2_aes/\[0-9\]+\\nfn\._Msve2_bitperm/\[0-9\]+\\nfn\._Msve2_sha3/\[0-9\]+\\n" 1 "targetclone1" } } */ /* { dg-final { scan-ipa-dump-times "fn\._Msve2_sha3/\[0-9\]+\\nfn\._Msve2_sm4/\[0-9\]+\\nfn\._Msve2Msme/\[0-9\]+\\n" 1 "targetclone1" } } */ -/* { dg-final { scan-ipa-dump-times "fn\._Msve2Msme/\[0-9\]+\\nfn\._Msb/\[0-9\]+\\nfn\._Mwfxt/\[0-9\]+\\n" 1 "targetclone1" } } */ +/* { dg-final { scan-ipa-dump-times "fn\._Msve2Msme/\[0-9\]+\\nfn\._Mmemtag/\[0-9\]+\\nfn\._Msb/\[0-9\]+\\n" 1 "targetclone1" } } */ +/* { dg-final { scan-ipa-dump-times "fn\._Msb/\[0-9\]+\\nfn\._Mssbs/\[0-9\]+\\nfn\._Mbti/\[0-9\]+\\n" 1 "targetclone1" } } */ +/* { dg-final { scan-ipa-dump-times "fn\._Mbti/\[0-9\]+\\nfn\._Mwfxt/\[0-9\]+\\n" 1 "targetclone1" } } */ /* { dg-final { scan-ipa-dump-times "fn\._Mwfxt/\[0-9\]+\\nfn\._Msve2Msme_f64f64/\[0-9\]+\\nfn\._Msve2Msme_i16i64/\[0-9\]+\\n" 1 "targetclone1" } } */ /* { dg-final { scan-ipa-dump-times "fn\._Msve2Msme_i16i64/\[0-9\]+\\nfn\._Msve2Msme2/\[0-9\]+\\nfn\._Mmops/\[0-9\]+\\n" 1 "targetclone1" } } */ /* { dg-final { scan-ipa-dump-times "fn\._Mmops/\[0-9\]+\\nfn\._Mcssc/\[0-9\]+\\n" 1 "targetclone1" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr121853_1.c b/gcc/testsuite/gcc.target/aarch64/pr121853_1.c new file mode 100644 index 0000000..24b2fdc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr121853_1.c @@ -0,0 +1,64 @@ +/* { dg-do run } */ +/* { dg-additional-options "-O2 -std=c99" } */ + +#include <stdint.h> +#include <stdio.h> +#include <string.h> + +__attribute__ ((noipa)) +float convert(__bf16 value) { + return (float)value; +} + +static inline uint32_t f32_bits(float f) { + uint32_t u; memcpy(&u, &f, sizeof u); return u; +} +static inline __bf16 bf16_from_bits(uint16_t u) { + __bf16 b; memcpy(&b, &u, sizeof b); return b; +} + +/* Fixed bf16 inputs (as raw 16-bit payloads) covering edge cases. */ +static const uint16_t inputs[] = { + 0x0000, // +0 + 0x8000, // -0 + 0x7F80, // +inf + 0xFF80, // -inf + 0x7FC0, // qNaN (+) (quiet bit set in bf16) + 0xFFC0, // qNaN (-) + 0x7F01, // sNaN (+) (will be quieted by conversion) + 0xFF01, // sNaN (-) + 0x0001, // smallest +subnormal + 0x007F, // largest +subnormal + 0x8001, // smallest -subnormal + 0x807F, // largest -subnormal + 0x0080, // smallest +normal + 0x3F80, // +1.0 + 0xBF80, // -1.0 + 0x3F00, // +0.5 + 0xBF00, // -0.5 + 0x3FC0, // +1.5 + 0x7F7F, // max finite + + 0xFF7F, // max finite - +}; + +int main(void) { + const size_t N = sizeof(inputs)/sizeof(inputs[0]); + size_t fails = 0; + + for (size_t i = 0; i < N; ++i) { + __bf16 in = bf16_from_bits(inputs[i]); + float out = convert(in); + uint32_t got = f32_bits(out); + uint32_t exp = inputs[i] << 16; + + if (got != exp) { + printf("FAIL[%zu]: in_bf16=0x%04X exp_f32=0x%08X got_f32=0x%08X\n", + i, inputs[i], exp, got); + ++fails; + } + } + + if (fails != 0) + __builtin_abort (); +} + diff --git a/gcc/testsuite/gcc.target/aarch64/pr121853_2.c b/gcc/testsuite/gcc.target/aarch64/pr121853_2.c new file mode 100644 index 0000000..e9fb401 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr121853_2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O1" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +float convert(__bf16 value) { + return (float)value; +} + +/* +** convert: +** movi v[0-9]+.4s, 0 +** ext v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b, #14 +** ret +*/ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c b/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c new file mode 100644 index 0000000..41dcbba --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fdump-tree-optimized" } */ +/* PR target/116075 */ + +#include <arm_sve.h> + +svint8_t f(void) +{ + svint8_t tt; + tt = svdup_s8 (0); + tt = svinsr (tt, 0); + return tt; +} + +svint8_t f1(int8_t t) +{ + svint8_t tt; + tt = svdup_s8 (t); + tt = svinsr (tt, t); + return tt; +} + +/* The above 2 functions should have removed the VEC_SHL_INSERT. */ + +/* { dg-final { scan-tree-dump-not ".VEC_SHL_INSERT " "optimized" } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c b/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c new file mode 100644 index 0000000..8eafe97 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fdump-tree-optimized" } */ +/* PR target/116075 */ + +#include <arm_sve.h> + +svint8_t f(int8_t t) +{ + svint8_t tt; + tt = svdup_s8 (0); + tt = svinsr (tt, t); + return tt; +} + +svint8_t f1(int8_t t) +{ + svint8_t tt; + tt = svdup_s8 (t); + tt = svinsr (tt, 0); + return tt; +} + +/* The above 2 functions should not have removed the VEC_SHL_INSERT. */ + +/* { dg-final { scan-tree-dump-times ".VEC_SHL_INSERT " 2 "optimized" } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vect-reduc-bool-19.c b/gcc/testsuite/gcc.target/aarch64/sve/vect-reduc-bool-19.c new file mode 100644 index 0000000..6492c44 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/vect-reduc-bool-19.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-mautovec-preference=sve-only -fdump-tree-vect-details -O3 --param vect-epilogues-nomask=0" } */ + +int p[128]; + +bool __attribute__((noipa)) +fand (int n, bool r1, bool r2) +{ + bool r = true; + for (int i = 0; i < (n/2); i+=2) + { + r &= (p[i] != 0) & r1; + r &= (p[i+1] != 0) & r2; + } + return r; +} +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vect-reduc-bool-20.c b/gcc/testsuite/gcc.target/aarch64/sve/vect-reduc-bool-20.c new file mode 100644 index 0000000..83c5c20 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/vect-reduc-bool-20.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-mautovec-preference=sve-only -fdump-tree-vect-details -O3 --param vect-epilogues-nomask=0" } */ + +#include <stdbool.h> +#include <stdint.h> + +void vec_slp_cmp (char* restrict a, char* restrict b, int n) { + bool x0 = b[0] != 0; + bool x1 = b[1] != 0; + bool x2 = b[2] != 0; + bool x3 = b[3] != 0; + for (int i = 0; i < n; ++i) { + x0 &= (a[i * 4] != 0); + x1 &= (a[i * 4 + 1] != 0); + x2 &= (a[i * 4 + 2] != 0); + x3 &= (a[i * 4 + 3] != 0); + } + b[0] = x0; + b[1] = x1; + b[2] = x2; + b[3] = x3; +} + +void vec_slp_cmp1 (char* restrict a, char* restrict b, int n) { + bool x0 = b[0] != 0; + for (int i = 0; i < n; ++i) { + x0 &= (a[i] != 0); + } + b[0] = x0; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" { target aarch64*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/arc/movv2hi-be.c b/gcc/testsuite/gcc.target/arc/movv2hi-be.c new file mode 100644 index 0000000..7d4b8e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/movv2hi-be.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +typedef short v2hi __attribute__((vector_size(4))); + +__attribute__((noinline)) void foo3(short a) +{ + if (a != 520) + { + __builtin_abort(); + } +} + +__attribute__((noinline)) void foo2(v2hi v) +{ + foo3(v[0]); +} + +__attribute__((noinline)) void foo(v2hi *v) +{ + foo2(*v); +} + +int main (void) +{ + v2hi v; + v[0] = 520; + v[1] = -1; + foo(&v); + foo2(v); + return 0; +} diff --git a/gcc/testsuite/gcc.target/avr/pr121198.c b/gcc/testsuite/gcc.target/avr/pr121198.c new file mode 100644 index 0000000..551247e --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr121198.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mmcu=atmega8" } */ + +long +test (void) +{ + long x; + __asm__ ("" : "={r22}" (x)); + return x; +} diff --git a/gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-1.c b/gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-1.c index 82ce227..4924e9d 100644 --- a/gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-1.c +++ b/gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-additional-options -std=gnu99 } */ +/* Disable LTO since it has problems with flobal asm. */ +/* { dg-additional-options { -std=gnu99 -fno-lto } } */ #define USE_VALUE 0 diff --git a/gcc/testsuite/gcc.target/avr/torture/pr92606.c b/gcc/testsuite/gcc.target/avr/torture/pr92606.c index a391d7e..99d1ca6 100644 --- a/gcc/testsuite/gcc.target/avr/torture/pr92606.c +++ b/gcc/testsuite/gcc.target/avr/torture/pr92606.c @@ -14,10 +14,10 @@ typedef uint32_t T; { \ uint16_t __addr16 = (uint16_t)(X); \ uint32_t __result; \ - __asm__ __volatile__ ("lpm %A0, Z+" "\n\t" \ - "lpm %B0, Z+" "\n\t" \ - "lpm %C0, Z+" "\n\t" \ - "lpm %D0, Z" "\n\t" \ + __asm__ __volatile__ ("lpm $ mov %A0,r0 $ adiw %1,1" "\n\t" \ + "lpm $ mov %B0,r0 $ adiw %1,1" "\n\t" \ + "lpm $ mov %C0,r0 $ adiw %1,1" "\n\t" \ + "lpm $ mov %D0,r0" \ : "=r" (__result), "+z" (__addr16)); \ __result; \ })) diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-10.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-10.c new file mode 100644 index 0000000..43d6489 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-10.c @@ -0,0 +1,105 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove: +**.LFB0: +** .cfi_startproc +** cmpq \$63, %rdx +** ja .L12 +**.L1: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L12: +** movq %rdi, %rcx +** movq %rsi, %rax +** cmpq \$128, %rdx +** jbe .L13 +** movq %rdx, %rsi +** cmpq %rdi, %rax +** jb .L6 +** je .L1 +** movdqu -16\(%rax,%rdx\), %xmm7 +** movdqu -32\(%rax,%rdx\), %xmm6 +** movdqu -48\(%rax,%rdx\), %xmm5 +** movdqu -64\(%rax,%rdx\), %xmm4 +**.L7: +** movdqu \(%rax\), %xmm3 +** subq \$64, %rsi +** addq \$64, %rcx +** addq \$64, %rax +** movdqu -48\(%rax\), %xmm2 +** movdqu -32\(%rax\), %xmm1 +** movdqu -16\(%rax\), %xmm0 +** movups %xmm3, -64\(%rcx\) +** movups %xmm2, -48\(%rcx\) +** movups %xmm1, -32\(%rcx\) +** movups %xmm0, -16\(%rcx\) +** cmpq \$64, %rsi +** ja .L7 +** movups %xmm7, -16\(%rdi,%rdx\) +** movups %xmm6, -32\(%rdi,%rdx\) +** movups %xmm5, -48\(%rdi,%rdx\) +** movups %xmm4, -64\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L13: +** movdqu \(%rsi\), %xmm7 +** movdqu 16\(%rsi\), %xmm6 +** movdqu 32\(%rsi\), %xmm5 +** movdqu 48\(%rsi\), %xmm4 +** movdqu -16\(%rsi,%rdx\), %xmm3 +** movdqu -32\(%rsi,%rdx\), %xmm2 +** movdqu -48\(%rsi,%rdx\), %xmm1 +** movdqu -64\(%rsi,%rdx\), %xmm0 +** movups %xmm7, \(%rdi\) +** movups %xmm6, 16\(%rdi\) +** movups %xmm5, 32\(%rdi\) +** movups %xmm4, 48\(%rdi\) +** movups %xmm3, -16\(%rdi,%rdx\) +** movups %xmm2, -32\(%rdi,%rdx\) +** movups %xmm1, -48\(%rdi,%rdx\) +** movups %xmm0, -64\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L6: +** movdqu \(%rax\), %xmm3 +** movdqu 16\(%rax\), %xmm2 +** leaq \(%rdi,%rdx\), %rcx +** movdqu 32\(%rax\), %xmm1 +** movdqu 48\(%rax\), %xmm0 +** addq %rdx, %rax +**.L8: +** movdqu -16\(%rax\), %xmm7 +** movdqu -32\(%rax\), %xmm6 +** subq \$64, %rsi +** subq \$64, %rcx +** movdqu -48\(%rax\), %xmm5 +** movdqu -64\(%rax\), %xmm4 +** subq \$64, %rax +** movups %xmm7, 48\(%rcx\) +** movups %xmm6, 32\(%rcx\) +** movups %xmm5, 16\(%rcx\) +** movups %xmm4, \(%rcx\) +** cmpq \$64, %rsi +** ja .L8 +** movups %xmm3, \(%rdi\) +** movups %xmm2, 16\(%rdi\) +** movups %xmm1, 32\(%rdi\) +** movups %xmm0, 48\(%rdi\) +** ret +** .cfi_endproc +**... +*/ + +void +gcc_memmove (void *a, void *b, __SIZE_TYPE__ n) +{ + if (n >= 64) + __builtin_memmove (a, b, n); +} diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-11a.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-11a.c new file mode 100644 index 0000000..3f4e2ca --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-11a.c @@ -0,0 +1,79 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_xmm: +**.LFB0: +** .cfi_startproc +** movq %rdi, %rax +** movl \$512, %edx +** cmpq %rdi, %rsi +** jb .L5 +** je .L1 +** movdqu 496\(%rsi\), %xmm7 +** movdqu 480\(%rsi\), %xmm6 +** movdqu 464\(%rsi\), %xmm5 +** movdqu 448\(%rsi\), %xmm4 +**.L6: +** movdqu \(%rsi\), %xmm3 +** movdqu 16\(%rsi\), %xmm2 +** subl \$64, %edx +** addq \$64, %rax +** movdqu 32\(%rsi\), %xmm1 +** movdqu 48\(%rsi\), %xmm0 +** addq \$64, %rsi +** movups %xmm3, -64\(%rax\) +** movups %xmm2, -48\(%rax\) +** movups %xmm1, -32\(%rax\) +** movups %xmm0, -16\(%rax\) +** cmpl \$64, %edx +** ja .L6 +** movups %xmm7, 496\(%rdi\) +** movups %xmm6, 480\(%rdi\) +** movups %xmm5, 464\(%rdi\) +** movups %xmm4, 448\(%rdi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L5: +** movdqu \(%rsi\), %xmm7 +** movdqu 16\(%rsi\), %xmm6 +** leaq 512\(%rdi\), %rax +** addq \$512, %rsi +** movdqu -480\(%rsi\), %xmm5 +** movdqu -464\(%rsi\), %xmm4 +**.L7: +** movdqu -16\(%rsi\), %xmm3 +** subl \$64, %edx +** subq \$64, %rax +** subq \$64, %rsi +** movdqu 32\(%rsi\), %xmm2 +** movdqu 16\(%rsi\), %xmm1 +** movdqu \(%rsi\), %xmm0 +** movups %xmm3, 48\(%rax\) +** movups %xmm2, 32\(%rax\) +** movups %xmm1, 16\(%rax\) +** movups %xmm0, \(%rax\) +** cmpl \$64, %edx +** ja .L7 +** movups %xmm7, \(%rdi\) +** movups %xmm6, 16\(%rdi\) +** movups %xmm5, 32\(%rdi\) +** movups %xmm4, 48\(%rdi\) +**.L1: +** ret +** .cfi_endproc +**... +*/ + +#ifndef gcc_memmove +#define gcc_memmove gcc_memmove_xmm +#endif + +void +gcc_memmove (void *a, void *b) +{ + __builtin_memmove (a, b, 512); +} diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-11b.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-11b.c new file mode 100644 index 0000000..031dd12 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-11b.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx512f -march=x86-64-v3 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_ymm: +**.LFB0: +** .cfi_startproc +** movq %rdi, %rax +** movl \$512, %edx +** cmpq %rdi, %rsi +** jb .L5 +** je .L10 +** vmovdqu 480\(%rsi\), %ymm7 +** vmovdqu 448\(%rsi\), %ymm6 +** vmovdqu 416\(%rsi\), %ymm5 +** vmovdqu 384\(%rsi\), %ymm4 +**.L6: +** vmovdqu \(%rsi\), %ymm3 +** vmovdqu 32\(%rsi\), %ymm2 +** addl \$-128, %edx +** subq \$-128, %rax +** vmovdqu 64\(%rsi\), %ymm1 +** vmovdqu 96\(%rsi\), %ymm0 +** subq \$-128, %rsi +** vmovdqu %ymm3, -128\(%rax\) +** vmovdqu %ymm2, -96\(%rax\) +** vmovdqu %ymm1, -64\(%rax\) +** vmovdqu %ymm0, -32\(%rax\) +** cmpl \$128, %edx +** ja .L6 +** vmovdqu %ymm7, 480\(%rdi\) +** vmovdqu %ymm6, 448\(%rdi\) +** vmovdqu %ymm5, 416\(%rdi\) +** vmovdqu %ymm4, 384\(%rdi\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L5: +** vmovdqu \(%rsi\), %ymm7 +** vmovdqu 32\(%rsi\), %ymm6 +** leaq 512\(%rdi\), %rax +** addq \$512, %rsi +** vmovdqu -448\(%rsi\), %ymm5 +** vmovdqu -416\(%rsi\), %ymm4 +**.L7: +** vmovdqu -32\(%rsi\), %ymm3 +** addl \$-128, %edx +** addq \$-128, %rax +** addq \$-128, %rsi +** vmovdqu 64\(%rsi\), %ymm2 +** vmovdqu 32\(%rsi\), %ymm1 +** vmovdqu \(%rsi\), %ymm0 +** vmovdqu %ymm3, 96\(%rax\) +** vmovdqu %ymm2, 64\(%rax\) +** vmovdqu %ymm1, 32\(%rax\) +** vmovdqu %ymm0, \(%rax\) +** cmpl \$128, %edx +** ja .L7 +** vmovdqu %ymm7, \(%rdi\) +** vmovdqu %ymm6, 32\(%rdi\) +** vmovdqu %ymm5, 64\(%rdi\) +** vmovdqu %ymm4, 96\(%rdi\) +** vzeroupper +**.L10: +** ret +** .cfi_endproc +**... +*/ + +#define gcc_memmove gcc_memmove_ymm +#include "builtin-memmove-11a.c" diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-11c.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-11c.c new file mode 100644 index 0000000..9c5e2c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-11c.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -mmove-max=512 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**gcc_memmove_zmm: +**.LFB0: +** .cfi_startproc +** vmovdqu64 \(%(e|r)si\), %zmm7 +** vmovdqu64 64\(%(e|r)si\), %zmm6 +** vmovdqu64 128\(%(e|r)si\), %zmm5 +** vmovdqu64 192\(%(e|r)si\), %zmm4 +** vmovdqu64 256\(%(e|r)si\), %zmm3 +** vmovdqu64 320\(%(e|r)si\), %zmm2 +** vmovdqu64 384\(%(e|r)si\), %zmm1 +** vmovdqu64 448\(%(e|r)si\), %zmm0 +** vmovdqu64 %zmm7, \(%(e|r)di\) +** vmovdqu64 %zmm6, 64\(%(e|r)di\) +** vmovdqu64 %zmm5, 128\(%(e|r)di\) +** vmovdqu64 %zmm4, 192\(%(e|r)di\) +** vmovdqu64 %zmm3, 256\(%(e|r)di\) +** vmovdqu64 %zmm2, 320\(%(e|r)di\) +** vmovdqu64 %zmm1, 384\(%(e|r)di\) +** vmovdqu64 %zmm0, 448\(%(e|r)di\) +** vzeroupper +** ret +** .cfi_endproc +**... +*/ + +#define gcc_memmove gcc_memmove_zmm +#include "builtin-memmove-11a.c" diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-12.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-12.c new file mode 100644 index 0000000..270df03 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-12.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**foo: +**.LFB0: +** .cfi_startproc +** movdqu a\+20\(%rip\), %xmm5 +** movdqu a\+36\(%rip\), %xmm4 +** movdqu a\+52\(%rip\), %xmm3 +** movdqu a\+68\(%rip\), %xmm2 +** movdqu a\+84\(%rip\), %xmm1 +** movdqu a\+100\(%rip\), %xmm0 +** movups %xmm5, a\+24\(%rip\) +** movq a\+116\(%rip\), %rax +** movdqu a\+4\(%rip\), %xmm6 +** movups %xmm4, a\+40\(%rip\) +** movl %edi, a\+4\(%rip\) +** movq %rax, a\+120\(%rip\) +** movups %xmm6, a\+8\(%rip\) +** movups %xmm3, a\+56\(%rip\) +** movups %xmm2, a\+72\(%rip\) +** movups %xmm1, a\+88\(%rip\) +** movups %xmm0, a\+104\(%rip\) +** ret +** .cfi_endproc +**... +*/ + +#define N 32 + +int a[N]; + +void +foo (int x) +{ + __builtin_memmove (a + 2, a + 1, sizeof a - 2 * sizeof *a); + a[1] = x; +} diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-13.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-13.c new file mode 100644 index 0000000..1c71cce --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-13.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**foo: +**.LFB0: +** .cfi_startproc +** movl a\+3\(%rip\), %eax +** movl %eax, a\(%rip\) +** movzbl a\+7\(%rip\), %eax +** movb %al, a\+4\(%rip\) +** ret +** .cfi_endproc +**... +*/ + +char a[8] = "12345678"; + +void +foo (void) +{ + __builtin_memmove (a, a + 3, sizeof a - 3); +} diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-14.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-14.c new file mode 100644 index 0000000..009c61d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-14.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove: +**.LFB0: +** .cfi_startproc +** cmpq \$64, %rdx +** jbe .L12 +**.L1: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L12: +** cmpl \$16, %edx +** jnb .L13 +** cmpl \$8, %edx +** jnb .L6 +** cmpl \$4, %edx +** jnb .L7 +** cmpl \$1, %edx +** ja .L8 +** jb .L1 +** movzbl \(%rsi\), %eax +** movb %al, \(%rdi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L13: +** cmpl \$32, %edx +** ja .L5 +** movl %edx, %edx +** movdqu \(%rsi\), %xmm1 +** movdqu -16\(%rsi,%rdx\), %xmm0 +** movups %xmm1, \(%rdi\) +** movups %xmm0, -16\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L5: +** movl %edx, %edx +** movdqu \(%rsi\), %xmm3 +** movdqu 16\(%rsi\), %xmm2 +** addq %rdx, %rsi +** movdqu -16\(%rsi\), %xmm1 +** movdqu -32\(%rsi\), %xmm0 +** movups %xmm3, \(%rdi\) +** movups %xmm2, 16\(%rdi\) +** movups %xmm1, -16\(%rdi,%rdx\) +** movups %xmm0, -32\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L6: +** movl %edx, %edx +** movq \(%rsi\), %rcx +** movq -8\(%rsi,%rdx\), %rax +** movq %rcx, \(%rdi\) +** movq %rax, -8\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L7: +** movl %edx, %edx +** movl \(%rsi\), %ecx +** movl -4\(%rsi,%rdx\), %eax +** movl %ecx, \(%rdi\) +** movl %eax, -4\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L8: +** movl %edx, %edx +** movzwl \(%rsi\), %ecx +** movzwl -2\(%rsi,%rdx\), %eax +** movw %cx, \(%rdi\) +** movw %ax, -2\(%rdi,%rdx\) +** ret +** .cfi_endproc +**... +*/ + +void +gcc_memmove (void *a, void *b, __SIZE_TYPE__ n) +{ + if (n <= 64) + __builtin_memmove (a, b, n); +} diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-15.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-15.c new file mode 100644 index 0000000..c1ccf44 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-15.c @@ -0,0 +1,114 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove: +**.LFB0: +** .cfi_startproc +** cmpq \$66, %rdx +** jbe .L12 +**.L1: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L12: +** cmpl \$16, %edx +** jnb .L13 +** cmpl \$8, %edx +** jnb .L6 +** cmpl \$4, %edx +** jnb .L7 +** cmpl \$1, %edx +** ja .L8 +** jb .L1 +** movzbl \(%rsi\), %eax +** movb %al, \(%rdi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L13: +** cmpl \$32, %edx +** ja .L5 +** movl %edx, %edx +** movdqu \(%rsi\), %xmm1 +** movdqu -16\(%rsi,%rdx\), %xmm0 +** movups %xmm1, \(%rdi\) +** movups %xmm0, -16\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L5: +** cmpl \$64, %edx +** jnb .L14 +** movl %edx, %edx +** movdqu \(%rsi\), %xmm3 +** movdqu 16\(%rsi\), %xmm2 +** addq %rdx, %rsi +** movdqu -16\(%rsi\), %xmm1 +** movdqu -32\(%rsi\), %xmm0 +** movups %xmm3, \(%rdi\) +** movups %xmm2, 16\(%rdi\) +** movups %xmm1, -16\(%rdi,%rdx\) +** movups %xmm0, -32\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L6: +** movl %edx, %edx +** movq \(%rsi\), %rcx +** movq -8\(%rsi,%rdx\), %rax +** movq %rcx, \(%rdi\) +** movq %rax, -8\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L14: +** movl %edx, %edx +** movdqu \(%rsi\), %xmm7 +** movdqu 16\(%rsi\), %xmm6 +** movdqu 32\(%rsi\), %xmm5 +** movdqu 48\(%rsi\), %xmm4 +** addq %rdx, %rsi +** movdqu -16\(%rsi\), %xmm3 +** movdqu -32\(%rsi\), %xmm2 +** movdqu -48\(%rsi\), %xmm1 +** movdqu -64\(%rsi\), %xmm0 +** movups %xmm7, \(%rdi\) +** movups %xmm6, 16\(%rdi\) +** movups %xmm5, 32\(%rdi\) +** movups %xmm4, 48\(%rdi\) +** movups %xmm3, -16\(%rdi,%rdx\) +** movups %xmm2, -32\(%rdi,%rdx\) +** movups %xmm1, -48\(%rdi,%rdx\) +** movups %xmm0, -64\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L7: +** movl %edx, %edx +** movl \(%rsi\), %ecx +** movl -4\(%rsi,%rdx\), %eax +** movl %ecx, \(%rdi\) +** movl %eax, -4\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L8: +** movl %edx, %edx +** movzwl \(%rsi\), %ecx +** movzwl -2\(%rsi,%rdx\), %eax +** movw %cx, \(%rdi\) +** movw %ax, -2\(%rdi,%rdx\) +** ret +** .cfi_endproc +**... +*/ + +void +gcc_memmove (void *a, void *b, __SIZE_TYPE__ n) +{ + if (n <= 66) + __builtin_memmove (a, b, n); +} diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-1a.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-1a.c new file mode 100644 index 0000000..3459875 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-1a.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**memmove7: +**.LFB[0-9]+: +** .cfi_startproc +** movl \(%(?:r|e)si\), %edx +** movl 3\(%(?:r|e)si\), %eax +** movl %edx, \(%(?:r|e)di\) +** movl %eax, 3\(%(?:r|e)di\) +** ret +**... +*/ + +/* +**memmove13: +**.LFB[0-9]+: +** .cfi_startproc +** movq \(%(?:r|e)si\), %rdx +** movq 5\(%(?:r|e)si\), %rax +** movq %rdx, \(%(?:r|e)di\) +** movq %rax, 5\(%(?:r|e)di\) +** ret +**... +*/ + +/* +**memmove31: +**.LFB[0-9]+: +** .cfi_startproc +** movdqu \(%(?:r|e)si\), %xmm1 +** movdqu 15\(%(?:r|e)si\), %xmm0 +** movups %xmm1, \(%(?:r|e)di\) +** movups %xmm0, 15\(%(?:r|e)di\) +** ret +**... +*/ + +/* +**memmove39: +**.LFB[0-9]+: +** .cfi_startproc +** movdqu \(%(?:r|e)si\), %xmm1 +** movdqu 16\(%(?:r|e)si\), %xmm0 +** movq 31\(%(?:r|e)si\), %rax +** movups %xmm0, 16\(%(?:r|e)di\) +** movups %xmm1, \(%(?:r|e)di\) +** movq %rax, 31\(%(?:r|e)di\) +** ret +**... +*/ + +/* +**memmove61: +**.LFB[0-9]+: +** .cfi_startproc +** movdqu \(%(?:r|e)si\), %xmm3 +** movdqu 16\(%(?:r|e)si\), %xmm2 +** movdqu 32\(%(?:r|e)si\), %xmm1 +** movdqu 45\(%(?:r|e)si\), %xmm0 +** movups %xmm3, \(%(?:r|e)di\) +** movups %xmm1, 32\(%(?:r|e)di\) +** movups %xmm2, 16\(%(?:r|e)di\) +** movups %xmm0, 45\(%(?:r|e)di\) +** ret +**... +*/ + +/* +**memmove69: +**.LFB[0-9]+: +** .cfi_startproc +** movdqu \(%(?:r|e)si\), %xmm3 +** movdqu 16\(%(?:r|e)si\), %xmm2 +** movdqu 32\(%(?:r|e)si\), %xmm1 +** movdqu 48\(%(?:r|e)si\), %xmm0 +** movq 61\(%(?:r|e)si\), %rax +** movups %xmm3, \(%(?:r|e)di\) +** movups %xmm0, 48\(%(?:r|e)di\) +** movups %xmm2, 16\(%(?:r|e)di\) +** movq %rax, 61\(%(?:r|e)di\) +** movups %xmm1, 32\(%(?:r|e)di\) +** ret +**... +*/ + +/* +**memmove93: +**.LFB[0-9]+: +** .cfi_startproc +** movdqu \(%(?:r|e)si\), %xmm5 +** movdqu 16\(%(?:r|e)si\), %xmm4 +** movdqu 32\(%(?:r|e)si\), %xmm3 +** movdqu 48\(%(?:r|e)si\), %xmm2 +** movdqu 64\(%(?:r|e)si\), %xmm1 +** movdqu 77\(%(?:r|e)si\), %xmm0 +** movups %xmm5, \(%(?:r|e)di\) +** movups %xmm4, 16\(%(?:r|e)di\) +** movups %xmm1, 64\(%(?:r|e)di\) +** movups %xmm3, 32\(%(?:r|e)di\) +** movups %xmm2, 48\(%(?:r|e)di\) +** movups %xmm0, 77\(%(?:r|e)di\) +** ret +**... +*/ + +#define TEST(n) \ + void \ + memmove##n (void *a, void *b) \ + { \ + __builtin_memmove (a, b, n); \ + } + +TEST (7) +TEST (13) +TEST (31) +TEST (39) +TEST (61) +TEST (69) +TEST (93) diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-1b.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-1b.c new file mode 100644 index 0000000..25d008c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-1b.c @@ -0,0 +1,98 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx512f -march=x86-64-v3 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**memmove7: +**.LFB[0-9]+: +** .cfi_startproc +** movl \(%(?:r|e)si\), %edx +** movl 3\(%(?:r|e)si\), %eax +** movl %edx, \(%(?:r|e)di\) +** movl %eax, 3\(%(?:r|e)di\) +** ret +**... +*/ + +/* +**memmove13: +**.LFB[0-9]+: +** .cfi_startproc +** movq \(%(?:r|e)si\), %rdx +** movq 5\(%(?:r|e)si\), %rax +** movq %rdx, \(%(?:r|e)di\) +** movq %rax, 5\(%(?:r|e)di\) +** ret +**... +*/ + +/* +**memmove31: +**.LFB[0-9]+: +** .cfi_startproc +** vmovdqu \(%(?:r|e)si\), %xmm1 +** vmovdqu 15\(%(?:r|e)si\), %xmm0 +** vmovdqu %xmm1, \(%(?:r|e)di\) +** vmovdqu %xmm0, 15\(%(?:r|e)di\) +** ret +**... +*/ + +/* +**memmove39: +**.LFB[0-9]+: +** .cfi_startproc +** vmovdqu \(%(?:r|e)si\), %ymm0 +** movq 31\(%(?:r|e)si\), %rax +** vmovdqu %ymm0, \(%(?:r|e)di\) +** movq %rax, 31\(%(?:r|e)di\) +** vzeroupper +** ret +**... +*/ + +/* +**memmove61: +**.LFB[0-9]+: +** .cfi_startproc +** vmovdqu \(%(?:r|e)si\), %ymm1 +** vmovdqu 29\(%(?:r|e)si\), %ymm0 +** vmovdqu %ymm1, \(%(?:r|e)di\) +** vmovdqu %ymm0, 29\(%(?:r|e)di\) +** vzeroupper +** ret +**... +*/ + +/* +**memmove69: +**.LFB[0-9]+: +** .cfi_startproc +** vmovdqu 32\(%(?:r|e)si\), %ymm0 +** movq 61\(%(?:r|e)si\), %rax +** vmovdqu \(%(?:r|e)si\), %ymm1 +** vmovdqu %ymm0, 32\(%(?:r|e)di\) +** movq %rax, 61\(%(?:r|e)di\) +** vmovdqu %ymm1, \(%(?:r|e)di\) +** vzeroupper +** ret +**... +*/ + +/* +**memmove93: +**.LFB[0-9]+: +** .cfi_startproc +** vmovdqu \(%(?:r|e)si\), %ymm2 +** vmovdqu 32\(%(?:r|e)si\), %ymm1 +** vmovdqu 61\(%(?:r|e)si\), %ymm0 +** vmovdqu %ymm1, 32\(%(?:r|e)di\) +** vmovdqu %ymm2, \(%(?:r|e)di\) +** vmovdqu %ymm0, 61\(%(?:r|e)di\) +** vzeroupper +** ret +**... +*/ + +#include "builtin-memmove-1a.c" diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-1c.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-1c.c new file mode 100644 index 0000000..9eb9a39 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-1c.c @@ -0,0 +1,94 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -mmove-max=512 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**memmove7: +**.LFB[0-9]+: +** .cfi_startproc +** movl \(%(?:r|e)si\), %edx +** movl 3\(%(?:r|e)si\), %eax +** movl %edx, \(%(?:r|e)di\) +** movl %eax, 3\(%(?:r|e)di\) +** ret +**... +*/ + +/* +**memmove13: +**.LFB[0-9]+: +** .cfi_startproc +** movq \(%(?:r|e)si\), %rdx +** movq 5\(%(?:r|e)si\), %rax +** movq %rdx, \(%(?:r|e)di\) +** movq %rax, 5\(%(?:r|e)di\) +** ret +**... +*/ + +/* +**memmove31: +**.LFB[0-9]+: +** .cfi_startproc +** vmovdqu \(%(?:r|e)si\), %xmm1 +** vmovdqu 15\(%(?:r|e)si\), %xmm0 +** vmovdqu %xmm1, \(%(?:r|e)di\) +** vmovdqu %xmm0, 15\(%(?:r|e)di\) +** ret +**... +*/ + +/* +**memmove39: +**.LFB[0-9]+: +** .cfi_startproc +** vmovdqu \(%(?:r|e)si\), %ymm0 +** movq 31\(%(?:r|e)si\), %rax +** vmovdqu %ymm0, \(%(?:r|e)di\) +** movq %rax, 31\(%(?:r|e)di\) +** vzeroupper +** ret +**... +*/ + +/* +**memmove61: +**.LFB[0-9]+: +** .cfi_startproc +** vmovdqu \(%(?:r|e)si\), %ymm1 +** vmovdqu 29\(%(?:r|e)si\), %ymm0 +** vmovdqu %ymm1, \(%(?:r|e)di\) +** vmovdqu %ymm0, 29\(%(?:r|e)di\) +** vzeroupper +** ret +**... +*/ + +/* +**memmove69: +**.LFB[0-9]+: +** .cfi_startproc +** vmovdqu64 \(%(?:r|e)si\), %zmm0 +** movq 61\(%(?:r|e)si\), %rax +** vmovdqu64 %zmm0, \(%(?:r|e)di\) +** movq %rax, 61\(%(?:r|e)di\) +** vzeroupper +** ret +**... +*/ + +/* +**memmove93: +**.LFB[0-9]+: +** .cfi_startproc +** vmovdqu64 \(%(?:r|e)si\), %zmm1 +** vmovdqu 61\(%(?:r|e)si\), %ymm0 +** vmovdqu64 %zmm1, \(%(?:r|e)di\) +** vmovdqu %ymm0, 61\(%(?:r|e)di\) +** vzeroupper +** ret +**... +*/ + +#include "builtin-memmove-1a.c" diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-1d.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-1d.c new file mode 100644 index 0000000..ffa7575 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-1d.c @@ -0,0 +1,226 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mgeneral-regs-only -march=x86-64 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**memmove7: +**.LFB[0-9]+: +** .cfi_startproc +** movl \(%rsi\), %edx +** movl 3\(%rsi\), %eax +** movl %edx, \(%rdi\) +** movl %eax, 3\(%rdi\) +** ret +**... +*/ + +/* +**memmove13: +**.LFB[0-9]+: +** .cfi_startproc +** movq \(%rsi\), %rdx +** movq 5\(%rsi\), %rax +** movq %rdx, \(%rdi\) +** movq %rax, 5\(%rdi\) +** ret +**... +*/ + +/* +**memmove31: +**.LFB[0-9]+: +** .cfi_startproc +** movq \(%(e|r)si\), %r8 +** movq 8\(%(e|r)si\), %rcx +** movq 16\(%(e|r)si\), %rdx +** movq 23\(%(e|r)si\), %rax +** movq %r8, \(%(e|r)di\) +** movq %rdx, 16\(%(e|r)di\) +** movq %rcx, 8\(%(e|r)di\) +** movq %rax, 23\(%(e|r)di\) +** ret +**... +*/ + +/* +**memmove39: +**.LFB[0-9]+: +** .cfi_startproc +** movq \(%rsi\), %r9 +** movq 8\(%rsi\), %r8 +** movq 16\(%rsi\), %rcx +** movq 24\(%rsi\), %rdx +** movq 31\(%rsi\), %rax +** movq %r9, \(%rdi\) +** movq %rdx, 24\(%rdi\) +** movq %r8, 8\(%rdi\) +** movq %rcx, 16\(%rdi\) +** movq %rax, 31\(%rdi\) +** ret +**... +*/ + +/* +**memmove61: +**.LFB[0-9]+: +** .cfi_startproc +** movq 8\(%rsi\), %r11 +** movq 16\(%rsi\), %r10 +** pushq %rbx +** .cfi_def_cfa_offset 16 +** .cfi_offset 3, -16 +** movq 24\(%rsi\), %r9 +** movq \(%rsi\), %rbx +** movq 32\(%rsi\), %r8 +** movq 40\(%rsi\), %rcx +** movq 48\(%rsi\), %rdx +** movq 53\(%rsi\), %rax +** movq %rbx, \(%rdi\) +** movq %r11, 8\(%rdi\) +** popq %rbx +** .cfi_def_cfa_offset 8 +** movq %rdx, 48\(%rdi\) +** movq %r10, 16\(%rdi\) +** movq %r9, 24\(%rdi\) +** movq %r8, 32\(%rdi\) +** movq %rcx, 40\(%rdi\) +** movq %rax, 53\(%rdi\) +** ret +**... +*/ + +/* +**memmove69: +**.LFB5: +** .cfi_startproc +** movq 16\(%rsi\), %r11 +** movq 24\(%rsi\), %r10 +** pushq %rbp +** .cfi_def_cfa_offset 16 +** .cfi_offset 6, -16 +** movq 32\(%rsi\), %r9 +** movq \(%rsi\), %rbp +** pushq %rbx +** .cfi_def_cfa_offset 24 +** .cfi_offset 3, -24 +** movq 40\(%rsi\), %r8 +** movq 8\(%rsi\), %rbx +** movq 48\(%rsi\), %rcx +** movq 56\(%rsi\), %rdx +** movq 61\(%rsi\), %rax +** movq %rbp, \(%rdi\) +** movq %rbx, 8\(%rdi\) +** popq %rbx +** .cfi_def_cfa_offset 16 +** movq %rdx, 56\(%rdi\) +** popq %rbp +** .cfi_def_cfa_offset 8 +** movq %r11, 16\(%rdi\) +** movq %r10, 24\(%rdi\) +** movq %r9, 32\(%rdi\) +** movq %r8, 40\(%rdi\) +** movq %rcx, 48\(%rdi\) +** movq %rax, 61\(%rdi\) +** ret +**... +*/ + +/* +**memmove93: +**.LFB[0-9]+: +** .cfi_startproc +** sub(l|q) \$24, %(e|r)sp +** .cfi_def_cfa_offset 32 +** mov(l|q) %(e|r)si, %(e|r)ax +** movl \$93, %ecx +** cmp(l|q) %(e|r)di, %(e|r)si +** jb .L14 +** je .L10 +** movq %rbx, \(%(e|r)sp\) +** mov(l|q) %(e|r)di, %(e|r)dx +** movq %r14, 8\(%(e|r)sp\) +** movq %r15, 16\(%(e|r)sp\) +** .cfi_offset 3, -32 +** .cfi_offset 14, -24 +** .cfi_offset 15, -16 +** movq 85\(%(e|r)si\), %r14 +** movq 77\(%(e|r)si\), %r15 +** movq 69\(%(e|r)si\), %r10 +** movq 61\(%(e|r)si\), %r11 +**.L15: +** movq 8\(%(e|r)ax\), %r9 +** movq 16\(%(e|r)ax\), %r8 +** subl \$32, %ecx +** add(l|q) \$32, %(e|r)dx +** movq 24\(%(e|r)ax\), %rsi +** movq \(%(e|r)ax\), %rbx +** add(l|q) \$32, %(e|r)ax +** movq %r9, -24\(%(e|r)dx\) +** movq %rbx, -32\(%(e|r)dx\) +** movq %r8, -16\(%(e|r)dx\) +** movq %rsi, -8\(%(e|r)dx\) +** cmpl \$32, %ecx +** ja .L15 +** movq %r10, 69\(%(e|r)di\) +** movq \(%(e|r)sp\), %rbx +** .cfi_restore 3 +** movq %r11, 61\(%(e|r)di\) +** movq %r14, 85\(%(e|r)di\) +** movq 8\(%(e|r)sp\), %r14 +** .cfi_restore 14 +** movq %r15, 77\(%(e|r)di\) +** movq 16\(%(e|r)sp\), %r15 +** .cfi_restore 15 +**.L10: +** add(l|q) \$24, %(e|r)sp +** .cfi_remember_state +** .cfi_def_cfa_offset 8 +** ret +** .p2align 4,,10 +** .p2align 3 +**.L14: +** .cfi_restore_state +** movq %rbx, \(%(e|r)sp\) +** lea(l|q) 93\(%(e|r)di\), %(e|r)dx +** add(l|q) \$93, %(e|r)ax +** movq %r14, 8\(%(e|r)sp\) +** movq %r15, 16\(%(e|r)sp\) +** .cfi_offset 3, -32 +** .cfi_offset 14, -24 +** .cfi_offset 15, -16 +** movq \(%(e|r)si\), %r14 +** movq 8\(%(e|r)si\), %r15 +** movq 16\(%(e|r)si\), %r10 +** movq 24\(%(e|r)si\), %r11 +**.L16: +** movq -16\(%(e|r)ax\), %r9 +** movq -24\(%(e|r)ax\), %r8 +** subl \$32, %ecx +** sub(l|q) \$32, %(e|r)dx +** movq -32\(%(e|r)ax\), %rsi +** movq -8\(%(e|r)ax\), %rbx +** sub(l|q) \$32, %(e|r)ax +** movq %r9, 16\(%(e|r)dx\) +** movq %rbx, 24\(%(e|r)dx\) +** movq %r8, 8\(%(e|r)dx\) +** movq %rsi, \(%(e|r)dx\) +** cmpl \$32, %ecx +** ja .L16 +** movq %r14, \(%(e|r)di\) +** movq \(%(e|r)sp\), %rbx +** .cfi_restore 3 +** movq %r15, 8\(%(e|r)di\) +** movq 8\(%(e|r)sp\), %r14 +** .cfi_restore 14 +** movq %r10, 16\(%(e|r)di\) +** movq 16\(%(e|r)sp\), %r15 +** .cfi_restore 15 +** movq %r11, 24\(%(e|r)di\) +** add(l|q) \$24, %(e|r)sp +** .cfi_def_cfa_offset 8 +** ret +**... +*/ + +#include "builtin-memmove-1a.c" diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-2a.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-2a.c new file mode 100644 index 0000000..0a7e704 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-2a.c @@ -0,0 +1,165 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_xmm: +**.LFB0: +** .cfi_startproc +** movq %rdi, %rax +** movq %rsi, %rcx +** cmpq \$16, %rdx +** jb .L3 +** cmpq \$32, %rdx +** jbe .L17 +** cmpq \$128, %rdx +** jbe .L18 +** movq %rdx, %rsi +** cmpq %rdi, %rcx +** jb .L11 +** je .L2 +** movdqu -16\(%rcx,%rdx\), %xmm7 +** movdqu -32\(%rcx,%rdx\), %xmm6 +** movdqu -48\(%rcx,%rdx\), %xmm5 +** movdqu -64\(%rcx,%rdx\), %xmm4 +**.L12: +** movdqu \(%rcx\), %xmm3 +** subq \$64, %rsi +** addq \$64, %rdi +** addq \$64, %rcx +** movdqu -48\(%rcx\), %xmm2 +** movdqu -32\(%rcx\), %xmm1 +** movdqu -16\(%rcx\), %xmm0 +** movups %xmm3, -64\(%rdi\) +** movups %xmm2, -48\(%rdi\) +** movups %xmm1, -32\(%rdi\) +** movups %xmm0, -16\(%rdi\) +** cmpq \$64, %rsi +** ja .L12 +** movups %xmm7, -16\(%rax,%rdx\) +** movups %xmm6, -32\(%rax,%rdx\) +** movups %xmm5, -48\(%rax,%rdx\) +** movups %xmm4, -64\(%rax,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L3: +** cmpq \$8, %rdx +** jb .L19 +** movq \(%rsi\), %rdi +** movq -8\(%rsi,%rdx\), %rcx +** movq %rdi, \(%rax\) +** movq %rcx, -8\(%rax,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L19: +** cmpq \$4, %rdx +** jnb .L6 +** cmpq \$1, %rdx +** ja .L7 +** jb .L2 +** movzbl \(%rsi\), %edx +** movb %dl, \(%rdi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L17: +** movdqu \(%rsi\), %xmm1 +** movdqu -16\(%rsi,%rdx\), %xmm0 +** movups %xmm1, \(%rdi\) +** movups %xmm0, -16\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L18: +** cmpq \$64, %rdx +** jb .L10 +** movdqu \(%rsi\), %xmm7 +** movdqu 16\(%rsi\), %xmm6 +** movdqu 32\(%rsi\), %xmm5 +** movdqu 48\(%rsi\), %xmm4 +** movdqu -16\(%rsi,%rdx\), %xmm3 +** movdqu -32\(%rsi,%rdx\), %xmm2 +** movdqu -48\(%rsi,%rdx\), %xmm1 +** movdqu -64\(%rsi,%rdx\), %xmm0 +** movups %xmm7, \(%rdi\) +** movups %xmm6, 16\(%rdi\) +** movups %xmm5, 32\(%rdi\) +** movups %xmm4, 48\(%rdi\) +** movups %xmm3, -16\(%rdi,%rdx\) +** movups %xmm2, -32\(%rdi,%rdx\) +** movups %xmm1, -48\(%rdi,%rdx\) +** movups %xmm0, -64\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L6: +** movl \(%rsi\), %edi +** movl -4\(%rsi,%rdx\), %ecx +** movl %edi, \(%rax\) +** movl %ecx, -4\(%rax,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L11: +** movdqu \(%rcx\), %xmm7 +** movdqu 16\(%rcx\), %xmm6 +** leaq \(%rdi,%rdx\), %rdi +** movdqu 32\(%rcx\), %xmm5 +** movdqu 48\(%rcx\), %xmm4 +** addq %rdx, %rcx +**.L13: +** movdqu -16\(%rcx\), %xmm3 +** movdqu -32\(%rcx\), %xmm2 +** subq \$64, %rsi +** subq \$64, %rdi +** movdqu -48\(%rcx\), %xmm1 +** movdqu -64\(%rcx\), %xmm0 +** subq \$64, %rcx +** movups %xmm3, 48\(%rdi\) +** movups %xmm2, 32\(%rdi\) +** movups %xmm1, 16\(%rdi\) +** movups %xmm0, \(%rdi\) +** cmpq \$64, %rsi +** ja .L13 +** movups %xmm7, \(%rax\) +** movups %xmm6, 16\(%rax\) +** movups %xmm5, 32\(%rax\) +** movups %xmm4, 48\(%rax\) +**.L2: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L10: +** movdqu \(%rsi\), %xmm3 +** movdqu 16\(%rsi\), %xmm2 +** movdqu -16\(%rsi,%rdx\), %xmm1 +** movdqu -32\(%rsi,%rdx\), %xmm0 +** movups %xmm3, \(%rdi\) +** movups %xmm2, 16\(%rdi\) +** movups %xmm1, -16\(%rdi,%rdx\) +** movups %xmm0, -32\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L7: +** movzwl \(%rsi\), %edi +** movzwl -2\(%rsi,%rdx\), %ecx +** movw %di, \(%rax\) +** movw %cx, -2\(%rax,%rdx\) +** ret +** .cfi_endproc +**... +*/ + +#ifndef gcc_memmove +#define gcc_memmove gcc_memmove_xmm +#endif + +void * +gcc_memmove (void *a, void *b, __SIZE_TYPE__ n) +{ + return __builtin_memmove (a, b, n); +} diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-2b.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-2b.c new file mode 100644 index 0000000..0596ca7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-2b.c @@ -0,0 +1,173 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx512f -march=x86-64-v3 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_ymm: +**.LFB0: +** .cfi_startproc +** movq %rdi, %rax +** movq %rsi, %rcx +** cmpq \$32, %rdx +** jb .L3 +** cmpq \$64, %rdx +** jbe .L18 +** cmpq \$256, %rdx +** jbe .L19 +** movq %rdx, %rsi +** cmpq %rdi, %rcx +** jb .L12 +** je .L2 +** vmovdqu -32\(%rcx,%rdx\), %ymm7 +** vmovdqu -64\(%rcx,%rdx\), %ymm6 +** vmovdqu -96\(%rcx,%rdx\), %ymm5 +** vmovdqu -128\(%rcx,%rdx\), %ymm4 +**.L13: +** vmovdqu \(%rcx\), %ymm3 +** addq \$-128, %rsi +** subq \$-128, %rdi +** subq \$-128, %rcx +** vmovdqu -96\(%rcx\), %ymm2 +** vmovdqu -64\(%rcx\), %ymm1 +** vmovdqu -32\(%rcx\), %ymm0 +** vmovdqu %ymm3, -128\(%rdi\) +** vmovdqu %ymm2, -96\(%rdi\) +** vmovdqu %ymm1, -64\(%rdi\) +** vmovdqu %ymm0, -32\(%rdi\) +** cmpq \$128, %rsi +** ja .L13 +** vmovdqu %ymm7, -32\(%rax,%rdx\) +** vmovdqu %ymm6, -64\(%rax,%rdx\) +** vmovdqu %ymm5, -96\(%rax,%rdx\) +** vmovdqu %ymm4, -128\(%rax,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L3: +** cmpq \$16, %rdx +** jb .L20 +** vmovdqu \(%rsi\), %xmm1 +** vmovdqu -16\(%rsi,%rdx\), %xmm0 +** vmovdqu %xmm1, \(%rdi\) +** vmovdqu %xmm0, -16\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L20: +** cmpq \$8, %rdx +** jnb .L6 +** cmpq \$4, %rdx +** jnb .L7 +** cmpq \$1, %rdx +** ja .L8 +** jb .L2 +** movzbl \(%rsi\), %edx +** movb %dl, \(%rdi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L18: +** vmovdqu \(%rsi\), %ymm1 +** vmovdqu -32\(%rsi,%rdx\), %ymm0 +** vmovdqu %ymm1, \(%rdi\) +** vmovdqu %ymm0, -32\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L19: +** cmpq \$128, %rdx +** jb .L11 +** vmovdqu \(%rsi\), %ymm7 +** vmovdqu 32\(%rsi\), %ymm6 +** vmovdqu 64\(%rsi\), %ymm5 +** vmovdqu 96\(%rsi\), %ymm4 +** vmovdqu -32\(%rsi,%rdx\), %ymm3 +** vmovdqu -64\(%rsi,%rdx\), %ymm2 +** vmovdqu -96\(%rsi,%rdx\), %ymm1 +** vmovdqu -128\(%rsi,%rdx\), %ymm0 +** vmovdqu %ymm7, \(%rdi\) +** vmovdqu %ymm6, 32\(%rdi\) +** vmovdqu %ymm5, 64\(%rdi\) +** vmovdqu %ymm4, 96\(%rdi\) +** vmovdqu %ymm3, -32\(%rdi,%rdx\) +** vmovdqu %ymm2, -64\(%rdi,%rdx\) +** vmovdqu %ymm1, -96\(%rdi,%rdx\) +** vmovdqu %ymm0, -128\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L6: +** movq \(%rsi\), %rdi +** movq -8\(%rsi,%rdx\), %rcx +** movq %rdi, \(%rax\) +** movq %rcx, -8\(%rax,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L12: +** vmovdqu \(%rcx\), %ymm7 +** vmovdqu 32\(%rcx\), %ymm6 +** leaq \(%rdi,%rdx\), %rdi +** vmovdqu 64\(%rcx\), %ymm5 +** vmovdqu 96\(%rcx\), %ymm4 +** addq %rdx, %rcx +**.L14: +** vmovdqu -32\(%rcx\), %ymm3 +** vmovdqu -64\(%rcx\), %ymm2 +** addq \$-128, %rsi +** addq \$-128, %rdi +** vmovdqu -96\(%rcx\), %ymm1 +** vmovdqu -128\(%rcx\), %ymm0 +** addq \$-128, %rcx +** vmovdqu %ymm3, 96\(%rdi\) +** vmovdqu %ymm2, 64\(%rdi\) +** vmovdqu %ymm1, 32\(%rdi\) +** vmovdqu %ymm0, \(%rdi\) +** cmpq \$128, %rsi +** ja .L14 +** vmovdqu %ymm7, \(%rax\) +** vmovdqu %ymm6, 32\(%rax\) +** vmovdqu %ymm5, 64\(%rax\) +** vmovdqu %ymm4, 96\(%rax\) +** vzeroupper +**.L2: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L11: +** vmovdqu \(%rsi\), %ymm3 +** vmovdqu 32\(%rsi\), %ymm2 +** vmovdqu -32\(%rsi,%rdx\), %ymm1 +** vmovdqu -64\(%rsi,%rdx\), %ymm0 +** vmovdqu %ymm3, \(%rdi\) +** vmovdqu %ymm2, 32\(%rdi\) +** vmovdqu %ymm1, -32\(%rdi,%rdx\) +** vmovdqu %ymm0, -64\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L7: +** movl \(%rsi\), %edi +** movl -4\(%rsi,%rdx\), %ecx +** movl %edi, \(%rax\) +** movl %ecx, -4\(%rax,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L8: +** movzwl \(%rsi\), %edi +** movzwl -2\(%rsi,%rdx\), %ecx +** movw %di, \(%rax\) +** movw %cx, -2\(%rax,%rdx\) +** ret +** .cfi_endproc +**... +*/ + +#define gcc_memmove gcc_memmove_ymm +#include "builtin-memmove-2a.c" diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-2c.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-2c.c new file mode 100644 index 0000000..cb3cb9e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-2c.c @@ -0,0 +1,184 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -mmove-max=512 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_zmm: +**.LFB0: +** .cfi_startproc +** movq %rdi, %rax +** movq %rsi, %rcx +** cmpq \$64, %rdx +** jb .L3 +** cmpq \$128, %rdx +** jbe .L19 +** cmpq \$512, %rdx +** jbe .L20 +** movq %rdx, %rsi +** cmpq %rdi, %rcx +** jb .L13 +** je .L2 +** vmovdqu64 -64\(%rcx,%rdx\), %zmm7 +** vmovdqu64 -128\(%rcx,%rdx\), %zmm6 +** vmovdqu64 -192\(%rcx,%rdx\), %zmm5 +** vmovdqu64 -256\(%rcx,%rdx\), %zmm4 +**.L14: +** vmovdqu64 \(%rcx\), %zmm3 +** vmovdqu64 64\(%rcx\), %zmm2 +** subq \$256, %rsi +** addq \$256, %rdi +** vmovdqu64 128\(%rcx\), %zmm1 +** addq \$256, %rcx +** vmovdqu64 -64\(%rcx\), %zmm0 +** vmovdqu64 %zmm3, -256\(%rdi\) +** vmovdqu64 %zmm2, -192\(%rdi\) +** vmovdqu64 %zmm1, -128\(%rdi\) +** vmovdqu64 %zmm0, -64\(%rdi\) +** cmpq \$256, %rsi +** ja .L14 +** vmovdqu64 %zmm7, -64\(%rax,%rdx\) +** vmovdqu64 %zmm6, -128\(%rax,%rdx\) +** vmovdqu64 %zmm5, -192\(%rax,%rdx\) +** vmovdqu64 %zmm4, -256\(%rax,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L3: +** cmpq \$32, %rdx +** jb .L21 +** vmovdqu \(%rsi\), %ymm1 +** vmovdqu -32\(%rsi,%rdx\), %ymm0 +** vmovdqu %ymm1, \(%rdi\) +** vmovdqu %ymm0, -32\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L21: +** cmpq \$16, %rdx +** jnb .L6 +** cmpq \$8, %rdx +** jnb .L7 +** cmpq \$4, %rdx +** jnb .L8 +** cmpq \$1, %rdx +** ja .L9 +** jb .L2 +** movzbl \(%rsi\), %edx +** movb %dl, \(%rdi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L19: +** vmovdqu64 \(%rsi\), %zmm1 +** vmovdqu64 -64\(%rsi,%rdx\), %zmm0 +** vmovdqu64 %zmm1, \(%rdi\) +** vmovdqu64 %zmm0, -64\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L20: +** cmpq \$256, %rdx +** jb .L12 +** vmovdqu64 \(%rsi\), %zmm7 +** vmovdqu64 64\(%rsi\), %zmm6 +** vmovdqu64 -64\(%rsi,%rdx\), %zmm3 +** vmovdqu64 -128\(%rsi,%rdx\), %zmm2 +** vmovdqu64 128\(%rsi\), %zmm5 +** vmovdqu64 192\(%rsi\), %zmm4 +** vmovdqu64 -192\(%rsi,%rdx\), %zmm1 +** vmovdqu64 -256\(%rsi,%rdx\), %zmm0 +** vmovdqu64 %zmm7, \(%rdi\) +** vmovdqu64 %zmm6, 64\(%rdi\) +** vmovdqu64 %zmm5, 128\(%rdi\) +** vmovdqu64 %zmm4, 192\(%rdi\) +** vmovdqu64 %zmm3, -64\(%rdi,%rdx\) +** vmovdqu64 %zmm2, -128\(%rdi,%rdx\) +** vmovdqu64 %zmm1, -192\(%rdi,%rdx\) +** vmovdqu64 %zmm0, -256\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L6: +** vmovdqu \(%rsi\), %xmm1 +** vmovdqu -16\(%rsi,%rdx\), %xmm0 +** vmovdqu %xmm1, \(%rdi\) +** vmovdqu %xmm0, -16\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L13: +** vmovdqu64 \(%rcx\), %zmm7 +** leaq \(%rdi,%rdx\), %rdi +** vmovdqu64 64\(%rcx\), %zmm6 +** vmovdqu64 128\(%rcx\), %zmm5 +** vmovdqu64 192\(%rcx\), %zmm4 +** addq %rdx, %rcx +**.L15: +** vmovdqu64 -64\(%rcx\), %zmm3 +** vmovdqu64 -128\(%rcx\), %zmm2 +** subq \$256, %rsi +** subq \$256, %rdi +** vmovdqu64 -192\(%rcx\), %zmm1 +** subq \$256, %rcx +** vmovdqu64 \(%rcx\), %zmm0 +** vmovdqu64 %zmm3, 192\(%rdi\) +** vmovdqu64 %zmm2, 128\(%rdi\) +** vmovdqu64 %zmm1, 64\(%rdi\) +** vmovdqu64 %zmm0, \(%rdi\) +** cmpq \$256, %rsi +** ja .L15 +** vmovdqu64 %zmm7, \(%rax\) +** vmovdqu64 %zmm6, 64\(%rax\) +** vmovdqu64 %zmm5, 128\(%rax\) +** vmovdqu64 %zmm4, 192\(%rax\) +** vzeroupper +**.L2: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L12: +** vmovdqu64 \(%rsi\), %zmm3 +** vmovdqu64 64\(%rsi\), %zmm2 +** vmovdqu64 -64\(%rsi,%rdx\), %zmm1 +** vmovdqu64 -128\(%rsi,%rdx\), %zmm0 +** vmovdqu64 %zmm3, \(%rdi\) +** vmovdqu64 %zmm2, 64\(%rdi\) +** vmovdqu64 %zmm1, -64\(%rdi,%rdx\) +** vmovdqu64 %zmm0, -128\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L7: +** movq \(%rsi\), %rdi +** movq -8\(%rsi,%rdx\), %rcx +** movq %rdi, \(%rax\) +** movq %rcx, -8\(%rax,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L8: +** movl \(%rsi\), %edi +** movl -4\(%rsi,%rdx\), %ecx +** movl %edi, \(%rax\) +** movl %ecx, -4\(%rax,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L9: +** movzwl \(%rsi\), %edi +** movzwl -2\(%rsi,%rdx\), %ecx +** movw %di, \(%rax\) +** movw %cx, -2\(%rax,%rdx\) +** ret +** .cfi_endproc +**... +*/ + +#define gcc_memmove gcc_memmove_zmm +#include "builtin-memmove-2a.c" diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-2d.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-2d.c new file mode 100644 index 0000000..c27edfe --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-2d.c @@ -0,0 +1,195 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mgeneral-regs-only -march=x86-64 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_gpr: +**.LFB0: +** .cfi_startproc +** movq %rdi, %rax +** cmpq \$8, %rdx +** jb .L3 +** cmpq \$16, %rdx +** jbe .L19 +** subq \$32, %rsp +** .cfi_def_cfa_offset 40 +** cmpq \$64, %rdx +** jbe .L20 +** movq %rsi, %rcx +** movq %rdx, %rsi +** cmpq %rdi, %rcx +** jb .L10 +** je .L2 +** movq %rbx, \(%rsp\) +** movq %rbp, 8\(%rsp\) +** movq %r14, 16\(%rsp\) +** movq %r15, 24\(%rsp\) +** .cfi_offset 3, -40 +** .cfi_offset 6, -32 +** .cfi_offset 14, -24 +** .cfi_offset 15, -16 +** movq -8\(%rcx,%rdx\), %r15 +** movq -16\(%rcx,%rdx\), %r14 +** movq -24\(%rcx,%rdx\), %rbp +** movq -32\(%rcx,%rdx\), %r11 +**.L11: +** movq 8\(%rcx\), %r10 +** movq 16\(%rcx\), %r9 +** subq \$32, %rsi +** addq \$32, %rdi +** movq 24\(%rcx\), %r8 +** movq \(%rcx\), %rbx +** addq \$32, %rcx +** movq %r10, -24\(%rdi\) +** movq %rbx, -32\(%rdi\) +** movq %r9, -16\(%rdi\) +** movq %r8, -8\(%rdi\) +** cmpq \$32, %rsi +** ja .L11 +** movq %r15, -8\(%rax,%rdx\) +** movq %r14, -16\(%rax,%rdx\) +** movq %rbp, -24\(%rax,%rdx\) +** movq %r11, -32\(%rax,%rdx\) +** movq \(%rsp\), %rbx +** .cfi_restore 3 +** movq 8\(%rsp\), %rbp +** .cfi_restore 6 +** movq 16\(%rsp\), %r14 +** .cfi_restore 14 +** movq 24\(%rsp\), %r15 +** .cfi_restore 15 +** jmp .L2 +** .p2align 4,,10 +** .p2align 3 +**.L3: +** .cfi_def_cfa_offset 8 +** cmpq \$4, %rdx +** jb .L21 +** movl \(%rsi\), %edi +** movl -4\(%rsi,%rdx\), %ecx +** movl %edi, \(%rax\) +** movl %ecx, -4\(%rax,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L21: +** cmpq \$1, %rdx +** ja .L6 +** jb .L16 +** movzbl \(%rsi\), %edx +** movb %dl, \(%rdi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L19: +** movq \(%rsi\), %rdi +** movq -8\(%rsi,%rdx\), %rcx +** movq %rdi, \(%rax\) +** movq %rcx, -8\(%rax,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L20: +** .cfi_def_cfa_offset 40 +** cmpq \$32, %rdx +** jb .L9 +** movq %rbx, \(%rsp\) +** movq %r14, 16\(%rsp\) +** .cfi_offset 3, -40 +** .cfi_offset 14, -24 +** movq \(%rsi\), %rbx +** movq 8\(%rsi\), %r14 +** movq 16\(%rsi\), %r11 +** movq 24\(%rsi\), %r10 +** movq -8\(%rsi,%rdx\), %r9 +** movq -16\(%rsi,%rdx\), %r8 +** movq -24\(%rsi,%rdx\), %rdi +** movq -32\(%rsi,%rdx\), %rcx +** movq %rbx, \(%rax\) +** movq %r14, 8\(%rax\) +** movq %r11, 16\(%rax\) +** movq %r10, 24\(%rax\) +** movq %r9, -8\(%rax,%rdx\) +** movq %r8, -16\(%rax,%rdx\) +** movq %rdi, -24\(%rax,%rdx\) +** movq %rcx, -32\(%rax,%rdx\) +** movq \(%rsp\), %rbx +** .cfi_restore 3 +** movq 16\(%rsp\), %r14 +** .cfi_restore 14 +**.L2: +** addq \$32, %rsp +** .cfi_def_cfa_offset 8 +** ret +** .p2align 4,,10 +** .p2align 3 +**.L6: +** movzwl \(%rsi\), %edi +** movzwl -2\(%rsi,%rdx\), %ecx +** movw %di, \(%rax\) +** movw %cx, -2\(%rax,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L16: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L9: +** .cfi_def_cfa_offset 40 +** movq \(%rsi\), %r9 +** movq 8\(%rsi\), %r8 +** movq -8\(%rsi,%rdx\), %rdi +** movq -16\(%rsi,%rdx\), %rcx +** movq %r9, \(%rax\) +** movq %r8, 8\(%rax\) +** movq %rdi, -8\(%rax,%rdx\) +** movq %rcx, -16\(%rax,%rdx\) +** jmp .L2 +** .p2align 4,,10 +** .p2align 3 +**.L10: +** movq %rbx, \(%rsp\) +** leaq \(%rdi,%rdx\), %rdi +** movq %r14, 16\(%rsp\) +** movq %r15, 24\(%rsp\) +** .cfi_offset 3, -40 +** .cfi_offset 14, -24 +** .cfi_offset 15, -16 +** movq \(%rcx\), %r14 +** movq 8\(%rcx\), %r15 +** movq 16\(%rcx\), %r10 +** movq 24\(%rcx\), %r11 +** addq %rdx, %rcx +**.L12: +** movq -16\(%rcx\), %r9 +** movq -24\(%rcx\), %r8 +** subq \$32, %rsi +** subq \$32, %rdi +** movq -32\(%rcx\), %rdx +** movq -8\(%rcx\), %rbx +** subq \$32, %rcx +** movq %r9, 16\(%rdi\) +** movq %rbx, 24\(%rdi\) +** movq %r8, 8\(%rdi\) +** movq %rdx, \(%rdi\) +** cmpq \$32, %rsi +** ja .L12 +** movq %r14, \(%rax\) +** movq \(%rsp\), %rbx +** .cfi_restore 3 +** movq %r15, 8\(%rax\) +** movq 16\(%rsp\), %r14 +** .cfi_restore 14 +** movq %r10, 16\(%rax\) +** movq 24\(%rsp\), %r15 +** .cfi_restore 15 +** movq %r11, 24\(%rax\) +** jmp .L2 +** .cfi_endproc +**... +*/ + +#define gcc_memmove gcc_memmove_gpr +#include "builtin-memmove-2a.c" diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-3a.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-3a.c new file mode 100644 index 0000000..83cb8e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-3a.c @@ -0,0 +1,133 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_xmm: +**.LFB0: +** .cfi_startproc +** cmpq \$16, %rdx +** ja .L13 +**.L1: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L13: +** movq %rdi, %rcx +** movq %rsi, %rax +** cmpq \$32, %rdx +** jbe .L14 +** cmpq \$128, %rdx +** ja .L5 +** cmpq \$64, %rdx +** jnb .L15 +** movdqu \(%rsi\), %xmm3 +** movdqu 16\(%rsi\), %xmm2 +** movdqu -16\(%rsi,%rdx\), %xmm1 +** movdqu -32\(%rsi,%rdx\), %xmm0 +** movups %xmm3, \(%rdi\) +** movups %xmm2, 16\(%rdi\) +** movups %xmm1, -16\(%rdi,%rdx\) +** movups %xmm0, -32\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L14: +** movdqu \(%rsi\), %xmm1 +** movdqu -16\(%rsi,%rdx\), %xmm0 +** movups %xmm1, \(%rdi\) +** movups %xmm0, -16\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L5: +** movq %rdx, %rsi +** cmpq %rdi, %rax +** jb .L7 +** je .L1 +** movdqu -16\(%rax,%rdx\), %xmm7 +** movdqu -32\(%rax,%rdx\), %xmm6 +** movdqu -48\(%rax,%rdx\), %xmm5 +** movdqu -64\(%rax,%rdx\), %xmm4 +**.L8: +** movdqu \(%rax\), %xmm3 +** subq \$64, %rsi +** addq \$64, %rcx +** addq \$64, %rax +** movdqu -48\(%rax\), %xmm2 +** movdqu -32\(%rax\), %xmm1 +** movdqu -16\(%rax\), %xmm0 +** movups %xmm3, -64\(%rcx\) +** movups %xmm2, -48\(%rcx\) +** movups %xmm1, -32\(%rcx\) +** movups %xmm0, -16\(%rcx\) +** cmpq \$64, %rsi +** ja .L8 +** movups %xmm7, -16\(%rdi,%rdx\) +** movups %xmm6, -32\(%rdi,%rdx\) +** movups %xmm5, -48\(%rdi,%rdx\) +** movups %xmm4, -64\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L7: +** movdqu \(%rax\), %xmm3 +** movdqu 16\(%rax\), %xmm2 +** leaq \(%rdi,%rdx\), %rcx +** movdqu 32\(%rax\), %xmm1 +** movdqu 48\(%rax\), %xmm0 +** addq %rdx, %rax +**.L9: +** movdqu -16\(%rax\), %xmm7 +** movdqu -32\(%rax\), %xmm6 +** subq \$64, %rsi +** subq \$64, %rcx +** movdqu -48\(%rax\), %xmm5 +** movdqu -64\(%rax\), %xmm4 +** subq \$64, %rax +** movups %xmm7, 48\(%rcx\) +** movups %xmm6, 32\(%rcx\) +** movups %xmm5, 16\(%rcx\) +** movups %xmm4, \(%rcx\) +** cmpq \$64, %rsi +** ja .L9 +** movups %xmm3, \(%rdi\) +** movups %xmm2, 16\(%rdi\) +** movups %xmm1, 32\(%rdi\) +** movups %xmm0, 48\(%rdi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L15: +** movdqu \(%rsi\), %xmm7 +** movdqu 16\(%rsi\), %xmm6 +** movdqu 32\(%rsi\), %xmm5 +** movdqu 48\(%rsi\), %xmm4 +** movdqu -16\(%rsi,%rdx\), %xmm3 +** movdqu -32\(%rsi,%rdx\), %xmm2 +** movdqu -48\(%rsi,%rdx\), %xmm1 +** movdqu -64\(%rsi,%rdx\), %xmm0 +** movups %xmm7, \(%rdi\) +** movups %xmm6, 16\(%rdi\) +** movups %xmm5, 32\(%rdi\) +** movups %xmm4, 48\(%rdi\) +** movups %xmm3, -16\(%rdi,%rdx\) +** movups %xmm2, -32\(%rdi,%rdx\) +** movups %xmm1, -48\(%rdi,%rdx\) +** movups %xmm0, -64\(%rdi,%rdx\) +** ret +** .cfi_endproc +**... +*/ + +#ifndef gcc_memmove +#define gcc_memmove gcc_memmove_xmm +#endif + +void +gcc_memmove (void *a, void *b, __SIZE_TYPE__ n) +{ + if (n > 16) + __builtin_memmove (a, b, n); +} diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-3b.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-3b.c new file mode 100644 index 0000000..43fae5c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-3b.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx512f -march=x86-64-v3 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_ymm: +**.LFB0: +** .cfi_startproc +** cmpq \$16, %rdx +** ja .L16 +**.L14: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L16: +** movq %rdi, %rcx +** movq %rsi, %rax +** cmpq \$32, %rdx +** jb .L6 +** cmpq \$64, %rdx +** ja .L5 +** vmovdqu \(%rsi\), %ymm1 +** vmovdqu -32\(%rsi,%rdx\), %ymm0 +** vmovdqu %ymm1, \(%rdi\) +** vmovdqu %ymm0, -32\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L6: +** vmovdqu \(%rsi\), %xmm1 +** vmovdqu -16\(%rsi,%rdx\), %xmm0 +** vmovdqu %xmm1, \(%rdi\) +** vmovdqu %xmm0, -16\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L5: +** cmpq \$256, %rdx +** jbe .L17 +** movq %rdx, %rsi +** cmpq %rdi, %rax +** jb .L9 +** je .L14 +** vmovdqu -32\(%rax,%rdx\), %ymm7 +** vmovdqu -64\(%rax,%rdx\), %ymm6 +** vmovdqu -96\(%rax,%rdx\), %ymm5 +** vmovdqu -128\(%rax,%rdx\), %ymm4 +**.L10: +** vmovdqu \(%rax\), %ymm3 +** addq \$-128, %rsi +** subq \$-128, %rcx +** subq \$-128, %rax +** vmovdqu -96\(%rax\), %ymm2 +** vmovdqu -64\(%rax\), %ymm1 +** vmovdqu -32\(%rax\), %ymm0 +** vmovdqu %ymm3, -128\(%rcx\) +** vmovdqu %ymm2, -96\(%rcx\) +** vmovdqu %ymm1, -64\(%rcx\) +** vmovdqu %ymm0, -32\(%rcx\) +** cmpq \$128, %rsi +** ja .L10 +** vmovdqu %ymm7, -32\(%rdi,%rdx\) +** vmovdqu %ymm6, -64\(%rdi,%rdx\) +** vmovdqu %ymm5, -96\(%rdi,%rdx\) +** vmovdqu %ymm4, -128\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L17: +** cmpq \$128, %rdx +** jb .L8 +** vmovdqu \(%rsi\), %ymm7 +** vmovdqu 32\(%rsi\), %ymm6 +** vmovdqu 64\(%rsi\), %ymm5 +** vmovdqu 96\(%rsi\), %ymm4 +** vmovdqu -32\(%rsi,%rdx\), %ymm3 +** vmovdqu -64\(%rsi,%rdx\), %ymm2 +** vmovdqu -96\(%rsi,%rdx\), %ymm1 +** vmovdqu -128\(%rsi,%rdx\), %ymm0 +** vmovdqu %ymm7, \(%rdi\) +** vmovdqu %ymm6, 32\(%rdi\) +** vmovdqu %ymm5, 64\(%rdi\) +** vmovdqu %ymm4, 96\(%rdi\) +** vmovdqu %ymm3, -32\(%rdi,%rdx\) +** vmovdqu %ymm2, -64\(%rdi,%rdx\) +** vmovdqu %ymm1, -96\(%rdi,%rdx\) +** vmovdqu %ymm0, -128\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L8: +** vmovdqu \(%rsi\), %ymm3 +** vmovdqu 32\(%rsi\), %ymm2 +** vmovdqu -32\(%rsi,%rdx\), %ymm1 +** vmovdqu -64\(%rsi,%rdx\), %ymm0 +** vmovdqu %ymm3, \(%rdi\) +** vmovdqu %ymm2, 32\(%rdi\) +** vmovdqu %ymm1, -32\(%rdi,%rdx\) +** vmovdqu %ymm0, -64\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L9: +** vmovdqu \(%rax\), %ymm3 +** vmovdqu 32\(%rax\), %ymm2 +** leaq \(%rdi,%rdx\), %rcx +** vmovdqu 64\(%rax\), %ymm1 +** vmovdqu 96\(%rax\), %ymm0 +** addq %rdx, %rax +**.L11: +** vmovdqu -32\(%rax\), %ymm7 +** vmovdqu -64\(%rax\), %ymm6 +** addq \$-128, %rsi +** addq \$-128, %rcx +** vmovdqu -96\(%rax\), %ymm5 +** vmovdqu -128\(%rax\), %ymm4 +** addq \$-128, %rax +** vmovdqu %ymm7, 96\(%rcx\) +** vmovdqu %ymm6, 64\(%rcx\) +** vmovdqu %ymm5, 32\(%rcx\) +** vmovdqu %ymm4, \(%rcx\) +** cmpq \$128, %rsi +** ja .L11 +** vmovdqu %ymm3, \(%rdi\) +** vmovdqu %ymm2, 32\(%rdi\) +** vmovdqu %ymm1, 64\(%rdi\) +** vmovdqu %ymm0, 96\(%rdi\) +** vzeroupper +** ret +** .cfi_endproc +**... +*/ + +#define gcc_memmove gcc_memmove_ymm +#include "builtin-memmove-3a.c" diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-3c.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-3c.c new file mode 100644 index 0000000..11ccb69 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-3c.c @@ -0,0 +1,151 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -mmove-max=512 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_zmm: +**.LFB0: +** .cfi_startproc +** cmpq \$16, %rdx +** ja .L18 +**.L16: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L18: +** movq %rdi, %rcx +** movq %rsi, %rax +** cmpq \$64, %rdx +** jnb .L19 +** cmpq \$32, %rdx +** jb .L15 +** vmovdqu \(%rsi\), %ymm1 +** vmovdqu -32\(%rsi,%rdx\), %ymm0 +** vmovdqu %ymm1, \(%rdi\) +** vmovdqu %ymm0, -32\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L19: +** cmpq \$128, %rdx +** ja .L5 +** vmovdqu64 \(%rsi\), %zmm1 +** vmovdqu64 -64\(%rsi,%rdx\), %zmm0 +** vmovdqu64 %zmm1, \(%rdi\) +** vmovdqu64 %zmm0, -64\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L5: +** cmpq \$512, %rdx +** jbe .L20 +** movq %rdx, %rsi +** cmpq %rdi, %rax +** jb .L10 +** je .L16 +** vmovdqu64 -64\(%rax,%rdx\), %zmm7 +** vmovdqu64 -128\(%rax,%rdx\), %zmm6 +** vmovdqu64 -192\(%rax,%rdx\), %zmm5 +** vmovdqu64 -256\(%rax,%rdx\), %zmm4 +**.L11: +** vmovdqu64 \(%rax\), %zmm3 +** addq \$256, %rax +** vmovdqu64 -192\(%rax\), %zmm2 +** subq \$256, %rsi +** vmovdqu64 -128\(%rax\), %zmm1 +** vmovdqu64 -64\(%rax\), %zmm0 +** addq \$256, %rcx +** vmovdqu64 %zmm3, -256\(%rcx\) +** vmovdqu64 %zmm2, -192\(%rcx\) +** vmovdqu64 %zmm1, -128\(%rcx\) +** vmovdqu64 %zmm0, -64\(%rcx\) +** cmpq \$256, %rsi +** ja .L11 +** vmovdqu64 %zmm7, -64\(%rdi,%rdx\) +** vmovdqu64 %zmm6, -128\(%rdi,%rdx\) +** vmovdqu64 %zmm5, -192\(%rdi,%rdx\) +** vmovdqu64 %zmm4, -256\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L15: +** vmovdqu \(%rsi\), %xmm1 +** vmovdqu -16\(%rsi,%rdx\), %xmm0 +** vmovdqu %xmm1, \(%rdi\) +** vmovdqu %xmm0, -16\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L20: +** cmpq \$256, %rdx +** jb .L9 +** vmovdqu64 \(%rsi\), %zmm7 +** vmovdqu64 64\(%rsi\), %zmm6 +** vmovdqu64 -64\(%rsi,%rdx\), %zmm3 +** vmovdqu64 -128\(%rsi,%rdx\), %zmm2 +** vmovdqu64 128\(%rsi\), %zmm5 +** vmovdqu64 192\(%rsi\), %zmm4 +** vmovdqu64 -192\(%rsi,%rdx\), %zmm1 +** vmovdqu64 -256\(%rsi,%rdx\), %zmm0 +** vmovdqu64 %zmm7, \(%rdi\) +** vmovdqu64 %zmm6, 64\(%rdi\) +** vmovdqu64 %zmm5, 128\(%rdi\) +** vmovdqu64 %zmm4, 192\(%rdi\) +** vmovdqu64 %zmm3, -64\(%rdi,%rdx\) +** vmovdqu64 %zmm2, -128\(%rdi,%rdx\) +** vmovdqu64 %zmm1, -192\(%rdi,%rdx\) +** vmovdqu64 %zmm0, -256\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L9: +** vmovdqu64 \(%rsi\), %zmm3 +** vmovdqu64 64\(%rsi\), %zmm2 +** vmovdqu64 -64\(%rsi,%rdx\), %zmm1 +** vmovdqu64 -128\(%rsi,%rdx\), %zmm0 +** vmovdqu64 %zmm3, \(%rdi\) +** vmovdqu64 %zmm2, 64\(%rdi\) +** vmovdqu64 %zmm1, -64\(%rdi,%rdx\) +** vmovdqu64 %zmm0, -128\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L10: +** vmovdqu64 \(%rax\), %zmm3 +** leaq \(%rdi,%rdx\), %rcx +** vmovdqu64 64\(%rax\), %zmm2 +** vmovdqu64 128\(%rax\), %zmm1 +** vmovdqu64 192\(%rax\), %zmm0 +** addq %rdx, %rax +**.L12: +** vmovdqu64 -64\(%rax\), %zmm7 +** subq \$256, %rax +** vmovdqu64 128\(%rax\), %zmm6 +** subq \$256, %rsi +** vmovdqu64 64\(%rax\), %zmm5 +** vmovdqu64 \(%rax\), %zmm4 +** subq \$256, %rcx +** vmovdqu64 %zmm7, 192\(%rcx\) +** vmovdqu64 %zmm6, 128\(%rcx\) +** vmovdqu64 %zmm5, 64\(%rcx\) +** vmovdqu64 %zmm4, \(%rcx\) +** cmpq \$256, %rsi +** ja .L12 +** vmovdqu64 %zmm3, \(%rdi\) +** vmovdqu64 %zmm2, 64\(%rdi\) +** vmovdqu64 %zmm1, 128\(%rdi\) +** vmovdqu64 %zmm0, 192\(%rdi\) +** vzeroupper +** ret +** .cfi_endproc +**... +*/ + +#define gcc_memmove gcc_memmove_zmm +#include "builtin-memmove-3a.c" diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-4a.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-4a.c new file mode 100644 index 0000000..c437a53 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-4a.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_xmm: +**.LFB0: +** .cfi_startproc +** cmpq \$32, %rdx +** ja .L13 +**.L1: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L13: +** movq %rdi, %rcx +** movq %rsi, %rax +** cmpq \$128, %rdx +** jbe .L14 +** movq %rdx, %rsi +** cmpq %rdi, %rax +** jb .L7 +** je .L1 +** movdqu -16\(%rax,%rdx\), %xmm7 +** movdqu -32\(%rax,%rdx\), %xmm6 +** movdqu -48\(%rax,%rdx\), %xmm5 +** movdqu -64\(%rax,%rdx\), %xmm4 +**.L8: +** movdqu \(%rax\), %xmm3 +** subq \$64, %rsi +** addq \$64, %rcx +** addq \$64, %rax +** movdqu -48\(%rax\), %xmm2 +** movdqu -32\(%rax\), %xmm1 +** movdqu -16\(%rax\), %xmm0 +** movups %xmm3, -64\(%rcx\) +** movups %xmm2, -48\(%rcx\) +** movups %xmm1, -32\(%rcx\) +** movups %xmm0, -16\(%rcx\) +** cmpq \$64, %rsi +** ja .L8 +** movups %xmm7, -16\(%rdi,%rdx\) +** movups %xmm6, -32\(%rdi,%rdx\) +** movups %xmm5, -48\(%rdi,%rdx\) +** movups %xmm4, -64\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L14: +** cmpq \$64, %rdx +** jb .L6 +** movdqu \(%rsi\), %xmm7 +** movdqu 16\(%rsi\), %xmm6 +** movdqu 32\(%rsi\), %xmm5 +** movdqu 48\(%rsi\), %xmm4 +** movdqu -16\(%rsi,%rdx\), %xmm3 +** movdqu -32\(%rsi,%rdx\), %xmm2 +** movdqu -48\(%rsi,%rdx\), %xmm1 +** movdqu -64\(%rsi,%rdx\), %xmm0 +** movups %xmm7, \(%rdi\) +** movups %xmm6, 16\(%rdi\) +** movups %xmm5, 32\(%rdi\) +** movups %xmm4, 48\(%rdi\) +** movups %xmm3, -16\(%rdi,%rdx\) +** movups %xmm2, -32\(%rdi,%rdx\) +** movups %xmm1, -48\(%rdi,%rdx\) +** movups %xmm0, -64\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L6: +** movdqu \(%rsi\), %xmm3 +** movdqu 16\(%rsi\), %xmm2 +** movdqu -16\(%rsi,%rdx\), %xmm1 +** movdqu -32\(%rsi,%rdx\), %xmm0 +** movups %xmm3, \(%rdi\) +** movups %xmm2, 16\(%rdi\) +** movups %xmm1, -16\(%rdi,%rdx\) +** movups %xmm0, -32\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L7: +** movdqu \(%rax\), %xmm3 +** movdqu 16\(%rax\), %xmm2 +** leaq \(%rdi,%rdx\), %rcx +** movdqu 32\(%rax\), %xmm1 +** movdqu 48\(%rax\), %xmm0 +** addq %rdx, %rax +**.L9: +** movdqu -16\(%rax\), %xmm7 +** movdqu -32\(%rax\), %xmm6 +** subq \$64, %rsi +** subq \$64, %rcx +** movdqu -48\(%rax\), %xmm5 +** movdqu -64\(%rax\), %xmm4 +** subq \$64, %rax +** movups %xmm7, 48\(%rcx\) +** movups %xmm6, 32\(%rcx\) +** movups %xmm5, 16\(%rcx\) +** movups %xmm4, \(%rcx\) +** cmpq \$64, %rsi +** ja .L9 +** movups %xmm3, \(%rdi\) +** movups %xmm2, 16\(%rdi\) +** movups %xmm1, 32\(%rdi\) +** movups %xmm0, 48\(%rdi\) +** ret +** .cfi_endproc +**... +*/ + +#ifndef gcc_memmove +#define gcc_memmove gcc_memmove_xmm +#endif + +void +gcc_memmove (void *a, void *b, __SIZE_TYPE__ n) +{ + if (n > 32) + __builtin_memmove (a, b, n); +} diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-4b.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-4b.c new file mode 100644 index 0000000..4b65fca --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-4b.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx512f -march=x86-64-v3 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_ymm: +**.LFB0: +** .cfi_startproc +** cmpq \$32, %rdx +** ja .L14 +**.L12: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L14: +** movq %rdi, %rcx +** movq %rsi, %rax +** cmpq \$64, %rdx +** jbe .L15 +** cmpq \$256, %rdx +** ja .L5 +** cmpq \$128, %rdx +** jnb .L16 +** vmovdqu \(%rsi\), %ymm3 +** vmovdqu 32\(%rsi\), %ymm2 +** vmovdqu -32\(%rsi,%rdx\), %ymm1 +** vmovdqu -64\(%rsi,%rdx\), %ymm0 +** vmovdqu %ymm3, \(%rdi\) +** vmovdqu %ymm2, 32\(%rdi\) +** vmovdqu %ymm1, -32\(%rdi,%rdx\) +** vmovdqu %ymm0, -64\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L15: +** vmovdqu \(%rsi\), %ymm1 +** vmovdqu -32\(%rsi,%rdx\), %ymm0 +** vmovdqu %ymm1, \(%rdi\) +** vmovdqu %ymm0, -32\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L5: +** movq %rdx, %rsi +** cmpq %rdi, %rax +** jb .L7 +** je .L12 +** vmovdqu -32\(%rax,%rdx\), %ymm7 +** vmovdqu -64\(%rax,%rdx\), %ymm6 +** vmovdqu -96\(%rax,%rdx\), %ymm5 +** vmovdqu -128\(%rax,%rdx\), %ymm4 +**.L8: +** vmovdqu \(%rax\), %ymm3 +** addq \$-128, %rsi +** subq \$-128, %rcx +** subq \$-128, %rax +** vmovdqu -96\(%rax\), %ymm2 +** vmovdqu -64\(%rax\), %ymm1 +** vmovdqu -32\(%rax\), %ymm0 +** vmovdqu %ymm3, -128\(%rcx\) +** vmovdqu %ymm2, -96\(%rcx\) +** vmovdqu %ymm1, -64\(%rcx\) +** vmovdqu %ymm0, -32\(%rcx\) +** cmpq \$128, %rsi +** ja .L8 +** vmovdqu %ymm7, -32\(%rdi,%rdx\) +** vmovdqu %ymm6, -64\(%rdi,%rdx\) +** vmovdqu %ymm5, -96\(%rdi,%rdx\) +** vmovdqu %ymm4, -128\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L7: +** vmovdqu \(%rax\), %ymm3 +** vmovdqu 32\(%rax\), %ymm2 +** leaq \(%rdi,%rdx\), %rcx +** vmovdqu 64\(%rax\), %ymm1 +** vmovdqu 96\(%rax\), %ymm0 +** addq %rdx, %rax +**.L9: +** vmovdqu -32\(%rax\), %ymm7 +** vmovdqu -64\(%rax\), %ymm6 +** addq \$-128, %rsi +** addq \$-128, %rcx +** vmovdqu -96\(%rax\), %ymm5 +** vmovdqu -128\(%rax\), %ymm4 +** addq \$-128, %rax +** vmovdqu %ymm7, 96\(%rcx\) +** vmovdqu %ymm6, 64\(%rcx\) +** vmovdqu %ymm5, 32\(%rcx\) +** vmovdqu %ymm4, \(%rcx\) +** cmpq \$128, %rsi +** ja .L9 +** vmovdqu %ymm3, \(%rdi\) +** vmovdqu %ymm2, 32\(%rdi\) +** vmovdqu %ymm1, 64\(%rdi\) +** vmovdqu %ymm0, 96\(%rdi\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L16: +** vmovdqu \(%rsi\), %ymm7 +** vmovdqu 32\(%rsi\), %ymm6 +** vmovdqu 64\(%rsi\), %ymm5 +** vmovdqu 96\(%rsi\), %ymm4 +** vmovdqu -32\(%rsi,%rdx\), %ymm3 +** vmovdqu -64\(%rsi,%rdx\), %ymm2 +** vmovdqu -96\(%rsi,%rdx\), %ymm1 +** vmovdqu -128\(%rsi,%rdx\), %ymm0 +** vmovdqu %ymm7, \(%rdi\) +** vmovdqu %ymm6, 32\(%rdi\) +** vmovdqu %ymm5, 64\(%rdi\) +** vmovdqu %ymm4, 96\(%rdi\) +** vmovdqu %ymm3, -32\(%rdi,%rdx\) +** vmovdqu %ymm2, -64\(%rdi,%rdx\) +** vmovdqu %ymm1, -96\(%rdi,%rdx\) +** vmovdqu %ymm0, -128\(%rdi,%rdx\) +** vzeroupper +** ret +** .cfi_endproc +**... +*/ + +#define gcc_memmove gcc_memmove_ymm +#include "builtin-memmove-4a.c" diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-4c.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-4c.c new file mode 100644 index 0000000..fea3e49 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-4c.c @@ -0,0 +1,141 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -mmove-max=512 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_zmm: +**.LFB0: +** .cfi_startproc +** cmpq \$32, %rdx +** ja .L16 +**.L14: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L16: +** movq %rdi, %rcx +** movq %rsi, %rax +** cmpq \$64, %rdx +** jb .L6 +** cmpq \$128, %rdx +** ja .L5 +** vmovdqu64 \(%rsi\), %zmm1 +** vmovdqu64 -64\(%rsi,%rdx\), %zmm0 +** vmovdqu64 %zmm1, \(%rdi\) +** vmovdqu64 %zmm0, -64\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L6: +** vmovdqu \(%rsi\), %ymm1 +** vmovdqu -32\(%rsi,%rdx\), %ymm0 +** vmovdqu %ymm1, \(%rdi\) +** vmovdqu %ymm0, -32\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L5: +** cmpq \$512, %rdx +** jbe .L17 +** movq %rdx, %rsi +** cmpq %rdi, %rax +** jb .L9 +** je .L14 +** vmovdqu64 -64\(%rax,%rdx\), %zmm7 +** vmovdqu64 -128\(%rax,%rdx\), %zmm6 +** vmovdqu64 -192\(%rax,%rdx\), %zmm5 +** vmovdqu64 -256\(%rax,%rdx\), %zmm4 +**.L10: +** vmovdqu64 \(%rax\), %zmm3 +** addq \$256, %rax +** vmovdqu64 -192\(%rax\), %zmm2 +** subq \$256, %rsi +** vmovdqu64 -128\(%rax\), %zmm1 +** vmovdqu64 -64\(%rax\), %zmm0 +** addq \$256, %rcx +** vmovdqu64 %zmm3, -256\(%rcx\) +** vmovdqu64 %zmm2, -192\(%rcx\) +** vmovdqu64 %zmm1, -128\(%rcx\) +** vmovdqu64 %zmm0, -64\(%rcx\) +** cmpq \$256, %rsi +** ja .L10 +** vmovdqu64 %zmm7, -64\(%rdi,%rdx\) +** vmovdqu64 %zmm6, -128\(%rdi,%rdx\) +** vmovdqu64 %zmm5, -192\(%rdi,%rdx\) +** vmovdqu64 %zmm4, -256\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L17: +** cmpq \$256, %rdx +** jb .L8 +** vmovdqu64 \(%rsi\), %zmm7 +** vmovdqu64 64\(%rsi\), %zmm6 +** vmovdqu64 -64\(%rsi,%rdx\), %zmm3 +** vmovdqu64 -128\(%rsi,%rdx\), %zmm2 +** vmovdqu64 128\(%rsi\), %zmm5 +** vmovdqu64 192\(%rsi\), %zmm4 +** vmovdqu64 -192\(%rsi,%rdx\), %zmm1 +** vmovdqu64 -256\(%rsi,%rdx\), %zmm0 +** vmovdqu64 %zmm7, \(%rdi\) +** vmovdqu64 %zmm6, 64\(%rdi\) +** vmovdqu64 %zmm5, 128\(%rdi\) +** vmovdqu64 %zmm4, 192\(%rdi\) +** vmovdqu64 %zmm3, -64\(%rdi,%rdx\) +** vmovdqu64 %zmm2, -128\(%rdi,%rdx\) +** vmovdqu64 %zmm1, -192\(%rdi,%rdx\) +** vmovdqu64 %zmm0, -256\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L8: +** vmovdqu64 \(%rsi\), %zmm3 +** vmovdqu64 64\(%rsi\), %zmm2 +** vmovdqu64 -64\(%rsi,%rdx\), %zmm1 +** vmovdqu64 -128\(%rsi,%rdx\), %zmm0 +** vmovdqu64 %zmm3, \(%rdi\) +** vmovdqu64 %zmm2, 64\(%rdi\) +** vmovdqu64 %zmm1, -64\(%rdi,%rdx\) +** vmovdqu64 %zmm0, -128\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L9: +** vmovdqu64 \(%rax\), %zmm3 +** leaq \(%rdi,%rdx\), %rcx +** vmovdqu64 64\(%rax\), %zmm2 +** vmovdqu64 128\(%rax\), %zmm1 +** vmovdqu64 192\(%rax\), %zmm0 +** addq %rdx, %rax +**.L11: +** vmovdqu64 -64\(%rax\), %zmm7 +** subq \$256, %rax +** vmovdqu64 128\(%rax\), %zmm6 +** subq \$256, %rsi +** vmovdqu64 64\(%rax\), %zmm5 +** vmovdqu64 \(%rax\), %zmm4 +** subq \$256, %rcx +** vmovdqu64 %zmm7, 192\(%rcx\) +** vmovdqu64 %zmm6, 128\(%rcx\) +** vmovdqu64 %zmm5, 64\(%rcx\) +** vmovdqu64 %zmm4, \(%rcx\) +** cmpq \$256, %rsi +** ja .L11 +** vmovdqu64 %zmm3, \(%rdi\) +** vmovdqu64 %zmm2, 64\(%rdi\) +** vmovdqu64 %zmm1, 128\(%rdi\) +** vmovdqu64 %zmm0, 192\(%rdi\) +** vzeroupper +** ret +** .cfi_endproc +**... +*/ + +#define gcc_memmove gcc_memmove_zmm +#include "builtin-memmove-4a.c" diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-5a.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-5a.c new file mode 100644 index 0000000..c86defb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-5a.c @@ -0,0 +1,109 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_xmm: +**.LFB0: +** .cfi_startproc +** cmpq \$67, %rdx +** ja .L12 +**.L1: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L12: +** movq %rdi, %rcx +** movq %rsi, %rax +** cmpq \$128, %rdx +** jbe .L13 +** movq %rdx, %rsi +** cmpq %rdi, %rax +** jb .L6 +** je .L1 +** movdqu -16\(%rax,%rdx\), %xmm7 +** movdqu -32\(%rax,%rdx\), %xmm6 +** movdqu -48\(%rax,%rdx\), %xmm5 +** movdqu -64\(%rax,%rdx\), %xmm4 +**.L7: +** movdqu \(%rax\), %xmm3 +** subq \$64, %rsi +** addq \$64, %rcx +** addq \$64, %rax +** movdqu -48\(%rax\), %xmm2 +** movdqu -32\(%rax\), %xmm1 +** movdqu -16\(%rax\), %xmm0 +** movups %xmm3, -64\(%rcx\) +** movups %xmm2, -48\(%rcx\) +** movups %xmm1, -32\(%rcx\) +** movups %xmm0, -16\(%rcx\) +** cmpq \$64, %rsi +** ja .L7 +** movups %xmm7, -16\(%rdi,%rdx\) +** movups %xmm6, -32\(%rdi,%rdx\) +** movups %xmm5, -48\(%rdi,%rdx\) +** movups %xmm4, -64\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L13: +** movdqu \(%rsi\), %xmm7 +** movdqu 16\(%rsi\), %xmm6 +** movdqu 32\(%rsi\), %xmm5 +** movdqu 48\(%rsi\), %xmm4 +** movdqu -16\(%rsi,%rdx\), %xmm3 +** movdqu -32\(%rsi,%rdx\), %xmm2 +** movdqu -48\(%rsi,%rdx\), %xmm1 +** movdqu -64\(%rsi,%rdx\), %xmm0 +** movups %xmm7, \(%rdi\) +** movups %xmm6, 16\(%rdi\) +** movups %xmm5, 32\(%rdi\) +** movups %xmm4, 48\(%rdi\) +** movups %xmm3, -16\(%rdi,%rdx\) +** movups %xmm2, -32\(%rdi,%rdx\) +** movups %xmm1, -48\(%rdi,%rdx\) +** movups %xmm0, -64\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L6: +** movdqu \(%rax\), %xmm3 +** movdqu 16\(%rax\), %xmm2 +** leaq \(%rdi,%rdx\), %rcx +** movdqu 32\(%rax\), %xmm1 +** movdqu 48\(%rax\), %xmm0 +** addq %rdx, %rax +**.L8: +** movdqu -16\(%rax\), %xmm7 +** movdqu -32\(%rax\), %xmm6 +** subq \$64, %rsi +** subq \$64, %rcx +** movdqu -48\(%rax\), %xmm5 +** movdqu -64\(%rax\), %xmm4 +** subq \$64, %rax +** movups %xmm7, 48\(%rcx\) +** movups %xmm6, 32\(%rcx\) +** movups %xmm5, 16\(%rcx\) +** movups %xmm4, \(%rcx\) +** cmpq \$64, %rsi +** ja .L8 +** movups %xmm3, \(%rdi\) +** movups %xmm2, 16\(%rdi\) +** movups %xmm1, 32\(%rdi\) +** movups %xmm0, 48\(%rdi\) +** ret +** .cfi_endproc +**... +*/ + +#ifndef gcc_memmove +#define gcc_memmove gcc_memmove_xmm +#endif + +void +gcc_memmove (void *a, void *b, __SIZE_TYPE__ n) +{ + if (n > 67) + __builtin_memmove (a, b, n); +} diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-5b.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-5b.c new file mode 100644 index 0000000..e5fc156 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-5b.c @@ -0,0 +1,120 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx512f -march=x86-64-v3 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_ymm: +**.LFB0: +** .cfi_startproc +** cmpq \$67, %rdx +** ja .L14 +**.L12: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L14: +** movq %rdi, %rcx +** movq %rsi, %rax +** cmpq \$256, %rdx +** jbe .L15 +** movq %rdx, %rsi +** cmpq %rdi, %rax +** jb .L7 +** je .L12 +** vmovdqu -32\(%rax,%rdx\), %ymm7 +** vmovdqu -64\(%rax,%rdx\), %ymm6 +** vmovdqu -96\(%rax,%rdx\), %ymm5 +** vmovdqu -128\(%rax,%rdx\), %ymm4 +**.L8: +** vmovdqu \(%rax\), %ymm3 +** addq \$-128, %rsi +** subq \$-128, %rcx +** subq \$-128, %rax +** vmovdqu -96\(%rax\), %ymm2 +** vmovdqu -64\(%rax\), %ymm1 +** vmovdqu -32\(%rax\), %ymm0 +** vmovdqu %ymm3, -128\(%rcx\) +** vmovdqu %ymm2, -96\(%rcx\) +** vmovdqu %ymm1, -64\(%rcx\) +** vmovdqu %ymm0, -32\(%rcx\) +** cmpq \$128, %rsi +** ja .L8 +** vmovdqu %ymm7, -32\(%rdi,%rdx\) +** vmovdqu %ymm6, -64\(%rdi,%rdx\) +** vmovdqu %ymm5, -96\(%rdi,%rdx\) +** vmovdqu %ymm4, -128\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L15: +** cmpq \$128, %rdx +** jb .L6 +** vmovdqu \(%rsi\), %ymm7 +** vmovdqu 32\(%rsi\), %ymm6 +** vmovdqu 64\(%rsi\), %ymm5 +** vmovdqu 96\(%rsi\), %ymm4 +** vmovdqu -32\(%rsi,%rdx\), %ymm3 +** vmovdqu -64\(%rsi,%rdx\), %ymm2 +** vmovdqu -96\(%rsi,%rdx\), %ymm1 +** vmovdqu -128\(%rsi,%rdx\), %ymm0 +** vmovdqu %ymm7, \(%rdi\) +** vmovdqu %ymm6, 32\(%rdi\) +** vmovdqu %ymm5, 64\(%rdi\) +** vmovdqu %ymm4, 96\(%rdi\) +** vmovdqu %ymm3, -32\(%rdi,%rdx\) +** vmovdqu %ymm2, -64\(%rdi,%rdx\) +** vmovdqu %ymm1, -96\(%rdi,%rdx\) +** vmovdqu %ymm0, -128\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L6: +** vmovdqu \(%rsi\), %ymm3 +** vmovdqu 32\(%rsi\), %ymm2 +** vmovdqu -32\(%rsi,%rdx\), %ymm1 +** vmovdqu -64\(%rsi,%rdx\), %ymm0 +** vmovdqu %ymm3, \(%rdi\) +** vmovdqu %ymm2, 32\(%rdi\) +** vmovdqu %ymm1, -32\(%rdi,%rdx\) +** vmovdqu %ymm0, -64\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L7: +** vmovdqu \(%rax\), %ymm3 +** vmovdqu 32\(%rax\), %ymm2 +** leaq \(%rdi,%rdx\), %rcx +** vmovdqu 64\(%rax\), %ymm1 +** vmovdqu 96\(%rax\), %ymm0 +** addq %rdx, %rax +**.L9: +** vmovdqu -32\(%rax\), %ymm7 +** vmovdqu -64\(%rax\), %ymm6 +** addq \$-128, %rsi +** addq \$-128, %rcx +** vmovdqu -96\(%rax\), %ymm5 +** vmovdqu -128\(%rax\), %ymm4 +** addq \$-128, %rax +** vmovdqu %ymm7, 96\(%rcx\) +** vmovdqu %ymm6, 64\(%rcx\) +** vmovdqu %ymm5, 32\(%rcx\) +** vmovdqu %ymm4, \(%rcx\) +** cmpq \$128, %rsi +** ja .L9 +** vmovdqu %ymm3, \(%rdi\) +** vmovdqu %ymm2, 32\(%rdi\) +** vmovdqu %ymm1, 64\(%rdi\) +** vmovdqu %ymm0, 96\(%rdi\) +** vzeroupper +** ret +** .cfi_endproc +**.LFE0: +**... +*/ + +#define gcc_memmove gcc_memmove_ymm +#include "builtin-memmove-5a.c" diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-5c.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-5c.c new file mode 100644 index 0000000..a8443f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-5c.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -mmove-max=512 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove_zmm: +**.LFB0: +** .cfi_startproc +** cmpq \$67, %rdx +** ja .L14 +**.L12: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L14: +** movq %rdi, %rcx +** movq %rsi, %rax +** cmpq \$128, %rdx +** jbe .L15 +** cmpq \$512, %rdx +** ja .L5 +** cmpq \$256, %rdx +** jnb .L16 +** vmovdqu64 \(%rsi\), %zmm3 +** vmovdqu64 64\(%rsi\), %zmm2 +** vmovdqu64 -64\(%rsi,%rdx\), %zmm1 +** vmovdqu64 -128\(%rsi,%rdx\), %zmm0 +** vmovdqu64 %zmm3, \(%rdi\) +** vmovdqu64 %zmm2, 64\(%rdi\) +** vmovdqu64 %zmm1, -64\(%rdi,%rdx\) +** vmovdqu64 %zmm0, -128\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L15: +** vmovdqu64 \(%rsi\), %zmm1 +** vmovdqu64 -64\(%rsi,%rdx\), %zmm0 +** vmovdqu64 %zmm1, \(%rdi\) +** vmovdqu64 %zmm0, -64\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L5: +** movq %rdx, %rsi +** cmpq %rdi, %rax +** jb .L7 +** je .L12 +** vmovdqu64 -64\(%rax,%rdx\), %zmm7 +** vmovdqu64 -128\(%rax,%rdx\), %zmm6 +** vmovdqu64 -192\(%rax,%rdx\), %zmm5 +** vmovdqu64 -256\(%rax,%rdx\), %zmm4 +**.L8: +** vmovdqu64 \(%rax\), %zmm3 +** addq \$256, %rax +** vmovdqu64 -192\(%rax\), %zmm2 +** subq \$256, %rsi +** vmovdqu64 -128\(%rax\), %zmm1 +** vmovdqu64 -64\(%rax\), %zmm0 +** addq \$256, %rcx +** vmovdqu64 %zmm3, -256\(%rcx\) +** vmovdqu64 %zmm2, -192\(%rcx\) +** vmovdqu64 %zmm1, -128\(%rcx\) +** vmovdqu64 %zmm0, -64\(%rcx\) +** cmpq \$256, %rsi +** ja .L8 +** vmovdqu64 %zmm7, -64\(%rdi,%rdx\) +** vmovdqu64 %zmm6, -128\(%rdi,%rdx\) +** vmovdqu64 %zmm5, -192\(%rdi,%rdx\) +** vmovdqu64 %zmm4, -256\(%rdi,%rdx\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L7: +** vmovdqu64 \(%rax\), %zmm3 +** leaq \(%rdi,%rdx\), %rcx +** vmovdqu64 64\(%rax\), %zmm2 +** vmovdqu64 128\(%rax\), %zmm1 +** vmovdqu64 192\(%rax\), %zmm0 +** addq %rdx, %rax +**.L9: +** vmovdqu64 -64\(%rax\), %zmm7 +** subq \$256, %rax +** vmovdqu64 128\(%rax\), %zmm6 +** subq \$256, %rsi +** vmovdqu64 64\(%rax\), %zmm5 +** vmovdqu64 \(%rax\), %zmm4 +** subq \$256, %rcx +** vmovdqu64 %zmm7, 192\(%rcx\) +** vmovdqu64 %zmm6, 128\(%rcx\) +** vmovdqu64 %zmm5, 64\(%rcx\) +** vmovdqu64 %zmm4, \(%rcx\) +** cmpq \$256, %rsi +** ja .L9 +** vmovdqu64 %zmm3, \(%rdi\) +** vmovdqu64 %zmm2, 64\(%rdi\) +** vmovdqu64 %zmm1, 128\(%rdi\) +** vmovdqu64 %zmm0, 192\(%rdi\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L16: +** vmovdqu64 \(%rsi\), %zmm7 +** vmovdqu64 64\(%rsi\), %zmm6 +** vmovdqu64 -64\(%rsi,%rdx\), %zmm3 +** vmovdqu64 -128\(%rsi,%rdx\), %zmm2 +** vmovdqu64 128\(%rsi\), %zmm5 +** vmovdqu64 192\(%rsi\), %zmm4 +** vmovdqu64 -192\(%rsi,%rdx\), %zmm1 +** vmovdqu64 -256\(%rsi,%rdx\), %zmm0 +** vmovdqu64 %zmm7, \(%rdi\) +** vmovdqu64 %zmm6, 64\(%rdi\) +** vmovdqu64 %zmm5, 128\(%rdi\) +** vmovdqu64 %zmm4, 192\(%rdi\) +** vmovdqu64 %zmm3, -64\(%rdi,%rdx\) +** vmovdqu64 %zmm2, -128\(%rdi,%rdx\) +** vmovdqu64 %zmm1, -192\(%rdi,%rdx\) +** vmovdqu64 %zmm0, -256\(%rdi,%rdx\) +** vzeroupper +** ret +** .cfi_endproc +**... +*/ + +#define gcc_memmove gcc_memmove_zmm +#include "builtin-memmove-5a.c" diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-6.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-6.c new file mode 100644 index 0000000..6d15916 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-6.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove: +**.LFB0: +** .cfi_startproc +** cmpq \$7, %rdx +** jbe .L8 +**.L1: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L8: +** cmpl \$4, %edx +** jnb .L9 +** cmpl \$1, %edx +** ja .L5 +** jb .L1 +** movzbl \(%rsi\), %eax +** movb %al, \(%rdi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L9: +** movl %edx, %edx +** movl \(%rsi\), %ecx +** movl -4\(%rsi,%rdx\), %eax +** movl %ecx, \(%rdi\) +** movl %eax, -4\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L5: +** movl %edx, %edx +** movzwl \(%rsi\), %ecx +** movzwl -2\(%rsi,%rdx\), %eax +** movw %cx, \(%rdi\) +** movw %ax, -2\(%rdi,%rdx\) +** ret +** .cfi_endproc +**... +*/ + +void +gcc_memmove (void *a, void *b, __SIZE_TYPE__ n) +{ + if (n < 8) + __builtin_memmove (a, b, n); +} diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-7.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-7.c new file mode 100644 index 0000000..4118b13 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-7.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove: +**.LFB0: +** .cfi_startproc +** cmpq \$3, %rdx +** jbe .L7 +**.L1: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L7: +** cmpl \$2, %edx +** jnb .L8 +** cmpl \$1, %edx +** jb .L1 +** movzbl \(%rsi\), %eax +** movb %al, \(%rdi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L8: +** movl %edx, %edx +** movzwl \(%rsi\), %ecx +** movzwl -2\(%rsi,%rdx\), %eax +** movw %cx, \(%rdi\) +** movw %ax, -2\(%rdi,%rdx\) +** ret +** .cfi_endproc +**... +*/ + +void +gcc_memmove (void *a, void *b, __SIZE_TYPE__ n) +{ + if (n < 4) + __builtin_memmove (a, b, n); +} diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-8.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-8.c new file mode 100644 index 0000000..aa57a10 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-8.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove: +**.LFB0: +** .cfi_startproc +** cmpq \$33, %rdx +** jbe .L12 +**.L1: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L12: +** cmpl \$16, %edx +** jnb .L13 +** cmpl \$8, %edx +** jnb .L6 +** cmpl \$4, %edx +** jnb .L7 +** cmpl \$1, %edx +** ja .L8 +** jb .L1 +** movzbl \(%rsi\), %eax +** movb %al, \(%rdi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L13: +** cmpl \$32, %edx +** ja .L5 +** movl %edx, %edx +** movdqu \(%rsi\), %xmm1 +** movdqu -16\(%rsi,%rdx\), %xmm0 +** movups %xmm1, \(%rdi\) +** movups %xmm0, -16\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L5: +** movl %edx, %edx +** movdqu \(%rsi\), %xmm3 +** movdqu 16\(%rsi\), %xmm2 +** addq %rdx, %rsi +** movdqu -16\(%rsi\), %xmm1 +** movdqu -32\(%rsi\), %xmm0 +** movups %xmm3, \(%rdi\) +** movups %xmm2, 16\(%rdi\) +** movups %xmm1, -16\(%rdi,%rdx\) +** movups %xmm0, -32\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L6: +** movl %edx, %edx +** movq \(%rsi\), %rcx +** movq -8\(%rsi,%rdx\), %rax +** movq %rcx, \(%rdi\) +** movq %rax, -8\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L7: +** movl %edx, %edx +** movl \(%rsi\), %ecx +** movl -4\(%rsi,%rdx\), %eax +** movl %ecx, \(%rdi\) +** movl %eax, -4\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L8: +** movl %edx, %edx +** movzwl \(%rsi\), %ecx +** movzwl -2\(%rsi,%rdx\), %eax +** movw %cx, \(%rdi\) +** movw %ax, -2\(%rdi,%rdx\) +** ret +** .cfi_endproc +**... +*/ + +void +gcc_memmove (void *a, void *b, __SIZE_TYPE__ n) +{ + if (n < 34) + __builtin_memmove (a, b, n); +} diff --git a/gcc/testsuite/gcc.target/i386/builtin-memmove-9.c b/gcc/testsuite/gcc.target/i386/builtin-memmove-9.c new file mode 100644 index 0000000..f84565e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/builtin-memmove-9.c @@ -0,0 +1,63 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { lp64 } } {^\t?\.} } } */ + +/* +**gcc_memmove: +**.LFB0: +** .cfi_startproc +** cmpq \$15, %rdx +** jbe .L9 +**.L1: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L9: +** cmpl \$8, %edx +** jnb .L10 +** cmpl \$4, %edx +** jnb .L5 +** cmpl \$1, %edx +** ja .L6 +** jb .L1 +** movzbl \(%rsi\), %eax +** movb %al, \(%rdi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L10: +** movl %edx, %edx +** movq \(%rsi\), %rcx +** movq -8\(%rsi,%rdx\), %rax +** movq %rcx, \(%rdi\) +** movq %rax, -8\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L5: +** movl %edx, %edx +** movl \(%rsi\), %ecx +** movl -4\(%rsi,%rdx\), %eax +** movl %ecx, \(%rdi\) +** movl %eax, -4\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L6: +** movl %edx, %edx +** movzwl \(%rsi\), %ecx +** movzwl -2\(%rsi,%rdx\), %eax +** movw %cx, \(%rdi\) +** movw %ax, -2\(%rdi,%rdx\) +** ret +** .cfi_endproc +**... +*/ + +void +gcc_memmove (void *a, void *b, __SIZE_TYPE__ n) +{ + if (n < 16) + __builtin_memmove (a, b, n); +} diff --git a/gcc/testsuite/gcc.target/i386/pr116815.c b/gcc/testsuite/gcc.target/i386/pr116815.c new file mode 100644 index 0000000..1cd2f72 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr116815.c @@ -0,0 +1,31 @@ +/* PR target/116815 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-additional-options "-march=pentiumpro" { target ia32 } } */ + +static inline __attribute__ ((always_inline)) +unsigned max (unsigned a, unsigned b) { return a > b ? a : b; } + +static inline __attribute__ ((always_inline)) +unsigned min (unsigned a, unsigned b) { return a < b ? a : b; } + +#define OPERATION(op, type, N, exp1, exp2) \ + unsigned u##op##type##N (unsigned a, unsigned b) { return op (exp1, exp2); } + +OPERATION (max, add, 1, a, a + b) +OPERATION (max, add, 2, a, b + a) +OPERATION (max, add, 3, a + b, a) +OPERATION (max, add, 4, b + a, a) + +OPERATION (min, add, 1, a, a + b) +OPERATION (min, add, 2, a, b + a) +OPERATION (min, add, 3, a + b, a) +OPERATION (min, add, 4, b + a, a) + +OPERATION (max, sub, 1, a, a - b) +OPERATION (max, sub, 2, a - b, a) + +OPERATION (min, sub, 1, a, a - b) +OPERATION (min, sub, 2, a - b, a) + +/* { dg-final { scan-assembler-not "cmp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr122457.c b/gcc/testsuite/gcc.target/i386/pr122457.c new file mode 100644 index 0000000..dc57fb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr122457.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -mavxvnniint16" } */ + +#include "vnniint16-auto-vectorize-2.c" diff --git a/gcc/testsuite/gcc.target/i386/pr122518.c b/gcc/testsuite/gcc.target/i386/pr122518.c new file mode 100644 index 0000000..2791889 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr122518.c @@ -0,0 +1,15 @@ +/* PR target/122518 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +inline unsigned min (unsigned a, unsigned b) +{ + return (a < b) ? a : b; +} + +unsigned uminsub (unsigned a, unsigned b) +{ + return min (a - b, a); +} + +/* { dg-final { scan-assembler-not "cmp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr122534.c b/gcc/testsuite/gcc.target/i386/pr122534.c new file mode 100644 index 0000000..b1988fb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr122534.c @@ -0,0 +1,15 @@ +/* PR target/122534 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int test (unsigned long p[6], int index) +{ + __SIZE_TYPE__ i; + + for (i = 0; i < 6; i++) + if (p[i] & (1UL << index)) + return i; + return 0; +} + +/* { dg-final { scan-assembler-not "and" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/and-large-immediate-opt.c b/gcc/testsuite/gcc.target/loongarch/and-large-immediate-opt.c new file mode 100644 index 0000000..921bef6 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/and-large-immediate-opt.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-O3" } */ +/* { dg-final { scan-assembler-not "\tlu12i.w" } } */ +/* { dg-final { scan-assembler-not "\tori" } } */ +/* { dg-final { scan-assembler-not "\tlu52i.d" } } */ +/* { dg-final { scan-assembler-not "\tand" } } */ +/* { dg-final { scan-assembler "\tbstrpick.d" } } */ +/* { dg-final { scan-assembler "\tbstrins.d" } } */ + +long +test (long a) +{ + return a & 0x3fffffffefffffff; +} diff --git a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c index ed13471..47802aa 100644 --- a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c +++ b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c @@ -27,7 +27,7 @@ void test_lt () { if (lm < ln) - lr *= (1 << 16); + lr += (1 << 16); lr += lm; } @@ -35,7 +35,7 @@ void test_le () { if (lm <= ln) - lr = lm * ((long)1 << 32); + lr = lm + ((long)1 << 32); else lr = lm; lr += lm; diff --git a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c index ac72d4d..743fd5e 100644 --- a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c +++ b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c @@ -29,7 +29,7 @@ void test_lez () { if (lm <= 0) - lr &= (1 << 16); + lr |= (1 << 16); lr += lm; } diff --git a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c new file mode 100644 index 0000000..9588798 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "maskeqz" } } */ +/* { dg-final { scan-assembler "masknez" } } */ + +extern long lm, ln, lr; + +void +test_and () +{ + if (lm < 0) + lr &= (1 << 16); + lr += lm; +} diff --git a/gcc/testsuite/gcc.target/loongarch/extendsidi2-combine.c b/gcc/testsuite/gcc.target/loongarch/extendsidi2-combine.c new file mode 100644 index 0000000..0c3613c --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/extendsidi2-combine.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-O3 -fno-strict-aliasing" } */ + +int +test (double a) +{ + int z; + + *((double *)&z) = a; + return z; +} + +/* { dg-final { scan-assembler-not "slli\\.w" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/fnmam4-vec.c b/gcc/testsuite/gcc.target/loongarch/fnmam4-vec.c new file mode 100644 index 0000000..0969303 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/fnmam4-vec.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -mlasx -ftree-vectorize" } */ +/* { dg-require-effective-target loongarch_asx } */ + +void +foo (float *u, float x, float *y, float z) +{ + int i; + for (i = 0; i < 1024; i++) + *(u++) = (x - y[i] * z); +} + +/* { dg-final { scan-assembler-not "\tvori.b"} } */ +/* { dg-final { scan-assembler-not "\txvori.b"} } */ diff --git a/gcc/testsuite/gcc.target/loongarch/imm-load.c b/gcc/testsuite/gcc.target/loongarch/imm-load.c index 33291fe..a125840 100644 --- a/gcc/testsuite/gcc.target/loongarch/imm-load.c +++ b/gcc/testsuite/gcc.target/loongarch/imm-load.c @@ -7,5 +7,5 @@ test (void) { return 0x1234567890abcdef; } -/* { dg-final { scan-rtl-dump-times "scanning new insn with uid" 6 "split1" } } */ +/* { dg-final { scan-rtl-dump-times "scanning new insn with uid" 4 "split1" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/lasx-xvpermi_q-opt.c b/gcc/testsuite/gcc.target/loongarch/lasx-xvpermi_q-opt.c new file mode 100644 index 0000000..16fb9df --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/lasx-xvpermi_q-opt.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mlasx -ftree-vectorize" } */ + +#include <lasxintrin.h> + +#define TEST_FUNC(imm) \ + __m256i \ + test_##imm (__m256i op0, __m256i op1) \ + { \ + return __lasx_xvpermi_q (op0, op1, imm); \ + } + +TEST_FUNC (0x00) +/* { dg-final { scan-assembler-not "test_0x00:.*\txvld.*xvld.*-test_0x00"} } */ +/* { dg-final { scan-assembler-times "test_0x00:.*\txvpermi\\.d.*-test_0x00" 1 } } */ + +TEST_FUNC (0x01) +/* { dg-final { scan-assembler-not "test_0x01:.*\txvld.*xvld.*-test_0x01"} } */ +/* { dg-final { scan-assembler-times "test_0x01:.*\txvpermi\\.d.*-test_0x01" 1 } } */ + +TEST_FUNC (0x10) +/* { dg-final { scan-assembler-not "test_0x10:.*\txvld.*xvld.*-test_0x10"} } */ +/* { dg-final { scan-assembler-not "test_0x10:.*\txvpermi.*-test_0x10"} } */ + +TEST_FUNC (0x11) +/* { dg-final { scan-assembler-not "test_0x11:.*\txvld.*xvld.*-test_0x11"} } */ +/* { dg-final { scan-assembler-times "test_0x11:.*\txvpermi\\.d.*-test_0x11" 1 } } */ + +TEST_FUNC (0x22) +/* { dg-final { scan-assembler-not "test_0x22:.*\txvld.*xvld.*-test_0x22"} } */ +/* { dg-final { scan-assembler-times "test_0x22:.*\txvpermi\\.d.*-test_0x22" 1 } } */ + +TEST_FUNC (0x23) +/* { dg-final { scan-assembler-not "test_0x23:.*\txvld.*xvld.*-test_0x23"} } */ +/* { dg-final { scan-assembler-times "test_0x23:.*\txvpermi\\.d.*-test_0x23" 1 } } */ + +TEST_FUNC (0x32) +/* { dg-final { scan-assembler-not "test_0x32:.*\txvld.*xvld.*-test_0x32"} } */ +/* { dg-final { scan-assembler-not "test_0x32:.*\txvpermi.*-test_0x32"} } */ + +TEST_FUNC (0x33) +/* { dg-final { scan-assembler-not "test_0x33:.*\txvld.*xvld.*-test_0x33"} } */ +/* { dg-final { scan-assembler-times "test_0x33:.*\txvpermi\\.d.*-test_0x33" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/loongarch/mem-and-mask-opt.c b/gcc/testsuite/gcc.target/loongarch/mem-and-mask-opt.c new file mode 100644 index 0000000..9b3a5cd --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/mem-and-mask-opt.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-final { scan-assembler-not "bstrpick" } } */ +/* { dg-final { scan-assembler "ld\\.wu" } } */ + +struct st +{ + char const *name; +}; +struct fst +{ + struct st *groups; +}; + +struct fst *pfunc (int); + +const char * +test (int pc, unsigned group) +{ + struct fst *pci = pfunc (pc); + + return pci->groups[group].name; +} diff --git a/gcc/testsuite/gcc.target/loongarch/mode-tieable-opt.c b/gcc/testsuite/gcc.target/loongarch/mode-tieable-opt.c new file mode 100644 index 0000000..d6a6577 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/mode-tieable-opt.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-O3 -mno-lsx" } */ +/* { dg-final { scan-assembler-not "stptr\.d" } } */ +/* { dg-final { scan-assembler-not "fld\.d" } } */ +/* { dg-final { scan-assembler-not "fst\.d" } } */ +/* { dg-final { scan-assembler-not "ldptr\.d" } } */ +/* { dg-final { scan-assembler "movgr2fr\.d" } } */ +/* { dg-final { scan-assembler "movfr2gr\.d" } } */ + +typedef double vec __attribute__ ((vector_size(16))); + +vec +foo (vec x, double a) +{ + x[0] -= a; + return x; +} diff --git a/gcc/testsuite/gcc.target/loongarch/mulh_wu.c b/gcc/testsuite/gcc.target/loongarch/mulh_wu.c new file mode 100644 index 0000000..53fc518 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/mulh_wu.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-O3 -mabi=lp64d" } */ +/* { dg-final { scan-assembler "\tmulh.wu" } } */ +/* { dg-final { scan-assembler-not "\tlu32i.d" } } */ + +unsigned int +test (unsigned int *a) +{ + return *a / 60; +} diff --git a/gcc/testsuite/gcc.target/loongarch/spill-less.c b/gcc/testsuite/gcc.target/loongarch/spill-less.c new file mode 100644 index 0000000..77eb9b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/spill-less.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-O3 -fno-strict-aliasing" } */ + +double +convert (long long in) +{ + double f; + *((long long *)&f) = in; + return f; +} + +/* { dg-final { scan-assembler-not "st\\.d" } } */ +/* { dg-final { scan-assembler-not "fld\\.d" } } */ +/* { dg-final { scan-assembler "movgr2fr\\.d" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/vec_pack_unpack_256.c b/gcc/testsuite/gcc.target/loongarch/vec_pack_unpack_256.c index 506b7bd..5b2fd9b 100644 --- a/gcc/testsuite/gcc.target/loongarch/vec_pack_unpack_256.c +++ b/gcc/testsuite/gcc.target/loongarch/vec_pack_unpack_256.c @@ -55,7 +55,8 @@ test_vec_unpacks_float_hi_lo_v8si (void) } /* { dg-final { scan-assembler "test_vec_unpacks_hi_lo_v8si:.*\tvext2xv\\.d\\.w.*-test_vec_unpacks_hi_lo_v8si" } } */ -/* { dg-final { scan-assembler "test_vec_unpacks_hi_lo_v8si:.*\txvpermi\\.q.*-test_vec_unpacks_hi_lo_v8si" } } */ +/* { dg-final { scan-assembler "test_vec_unpacks_hi_lo_v8si:.*\txvpermi\\.d.*-test_vec_unpacks_hi_lo_v8si" } } */ +/* { dg-final { scan-assembler-not "test_vec_unpacks_hi_lo_v8si:.*\txvpermi\\.q.*-test_vec_unpacks_hi_lo_v8si" } } */ void test_vec_unpacks_hi_lo_v8si (void) { @@ -64,7 +65,8 @@ test_vec_unpacks_hi_lo_v8si (void) } /* { dg-final { scan-assembler "test_vec_unpacks_hi_lo_v16hi:.*\tvext2xv\\.w\\.h.*-test_vec_unpacks_hi_lo_v16hi" } } */ -/* { dg-final { scan-assembler "test_vec_unpacks_hi_lo_v16hi:.*\txvpermi\\.q.*-test_vec_unpacks_hi_lo_v16hi" } } */ +/* { dg-final { scan-assembler "test_vec_unpacks_hi_lo_v16hi:.*\txvpermi\\.d.*-test_vec_unpacks_hi_lo_v16hi" } } */ +/* { dg-final { scan-assembler-not "test_vec_unpacks_hi_lo_v16hi:.*\txvpermi\\.q.*-test_vec_unpacks_hi_lo_v16hi" } } */ void test_vec_unpacks_hi_lo_v16hi (void) { @@ -73,7 +75,8 @@ test_vec_unpacks_hi_lo_v16hi (void) } /* { dg-final { scan-assembler "test_vec_unpacks_hi_lo_v32qi:.*\tvext2xv\\.h\\.b.*-test_vec_unpacks_hi_lo_v32qi" } } */ -/* { dg-final { scan-assembler "test_vec_unpacks_hi_lo_v32qi:.*\txvpermi\\.q.*-test_vec_unpacks_hi_lo_v32qi" } } */ +/* { dg-final { scan-assembler "test_vec_unpacks_hi_lo_v32qi:.*\txvpermi\\.d.*-test_vec_unpacks_hi_lo_v32qi" } } */ +/* { dg-final { scan-assembler-not "test_vec_unpacks_hi_lo_v32qi:.*\txvpermi\\.q.*-test_vec_unpacks_hi_lo_v32qi" } } */ void test_vec_unpacks_hi_lo_v32qi (void) { @@ -91,7 +94,8 @@ test_vec_unpacks_hi_lo_v8sf (void) } /* { dg-final { scan-assembler "test_vec_unpacku_hi_lo_v8si:.*\tvext2xv\\.du\\.wu.*-test_vec_unpacku_hi_lo_v8si" } } */ -/* { dg-final { scan-assembler "test_vec_unpacku_hi_lo_v8si:.*\txvpermi\\.q.*-test_vec_unpacku_hi_lo_v8si" } } */ +/* { dg-final { scan-assembler "test_vec_unpacku_hi_lo_v8si:.*\txvpermi\\.d.*-test_vec_unpacku_hi_lo_v8si" } } */ +/* { dg-final { scan-assembler-not "test_vec_unpacku_hi_lo_v8si:.*\txvpermi\\.q.*-test_vec_unpacku_hi_lo_v8si" } } */ void test_vec_unpacku_hi_lo_v8si (void) { @@ -100,7 +104,8 @@ test_vec_unpacku_hi_lo_v8si (void) } /* { dg-final { scan-assembler "test_vec_unpacku_hi_lo_v16hi:.*\tvext2xv\\.wu\\.hu.*-test_vec_unpacku_hi_lo_v16hi" } } */ -/* { dg-final { scan-assembler "test_vec_unpacku_hi_lo_v16hi:.*\txvpermi\\.q.*-test_vec_unpacku_hi_lo_v16hi" } } */ +/* { dg-final { scan-assembler "test_vec_unpacku_hi_lo_v16hi:.*\txvpermi\\.d.*-test_vec_unpacku_hi_lo_v16hi" } } */ +/* { dg-final { scan-assembler-not "test_vec_unpacku_hi_lo_v16hi:.*\txvpermi\\.q.*-test_vec_unpacku_hi_lo_v16hi" } } */ void test_vec_unpacku_hi_lo_v16hi (void) { @@ -109,7 +114,8 @@ test_vec_unpacku_hi_lo_v16hi (void) } /* { dg-final { scan-assembler "test_vec_unpacku_hi_lo_v32qi:.*\tvext2xv\\.hu\\.bu.*-test_vec_unpacku_hi_lo_v32qi" } } */ -/* { dg-final { scan-assembler "test_vec_unpacku_hi_lo_v32qi:.*\txvpermi\\.q.*-test_vec_unpacku_hi_lo_v32qi" } } */ +/* { dg-final { scan-assembler "test_vec_unpacku_hi_lo_v32qi:.*\txvpermi\\.d.*-test_vec_unpacku_hi_lo_v32qi" } } */ +/* { dg-final { scan-assembler-not "test_vec_unpacku_hi_lo_v32qi:.*\txvpermi\\.q.*-test_vec_unpacku_hi_lo_v32qi" } } */ void test_vec_unpacku_hi_lo_v32qi (void) { diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c index 64ff870..3f34a43 100644 --- a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c @@ -3301,7 +3301,7 @@ __lasx_vext2xv_du_bu (v32i8 _1) v32i8 __lasx_xvpermi_q (v32i8 _1, v32i8 _2) { - return __builtin_lasx_xvpermi_q (_1, _2, 1); + return __builtin_lasx_xvpermi_q (_1, _2, 0x20); } v4i64 __lasx_xvpermi_d (v4i64 _1) diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-concat-128-256-result.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-concat-128-256-result.c new file mode 100644 index 0000000..e876c4a --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-concat-128-256-result.c @@ -0,0 +1,68 @@ +/* { dg-options "-mabi=lp64d -O2 -mlasx -w -fno-strict-aliasing" } */ + +#include "../simd_correctness_check.h" +#include <lasxintrin.h> + +int +main () +{ + __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; + __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; + __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; + + __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; + __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; + __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; + + //__m128_op0={1,2,3,4},__m128_op1={5,6,7,8}; + *((int *)&__m128_op0[3]) = 0x40800000; + *((int *)&__m128_op0[2]) = 0x40400000; + *((int *)&__m128_op0[1]) = 0x40000000; + *((int *)&__m128_op0[0]) = 0x3f800000; + *((int *)&__m128_op1[3]) = 0x41000000; + *((int *)&__m128_op1[2]) = 0x40e00000; + *((int *)&__m128_op1[1]) = 0x40c00000; + *((int *)&__m128_op1[0]) = 0x40a00000; + *((int *)&__m256_result[7]) = 0x41000000; + *((int *)&__m256_result[6]) = 0x40e00000; + *((int *)&__m256_result[5]) = 0x40c00000; + *((int *)&__m256_result[4]) = 0x40a00000; + *((int *)&__m256_result[3]) = 0x40800000; + *((int *)&__m256_result[2]) = 0x40400000; + *((int *)&__m256_result[1]) = 0x40000000; + *((int *)&__m256_result[0]) = 0x3f800000; + __m256_out = __lasx_concat_128_s (__m128_op0, __m128_op1); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); + __m256_out = __lasx_cast_128_s (__m128_op0); + ASSERTEQ_32 (__LINE__, __m256_out, __m128_op0); + + //__m128i_op0={1,2},__m128i_op1={3,4}; + *((unsigned long *)&__m128i_op0[1]) = 0x2; + *((unsigned long *)&__m128i_op0[0]) = 0x1; + *((unsigned long *)&__m128i_op1[1]) = 0x4; + *((unsigned long *)&__m128i_op1[0]) = 0x3; + *((unsigned long *)&__m256i_result[3]) = 0x4; + *((unsigned long *)&__m256i_result[2]) = 0x3; + *((unsigned long *)&__m256i_result[1]) = 0x2; + *((unsigned long *)&__m256i_result[0]) = 0x1; + __m256i_out = __lasx_concat_128 (__m128i_op0, __m128i_op1); + ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); + __m256i_out = __lasx_cast_128 (__m128i_op0); + ASSERTEQ_64 (__LINE__, __m256i_out, __m128i_op0); + + //__m128d_op0={1,2},__m128i_op1={3,4}; + *((unsigned long *)&__m128d_op0[1]) = 0x4000000000000000; + *((unsigned long *)&__m128d_op0[0]) = 0x3ff0000000000000; + *((unsigned long *)&__m128d_op1[1]) = 0x4010000000000000; + *((unsigned long *)&__m128d_op1[0]) = 0x4008000000000000; + *((unsigned long *)&__m256d_result[3]) = 0x4010000000000000; + *((unsigned long *)&__m256d_result[2]) = 0x4008000000000000; + *((unsigned long *)&__m256d_result[1]) = 0x4000000000000000; + *((unsigned long *)&__m256d_result[0]) = 0x3ff0000000000000; + __m256d_out = __lasx_concat_128_d (__m128d_op0, __m128d_op1); + ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); + __m256d_out = __lasx_cast_128_d (__m128d_op0); + ASSERTEQ_64 (__LINE__, __m256d_out, __m128d_op0); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-concat-128-256.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-concat-128-256.c new file mode 100644 index 0000000..5d8cbb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-concat-128-256.c @@ -0,0 +1,92 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-mabi=lp64d -O2 -mlasx" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <lasxintrin.h> + +/* +**foo1: +** vinsgr2vr.d (\$vr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r6,1 +** vinsgr2vr.d (\$vr[0-9]+),\$r8,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x02 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256 +foo1 (__m128 x, __m128 y) +{ + return __builtin_lasx_concat_128_s (x, y); +} + +/* +**foo2: +** vinsgr2vr.d (\$vr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r6,1 +** vinsgr2vr.d (\$vr[0-9]+),\$r8,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x02 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256d +foo2 (__m128d x, __m128d y) +{ + return __builtin_lasx_concat_128_d (x, y); +} + +/* +**foo3: +** vinsgr2vr.d (\$vr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r6,1 +** vinsgr2vr.d (\$vr[0-9]+),\$r8,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x02 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256i +foo3 (__m128i x, __m128i y) +{ + return __builtin_lasx_concat_128 (x, y); +} + +/* +**foo4: +** vinsgr2vr.d (\$vr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r6,1 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256 +foo4 (__m128 x) +{ + return __builtin_lasx_cast_128_s (x); +} + +/* +**foo5: +** vinsgr2vr.d (\$vr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r6,1 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256d +foo5 (__m128d x) +{ + return __builtin_lasx_cast_128_d (x); +} + +/* +**foo6: +** vinsgr2vr.d (\$vr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r6,1 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256i +foo6 (__m128i x) +{ + return __builtin_lasx_cast_128 (x); +} diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-extract-256-128-result.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-extract-256-128-result.c new file mode 100644 index 0000000..61064d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-extract-256-128-result.c @@ -0,0 +1,69 @@ +/* { dg-options "-mabi=lp64d -O2 -mlasx -w -fno-strict-aliasing" } */ + +#include "../simd_correctness_check.h" +#include <lasxintrin.h> + +extern void abort (void); +int +main () +{ + __m128i __m128i_result0, __m128i_result1, __m128i_out, __m128i_result; + __m128 __m128_result0, __m128_result1, __m128_out, __m128_result; + __m128d __m128d_result0, __m128d_result1, __m128d_out, __m128d_result; + + __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; + __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; + __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; + + //__m256_op0 = {1,2,3,4,5,6,7,8}; + *((int *)&__m256_op0[7]) = 0x41000000; + *((int *)&__m256_op0[6]) = 0x40e00000; + *((int *)&__m256_op0[5]) = 0x40c00000; + *((int *)&__m256_op0[4]) = 0x40a00000; + *((int *)&__m256_op0[3]) = 0x40800000; + *((int *)&__m256_op0[2]) = 0x40400000; + *((int *)&__m256_op0[1]) = 0x40000000; + *((int *)&__m256_op0[0]) = 0x3f800000; + *((int *)&__m128_result1[3]) = 0x41000000; + *((int *)&__m128_result1[2]) = 0x40e00000; + *((int *)&__m128_result1[1]) = 0x40c00000; + *((int *)&__m128_result1[0]) = 0x40a00000; + *((int *)&__m128_result0[3]) = 0x40800000; + *((int *)&__m128_result0[2]) = 0x40400000; + *((int *)&__m128_result0[1]) = 0x40000000; + *((int *)&__m128_result0[0]) = 0x3f800000; + __m128_out = __lasx_extract_128_lo_s (__m256_op0); + ASSERTEQ_32 (__LINE__, __m128_result0, __m128_out); + __m128_out = __lasx_extract_128_hi_s (__m256_op0); + ASSERTEQ_32 (__LINE__, __m128_result1, __m128_out); + + //__m256i_op0 = {1,2,3,4}; + *((unsigned long *)&__m256i_op0[3]) = 0x4; + *((unsigned long *)&__m256i_op0[2]) = 0x3; + *((unsigned long *)&__m256i_op0[1]) = 0x2; + *((unsigned long *)&__m256i_op0[0]) = 0x1; + *((unsigned long *)&__m128i_result0[1]) = 0x2; + *((unsigned long *)&__m128i_result0[0]) = 0x1; + *((unsigned long *)&__m128i_result1[1]) = 0x4; + *((unsigned long *)&__m128i_result1[0]) = 0x3; + __m128i_out = __lasx_extract_128_lo (__m256i_op0); + ASSERTEQ_64 (__LINE__, __m128i_result0, __m128i_out); + __m128i_out = __lasx_extract_128_hi (__m256i_op0); + ASSERTEQ_64 (__LINE__, __m128i_result1, __m128i_out); + + //__m256d_op0 = {1,2,3,4}; + *((unsigned long *)&__m256d_op0[3]) = 0x4010000000000000; + *((unsigned long *)&__m256d_op0[2]) = 0x4008000000000000; + *((unsigned long *)&__m256d_op0[1]) = 0x4000000000000000; + *((unsigned long *)&__m256d_op0[0]) = 0x3ff0000000000000; + *((unsigned long *)&__m128d_result0[1]) = 0x4000000000000000; + *((unsigned long *)&__m128d_result0[0]) = 0x3ff0000000000000; + *((unsigned long *)&__m128d_result1[1]) = 0x4010000000000000; + *((unsigned long *)&__m128d_result1[0]) = 0x4008000000000000; + __m128d_out = __lasx_extract_128_lo_d (__m256d_op0); + ASSERTEQ_64 (__LINE__, __m128d_result0, __m128d_out); + __m128d_out = __lasx_extract_128_hi_d (__m256d_op0); + ASSERTEQ_64 (__LINE__, __m128d_result1, __m128d_out); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-extract-256-128.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-extract-256-128.c new file mode 100644 index 0000000..d2219ea --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-extract-256-128.c @@ -0,0 +1,86 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-mabi=lp64d -O2 -mlasx" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <lasxintrin.h> + +/* +**foo1_lo: +** vld (\$vr[0-9]+),\$r4,0 +** vpickve2gr.du \$r4,(\$vr[0-9]+),0 +** vpickve2gr.du \$r5,(\$vr[0-9]+),1 +** jr \$r1 +*/ +__m128 +foo1_lo (__m256 x) +{ + return __lasx_extract_128_lo_s (x); +} + +/* +**foo1_hi: +** xvld (\$xr[0-9]+),\$r4,0 +** xvpermi.d (\$xr[0-9]+),(\$xr[0-9]+),0xe +** vpickve2gr.du \$r4,(\$vr[0-9]+),0 +** vpickve2gr.du \$r5,(\$vr[0-9]+),1 +** jr \$r1 +*/ +__m128 +foo1_hi (__m256 x) +{ + return __lasx_extract_128_hi_s (x); +} + +/* +**foo2_lo: +** vld (\$vr[0-9]+),\$r4,0 +** vpickve2gr.du \$r4,(\$vr[0-9]+),0 +** vpickve2gr.du \$r5,(\$vr[0-9]+),1 +** jr \$r1 +*/ +__m128d +foo2_lo (__m256d x) +{ + return __lasx_extract_128_lo_d (x); +} + +/* +**foo2_hi: +** xvld (\$xr[0-9]+),\$r4,0 +** xvpermi.d (\$xr[0-9]+),(\$xr[0-9]+),0xe +** vpickve2gr.du \$r4,(\$vr[0-9]+),0 +** vpickve2gr.du \$r5,(\$vr[0-9]+),1 +** jr \$r1 +*/ +__m128d +foo2_hi (__m256d x) +{ + return __lasx_extract_128_hi_d (x); +} + +/* +**foo3_lo: +** vld (\$vr[0-9]+),\$r4,0 +** vpickve2gr.du \$r4,(\$vr[0-9]+),0 +** vpickve2gr.du \$r5,(\$vr[0-9]+),1 +** jr \$r1 +*/ +__m128i +foo3_lo (__m256i x) +{ + return __lasx_extract_128_lo (x); +} + +/* +**foo3_hi: +** xvld (\$xr[0-9]+),\$r4,0 +** xvpermi.d (\$xr[0-9]+),(\$xr[0-9]+),0xe +** vpickve2gr.du \$r4,(\$vr[0-9]+),0 +** vpickve2gr.du \$r5,(\$vr[0-9]+),1 +** jr \$r1 +*/ +__m128i +foo3_hi (__m256i x) +{ + return __lasx_extract_128_hi (x); +} diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-insert-128-256-result.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-insert-128-256-result.c new file mode 100644 index 0000000..ce5abf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-insert-128-256-result.c @@ -0,0 +1,97 @@ +/* { dg-options "-mabi=lp64d -O2 -mlasx -w -fno-strict-aliasing" } */ + +#include "../simd_correctness_check.h" +#include <lasxintrin.h> + +extern void abort (void); +int +main () +{ + __m128i __m128i_op0, __m128i_op1, __m128i_out; + __m128 __m128_op0, __m128_op1, __m128_out; + __m128d __m128d_op0, __m128d_op1, __m128d_out; + + __m256i __m256i_op0, __m256i_result0, __m256i_result1, __m256i_out; + __m256 __m256_op0, __m256_result0, __m256_result1, __m256_out; + __m256d __m256d_op0, __m256d_result0, __m256d_result1, __m256d_out; + + //__m256_op0 = {1,2,3,4,5,6,7,8}, __m128_op0 ={9,9,9,9}; + *((int *)&__m256_op0[7]) = 0x41000000; + *((int *)&__m256_op0[6]) = 0x40e00000; + *((int *)&__m256_op0[5]) = 0x40c00000; + *((int *)&__m256_op0[4]) = 0x40a00000; + *((int *)&__m256_op0[3]) = 0x40800000; + *((int *)&__m256_op0[2]) = 0x40400000; + *((int *)&__m256_op0[1]) = 0x40000000; + *((int *)&__m256_op0[0]) = 0x3f800000; + *((int *)&__m128_op0[3]) = 0x41100000; + *((int *)&__m128_op0[2]) = 0x41100000; + *((int *)&__m128_op0[1]) = 0x41100000; + *((int *)&__m128_op0[0]) = 0x41100000; + *((int *)&__m256_result0[7]) = 0x41000000; + *((int *)&__m256_result0[6]) = 0x40e00000; + *((int *)&__m256_result0[5]) = 0x40c00000; + *((int *)&__m256_result0[4]) = 0x40a00000; + *((int *)&__m256_result0[3]) = 0x41100000; + *((int *)&__m256_result0[2]) = 0x41100000; + *((int *)&__m256_result0[1]) = 0x41100000; + *((int *)&__m256_result0[0]) = 0x41100000; + *((int *)&__m256_result1[7]) = 0x41100000; + *((int *)&__m256_result1[6]) = 0x41100000; + *((int *)&__m256_result1[5]) = 0x41100000; + *((int *)&__m256_result1[4]) = 0x41100000; + *((int *)&__m256_result1[3]) = 0x40800000; + *((int *)&__m256_result1[2]) = 0x40400000; + *((int *)&__m256_result1[1]) = 0x40000000; + *((int *)&__m256_result1[0]) = 0x3f800000; + __m256_out = __lasx_insert_128_lo_s (__m256_op0, __m128_op0); + ASSERTEQ_32 (__LINE__, __m256_result0, __m256_out); + __m256_out = __lasx_insert_128_hi_s (__m256_op0, __m128_op0); + ASSERTEQ_32 (__LINE__, __m256_result1, __m256_out); + + //__m256i_op0 ={1,2,3,4},__m128i_op0={5,6},__m128i_op1={7,8}; + *((unsigned long *)&__m256i_op0[3]) = 0x4; + *((unsigned long *)&__m256i_op0[2]) = 0x3; + *((unsigned long *)&__m256i_op0[1]) = 0x2; + *((unsigned long *)&__m256i_op0[0]) = 0x1; + *((unsigned long *)&__m128i_op0[1]) = 0x6; + *((unsigned long *)&__m128i_op0[0]) = 0x5; + *((unsigned long *)&__m128i_op1[1]) = 0x8; + *((unsigned long *)&__m128i_op1[0]) = 0x7; + *((unsigned long *)&__m256i_result0[3]) = 0x4; + *((unsigned long *)&__m256i_result0[2]) = 0x3; + *((unsigned long *)&__m256i_result0[1]) = 0x6; + *((unsigned long *)&__m256i_result0[0]) = 0x5; + *((unsigned long *)&__m256i_result1[3]) = 0x8; + *((unsigned long *)&__m256i_result1[2]) = 0x7; + *((unsigned long *)&__m256i_result1[1]) = 0x2; + *((unsigned long *)&__m256i_result1[0]) = 0x1; + __m256i_out = __lasx_insert_128_lo (__m256i_op0, __m128i_op0); + ASSERTEQ_64 (__LINE__, __m256i_result0, __m256i_out); + __m256i_out = __lasx_insert_128_hi (__m256i_op0, __m128i_op1); + ASSERTEQ_64 (__LINE__, __m256i_result1, __m256i_out); + + //__m256d_op0 ={1,2,3,4},__m128d_op0={5,6},__m128d_op1={7,8}; + *((unsigned long *)&__m256d_op0[3]) = 0x4010000000000000; + *((unsigned long *)&__m256d_op0[2]) = 0x4008000000000000; + *((unsigned long *)&__m256d_op0[1]) = 0x4000000000000000; + *((unsigned long *)&__m256d_op0[0]) = 0x3ff0000000000000; + *((unsigned long *)&__m128d_op0[1]) = 0x4018000000000000; + *((unsigned long *)&__m128d_op0[0]) = 0x4014000000000000; + *((unsigned long *)&__m128d_op1[1]) = 0x4020000000000000; + *((unsigned long *)&__m128d_op1[0]) = 0x401c000000000000; + *((unsigned long *)&__m256d_result0[3]) = 0x4010000000000000; + *((unsigned long *)&__m256d_result0[2]) = 0x4008000000000000; + *((unsigned long *)&__m256d_result0[1]) = 0x4018000000000000; + *((unsigned long *)&__m256d_result0[0]) = 0x4014000000000000; + *((unsigned long *)&__m256d_result1[3]) = 0x4020000000000000; + *((unsigned long *)&__m256d_result1[2]) = 0x401c000000000000; + *((unsigned long *)&__m256d_result1[1]) = 0x4000000000000000; + *((unsigned long *)&__m256d_result1[0]) = 0x3ff0000000000000; + __m256d_out = __lasx_insert_128_lo_d (__m256d_op0, __m128d_op0); + ASSERTEQ_64 (__LINE__, __m256d_result0, __m256d_out); + __m256d_out = __lasx_insert_128_hi_d (__m256d_op0, __m128d_op1); + ASSERTEQ_64 (__LINE__, __m256d_result1, __m256d_out); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-insert-128-256.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-insert-128-256.c new file mode 100644 index 0000000..326c855 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/vect-insert-128-256.c @@ -0,0 +1,95 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-mabi=lp64d -O2 -mlasx" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <lasxintrin.h> + +/* +**foo1: +** vinsgr2vr.d (\$vr[0-9]+),\$r6,0 +** xvld (\$xr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x30 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256 +foo1 (__m256 x, __m128 y) +{ + return __builtin_lasx_insert_128_lo_s (x, y); +} + +/* +**foo2: +** vinsgr2vr.d (\$vr[0-9]+),\$r6,0 +** xvld (\$xr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x02 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256 +foo2 (__m256 x, __m128 y) +{ + return __builtin_lasx_insert_128_hi_s (x, y); +} + +/* +**foo3: +** vinsgr2vr.d (\$vr[0-9]+),\$r6,0 +** xvld (\$xr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x30 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256d +foo3 (__m256d x, __m128d y) +{ + return __builtin_lasx_insert_128_lo_d (x, y); +} + +/* +**foo4: +** vinsgr2vr.d (\$vr[0-9]+),\$r6,0 +** xvld (\$xr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x02 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256d +foo4 (__m256d x, __m128d y) +{ + return __builtin_lasx_insert_128_hi_d (x, y); +} + +/* +**foo5: +** vinsgr2vr.d (\$vr[0-9]+),\$r6,0 +** xvld (\$xr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x30 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256i +foo5 (__m256i x, __m128i y) +{ + return __builtin_lasx_insert_128_lo (x, y); +} + +/* +**foo6: +** vinsgr2vr.d (\$vr[0-9]+),\$r6,0 +** xvld (\$xr[0-9]+),\$r5,0 +** vinsgr2vr.d (\$vr[0-9]+),\$r7,1 +** xvpermi.q (\$xr[0-9]+),(\$xr[0-9]+),0x02 +** xvst (\$xr[0-9]+),\$r4,0 +** jr \$r1 +*/ +__m256i +foo6 (__m256i x, __m128i y) +{ + return __builtin_lasx_insert_128_hi (x, y); +} diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct+union-1.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct+union-1.c new file mode 100644 index 0000000..4cea38e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct+union-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Su2e_1f { + union { + struct { + } e1, e2; + } u; + float f; +}; +struct Su2e_1f echo_Su2e_1f(int i, float f, struct Su2e_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct+union-2.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct+union-2.c new file mode 100644 index 0000000..e7271e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct+union-2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Su2e_2f { + union { + struct { + } e1, e2; + } u; + float f; + float g; +}; +struct Su2e_2f echo_Su2e_2f(int i, float f, struct Su2e_2f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct+union-3.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct+union-3.c new file mode 100644 index 0000000..9743d4a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct+union-3.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Smu2e_1f { + union { + struct { + } e1, e2; + } u1; + struct { + float f; + union { + struct { + } e1, e2; + } u; + } ue; + union { + struct { + } e1, e2; + } u2; +}; +struct Smu2e_1f echo_Smu2e_1f(int i, float f, struct Smu2e_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct+union-4.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct+union-4.c new file mode 100644 index 0000000..081ea68 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct+union-4.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Smu2e_2f { + union { + struct { + } e1, e2; + } u1; + struct { + float f; + float g; + union { + struct { + } e1, e2; + } u; + } ue; + union { + struct { + } e1, e2; + } u2; +}; +struct Smu2e_2f echo_Smu2e_2f(int i, float f, struct Smu2e_2f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct-1.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-1.c new file mode 100644 index 0000000..a0a4866 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Se_1f { + struct { + } e1; + float f; +}; +struct Se_1f echo_Se_1f(int i, float f, struct Se_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct-10.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-10.c new file mode 100644 index 0000000..de8ad02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-10.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct S1ae_2f { + struct { + } e1[1]; + float f; + float g; +}; +struct S1ae_2f echo_S1ae_2f(int i, float f, struct S1ae_2f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct-11.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-11.c new file mode 100644 index 0000000..c99bb22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-11.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Sm1ae_1f { + struct { + } e1[1]; + struct { + float f; + struct { + } e[1]; + } fe; + struct { + } e2[1]; +}; +struct Sm1ae_1f echo_Sm1ae_1f(int i, float f, struct Sm1ae_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct-12.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-12.c new file mode 100644 index 0000000..065ff02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-12.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Sm1ae_2f { + struct { + } e1[1]; + struct { + float f; + float g; + struct { + } e[1]; + } fe; + struct { + } e2[1]; +}; +struct Sm1ae_2f echo_Sm1ae_2f(int i, float f, struct Sm1ae_2f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct-2.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-2.c new file mode 100644 index 0000000..93210fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Se_2f { + struct { + } e1; + float f; + float g; +}; +struct Se_2f echo_Se_2f(int i, float f, struct Se_2f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct-3.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-3.c new file mode 100644 index 0000000..b8c3362 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Sme_1f { + struct { + } e1; + struct { + float f; + struct { + } e; + } fe; + struct { + } e2; +}; +struct Sme_1f echo_Sme_1f(int i, float f, struct Sme_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct-4.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-4.c new file mode 100644 index 0000000..0ce36d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-4.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Sme_2f { + struct { + } e1; + struct { + float f; + float g; + struct { + } e; + } fe; + struct { + } e2; +}; +struct Sme_2f echo_Sme_2f(int i, float f, struct Sme_2f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct-5.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-5.c new file mode 100644 index 0000000..0ae1e41 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-5.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct S0ae_1f { + struct { + } e1[0]; + float f; +}; +struct S0ae_1f echo_S0ae_1f(int i, float f, struct S0ae_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct-6.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-6.c new file mode 100644 index 0000000..d3d0b65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-6.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct S0ae_2f { + struct { + } e1[0]; + float f; + float g; +}; +struct S0ae_2f echo_S0ae_2f(int i, float f, struct S0ae_2f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct-7.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-7.c new file mode 100644 index 0000000..9eae13d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-7.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Sm0ae_1f { + struct { + } e1[0]; + struct { + float f; + struct { + } e[0]; + } fe; + struct { + } e2[0]; +}; +struct Sm0ae_1f echo_Sm0ae_1f(int i, float f, struct Sm0ae_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct-8.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-8.c new file mode 100644 index 0000000..e7c81f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Sm0ae_2f { + struct { + } e1[0]; + struct { + float f; + float g; + struct { + } e[0]; + } fe; + struct { + } e2[0]; +}; +struct Sm0ae_2f echo_Sm0ae_2f(int i, float f, struct Sm0ae_2f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-struct-9.c b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-9.c new file mode 100644 index 0000000..55c4be4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-struct-9.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct S1ae_1f { + struct { + } e1[1]; + float f; +}; +struct S1ae_1f echo_S1ae_1f(int i, float f, struct S1ae_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-union-1.c b/gcc/testsuite/gcc.target/riscv/abi/empty-union-1.c new file mode 100644 index 0000000..17beb0d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-union-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Seu_1f { + union { + } e1; + float f; +}; +struct Seu_1f echo_Seu_1f(int i, float f, struct Seu_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-union-2.c b/gcc/testsuite/gcc.target/riscv/abi/empty-union-2.c new file mode 100644 index 0000000..c583186 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-union-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct S2eu_2f { + union { + } e1; + float f; + float g; +}; +struct S2eu_2f echo_S2eu_2f(int i, float f, struct S2eu_2f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-union-3.c b/gcc/testsuite/gcc.target/riscv/abi/empty-union-3.c new file mode 100644 index 0000000..e9e189b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-union-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Smeu_1f { + union { + } e1; + struct { + float f; + union { + } e; + } fe; + union { + } e2; +}; +struct Smeu_1f echo_Smeu_1f(int i, float f, struct Smeu_1f s) { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/abi/empty-union-4.c b/gcc/testsuite/gcc.target/riscv/abi/empty-union-4.c new file mode 100644 index 0000000..91c2d89 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/abi/empty-union-4.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct Smeu_2f { + union { + } e1; + struct { + float f; + float g; + union { + } e; + } fe; + union { + } e2; +}; +struct Smeu_2f echo_Smeu_2f(int i, float f, struct Smeu_2f s) /* { dg-warning "ABI for flattened empty union and zero length array changed in GCC 16" } */ { + return s; +} + +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa1 \[ s \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ .*\)[[:space:]]+\(reg.*:SF \d+ fa2 \[ s\+4 \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa0\)[[:space:]]+\(reg.*:SF \d+ \[ <retval> \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SF \d+ fa1\)[[:space:]]+\(reg.*:SF \d+ \[ <retval>\+4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr52345.c b/gcc/testsuite/gcc.target/riscv/pr52345.c new file mode 100644 index 0000000..90feb91 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr52345.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gcbv_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-O2 -march=rv32gcbv_zicond -mabi=ilp32" { target { rv32 } } } */ + +int f(int a, int b) +{ + int c = a != 0; + int d = (c!=0|b!=0); + return d; +} + +int h (int a, int b) +{ + int c = (a!=0|b); + int d = c==0; + return d; +} + +/* { dg-final { scan-assembler-times {\tor} 2 } } */ +/* { dg-final { scan-assembler-times {\tsnez} 1 } } */ +/* { dg-final { scan-assembler-times {\tseqz} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr67731.c b/gcc/testsuite/gcc.target/riscv/pr67731.c new file mode 100644 index 0000000..6f254fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr67731.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gcbv -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-O2 -march=rv32gcbv -mabi=ilp32" { target { rv32 } } } */ + +typedef struct +{ + _Bool a : 1; + _Bool b : 1; + _Bool c : 1; + _Bool d : 1; + unsigned int e : 4; +} S; + +_Bool test_00 (S* s) +{ + return s->b | s->c; +} + +_Bool test_01 (S* s) +{ + return s->b | s->c | s->d; +} +/* { dg-final { scan-assembler-times {\tlw\ta0,0\(a0\).*?\n\tandi\ta0,a0,\d+.*?\n\tsnez\ta0,a0.*?\n\tret} 2 } } */ +/* { dg-final { scan-assembler-not {\tor} } } */ +/* { dg-final { scan-assembler-not {\tbexti} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/riscv.exp b/gcc/testsuite/gcc.target/riscv/riscv.exp index b5e7618..dd8443d 100644 --- a/gcc/testsuite/gcc.target/riscv/riscv.exp +++ b/gcc/testsuite/gcc.target/riscv/riscv.exp @@ -42,6 +42,8 @@ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/sched1-spills/*.{\[cS\], "" $DEFAULT_CFLAGS gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xandes/*.\[cS\]]] \ "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS # Saturation alu foreach opt { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c new file mode 100644 index 0000000..0e34bc1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c @@ -0,0 +1,150 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -w -O0" { target rv64 } } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -w -O0" { target rv32 } } */ + + +typedef int a; +typedef signed char b; +typedef char c; +typedef short d; +typedef unsigned short e; +typedef a f; +typedef unsigned g; +typedef long h; +h j, k, l, m, n, o; +int p, q, r, s; +short t; +volatile a u; +a v[]; +char w, x; +a *y, *z; +a **aa; +__attribute__((always_inline)) b __attribute__((vector_size(16))) +ab(f __attribute__((vector_size(8 * sizeof(f)))), d ac, + d __attribute__((vector_size(2 * sizeof(d)))), d) { + return __builtin_shufflevector( + (b __attribute__((vector_size(16)))) __builtin_convertvector( + (d __attribute__((vector_size(16 *sizeof(d))))){ + ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac}, + c __attribute__((vector_size(16)))) | + __builtin_convertvector( + (d __attribute__((vector_size(16 *sizeof(d))))){ + ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac}, + c __attribute__((vector_size(16)))), + __builtin_convertvector( + (d __attribute__((vector_size(16 *sizeof(d))))){ + ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac}, + b __attribute__((vector_size(16)))), + 3, 21, 0, 2, 2, 7, 1, 8, 4, 0, 8, 0, 8, 9, 5, 6); +} +__attribute__((always_inline)) g +ad(d ae, h __attribute__((vector_size(32 * sizeof(h))))) { + g f = 6318; + return (8 ? ae / 786856318u : 0) & ae; +} +a(af)(a, int); +void(ag)(long); +char(ah)(char, char); +char(ai)(char); +short(aj)(short, short); +int ak(long, int *, int *, char, int); +void al(signed, a *, int *, long); +char am(int *, short, short); +void an(int *, long, int); +void ao(int, int *, a *); +a ap() { + int *aq, *ar, *as; + short at; + char au, av, aw = 2; + long ax, ay, az = j; + int ba, i; + g __attribute__((vector_size(16 * sizeof(g)))) bb = {80}; + b __attribute__((vector_size(4))) bc = {6}; + int bd[1]; + char *be = &w; + int bf, bg = q; + a **bh[] = { + &y, &z, &z, &y, &y, &y, &y, &y, &z, &z, &y, &z, &y, &y, &y, &y, &z, &y, + &z, &y, &y, &y, &z, &z, &z, &y, &z, &z, &z, &y, &z, &z, &y, &z, &z, &y, + &z, &z, &z, &y, 0, &z, 0, &y, 0, &y, &y, &z, &z, &y, &y, 0, &z, 0, + &z, 0, &y, &z, &z, 0, &z, 0, &z, &z, &z, &y, &z, &z, &y, &z, &z, &y, + 0, &z, 0, &z, &z, &y, 0, &z, 0, &y, 0, &y, &y, &z, &z, &y, &y, 0, + &z, 0, &z, 0, &y, &z, &z, 0, &z, 0, &z, &z, &z, &y, &z, &z, &y, &z, + &z, &y, 0, &z, 0, &z, &z, &y, 0, &z, 0, &y, 0, &y, &y, &z, &z, &y, + &y, 0, &z, 0, &z, 0, &y, &z, &z, 0, &z, 0, &z, &z, &z, &y, &z, &z, + &y, &z, &z, &y, 0, &z, 0, &z, &z, &y, 0, &z, 0, &y, 0, &y, &y, &z, + &z, &y, &y, 0, &z, 0, &z, 0, &y, &z, &z, 0, 0, &z, 0, &z, &z, &z, + &y, &z, &z, &y, &z, &z, &y, 0, &z, 0, 0, &z, &z}; + for (; i; i++) + bd[i] = p; + h __attribute__((vector_size(32 * sizeof(h)))) + bi = {2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, + 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, + 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681}, + bj = __builtin_convertvector( + (c __attribute__((vector_size(32)))){ + aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, + aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw}, + h __attribute__((vector_size(32 * sizeof(h))))), + bk = __builtin_convertvector( + __builtin_shufflevector(bb, bb, 4, 8, 7, 9, 1, 10, 4, 7, 0, 4, 3, 5, 6, 7, + 6, 2, 2, 20, 6, 4, 7, 7, 9, 7, 4, 9, 8, 6, 1, 0, + 6, 9), + h __attribute__((vector_size(32 * sizeof(h))))); + bb = __builtin_convertvector( + ab(__builtin_shufflevector( + __builtin_shufflevector( + __builtin_convertvector( + __builtin_shufflevector(bb, bb, 1, 31, 8, 2, 3, 7, 4, 0, 7, + 3, 4, 6, 7, 1, 9, 3, 8, 7, 1, 8, 5, + 3, 9, 9, 0, 3, 2, 8, 5, 2, 5, 3), + f __attribute__((vector_size(32 * sizeof(f))))), + (f __attribute__((vector_size(32 * sizeof(f))))){ + 800761418310502961587690471176286910032020044212442466872080013589354162852207417903424527024812447907811618435019152886919380169872910001752451018659493155196043018716516518746289614523948734758456011127254301274351182132760058399143431214610613191313926994549901191890929084305862034120561651877003645}, + 32, 44), + (f __attribute__((vector_size(2 * sizeof(f))))){o}, 1, 0, 3, 0, 2, + 1, 3, 3), + ad(__builtin_clzg((g)aw, (f)bb[9]), + (h __attribute__((vector_size(32 * sizeof(h))))){ + bi[0] ?: bk[0], bi[1] ? 1 : bk[1], bi[2] ? 2 : bk[2], + bi[3] ? 3 : bk[3], bi[4] ? 4 : bk[4], bi[5] ? 5 : bk[5], + bi[6] ? 6 : bk[6], bi[7] ? 7 : bk[7], bi[8] ? 8 : bk[8], + bi[9] ? 9 : bk[9], bi[0] ? 10 : bk[0], bi[1] ? 1 : bk[1], + bi[2] ? 2 : bk[2], bi[3] ? 3 : bk[3], bi[4] ? 4 : bk[4], + bi[5] ? 5 : bk[5], bi[6] ? 6 : bk[6], bi[7] ? 7 : bk[7], + bi[8] ? 8 : bk[8], bi[9] ? 9 : bk[9], bi[0] ? 20 : bk[0], + bi[1] ? 1 : bk[1], bi[2] ? 2 : bk[2], bi[3] ? 3 : bk[3], + bi[4] ? bj[4] : 4, bi[5] ?: 5, bi[6] ?: 6, + bi[7] ? 0 : 7, bi[8] ?: 8, bi[9] ? 0 : 9, + bi[0] ? 0 : 30, bi[1] ?: 1}), + (d __attribute__((vector_size(2 * sizeof(d))))) + __builtin_shufflevector( + __builtin_convertvector( + __builtin_shufflevector(bb, bb, 2, 7, 21, 6), + e __attribute__((vector_size(4 * sizeof(e))))), + __builtin_convertvector( + (c __attribute__((vector_size(4)))){aw, aw}, + e __attribute__((vector_size(4 * sizeof(e))))), + 5, 1) + + (__builtin_convertvector( + __builtin_shufflevector(bb, bb, 4, 5), + e __attribute__((vector_size(2 * sizeof(e))))) <= + __builtin_convertvector( + (c __attribute__((vector_size(2)))){aw}, + e __attribute__((vector_size(2 * sizeof(e)))))), + n ? bb[5] << n : aw), + g __attribute__((vector_size(16 * sizeof(g))))); + ag(aw & t); + at = aj(aw, v[1]); + au = ah(at, aw); + ba = af((1 == ax != aw) <= aw <= au, aw); + ao(0, &bd[0], &r); + o = ay; + an(aq, aw, k); + av = am(ar, l, k); + *be = ai(*be); + al(x, as, &bd[0], aw); + bg = ak(u, &s, &bf, aw, aw); + as = *aa; + return m; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122445.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122445.c new file mode 100644 index 0000000..4736868 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122445.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcbv_zvl256b -mabi=lp64d -O3 -mrvv-vector-bits=zvl --param=riscv-autovec-mode=V4QI -mtune=generic-ooo -fdump-rtl-avlprop-all" } */ + +typedef unsigned char uint8_t; +typedef short int16_t; + +#define FDEC_STRIDE 32 + +static inline uint8_t x264_clip_uint8( int x ) +{ + return x; +} + +void +x264_add4x4_idct (uint8_t *p_dst, int16_t d[16]) +{ + for( int y = 0; y < 4; y++ ) + { + for( int x = 0; x < 4; x++ ) + p_dst[x] = x264_clip_uint8( p_dst[x] + d[y*4+x] ); + p_dst += FDEC_STRIDE; + } +} + +/* { dg-final { scan-rtl-dump "Propagating AVL: \\(const_int 4" "avlprop" } } */ +/* { dg-final { scan-rtl-dump-not "Propagating AVL: \\(const_int 1" "avlprop" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr119115.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr119115.c index ac8a70e..524201c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr119115.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr119115.c @@ -1,7 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target rv64 } */ /* { dg-require-effective-target rvv_zvl256b_ok } */ -/* { dg-additional-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fsigned-char -fwrapv -mrvv-vector-bits=zvl" } */ +/* { dg-additional-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fsigned-char -fwrapv -mrvv-vector-bits=zvl -std=gnu99" } */ short a[4][14][14]; void diff --git a/gcc/testsuite/gcc.target/sh/pr67731.c b/gcc/testsuite/gcc.target/sh/pr67731.c new file mode 100644 index 0000000..43c1657 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr67731.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -m4 -ml" } */ + +typedef struct +{ + _Bool a : 1; + _Bool b : 1; + _Bool c : 1; + _Bool d : 1; + unsigned int e : 4; +} S; + +_Bool test_00 (S* s) +{ + return s->b | s->c; +} + +_Bool test_01 (S* s) +{ + return s->b | s->c | s->d; +} + +/* { dg-final { scan-assembler-times {\ttst} 2 } } */ +/* { dg-final { scan-assembler-times {\tnegc} 2 } } */ +/* { dg-final { scan-assembler-not {\tor} } } */ diff --git a/gcc/testsuite/gcc.target/sparc/cbcond-1.c b/gcc/testsuite/gcc.target/sparc/cbcond-1.c index 74fe475..742ab1d 100644 --- a/gcc/testsuite/gcc.target/sparc/cbcond-1.c +++ b/gcc/testsuite/gcc.target/sparc/cbcond-1.c @@ -34,5 +34,5 @@ void cbcondle (int a) /* { dg-final { scan-assembler "cwbe\t%" { target ilp32 } } } */ /* { dg-final { scan-assembler "cwbne\t%" { target ilp32 } } } */ -/* { dg-final { scan-assembler "cwbl\t%" } } */ -/* { dg-final { scan-assembler "cwble\t%" } } */ +/* { dg-final { scan-assembler "cwbl|cwbge\t%" } } */ +/* { dg-final { scan-assembler "cwble|cwbg\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/cbcond-2.c b/gcc/testsuite/gcc.target/sparc/cbcond-2.c index da6c617..c55f9e9 100644 --- a/gcc/testsuite/gcc.target/sparc/cbcond-2.c +++ b/gcc/testsuite/gcc.target/sparc/cbcond-2.c @@ -35,5 +35,5 @@ void cbcondle (long a) /* { dg-final { scan-assembler "cxbe\t%" } } */ /* { dg-final { scan-assembler "cxbne\t%" } } */ -/* { dg-final { scan-assembler "cxbl\t%" } } */ -/* { dg-final { scan-assembler "cxble\t%" } } */ +/* { dg-final { scan-assembler "cxbl|cxbge\t%" } } */ +/* { dg-final { scan-assembler "cxble|cxbg\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/overflow-3.c b/gcc/testsuite/gcc.target/sparc/overflow-3.c index 52d6ab2..ce52de0 100644 --- a/gcc/testsuite/gcc.target/sparc/overflow-3.c +++ b/gcc/testsuite/gcc.target/sparc/overflow-3.c @@ -38,6 +38,6 @@ bool my_neg_overflow (int32_t a, int32_t *res) /* { dg-final { scan-assembler-times "addcc\t%" 2 } } */ /* { dg-final { scan-assembler-times "subcc\t%" 4 } } */ /* { dg-final { scan-assembler-times "addx\t%" 3 } } */ -/* { dg-final { scan-assembler-times "bvs" 3 } } */ +/* { dg-final { scan-assembler-times "bvs|bvc" 3 } } */ /* { dg-final { scan-assembler-not "cmp\t%" } } */ /* { dg-final { scan-assembler-not "save\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/overflow-4.c b/gcc/testsuite/gcc.target/sparc/overflow-4.c index c6121b9..2b62edf 100644 --- a/gcc/testsuite/gcc.target/sparc/overflow-4.c +++ b/gcc/testsuite/gcc.target/sparc/overflow-4.c @@ -38,7 +38,7 @@ bool my_neg_overflow (int64_t a, int64_t *res) /* { dg-final { scan-assembler-times "addcc\t%" 2 } } */ /* { dg-final { scan-assembler-times "subcc\t%" 4 } } */ /* { dg-final { scan-assembler-times "movlu\t%" 1 } } */ -/* { dg-final { scan-assembler-times "blu" 2 } } */ -/* { dg-final { scan-assembler-times "bvs" 3 } } */ +/* { dg-final { scan-assembler-times "blu|bgeu" 2 } } */ +/* { dg-final { scan-assembler-times "bvs|bvc" 3 } } */ /* { dg-final { scan-assembler-not "cmp\t%" } } */ /* { dg-final { scan-assembler-not "save\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/overflow-5.c b/gcc/testsuite/gcc.target/sparc/overflow-5.c index f00283f..0459a65 100644 --- a/gcc/testsuite/gcc.target/sparc/overflow-5.c +++ b/gcc/testsuite/gcc.target/sparc/overflow-5.c @@ -38,6 +38,6 @@ bool my_neg_overflow (int64_t a, int64_t *res) /* { dg-final { scan-assembler-times "addcc\t%" 2 } } */ /* { dg-final { scan-assembler-times "subcc\t%" 4 } } */ /* { dg-final { scan-assembler-times "addxc\t%" 3 } } */ -/* { dg-final { scan-assembler-times "bvs" 3 } } */ +/* { dg-final { scan-assembler-times "bvs|bvc" 3 } } */ /* { dg-final { scan-assembler-not "cmp\t%" } } */ /* { dg-final { scan-assembler-not "save\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/small-struct-1.c b/gcc/testsuite/gcc.target/sparc/small-struct-1.c index 4897288..1ceccd5 100644 --- a/gcc/testsuite/gcc.target/sparc/small-struct-1.c +++ b/gcc/testsuite/gcc.target/sparc/small-struct-1.c @@ -42,5 +42,5 @@ double get2x (struct vec2x v) return v.x + v.y; } -/* { dg-final { scan-assembler-not "ldx" } } */ -/* { dg-final { scan-assembler-not "stx" } } */ +/* { dg-final { scan-assembler-not "ldx" { target *-*-solaris* } } } */ +/* { dg-final { scan-assembler-not "stx" { target *-*-solaris* } } } */ diff --git a/gcc/testsuite/gfortran.dg/pdt_65.f03 b/gcc/testsuite/gfortran.dg/pdt_65.f03 new file mode 100644 index 0000000..d5e45c2 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pdt_65.f03 @@ -0,0 +1,135 @@ +! { dg-do compile } +! { dg-options "-fdump-tree-original" } +! +! Test fix for PR122452 +! +! Contributed by Damian Rouson <damian@archaeologic.codes> +! +module kind_parameters_m + integer, parameter :: default_real = kind(1e0) + integer, parameter :: double_precision = kind(1d0) +end module + +module tensor_m + use kind_parameters_m, only : default_real, double_precision + implicit none + + private + public :: tensor_t + + type tensor_t(k) + integer, kind :: k = default_real + real(k), allocatable, private :: values_(:) + contains + generic :: values => default_real_values, double_precision_values + procedure, private, non_overridable :: default_real_values, double_precision_values + generic :: num_components => default_real_num_components, double_precision_num_components + procedure, private :: default_real_num_components, double_precision_num_components + end type + + interface tensor_t + + pure module function construct_default_real(values) result(tensor) + implicit none + real, intent(in) :: values(:) + type(tensor_t) tensor + end function + + pure module function construct_double_precision(values) result(tensor) + implicit none + double precision, intent(in) :: values(:) + type(tensor_t(double_precision)) tensor + end function + + end interface + + interface + + pure module function default_real_values(self) result(tensor_values) + implicit none + class(tensor_t), intent(in) :: self + real, allocatable :: tensor_values(:) + end function + + pure module function double_precision_values(self) result(tensor_values) + implicit none + class(tensor_t(double_precision)), intent(in) :: self + double precision, allocatable :: tensor_values(:) + end function + + pure module function default_real_num_components(self) result(n) + implicit none + class(tensor_t), intent(in) :: self + integer n + end function + + pure module function double_precision_num_components(self) result(n) + implicit none + class(tensor_t(double_precision)), intent(in) :: self + integer n + end function + + end interface + +end module tensor_m + +submodule(tensor_m) tensor_s +contains + + pure module function construct_default_real(values) result(tensor) + implicit none + real, intent(in) :: values(:) + type(tensor_t) tensor + tensor = tensor_t ()(values) + end function + + pure module function construct_double_precision(values) result(tensor) + implicit none + double precision, intent(in) :: values(:) + type(tensor_t(double_precision)) tensor + tensor = tensor_t (double_precision)(values) + end function + + pure module function default_real_values(self) result(tensor_values) + implicit none + class(tensor_t), intent(in) :: self + real, allocatable :: tensor_values(:) + tensor_values = self%values_ + end function + + pure module function double_precision_values(self) result(tensor_values) + implicit none + class(tensor_t(double_precision)), intent(in) :: self + double precision, allocatable :: tensor_values(:) + tensor_values = self%values_ + end function + + + pure module function default_real_num_components(self) result(n) + implicit none + class(tensor_t), intent(in) :: self + integer n + n = default_real + end function + + pure module function double_precision_num_components(self) result(n) + implicit none + class(tensor_t(double_precision)), intent(in) :: self + integer n + n = double_precision + end function + +end submodule tensor_s + + + use tensor_m + type(tensor_t(kind(0e0))) :: a + type(tensor_t(kind(0D0))) :: b + a = tensor_t ([1e0,2e0]) + print *, a%num_components (), a%values () + b = tensor_t ([3d0,4d0]) + print *, b%num_components (), b%values () +end +! { dg-final { scan-tree-dump-times "construct_" 4 "original" } } +! { dg-final { scan-tree-dump-times "_components" 4 "original" } } +! { dg-final { scan-tree-dump-times "_values" 4 "original" } } diff --git a/gcc/testsuite/gfortran.dg/pr122513.f90 b/gcc/testsuite/gfortran.dg/pr122513.f90 new file mode 100644 index 0000000..9e12ab1 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr122513.f90 @@ -0,0 +1,13 @@ +! { dg-do compile } +! PR122513 do concurrent default (none) fails on parameter arrays +program test + implicit none + integer :: i + do concurrent (i=1:2) default (none) + block + integer, dimension(2,3), parameter :: & + ii = reshape((/ 1,2,3,4,5,6 /), (/2, 3/)) + print*,ii(i,:) + end block + end do +end program test diff --git a/gcc/testsuite/gfortran.dg/pure_result.f90 b/gcc/testsuite/gfortran.dg/pure_result.f90 new file mode 100644 index 0000000..a4d30aa --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pure_result.f90 @@ -0,0 +1,49 @@ +! { dg-do compile } +! PR fortran/78640 - constraints on pure function results +! +! F2018:C1585, F2023:C1594: +! "The function result of a pure function shall not be both polymorphic and +! allocatable, or have a polymorphic allocatable ultimate component." + +program pr78640 + implicit none + + type foo_t + end type + + type bar_t + integer, allocatable :: dummy + class(*), allocatable :: c + end type bar_t + +contains + + pure function f() result(foo) ! { dg-error "is polymorphic allocatable" } + class(foo_t), allocatable :: foo + foo = foo_t() + end function + + pure function f2() ! { dg-error "is polymorphic allocatable" } + class(foo_t), allocatable :: f2 + f2 = foo_t() + end function + + pure function g() result(foo) ! { dg-error "is polymorphic allocatable" } + class(*), allocatable :: foo + foo = foo_t() + end function + + pure function g2() ! { dg-error "is polymorphic allocatable" } + class(*), allocatable :: g2 + g2 = foo_t() + end function + + pure function h() result(bar) ! { dg-error "polymorphic allocatable component" } + type(bar_t) :: bar + end function + + pure function h2() ! { dg-error "polymorphic allocatable component" } + type(bar_t) :: h2 + end function + +end diff --git a/gcc/testsuite/gm2.dg/spell/iso/fail/badimport.mod b/gcc/testsuite/gm2.dg/spell/iso/fail/badimport.mod new file mode 100644 index 0000000..337cf34 --- /dev/null +++ b/gcc/testsuite/gm2.dg/spell/iso/fail/badimport.mod @@ -0,0 +1,14 @@ + +(* { dg-do compile } *) +(* { dg-options "-g -c" } *) + +MODULE badimport ; + +IMPORT ASCII ; +FROM StrIO IMPORT WriteString ; +FROM ASCIi IMPORT nul ; + (* { dg-error "error: the file containing the definition module 'ASCIi' cannot be found, did you mean ASCII" "ASCIi" { target *-*-* } 9 } *) + +BEGIN + +END badimport. diff --git a/gcc/testsuite/gm2.dg/spell/iso/fail/badimport2.mod b/gcc/testsuite/gm2.dg/spell/iso/fail/badimport2.mod new file mode 100644 index 0000000..63fd338 --- /dev/null +++ b/gcc/testsuite/gm2.dg/spell/iso/fail/badimport2.mod @@ -0,0 +1,12 @@ + +(* { dg-do compile } *) +(* { dg-options "-g -c" } *) + +MODULE badimport2 ; + +FROM StrIO IMPORT Writestring ; + (* { dg-error "error: In program module 'badimport2': unknown symbol 'Writestring', did you mean WriteString?" "Writestring" { target *-*-* } 7 } *) + +BEGIN + +END badimport2. diff --git a/gcc/testsuite/gm2.dg/spell/iso/fail/badimport3.mod b/gcc/testsuite/gm2.dg/spell/iso/fail/badimport3.mod new file mode 100644 index 0000000..ab82cd5 --- /dev/null +++ b/gcc/testsuite/gm2.dg/spell/iso/fail/badimport3.mod @@ -0,0 +1,17 @@ + +(* { dg-do compile } *) +(* { dg-options "-g -c" } *) + +MODULE badimport3 ; + +CONST + Foo = 42 ; + +MODULE inner ; +IMPORT foo ; + (* { dg-error "error: In inner module 'inner': unknown symbol 'foo', did you mean Foo?" "foo" { target *-*-* } 11 } *) +END inner ; + + +BEGIN +END badimport3. diff --git a/gcc/testsuite/gm2.dg/spell/iso/fail/badimport4.mod b/gcc/testsuite/gm2.dg/spell/iso/fail/badimport4.mod new file mode 100644 index 0000000..1b310d7 --- /dev/null +++ b/gcc/testsuite/gm2.dg/spell/iso/fail/badimport4.mod @@ -0,0 +1,17 @@ + +(* { dg-do compile } *) +(* { dg-options "-g -c" } *) + +MODULE badimport4 ; + +CONST + Foo = 42 ; + +MODULE inner ; +IMPORT foo ; + (* { dg-error "error: In inner module 'inner': unknown symbol 'foo', did you mean Foo?" "foo" { target *-*-* } 11 } *) +END inner ; + + +BEGIN +END badimport4. diff --git a/gcc/testsuite/gnat.dg/aggr32.adb b/gcc/testsuite/gnat.dg/aggr32.adb new file mode 100644 index 0000000..e5b0887 --- /dev/null +++ b/gcc/testsuite/gnat.dg/aggr32.adb @@ -0,0 +1,15 @@ +-- { dg-do compile } + +with Aggr32_Pkg.Child; + +procedure Aggr32 (W, H : Positive) is + + use Aggr32_Pkg; + + package Test_1 is new Child (Frame => (Width => W, Height => H)); + + package Test_2 is new Child (Frame => Rec'(Width => W, Height => H)); + +begin + null; +end; diff --git a/gcc/testsuite/gnat.dg/aggr32_pkg-child.ads b/gcc/testsuite/gnat.dg/aggr32_pkg-child.ads new file mode 100644 index 0000000..352e2b5 --- /dev/null +++ b/gcc/testsuite/gnat.dg/aggr32_pkg-child.ads @@ -0,0 +1,6 @@ +generic + + Frame : Rec; + +package Aggr32_Pkg.Child is +end Aggr32_Pkg.Child; diff --git a/gcc/testsuite/gnat.dg/aggr32_pkg.ads b/gcc/testsuite/gnat.dg/aggr32_pkg.ads new file mode 100644 index 0000000..e0e8bef --- /dev/null +++ b/gcc/testsuite/gnat.dg/aggr32_pkg.ads @@ -0,0 +1,8 @@ +package Aggr32_Pkg is + + type Rec is record + Width : Positive; + Height : Positive; + end record; + +end Aggr32_Pkg; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst6.ads b/gcc/testsuite/gnat.dg/specs/generic_inst6.ads new file mode 100644 index 0000000..0f15207 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst6.ads @@ -0,0 +1,6 @@ +-- { dg-do compile } + +with Generic_Inst6_Pkg1.Child.Grand2; +with Generic_Inst6_Pkg3; + +package Generic_Inst6 is new Generic_Inst6_Pkg3.Grand2; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand1.ads b/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand1.ads new file mode 100644 index 0000000..4d8e7ce --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand1.ads @@ -0,0 +1,3 @@ +generic +package Generic_Inst6_Pkg1.Child.Grand1 is +end Generic_Inst6_Pkg1.Child.Grand1; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand2.ads b/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand2.ads new file mode 100644 index 0000000..326a3e0 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand2.ads @@ -0,0 +1,6 @@ +with Generic_Inst6_Pkg1.Child.Grand1; + +generic +package Generic_Inst6_Pkg1.Child.Grand2 is + package My_Grand1 is new Generic_Inst6_Pkg1.Child.Grand1; +end Generic_Inst6_Pkg1.Child.Grand2; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child.ads b/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child.ads new file mode 100644 index 0000000..3676052 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child.ads @@ -0,0 +1,3 @@ +generic +package Generic_Inst6_Pkg1.Child is +end Generic_Inst6_Pkg1.Child; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1.ads b/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1.ads new file mode 100644 index 0000000..a480bbd --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1.ads @@ -0,0 +1,3 @@ +generic +package Generic_Inst6_Pkg1 is +end Generic_Inst6_Pkg1; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg2.ads b/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg2.ads new file mode 100644 index 0000000..98b2011 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg2.ads @@ -0,0 +1,3 @@ +with Generic_Inst6_Pkg1; + +package Generic_Inst6_Pkg2 is new Generic_Inst6_Pkg1; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg3.ads b/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg3.ads new file mode 100644 index 0000000..395b9f0 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg3.ads @@ -0,0 +1,4 @@ +with Generic_Inst6_Pkg1.Child; +with Generic_Inst6_Pkg2; + +package Generic_Inst6_Pkg3 is new Generic_Inst6_Pkg2.Child; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst7.ads b/gcc/testsuite/gnat.dg/specs/generic_inst7.ads new file mode 100644 index 0000000..3132525 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst7.ads @@ -0,0 +1,17 @@ +-- { dg-do compile } + +package Generic_Inst7 is + + function F return Integer is (0); + + generic + with function Foo return Integer; + package P is + type Color is (Foo); + end P; + + package My_P is new P (F); + + I : Integer := My_P.Foo; -- { dg-error "expected type|found type" } + +end Generic_Inst7; diff --git a/gcc/testsuite/gnat.dg/specs/generic_inst8.ads b/gcc/testsuite/gnat.dg/specs/generic_inst8.ads new file mode 100644 index 0000000..0eac709 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/generic_inst8.ads @@ -0,0 +1,18 @@ +-- { dg-do compile } + +package Generic_Inst8 is + + function F return Integer is (0); + + generic + with function Foo return Integer; + package P is + type Color1 is (Foo); + type Color2 is (Foo); + end P; + + package My_P is new P (F); + + I : Integer := My_P.Foo; -- { dg-error "no visible interpretation|use" } + +end Generic_Inst8; diff --git a/gcc/testsuite/gnat.dg/specs/unknown_discr1.ads b/gcc/testsuite/gnat.dg/specs/unknown_discr1.ads new file mode 100644 index 0000000..d1c85e1 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/unknown_discr1.ads @@ -0,0 +1,23 @@ +-- { dg-do compile } + +with Unknown_Discr1_Pkg; use Unknown_Discr1_Pkg; +with Unknown_Discr1_Pkg.Child; +with Unknown_Discr1_Pkg.Inst; + +package Unknown_Discr1 is + + A : Tagged_Type (0); -- { dg-error "type has unknown discriminants" } + + B : Child.Derived_1 (1); -- { dg-error "type has unknown discriminants" } + + C : Child.Derived_2 (2); -- { dg-error "type has unknown discriminants" } + + D : Child.Nested.Derived_3 (3); -- { dg-error "type has unknown discriminants" } + + E : Inst.Derived_1 (1); -- { dg-error "type has unknown discriminants" } + + F : Inst.Derived_2 (2); -- { dg-error "type has unknown discriminants" } + + G : Inst.Nested.Derived_3 (3); -- { dg-error "type has unknown discriminants" } + +end Unknown_Discr1; diff --git a/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-child.ads b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-child.ads new file mode 100644 index 0000000..681efbc --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-child.ads @@ -0,0 +1,17 @@ +package Unknown_Discr1_Pkg.Child is + + type Derived_1 is new Tagged_Type with null record; + + type Derived_2 is new Derived_1 with null record; + + package Nested is + + type Derived_3 is new Tagged_Type with private; + + private + + type Derived_3 is new Tagged_Type with null record; + + end Nested; + +end Unknown_Discr1_Pkg.Child; diff --git a/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-g.ads b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-g.ads new file mode 100644 index 0000000..1570405 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-g.ads @@ -0,0 +1,21 @@ +generic + + type Base (<>) is new Tagged_Type with private; + +package Unknown_Discr1_Pkg.G is + + type Derived_1 is new Base with null record; + + type Derived_2 is new Derived_1 with null record; + + package Nested is + + type Derived_3 is new Tagged_Type with private; + + private + + type Derived_3 is new Tagged_Type with null record; + + end Nested; + +end Unknown_Discr1_Pkg.G; diff --git a/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-inst.ads b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-inst.ads new file mode 100644 index 0000000..5dfe119 --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-inst.ads @@ -0,0 +1,3 @@ +with Unknown_Discr1_Pkg.G; + +package Unknown_Discr1_Pkg.Inst is new Unknown_Discr1_Pkg.G (Tagged_Type); diff --git a/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg.ads b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg.ads new file mode 100644 index 0000000..d769b4d --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg.ads @@ -0,0 +1,9 @@ +package Unknown_Discr1_Pkg is + + type Tagged_Type (<>) is tagged limited private; + +private + + type Tagged_Type (Kind : Integer) is tagged limited null record; + +end Unknown_Discr1_Pkg; diff --git a/gcc/testsuite/gnat.dg/use_type4.adb b/gcc/testsuite/gnat.dg/use_type4.adb new file mode 100644 index 0000000..5ceb288 --- /dev/null +++ b/gcc/testsuite/gnat.dg/use_type4.adb @@ -0,0 +1,29 @@ +-- { dg-do compile } + +procedure Use_Type4 is + + package P1 is + type T is new Integer; + function "and" (L, R : in Integer) return T; + end P1; + + package body P1 is + function "and" (L, R : in Integer) return T is + begin + return T (L * R); + end "and"; + end P1; + + use type P1.T; + + package Renaming renames P1; + + package P2 is + use Renaming; + end P2; + + G : P1.T := Integer'(1) and Integer'(2); + +begin + null; +end; diff --git a/gcc/testsuite/gnat.dg/vect19.adb b/gcc/testsuite/gnat.dg/vect19.adb new file mode 100644 index 0000000..af6f7e6 --- /dev/null +++ b/gcc/testsuite/gnat.dg/vect19.adb @@ -0,0 +1,17 @@ +-- { dg-do compile { target i?86-*-* x86_64-*-* } } +-- { dg-options "-O3 -msse2 -gnatn -fno-tree-slp-vectorize -fdump-tree-vect-details" } + +package body Vect19 is + + function NSum (X : Arr; N : Positive) return Arr is + Ret : Arr := X; + begin + for I in 1 .. N loop + Ret := Sum (Ret, X); + end loop; + return Ret; + end; + +end Vect19; + +-- { dg-final { scan-tree-dump "vectorized 1 loops" "vect" } } diff --git a/gcc/testsuite/gnat.dg/vect19.ads b/gcc/testsuite/gnat.dg/vect19.ads new file mode 100644 index 0000000..475f8d4 --- /dev/null +++ b/gcc/testsuite/gnat.dg/vect19.ads @@ -0,0 +1,7 @@ +with Vect19_Pkg; use Vect19_Pkg; + +package Vect19 is + + function NSum (X : Arr; N : Positive) return Arr; + +end Vect19; diff --git a/gcc/testsuite/gnat.dg/vect19_pkg.adb b/gcc/testsuite/gnat.dg/vect19_pkg.adb new file mode 100644 index 0000000..4c3b999 --- /dev/null +++ b/gcc/testsuite/gnat.dg/vect19_pkg.adb @@ -0,0 +1,12 @@ +package body Vect19_Pkg is + + function Sum (X : Arr; Y : Arr) return Arr is + Result : Arr; + begin + for I in X'Range loop + Result(I) := X(I) + Y(I); + end loop; + return Result; + end; + +end Vect19_Pkg; diff --git a/gcc/testsuite/gnat.dg/vect19_pkg.ads b/gcc/testsuite/gnat.dg/vect19_pkg.ads new file mode 100644 index 0000000..accd8af --- /dev/null +++ b/gcc/testsuite/gnat.dg/vect19_pkg.ads @@ -0,0 +1,9 @@ +package Vect19_Pkg is + + type Arr is array (1 .. 4) of Float; + for Arr'Alignment use 16; + + function Sum (X : Arr; Y : Arr) return Arr; + pragma Inline (Sum); + +end Vect19_Pkg; diff --git a/gcc/testsuite/rust/compile/attr-macro.rs b/gcc/testsuite/rust/compile/attr-macro.rs new file mode 100644 index 0000000..de9fce1 --- /dev/null +++ b/gcc/testsuite/rust/compile/attr-macro.rs @@ -0,0 +1,7 @@ +macro_rules! foo { + () => { #[cfg(all())] 12 } +} + +fn main() -> i32 { + foo!() +} diff --git a/gcc/testsuite/rust/compile/attr_malformed_doc.rs b/gcc/testsuite/rust/compile/attr_malformed_doc.rs new file mode 100644 index 0000000..6b9ef61 --- /dev/null +++ b/gcc/testsuite/rust/compile/attr_malformed_doc.rs @@ -0,0 +1,3 @@ +// { dg-error "valid forms for the attribute are ...doc.hidden.inline....... and ...doc = . string ..." "" { target *-*-* } .+1 } +#[doc] +trait MyTrait {} diff --git a/gcc/testsuite/rust/compile/attr_malformed_path.rs b/gcc/testsuite/rust/compile/attr_malformed_path.rs new file mode 100644 index 0000000..2bccf37 --- /dev/null +++ b/gcc/testsuite/rust/compile/attr_malformed_path.rs @@ -0,0 +1,3 @@ +#[cfg_attr(target_arch = "x86_64", path = (target_arch = "x86", path = "x86.rs"))] +mod imp {} +// { dg-error "malformed .path. attribute input" "" { target *-*-* } .-2 } diff --git a/gcc/testsuite/rust/compile/cfg-test.rs b/gcc/testsuite/rust/compile/cfg-test.rs new file mode 100644 index 0000000..a2e870c --- /dev/null +++ b/gcc/testsuite/rust/compile/cfg-test.rs @@ -0,0 +1,4 @@ +#[test] +fn foo() { + some_function_which_doesnt_exist(); +} diff --git a/gcc/testsuite/rust/compile/enum_discriminant3.rs b/gcc/testsuite/rust/compile/enum_discriminant3.rs new file mode 100644 index 0000000..32c79a5 --- /dev/null +++ b/gcc/testsuite/rust/compile/enum_discriminant3.rs @@ -0,0 +1,8 @@ +const x: isize = 1; +// { dg-warning "unused name" "" { target *-*-* } .-1 } + +fn main() { + enum Foo { + Bar = x, + } +} diff --git a/gcc/testsuite/rust/compile/format_args_concat.rs b/gcc/testsuite/rust/compile/format_args_concat.rs new file mode 100644 index 0000000..b180667 --- /dev/null +++ b/gcc/testsuite/rust/compile/format_args_concat.rs @@ -0,0 +1,51 @@ +#![feature(rustc_attrs)] + +#[rustc_builtin_macro] +macro_rules! format_args { + () => {}; +} + +#[rustc_builtin_macro] +macro_rules! concat { + () => {}; +} + +#[lang = "sized"] +trait Sized {} + +pub mod core { + pub mod fmt { + pub struct Formatter; + pub struct Result; + + pub struct Arguments<'a>; + + impl<'a> Arguments<'a> { + pub fn new_v1(_: &'a [&'static str], _: &'a [ArgumentV1<'a>]) -> Arguments<'a> { + Arguments + } + } + + pub struct ArgumentV1<'a>; + + impl<'a> ArgumentV1<'a> { + pub fn new<'b, T>(_: &'b T, _: fn(&T, &mut Formatter) -> Result) -> ArgumentV1 { + ArgumentV1 + } + } + + pub trait Display { + fn fmt(&self, _: &mut Formatter) -> Result; + } + + impl Display for i32 { + fn fmt(&self, _: &mut Formatter) -> Result { + Result + } + } + } +} + +fn main() { + let _formatted = format_args!(concat!("hello ", "{}"), 15); +} diff --git a/gcc/testsuite/rust/compile/global-path-array.rs b/gcc/testsuite/rust/compile/global-path-array.rs new file mode 100644 index 0000000..c3aa024 --- /dev/null +++ b/gcc/testsuite/rust/compile/global-path-array.rs @@ -0,0 +1,5 @@ +const X: i32 = 1; + +pub fn foo() -> [i32; 1] { + [::X] +} diff --git a/gcc/testsuite/rust/compile/impl_fnptr.rs b/gcc/testsuite/rust/compile/impl_fnptr.rs new file mode 100644 index 0000000..20c9d88 --- /dev/null +++ b/gcc/testsuite/rust/compile/impl_fnptr.rs @@ -0,0 +1,18 @@ +#[lang = "sized"] +pub trait Sized {} + +#[lang = "eq"] +pub trait PartialEq<Rhs: ?Sized = Self> { + fn eq(&self, other: &Rhs) -> bool; + + fn ne(&self, other: &Rhs) -> bool { + !self.eq(other) + } +} + +impl<Ret> PartialEq for extern "C" fn() -> Ret { + #[inline] + fn eq(&self, other: &Self) -> bool { + *self as usize == *other as usize + } +} diff --git a/gcc/testsuite/rust/compile/import_wildcards.rs b/gcc/testsuite/rust/compile/import_wildcards.rs new file mode 100644 index 0000000..3fc3658 --- /dev/null +++ b/gcc/testsuite/rust/compile/import_wildcards.rs @@ -0,0 +1,8 @@ +mod x {} + +mod y {} + +fn main() { + use x as _; + use y as _; +} diff --git a/gcc/testsuite/rust/compile/issue-1725-2.rs b/gcc/testsuite/rust/compile/issue-1725-2.rs index 726d967..d6a2d68 100644 --- a/gcc/testsuite/rust/compile/issue-1725-2.rs +++ b/gcc/testsuite/rust/compile/issue-1725-2.rs @@ -26,6 +26,5 @@ pub fn foo<T: core::ops::Add<Output = i32>>(a: T) -> i32 { pub fn main() { foo(123f32); - // { dg-error "type mismatch, expected .i32. but got .f32." "" { target *-*-* } .-1 } - // { dg-error "bounds not satisfied for f32 .Add. is not satisfied" "" { target *-*-* } .-2 } + // { dg-error "bounds not satisfied for f32 .Add. is not satisfied" "" { target *-*-* } .-1 } } diff --git a/gcc/testsuite/rust/compile/issue-2394.rs b/gcc/testsuite/rust/compile/issue-2394.rs index 92f7afc..b5b5394 100644 --- a/gcc/testsuite/rust/compile/issue-2394.rs +++ b/gcc/testsuite/rust/compile/issue-2394.rs @@ -1,5 +1,6 @@ const A: i32 = (1 / 0); // { dg-error "division by zero" "" { target *-*-* } .-1 } +// { dg-error "is not a constant expression" "" { target *-*-* } .-2 } fn main() { let a = 1 / 0; diff --git a/gcc/testsuite/rust/compile/issue-3538.rs b/gcc/testsuite/rust/compile/issue-3538.rs new file mode 100644 index 0000000..7269457 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3538.rs @@ -0,0 +1,9 @@ +enum A { + Value(()), +} + +fn main() { + let a = A::Value(()); + a == A::Value; + // { dg-error "variant expected constructor call" "" { target *-*-* } .-1 } +} diff --git a/gcc/testsuite/rust/compile/issue-3556.rs b/gcc/testsuite/rust/compile/issue-3556.rs new file mode 100644 index 0000000..be7d85a --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3556.rs @@ -0,0 +1,4 @@ +fn main() { + let ref mut a @ (ref mut b,); + // { dg-error "expected T\\?, found tuple" "" { target *-*-* } .-1 } +}
\ No newline at end of file diff --git a/gcc/testsuite/rust/compile/issue-3592.rs b/gcc/testsuite/rust/compile/issue-3592.rs new file mode 100644 index 0000000..34018d1 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3592.rs @@ -0,0 +1,7 @@ +pub trait X { + fn x() { + fn f(&mut self) {} + // { dg-error ".self. parameter is only allowed in associated functions" "" { target *-*-* } .-1 } + f(); + } +} diff --git a/gcc/testsuite/rust/compile/issue-3645.rs b/gcc/testsuite/rust/compile/issue-3645.rs new file mode 100644 index 0000000..91285f1 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3645.rs @@ -0,0 +1,6 @@ +// { dg-warning "unused name 'y'" "" { target *-*-* } 5 } +// { dg-warning "unused name 'z'" "" { target *-*-* } 5 } + +fn main() { + let (ref y,z) = (1i32, 2u32); +}
\ No newline at end of file diff --git a/gcc/testsuite/rust/compile/issue-3726.rs b/gcc/testsuite/rust/compile/issue-3726.rs new file mode 100644 index 0000000..ced87a5 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3726.rs @@ -0,0 +1,17 @@ +pub enum TypeCtor { + Slice, + Array, +} +pub struct ApplicationTy(TypeCtor); + +macro_rules! ty_app { + ($ctor:pat) => { + ApplicationTy($ctor) + }; +} + +pub fn foo(ty: ApplicationTy) { + match ty { + ty_app!(TypeCtor::Array) => {} + } +} diff --git a/gcc/testsuite/rust/compile/issue-3898.rs b/gcc/testsuite/rust/compile/issue-3898.rs new file mode 100644 index 0000000..114370c --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3898.rs @@ -0,0 +1,112 @@ +// { dg-additional-options "-frust-compile-until=lowering" } + +#[lang = "sized"] +trait Sized {} + +enum Result<T, E> { + Ok(T), + Err(E), +} + +use Result::{Err, Ok}; + +struct Utf8Error; + +const CONT_MASK: u8 = 15; +const TAG_CONT_U8: u8 = 15; + +#[inline(always)] +pub fn run_utf8_validation(v: &[u8]) -> Result<(), Utf8Error> { + let mut index = 0; + let len = 64; + + let usize_bytes = 8; + let ascii_block_size = 2 * usize_bytes; + let blocks_end = if len >= ascii_block_size { + len - ascii_block_size + 1 + } else { + 0 + }; + + while index < len { + let old_offset = index; + macro_rules! err { + ($error_len: expr) => { + return Err(Utf8Error) + }; + } + + macro_rules! next { + () => {{ + index += 1; + // we needed data, but there was none: error! + if index >= len { + err!(None) + } + v[index] + }}; + } + + let first = v[index]; + if first >= 128 { + let w = 15; + // 2-byte encoding is for codepoints \u{0080} to \u{07ff} + // first C2 80 last DF BF + // 3-byte encoding is for codepoints \u{0800} to \u{ffff} + // first E0 A0 80 last EF BF BF + // excluding surrogates codepoints \u{d800} to \u{dfff} + // ED A0 80 to ED BF BF + // 4-byte encoding is for codepoints \u{1000}0 to \u{10ff}ff + // first F0 90 80 80 last F4 8F BF BF + // + // Use the UTF-8 syntax from the RFC + // + // https://tools.ietf.org/html/rfc3629 + // UTF8-1 = %x00-7F + // UTF8-2 = %xC2-DF UTF8-tail + // UTF8-3 = %xE0 %xA0-BF UTF8-tail / %xE1-EC 2( UTF8-tail ) / + // %xED %x80-9F UTF8-tail / %xEE-EF 2( UTF8-tail ) + // UTF8-4 = %xF0 %x90-BF 2( UTF8-tail ) / %xF1-F3 3( UTF8-tail ) / + // %xF4 %x80-8F 2( UTF8-tail ) + match w { + 2 => { + if next!() & !CONT_MASK != TAG_CONT_U8 { + err!(Some(1)) + } + } + 3 => { + match (first, next!()) { + (0xE0, 0xA0..=0xBF) + | (0xE1..=0xEC, 0x80..=0xBF) + | (0xED, 0x80..=0x9F) + | (0xEE..=0xEF, 0x80..=0xBF) => {} + _ => err!(Some(1)), + } + if next!() & !CONT_MASK != TAG_CONT_U8 { + err!(Some(2)) + } + } + 4 => { + match (first, next!()) { + (0xF0, 0x90..=0xBF) | (0xF1..=0xF3, 0x80..=0xBF) | (0xF4, 0x80..=0x8F) => {} + _ => err!(Some(1)), + } + if next!() & !CONT_MASK != TAG_CONT_U8 { + err!(Some(2)) + } + if next!() & !CONT_MASK != TAG_CONT_U8 { + err!(Some(3)) + } + } + _ => err!(Some(1)), + } + index += 1; + } else { + index += 1; + } + } + + Ok(()) +} + +fn main() {} diff --git a/gcc/testsuite/rust/compile/issue-3922.rs b/gcc/testsuite/rust/compile/issue-3922.rs new file mode 100644 index 0000000..3c07f94 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3922.rs @@ -0,0 +1,12 @@ +struct S( + [u8; { + { + // { dg-error "mismatched types. expected .... but got ..integer.. .E0308." "" { target *-*-* } .-1 } + struct Z; + 0 + } + 0 + }], +); + +fn main() {} diff --git a/gcc/testsuite/rust/compile/issue-3924.rs b/gcc/testsuite/rust/compile/issue-3924.rs new file mode 100644 index 0000000..cc423ce --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3924.rs @@ -0,0 +1,6 @@ +pub fn main() { + const S: usize = 23 as i64; + // { dg-error {mismatched types, expected .usize. but got .i64.} "" { target *-*-* } .-1 } + [0; S]; + () +} diff --git a/gcc/testsuite/rust/compile/issue-3928.rs b/gcc/testsuite/rust/compile/issue-3928.rs new file mode 100644 index 0000000..639d4c8 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3928.rs @@ -0,0 +1,12 @@ +// { dg-do compile } +// { dg-options "-fsyntax-only" } + +#![feature(exclusive_range_pattern)] + +fn Foo() { + let x = 1u32; + + match x { + 3..-1 => 4, + }; +} diff --git a/gcc/testsuite/rust/compile/issue-3929-1.rs b/gcc/testsuite/rust/compile/issue-3929-1.rs new file mode 100644 index 0000000..3d7b056 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3929-1.rs @@ -0,0 +1,9 @@ +// { dg-options "-w" } +struct S(); + +fn main() { + let s = S{}; + match s { + S{..} => {} + } +} diff --git a/gcc/testsuite/rust/compile/issue-3929-2.rs b/gcc/testsuite/rust/compile/issue-3929-2.rs new file mode 100644 index 0000000..5f45a7c --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3929-2.rs @@ -0,0 +1,12 @@ +// { dg-options "-w" } +struct S { + x: i32, + y: i32, +} + +fn main() { + let s = S{x: 1, y: 2}; + match s { + S{x: 1, ..} => {} + } +} diff --git a/gcc/testsuite/rust/compile/issue-3930.rs b/gcc/testsuite/rust/compile/issue-3930.rs new file mode 100644 index 0000000..dfcd19a --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3930.rs @@ -0,0 +1,4 @@ +// { dg-additional-options "-w" } +fn main() { + let (a, .., b) = (2, 3); +} diff --git a/gcc/testsuite/rust/compile/issue-3947.rs b/gcc/testsuite/rust/compile/issue-3947.rs new file mode 100644 index 0000000..58ccde6 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3947.rs @@ -0,0 +1,10 @@ +enum _Enum { + A(), +} + +type _E = _Enum; + +// { dg-warning "function is never used: '_a'" "" { target *-*-* } .+1 } +const fn _a() -> _Enum { + _E::A() +} diff --git a/gcc/testsuite/rust/compile/issue-3958.rs b/gcc/testsuite/rust/compile/issue-3958.rs new file mode 100644 index 0000000..935b512 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3958.rs @@ -0,0 +1,11 @@ +// { dg-options "-fsyntax-only" } +trait A { + fn a(&self) -> <Self as A>::X; +} + +impl A for u32 {} + +fn main() { + let a: u32 = 0; + let b: u32 = a.a(); +} diff --git a/gcc/testsuite/rust/compile/issue-3965-1.rs b/gcc/testsuite/rust/compile/issue-3965-1.rs new file mode 100644 index 0000000..291a220 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3965-1.rs @@ -0,0 +1,4 @@ +fn main() { + [(); { continue }]; + // { dg-error ".continue. outside of a loop .E0268." "" { target *-*-* } .-1 } +} diff --git a/gcc/testsuite/rust/compile/issue-3965-2.rs b/gcc/testsuite/rust/compile/issue-3965-2.rs new file mode 100644 index 0000000..d48503f --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3965-2.rs @@ -0,0 +1,7 @@ +fn main() { + loop { continue } + + [(); {while true {break}; 0}]; + + [(); {while true {break}; 0}]; +} diff --git a/gcc/testsuite/rust/compile/issue-3966.rs b/gcc/testsuite/rust/compile/issue-3966.rs new file mode 100644 index 0000000..20d3031 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3966.rs @@ -0,0 +1,5 @@ +struct S { + #[cfg_attr()] + field: u8, + // { dg-error "malformed .cfg_attr. attribute input" "" { target *-*-* } .-2 } +} diff --git a/gcc/testsuite/rust/compile/issue-3969.rs b/gcc/testsuite/rust/compile/issue-3969.rs new file mode 100644 index 0000000..9608589 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3969.rs @@ -0,0 +1,30 @@ +#[lang = "sized"] +pub trait Sized { + // Empty. +} + +#[lang = "fn_once"] +pub trait FnOnce<Args> { + #[lang = "fn_once_output"] + type Output; + + extern "rust-call" fn call_once(self, args: Args) -> Self::Output; +} + +fn main() { + [(); { + while true { + // { dg-error ".constexpr. loop iteration count exceeds limit" "" { target *-*-* } .-1 } + break 9; + // { dg-error "can only .break. with a value inside a .loop. block .E0571." "" { target *-*-* } .-1 } + } + 51 + }]; + + while true { + break (|| { + // { dg-error "can only .break. with a value inside a .loop. block .E0571." "" { target *-*-* } .-1 } + let while_true = 9; + }); + } +} diff --git a/gcc/testsuite/rust/compile/issue-3974.rs b/gcc/testsuite/rust/compile/issue-3974.rs new file mode 100644 index 0000000..dfd693a --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-3974.rs @@ -0,0 +1,8 @@ +impl<'a, F> RunUntil<'a, F> { + // { dg-error "could not resolve type path" "" { target *-*-* } .-1 } + fn project<'pin>() -> Projection<'pin, 'a, F> { + // { dg-error "could not resolve type path" "" { target *-*-* } .-1 } + Self!() + // { dg-error "could not resolve macro invocation" "" { target *-*-* } .-1 } + } +} diff --git a/gcc/testsuite/rust/compile/issue-4090-1.rs b/gcc/testsuite/rust/compile/issue-4090-1.rs new file mode 100644 index 0000000..9f83835 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-4090-1.rs @@ -0,0 +1,68 @@ +mod core { + mod marker { + #[lang = "sized"] + pub trait Sized {} + + #[lang = "phantom_data"] + #[stable(feature = "rust1", since = "1.0.0")] + pub struct PhantomData<T: ?Sized>; + + #[unstable(feature = "structural_match", issue = "31434")] + #[lang = "structural_teq"] + pub trait StructuralEq { + // Empty. + } + + #[unstable(feature = "structural_match", issue = "31434")] + #[lang = "structural_peq"] + pub trait StructuralPartialEq { + // Empty. + } + } + + pub mod cmp { + use super::marker::Sized; + + #[lang = "eq"] + pub trait PartialEq<Rhs: ?Sized = Self> { + fn eq(&self, other: &Rhs) -> bool; + + fn ne(&self, other: &Rhs) -> bool { + !self.eq(other) + } + } + + pub trait Eq: PartialEq<Self> { + fn assert_receiver_is_total_eq(&self) {} + } + } + + pub mod ptr { + + use super::cmp::{Eq, PartialEq}; + + macro_rules! fnptr_impls_safety_abi { + ($FnTy: ty, $($Arg: ident),*) => { + #[stable(feature = "fnptr_impls", since = "1.4.0")] + impl<Ret, $($Arg),*> PartialEq for $FnTy { + #[inline] + fn eq(&self, other: &Self) -> bool { + *self as usize == *other as usize + } + } + + #[stable(feature = "fnptr_impls", since = "1.4.0")] + impl<Ret, $($Arg),*> Eq for $FnTy {} + + } + } + + fnptr_impls_safety_abi! { extern "Rust" fn() -> Ret, } + } +} + +#[derive(PartialEq, Eq)] +struct AllowedBelow { + // { dg-warning "struct is never constructed" "" { target *-*-* } .-1 } + f: fn(), +} diff --git a/gcc/testsuite/rust/compile/issue-4090-2.rs b/gcc/testsuite/rust/compile/issue-4090-2.rs new file mode 100644 index 0000000..75d6b7c --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-4090-2.rs @@ -0,0 +1,71 @@ +mod core { + mod marker { + #[lang = "sized"] + pub trait Sized {} + + #[lang = "phantom_data"] + #[stable(feature = "rust1", since = "1.0.0")] + pub struct PhantomData<T: ?Sized>; + + #[unstable(feature = "structural_match", issue = "31434")] + #[lang = "structural_teq"] + pub trait StructuralEq { + // Empty. + } + + #[unstable(feature = "structural_match", issue = "31434")] + #[lang = "structural_peq"] + pub trait StructuralPartialEq { + // Empty. + } + } + + pub mod cmp { + use super::marker::Sized; + + #[lang = "eq"] + pub trait PartialEq<Rhs: ?Sized = Self> { + fn eq(&self, other: &Rhs) -> bool; + + fn ne(&self, other: &Rhs) -> bool { + !self.eq(other) + } + } + + pub trait Eq: PartialEq<Self> { + fn assert_receiver_is_total_eq(&self) {} + } + } + + pub mod ptr { + + use super::cmp::{Eq, PartialEq}; + + macro_rules! fnptr_impls_safety_abi { + ($FnTy: ty, $($Arg: ident),*) => { + #[stable(feature = "fnptr_impls", since = "1.4.0")] + impl<Ret, $($Arg),*> PartialEq for $FnTy { + #[inline] + fn eq(&self, other: &Self) -> bool { + *self as usize == *other as usize + } + } + + #[stable(feature = "fnptr_impls", since = "1.4.0")] + impl<Ret, $($Arg),*> Eq for $FnTy {} + + } + } + + fnptr_impls_safety_abi! { extern "Rust" fn() -> Ret, } + fnptr_impls_safety_abi! { extern "C" fn() -> Ret, } + fnptr_impls_safety_abi! { unsafe extern "Rust" fn() -> Ret, } + fnptr_impls_safety_abi! { unsafe extern "C" fn() -> Ret, } + } +} + +#[derive(PartialEq, Eq)] +struct AllowedBelow { + // { dg-warning "struct is never constructed" "" { target *-*-* } .-1 } + f: fn(), +} diff --git a/gcc/testsuite/rust/compile/issue-4139.rs b/gcc/testsuite/rust/compile/issue-4139.rs new file mode 100644 index 0000000..dc62d1c --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-4139.rs @@ -0,0 +1,7 @@ +// { dg-skip-if "" { *-*-* } { "-m32" } { "" } } +const X: i32 = const { + let a = 0x736f6d6570736575; + // { dg-error "integer overflows the respective type" "" { target *-*-* } .-1 } + let b = 14; + a + b +}; diff --git a/gcc/testsuite/rust/compile/issue-4145.rs b/gcc/testsuite/rust/compile/issue-4145.rs new file mode 100644 index 0000000..98b33ca --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-4145.rs @@ -0,0 +1,13 @@ +// { dg-excess-errors "warnings" } + +struct S { + field: [u8; { + #[path = "outer/inner.rs"] + // { dg-warning "error handling module file for .inner." "#4145" { xfail *-*-* } .+1 } + mod inner; + // OK + 0 + }], +} + +fn main() {} diff --git a/gcc/testsuite/rust/compile/issue-4146.rs b/gcc/testsuite/rust/compile/issue-4146.rs new file mode 100644 index 0000000..efb3ee2 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-4146.rs @@ -0,0 +1,3 @@ +const _NISIZE_DIV_P: &isize = &(1isize / 0); +// { dg-error "division by zero" "" { target *-*-* } .-1 } +// { dg-error "is not a constant expression" "" { target *-*-* } .-2 } diff --git a/gcc/testsuite/rust/compile/issue-4148.rs b/gcc/testsuite/rust/compile/issue-4148.rs new file mode 100644 index 0000000..599d739 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-4148.rs @@ -0,0 +1,26 @@ +// { dg-excess-errors "warnings" } + +// TODO: all `xfail` conditions should be changed to `target` once the ICE in #4148 is resolved + +pub fn ret_parens(x: i32) -> i32 { + // { dg-warning "unnecessary parentheses around block return value" "#4148" { xfail *-*-* } .+1 } + ((x+1)) +} + +// { dg-warning "unnecessary parentheses around type" "#4148" { xfail *-*-* } .+1 } +// { dg-warning "unnecessary parentheses around pattern" "#4148" { xfail *-*-* } .+1 } +pub fn arg_ret_parens((x): (i32)) -> (i32) { + // { dg-warning "unnecessary parentheses around block return value" "#4148" { xfail *-*-* } .+1 } + ((x+1)) +} + +// { dg-warning "unnecessary parentheses around type" "#4148" { xfail *-*-* } .+1 } +pub fn ret_rpit_parens2(x: i32) -> (i32) { + // { dg-warning "unnecessary parentheses around block return value" "#4148" { xfail *-*-* } .+1 } + ((x+1)) +} + +pub fn ret_parens3(x: i32) -> i32 { + // { dg-warning "unnecessary parentheses around block return value" "#4148" { xfail *-*-* } .+1 } + ((x+1)) +} diff --git a/gcc/testsuite/rust/compile/issue-4155.rs b/gcc/testsuite/rust/compile/issue-4155.rs new file mode 100644 index 0000000..9fae613 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-4155.rs @@ -0,0 +1,7 @@ +struct Bug { + inner: [(); match Vec::new { + f @ |n() => 1 +// { dg-error "failed to parse pattern to bind" "" { target *-*-* } .-1 } +// { dg-error "unexpected token .|. in pattern" "" { target *-*-* } .-2 } + }], +} diff --git a/gcc/testsuite/rust/compile/issue-4165.rs b/gcc/testsuite/rust/compile/issue-4165.rs new file mode 100644 index 0000000..bc513da --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-4165.rs @@ -0,0 +1,12 @@ +const N: usize = 2; +const ARR: [i32; N] = [42; X]; +// { dg-error {cannot find value .X. in this scope \[E0425\]} "" { target *-*-* } .-1 } +// { dg-error {mismatched types, expected .\[i32; 2]. but got .<tyty::error>. \[E0308\]} "" { target *-*-* } .-2 } +// { dg-error {mismatched types, expected .usize. but got .bool. \[E0308\]} "" { target *-*-* } .-3 } +const X: bool = (N[0] == 99) && (ARR[0] == 0); +// { dg-error {the type .usize. cannot be indexed by .<integer>. \[E0277\]} "" { target *-*-* } .-1 } +// { dg-error {mismatched types, expected .<tyty::error>. but got .<integer>. \[E0308\]} "" { target *-*-* } .-2 } + +fn main() { + let _ = X; +} diff --git a/gcc/testsuite/rust/compile/issue-4168.rs b/gcc/testsuite/rust/compile/issue-4168.rs new file mode 100644 index 0000000..abb1190 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-4168.rs @@ -0,0 +1,7 @@ +const fn add(x: usize, y: usize) -> i32 { + add + y + // { dg-error "cannot apply operator .+. to types fn .x usize,y usize,. -> i32 and usize" "" { target *-*-* } .-1 } +} +const ARR: [i32; add(1, 2)] = [5, 6, 1]; +// { dg-error "mismatched types, expected .usize. but got .i32. .E0308." "" { target *-*-* } .-1 } +// { dg-error "mismatched types" "" { target *-*-* } .-2 } diff --git a/gcc/testsuite/rust/compile/issue-4212.rs b/gcc/testsuite/rust/compile/issue-4212.rs new file mode 100644 index 0000000..e068e45 --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-4212.rs @@ -0,0 +1,5 @@ +#![derive(PartialOrd, PartialEq)] +// { dg-error "derive attribute cannot be used at crate level" "" { target *-*-* } .-1 } +pub fn check_ge(a: i32, b: i32) -> bool { + a >= b +} diff --git a/gcc/testsuite/rust/compile/issue-4231.rs b/gcc/testsuite/rust/compile/issue-4231.rs new file mode 100644 index 0000000..4629baa --- /dev/null +++ b/gcc/testsuite/rust/compile/issue-4231.rs @@ -0,0 +1,6 @@ +#[repr = ""] // { dg-error "malformed .repr. attribute" } +struct ThreeInts { + first: i16, + second: i8, + third: i32 +} diff --git a/gcc/testsuite/rust/compile/macros/mbe/macro-issue4054.rs b/gcc/testsuite/rust/compile/macros/mbe/macro-issue4054.rs new file mode 100644 index 0000000..6dcab23 --- /dev/null +++ b/gcc/testsuite/rust/compile/macros/mbe/macro-issue4054.rs @@ -0,0 +1,14 @@ +#[allow(path_statements)] + +macro_rules! array_impl_default { + {$t:ident} => { + $t; + array_impl_default!{} + }; + {} => {} +} + +pub fn foo() { + let x = 12; + array_impl_default! {x} +} diff --git a/gcc/testsuite/rust/compile/macros/mbe/macro49.rs b/gcc/testsuite/rust/compile/macros/mbe/macro49.rs index 0900f7c..9d63ff1 100644 --- a/gcc/testsuite/rust/compile/macros/mbe/macro49.rs +++ b/gcc/testsuite/rust/compile/macros/mbe/macro49.rs @@ -1,3 +1,14 @@ +#[lang = "sized"] +pub trait Sized {} + +#[lang = "fn_once"] +trait FnOnce<Args> { + #[lang = "fn_once_output"] + type Output; + + extern "rust-call" fn call_once(self, args: Args) -> Self::Output; +} + macro_rules! closure { () => {{ 14 + 15 diff --git a/gcc/testsuite/rust/compile/macros/mbe/macro58.rs b/gcc/testsuite/rust/compile/macros/mbe/macro58.rs new file mode 100644 index 0000000..d8f7599 --- /dev/null +++ b/gcc/testsuite/rust/compile/macros/mbe/macro58.rs @@ -0,0 +1,12 @@ +pub fn print(a: *const u8) {} +#[macro_export] +macro_rules! pr_warn ( + ($($arg:tt)*) => ( + $($crate::print($arg))* + ) +); + +fn main() { + pr_warn!("test\0", "test\0"); + // { dg-error "expecting .;. but .identifier. found" "" { target *-*-* } .-1 } +} diff --git a/gcc/testsuite/rust/compile/match-tuplestructpattern-err.rs b/gcc/testsuite/rust/compile/match-tuplestructpattern-err.rs new file mode 100644 index 0000000..efd1a89 --- /dev/null +++ b/gcc/testsuite/rust/compile/match-tuplestructpattern-err.rs @@ -0,0 +1,14 @@ +fn main() { + struct A (i32, i32); + let a = A (0, 1); + + match a { + A (1, 2, 3, 4) => {}, + // { dg-error "this pattern has 4 fields but the corresponding tuple variant has 2 fields .E0023." "" { target *-*-* } .-1 } + A (1, 2, .., 3, 4) => {}, + // { dg-error "this pattern has 4 fields but the corresponding tuple variant has 2 fields .E0023." "" { target *-*-* } .-1 } + A (.., 3, 4, 5) => {}, + // { dg-error "this pattern has 3 fields but the corresponding tuple variant has 2 fields .E0023." "" { target *-*-* } .-1 } + _ => {} + } +}
\ No newline at end of file diff --git a/gcc/testsuite/rust/compile/match-tuplestructpattern-non-variant.rs b/gcc/testsuite/rust/compile/match-tuplestructpattern-non-variant.rs new file mode 100644 index 0000000..cf751cb --- /dev/null +++ b/gcc/testsuite/rust/compile/match-tuplestructpattern-non-variant.rs @@ -0,0 +1,20 @@ +enum Empty {} +enum NonEmpty { + Foo(i32), +} + +fn f(e: Empty) { + match e { + Empty(0) => {} // { dg-error "expected tuple struct or tuple variant, found enum 'Empty'" } + } + + match e { + Empty(Empty(..)) => {} // { dg-error "expected tuple struct or tuple variant, found enum 'Empty'" } + } +} + +fn g(e: NonEmpty) { + match e { + NonEmpty(0) => {} // { dg-error "expected tuple struct or tuple variant, found enum 'NonEmpty'" } + } +} diff --git a/gcc/testsuite/rust/compile/match-tuplestructpattern-rest.rs b/gcc/testsuite/rust/compile/match-tuplestructpattern-rest.rs new file mode 100644 index 0000000..4681acb --- /dev/null +++ b/gcc/testsuite/rust/compile/match-tuplestructpattern-rest.rs @@ -0,0 +1,9 @@ +fn main() { + struct A (i32, i32); + let a = A (0, 1); + + match a { + A (0, ..) => {}, + _ => {} + } +} diff --git a/gcc/testsuite/rust/compile/parse_closure_bind.rs b/gcc/testsuite/rust/compile/parse_closure_bind.rs new file mode 100644 index 0000000..1e08197 --- /dev/null +++ b/gcc/testsuite/rust/compile/parse_closure_bind.rs @@ -0,0 +1,19 @@ +// { dg-additional-options "-frust-compile-until=typecheck" } +// TODO: this should typecheck + +#[lang = "sized"] +trait Sized {} + +#[lang = "fn_once"] +pub trait FnOnce<Args> { + /// The returned type after the call operator is used. + #[lang = "fn_once_output"] + type Output; + + /// Performs the call operation. + extern "rust-call" fn call_once(self, args: Args) -> Self::Output; +} + +pub fn foo() { + (|_a @ _b| {}) (1) +} diff --git a/gcc/testsuite/rust/compile/parse_float_dot.rs b/gcc/testsuite/rust/compile/parse_float_dot.rs new file mode 100644 index 0000000..bfe3da2 --- /dev/null +++ b/gcc/testsuite/rust/compile/parse_float_dot.rs @@ -0,0 +1,3 @@ +// floating point literals can't start with a '.' +// TODO: improve the error message emitted here +const X: f32 = .5; // { dg-error ".*" } diff --git a/gcc/testsuite/rust/compile/primitive-import.rs b/gcc/testsuite/rust/compile/primitive-import.rs new file mode 100644 index 0000000..cc750af --- /dev/null +++ b/gcc/testsuite/rust/compile/primitive-import.rs @@ -0,0 +1,7 @@ +mod primitive { + pub use i32; +} + +pub fn foo() -> primitive::i32 { + 1 +} diff --git a/gcc/testsuite/rust/compile/slice_rest_pattern.rs b/gcc/testsuite/rust/compile/slice_rest_pattern.rs index c27a8dd..bb3c414 100644 --- a/gcc/testsuite/rust/compile/slice_rest_pattern.rs +++ b/gcc/testsuite/rust/compile/slice_rest_pattern.rs @@ -1,5 +1,4 @@ -// { dg-options "-fsyntax-only" } -fn foo(a: &[u32]) { +pub fn foo(a: &[u32]) { match a { [first, ..] => {} [.., last] => {} diff --git a/gcc/testsuite/rust/compile/tuple_index_on_non_tuple.rs b/gcc/testsuite/rust/compile/tuple_index_on_non_tuple.rs new file mode 100644 index 0000000..f94b8c3 --- /dev/null +++ b/gcc/testsuite/rust/compile/tuple_index_on_non_tuple.rs @@ -0,0 +1,15 @@ +enum E { + V(usize), +} + +struct S { + field: i32, +} + +fn main() { + let e = E::V(0); + let _ = e.0; // { dg-error "expected tuple or tuple struct, found 'E'" } + + let s = S { field: 0 }; + let _ = s.0; // { dg-error "expected tuple or tuple struct, found 'S'" } +} diff --git a/gcc/testsuite/rust/compile/tuplepattern-rest-readonly.rs b/gcc/testsuite/rust/compile/tuplepattern-rest-readonly.rs new file mode 100644 index 0000000..db165ef --- /dev/null +++ b/gcc/testsuite/rust/compile/tuplepattern-rest-readonly.rs @@ -0,0 +1,5 @@ +fn main() { + let (a, .., b) = (1, 1); + a = 2; // { dg-error "assignment of read-only variable .a." } + b = 2; // { dg-error "assignment of read-only variable .b." } +}
\ No newline at end of file diff --git a/gcc/testsuite/rust/compile/tuplepattern-restpattern-typecheck-err.rs b/gcc/testsuite/rust/compile/tuplepattern-restpattern-typecheck-err.rs new file mode 100644 index 0000000..d9f7c18 --- /dev/null +++ b/gcc/testsuite/rust/compile/tuplepattern-restpattern-typecheck-err.rs @@ -0,0 +1,8 @@ +fn main() { + match (1, 2.2, "not 3") { + // { dg-error "expected a tuple with 3 elements, found one with 5 elements" "" { target *-*-* } .+1 } + (a, b, .., c, d, e) => { + let _ = b + c; // { dg-error "cannot apply operator .+. to types <float> and & str" } + } + } +}
\ No newline at end of file diff --git a/gcc/testsuite/rust/compile/use_3.rs b/gcc/testsuite/rust/compile/use_3.rs new file mode 100644 index 0000000..2cfe38f --- /dev/null +++ b/gcc/testsuite/rust/compile/use_3.rs @@ -0,0 +1,10 @@ +mod intrinsic { + pub fn foo() {} +} + +pub mod a { + pub fn b() { + use crate::intrinsic; + intrinsic::foo(); + } +} diff --git a/gcc/testsuite/rust/compile/use_self_alone.rs b/gcc/testsuite/rust/compile/use_self_alone.rs new file mode 100644 index 0000000..1df923c --- /dev/null +++ b/gcc/testsuite/rust/compile/use_self_alone.rs @@ -0,0 +1,2 @@ +use self; +// { dg-error ".self. imports are only allowed within a { } list" "" { target *-*-* } .-1 } diff --git a/gcc/testsuite/rust/compile/use_self_alone_in_list.rs b/gcc/testsuite/rust/compile/use_self_alone_in_list.rs new file mode 100644 index 0000000..2e87227 --- /dev/null +++ b/gcc/testsuite/rust/compile/use_self_alone_in_list.rs @@ -0,0 +1,7 @@ +struct B; + +use {B as B2, self}; +// { dg-error ".self. import can only appear in an import list with a non-empty prefix" "" { target *-*-* } .-1 } + +use {self}; +// { dg-error ".self. import can only appear in an import list with a non-empty prefix" "" { target *-*-* } .-1 } diff --git a/gcc/testsuite/rust/core/core.exp b/gcc/testsuite/rust/core/core.exp new file mode 100644 index 0000000..330c6d5 --- /dev/null +++ b/gcc/testsuite/rust/core/core.exp @@ -0,0 +1,37 @@ +# Copyright (C) 2025 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# Compile test libcore, no torture testing. +# +# Skip torture testing for now, as it'd be slow + +# Load support procs. +load_lib rust-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +set saved-dg-do-what-default ${dg-do-what-default} + +set dg-do-what-default "compile" +set individual_timeout 600 +dg-additional-files [lsort [glob -nocomplain $srcdir/../../libgrust/rustc-lib/*]] +dg-runtest $srcdir/../../libgrust/rustc-lib/core/src/lib.rs "-frust-edition=2018 -frust-crate=core -frust-compile-until=astvalidation -w" "" +set dg-do-what-default ${saved-dg-do-what-default} + +# All done. +dg-finish diff --git a/gcc/testsuite/rust/execute/inline_asm_inout_ident.rs b/gcc/testsuite/rust/execute/inline_asm_inout_ident.rs index b0a3d25..324b84d 100644 --- a/gcc/testsuite/rust/execute/inline_asm_inout_ident.rs +++ b/gcc/testsuite/rust/execute/inline_asm_inout_ident.rs @@ -1,3 +1,4 @@ +/* { dg-do run { target x86_64*-*-* } } */ /* { dg-output "Value is: 5\r*\n" } */ #![feature(rustc_attrs)] diff --git a/gcc/testsuite/rust/execute/inline_asm_inout_var.rs b/gcc/testsuite/rust/execute/inline_asm_inout_var.rs index ff101b8..fff432e 100644 --- a/gcc/testsuite/rust/execute/inline_asm_inout_var.rs +++ b/gcc/testsuite/rust/execute/inline_asm_inout_var.rs @@ -1,3 +1,4 @@ +/* { dg-do run { target x86_64*-*-* } } */ /* { dg-output "Value is: 5\r*\n" } */ #![feature(rustc_attrs)] diff --git a/gcc/testsuite/rust/execute/torture/let-identifierpattern-subpattern.rs b/gcc/testsuite/rust/execute/torture/let-identifierpattern-subpattern.rs new file mode 100644 index 0000000..fa1f56e --- /dev/null +++ b/gcc/testsuite/rust/execute/torture/let-identifierpattern-subpattern.rs @@ -0,0 +1,11 @@ +fn main() -> i32 { + let foo @ (bar, _, _) = (0, 2, 3); + let mut ret = 1; + + match foo { + (0, 2, 3) => { ret = bar }, + _ => {} + } + + ret +}
\ No newline at end of file diff --git a/gcc/testsuite/rust/execute/torture/link-name.rs b/gcc/testsuite/rust/execute/torture/link-name.rs new file mode 100644 index 0000000..1ab1ac1 --- /dev/null +++ b/gcc/testsuite/rust/execute/torture/link-name.rs @@ -0,0 +1,16 @@ +// { dg-additional-options "-fdump-rtl-final" } +// { dg-final { scan-rtl-dump "printf" "final" } } +// { dg-output "gcc\r*\n" } + +extern "C" { + #[link_name = "printf"] + fn druckt(fmt: *const i8, ...); +} + +fn main() -> i32 { + let a = "gcc\0"; + + unsafe { druckt("%s\n\0" as *const str as *const i8, a as *const str as *const i8); } + + 0 +} diff --git a/gcc/testsuite/rust/execute/torture/match-slicepattern-array-2.rs b/gcc/testsuite/rust/execute/torture/match-slicepattern-array-2.rs new file mode 100644 index 0000000..c6e7762 --- /dev/null +++ b/gcc/testsuite/rust/execute/torture/match-slicepattern-array-2.rs @@ -0,0 +1,27 @@ +// { dg-output "correct\r*" } +extern "C" { + fn puts(s: *const i8); +} + +fn main() -> i32 { + let a = [0, 4, 5, 6, 1]; + let mut ret = 1; + + match a { + [1, .., b] => { + /* should not take this path */ + unsafe { puts("wrong\0" as *const str as *const i8) } + } + [0, .., 0] => { + /* should not take this path */ + unsafe { puts("wrong\0" as *const str as *const i8) } + }, + [0, .., b] => { + ret -= b; + unsafe { puts("correct\0" as *const str as *const i8) } + }, + _ => {} + } + + ret +} diff --git a/gcc/testsuite/rust/execute/torture/match-slicepattern-slice-2.rs b/gcc/testsuite/rust/execute/torture/match-slicepattern-slice-2.rs new file mode 100644 index 0000000..2fdffbb --- /dev/null +++ b/gcc/testsuite/rust/execute/torture/match-slicepattern-slice-2.rs @@ -0,0 +1,28 @@ +// { dg-output "correct\r*" } +extern "C" { + fn puts(s: *const i8); +} + +fn main() -> i32 { + let arr = [0, 4, 5, 6, 1]; + let a: &[i32] = &arr; + let mut ret = 1; + + match a { + [1, .., b] => { + /* should not take this path */ + unsafe { puts("wrong\0" as *const str as *const i8) } + } + [0, .., 0] => { + /* should not take this path */ + unsafe { puts("wrong\0" as *const str as *const i8) } + }, + [0, .., b] => { + ret -= b; + unsafe { puts("correct\0" as *const str as *const i8) } + }, + _ => {} + } + + ret +} diff --git a/gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-1.rs b/gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-1.rs new file mode 100644 index 0000000..8d7446d --- /dev/null +++ b/gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-1.rs @@ -0,0 +1,24 @@ +// { dg-output "correct\r*" } +extern "C" { + fn puts(s: *const i8); +} + +fn main() -> i32 { + struct A (i32, i32, i32); + let a = A (0, 1, 2); + let mut ret = 1; + + match a { + A (1, ..) => { + /* should not take this path */ + unsafe { puts("wrong\0" as *const str as *const i8) } + } + A (0, b, ..) => { + ret -= b; + unsafe { puts("correct\0" as *const str as *const i8) } + }, + _ => {} + } + + ret +} diff --git a/gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-2.rs b/gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-2.rs new file mode 100644 index 0000000..f433be9 --- /dev/null +++ b/gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-2.rs @@ -0,0 +1,28 @@ +// { dg-output "correct\r*" } +extern "C" { + fn puts(s: *const i8); +} + +fn main() -> i32 { + struct A (i32, i32, i32); + let a = A (0, 3, 1); + let mut ret = 1; + + match a { + A (1, ..) => { + /* should not take this path */ + unsafe { puts("wrong\0" as *const str as *const i8) } + } + A (.., 3) => { + /* should not take this path */ + unsafe { puts("wrong\0" as *const str as *const i8) } + } + A (.., b) => { + ret -= b; + unsafe { puts("correct\0" as *const str as *const i8) } + }, + _ => {} + } + + ret +} |