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-rw-r--r--gcc/testsuite/ChangeLog42
-rw-r--r--gcc/testsuite/gcc.dg/autopar/runtime-auto.c53
-rw-r--r--gcc/testsuite/gcc.dg/pr121468.c30
-rw-r--r--gcc/testsuite/gcc.dg/pr122200.c23
-rw-r--r--gcc/testsuite/gcc.dg/tree-ssa/vla-1.c15
-rw-r--r--gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c2
-rw-r--r--gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c4
-rw-r--r--gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-2.c2
-rw-r--r--gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq-check-carry.c48
-rw-r--r--gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c8
-rw-r--r--gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c8
-rw-r--r--gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c8
-rw-r--r--gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c8
-rw-r--r--gcc/testsuite/gcc.target/i386/pr122266.c10
14 files changed, 241 insertions, 20 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ca170a1..d910bc0 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,45 @@
+2025-10-15 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/121468
+ PR tree-optimization/121206
+ PR tree-optimization/122200
+ * gcc.dg/pr121468.c: New.
+ * gcc.dg/pr122200.c: New.
+
+2025-10-15 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/118460
+ * gcc.target/arm/armv8_2-fp16-move-1.c: Adjust expected output.
+ * gcc.target/arm/armv8_2-fp16-move-2.c: Likewise.
+
+2025-10-15 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
+
+ PR tree-optimization/122037
+ * gcc.dg/tree-ssa/vla-1.c: New test.
+
+2025-10-15 Alice Carlotti <alice.carlotti@arm.com>
+
+ * gcc.target/aarch64/acle/rwsr-armv8p9.c: Fix incorrect encoding.
+
+2025-10-15 Sebastian Pop <spop@nvidia.com>
+
+ * gcc.dg/autopar/runtime-auto.c: New test.
+
+2025-10-15 Christophe Lyon <christophe.lyon@linaro.org>
+
+ PR target/122189
+ * gcc.target/arm/mve/intrinsics/vadcq-check-carry.c: New test.
+ * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Adjust instructions
+ order.
+ * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Likewise.
+
+2025-10-15 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR rtl-optimization/122266
+ * gcc.target/i386/pr122266.c: New test case.
+
2025-10-14 Patrick Palka <ppalka@redhat.com>
PR c++/122192
diff --git a/gcc/testsuite/gcc.dg/autopar/runtime-auto.c b/gcc/testsuite/gcc.dg/autopar/runtime-auto.c
new file mode 100644
index 0000000..c1a3131
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/autopar/runtime-auto.c
@@ -0,0 +1,53 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-parallelize-loops -fdump-tree-parloops2-details" } */
+
+void abort (void);
+
+#define N 1000
+
+int a[N], b[N], c[N];
+
+void
+test_parallel_loop (void)
+{
+ int i;
+
+ /* This loop should be auto-parallelized when -ftree-parallelize-loops
+ (without =number) is used for runtime thread detection via OMP_NUM_THREADS. */
+ for (i = 0; i < N; i++)
+ a[i] = b[i] + c[i];
+}
+
+int
+main (void)
+{
+ int i;
+
+ for (i = 0; i < N; i++)
+ {
+ b[i] = i;
+ c[i] = i * 2;
+ }
+
+ test_parallel_loop ();
+
+ for (i = 0; i < N; i++)
+ {
+ if (a[i] != b[i] + c[i])
+ abort ();
+ }
+
+ return 0;
+}
+
+/* Check that the loop is parallelized with runtime thread detection. */
+/* { dg-final { scan-tree-dump "parallelizing" "parloops2" } } */
+
+/* Check that "#pragma omp parallel" is generated. */
+/* { dg-final { scan-tree-dump "pragma omp parallel" "parloops2" } } */
+
+/* Check that instead of generating a num_threads(x) clause, the compiler calls
+ "__builtin_omp_get_num_threads" that will set the number of threads at
+ program execution time. */
+/* { dg-final { scan-tree-dump "__builtin_omp_get_num_threads" "parloops2" } } */
+
diff --git a/gcc/testsuite/gcc.dg/pr121468.c b/gcc/testsuite/gcc.dg/pr121468.c
new file mode 100644
index 0000000..07df274
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr121468.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+int e, f, n;
+static int a () { return e; }
+void b () { while (a()); }
+static int d () { return e; }
+static void g (int h) {
+ if (e)
+ c:
+ if (d())
+ goto i;
+ do {
+ if (f)
+ goto c;
+ goto k;
+ i:
+ h = 2147483647;
+ k:
+ e = 2147483646;
+ e = 6 + e;
+ do {
+ b ();
+ } while (1784828957 / f + e + (808 + h) > 0);
+ } while (1 % h);
+}
+void m () { g (-2); }
+int main () {
+ if (n)
+ g (-1);
+}
diff --git a/gcc/testsuite/gcc.dg/pr122200.c b/gcc/testsuite/gcc.dg/pr122200.c
new file mode 100644
index 0000000..cd770fc
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr122200.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+/* { dg-additional-options "-mavx" { target { x86_64-*-* i?86-*-* } } } */
+
+
+int a, b;
+
+void f(float g[][5]) {
+ int c;
+
+ for (c = 0; c != a; c++)
+ g[1][c] = c;
+
+ for (int d; d; d++)
+ for (int e = 1; e != b; e++) {
+ for (c = 0; c != a; c++) {
+ g[0][1] = 1;
+
+ if (g[1][c])
+ g[1][c] = 1;
+ }
+ }
+}
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vla-1.c b/gcc/testsuite/gcc.dg/tree-ssa/vla-1.c
new file mode 100644
index 0000000..37b7514
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/vla-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-optimized -fdump-tree-cddce1-details" } */
+/* PR tree-optimization/122037 */
+
+void bar1 (char *, int) __attribute__((noreturn));
+void foo1 (int size)
+{
+ char temp[size];
+ temp[size-1] = '\0';
+ bar1 (temp, size);
+}
+
+/* The call to __builtin_stack_save should have been removed. */
+/* { dg-final { scan-tree-dump "Deleting : __builtin_stack_save" "cddce1" } } */
+/* { dg-final { scan-tree-dump-not "__builtin_stack_save " "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
index c49fbb5..1ff51de 100644
--- a/gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
+++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
@@ -72,7 +72,7 @@ readwrite_armv8p9a_sysregs (long long int a)
a = __arm_rsr64 ("pmicfiltr_el0"); /* { { dg-final { scan-assembler "mrs\tx0, s3_3_c9_c6_0" } } */
a = __arm_rsr64 ("pmicntr_el0"); /* { { dg-final { scan-assembler "mrs\tx0, s3_3_c9_c4_0" } } */
a = __arm_rsr64 ("pmicntsvr_el1"); /* { { dg-final { scan-assembler "mrs\tx0, s2_0_c14_c12_0" } } */
- a = __arm_rsr64 ("pmsdsfr_el1"); /* { { dg-final { scan-assembler "mrs\tx0, s3_4_c9_c10_4" } } */
+ a = __arm_rsr64 ("pmsdsfr_el1"); /* { { dg-final { scan-assembler "mrs\tx0, s3_0_c9_c10_4" } } */
a = __arm_rsr64 ("pmsscr_el1"); /* { { dg-final { scan-assembler "mrs\tx0, s3_0_c9_c13_3" } } */
a = __arm_rsr64 ("pmuacr_el1"); /* { { dg-final { scan-assembler "mrs\tx0, s3_0_c9_c14_4" } } */
a = __arm_rsr64 ("por_el0"); /* { { dg-final { scan-assembler "mrs\tx0, s3_3_c10_c2_4" } } */
diff --git a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c
index 444c4a3..02d7b51 100644
--- a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c
+++ b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c
@@ -134,8 +134,8 @@ test_select_8 (__fp16 a, __fp16 b, __fp16 c)
}
/* { dg-final { scan-assembler-times {vseleq\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {vselgt\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */
-/* { dg-final { scan-assembler-times {vselge\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vselgt\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vselge\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 2 } } */
/* { dg-final { scan-assembler-not {vmov\.f16} } } */
diff --git a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-2.c b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-2.c
index dff57ac..a249d71 100644
--- a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-2.c
+++ b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-2.c
@@ -8,4 +8,4 @@ test_select (__fp16 a, __fp16 b, __fp16 c)
{
return (a < b) ? b : c;
}
-/* { dg-final { scan-assembler "bx?(mi|pl)" } } */
+/* { dg-final { scan-assembler "vselgt\.f16\t" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq-check-carry.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq-check-carry.c
new file mode 100644
index 0000000..3a9b8de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq-check-carry.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "arm_mve.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <inttypes.h>
+#include <stdio.h>
+
+__attribute((noinline)) void print_uint32x4_t(const char *name, uint32x4_t val)
+{
+ printf("%s: %u, %u, %u, %u\n",
+ name,
+ vgetq_lane_u32(val, 0),
+ vgetq_lane_u32(val, 1),
+ vgetq_lane_u32(val, 2),
+ vgetq_lane_u32(val, 3));
+}
+
+void __attribute__ ((noinline)) test_2(void)
+{
+ uint32x4_t v12, v18, v108;
+ unsigned v17 = 0;
+ v12 = vdupq_n_u32(1);
+ v18 = vadcq_u32(v12, v12, &v17);
+ v17 = 1;
+ v108 = vadcq_u32(v12, v12, &v17);
+ print_uint32x4_t("v108", v108);
+}
+
+int main()
+{
+ test_2();
+ return 0;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-output "v108: 3, 2, 2, 2" } */
+/* { dg-final { scan-assembler-times {\tvmrs\t(?:ip|fp|r[0-9]+), FPSCR_nzcvqc} 3 } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
index 0d4cb77..c5a5878 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
@@ -14,12 +14,12 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** vpst(?: @.*|)
** ...
** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
@@ -41,12 +41,12 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** vpst(?: @.*|)
** ...
** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
index a0ba682..23908a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
@@ -14,12 +14,12 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** vpst(?: @.*|)
** ...
** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
@@ -41,12 +41,12 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** vpst(?: @.*|)
** ...
** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
index 7a33261..940e2ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
@@ -14,12 +14,12 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** vpst(?: @.*|)
** ...
** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
@@ -41,12 +41,12 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** vpst(?: @.*|)
** ...
** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
index 6090219..478b938 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
@@ -14,12 +14,12 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** vpst(?: @.*|)
** ...
** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
@@ -41,12 +41,12 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** vpst(?: @.*|)
** ...
** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
diff --git a/gcc/testsuite/gcc.target/i386/pr122266.c b/gcc/testsuite/gcc.target/i386/pr122266.c
new file mode 100644
index 0000000..4e31a6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr122266.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-O2" } */
+
+signed __int128 foo(signed __int128 x) {
+ signed __int128 t = x >> 127;
+ return ((x^t)>>1)^t;
+}
+
+/* { dg-final { scan-assembler-times "xorq" 4 } } */
+/* { dg-final { scan-assembler-times "sarq" 2 } } */
generated by cgit v1.1 at 2025-10-16 11:47:35 +0000