diff options
Diffstat (limited to 'gcc/testsuite')
75 files changed, 1764 insertions, 12 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8f13d2c..e80759b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,346 @@ +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + PR tree-optimization/123074 + * gcc.target/riscv/rvv/rvv.exp: Include *.C. + * gcc.target/riscv/rvv/autovec/pr123074.C: New test. + +2025-12-09 Qing Zhao <qing.zhao@oracle.com> + + PR c/122982 + * gcc.dg/pointer-counted-by-pr122982.c: New test. + +2025-12-09 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check + for vmslt.vx. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test + helper macros. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test + data for run test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i16.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i32.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i64.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i8.c: New test. + +2025-12-09 Richard Biener <rguenther@suse.de> + + PR target/121230 + * gcc.target/i386/pr121230.c: New testcase. + +2025-12-09 Nathaniel Shead <nathanieloshead@gmail.com> + + Revert: + 2025-12-09 Nathaniel Shead <nathanieloshead@gmail.com> + + PR c++/122819 + * g++.dg/modules/tpl-friend-22.C: New test. + +2025-12-09 Jakub Jelinek <jakub@redhat.com> + + PR c/123018 + * gcc.dg/pr123018.c: New test. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + PR tree-optimization/122635 + * gcc.target/aarch64/sve/pfalse-store.c: Expect more elided + stores. + * gcc.target/riscv/rvv/autovec/pr122635-1.c: New test. + * gcc.target/riscv/rvv/autovec/pr122635-2.c: New test. + * gcc.target/powerpc/p9-vec-length-epil-8.c: Expect two lxvl + less. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + * gcc.target/riscv/rvv/autovec/max-vect-1.c: New test. + * gcc.target/riscv/rvv/autovec/max-vect-2.c: New test. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + PR target/123022 + * gcc.target/riscv/rvv/autovec/pr123022-2.c: New test. + * gcc.target/riscv/rvv/autovec/pr123022.c: New test. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + PR target/115325 + * gcc.target/riscv/pragma-target-1.c: New test. + * gcc.target/riscv/pragma-target-2.c: New test. + +2025-12-09 Robin Dapp <rdapp@ventanamicro.com> + + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1-run.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2-run.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3-run.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4-run.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5-run.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6-run.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7-run.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8-run.c: New test. + * gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8.c: New test. + +2025-12-09 Richard Biener <rguenther@suse.de> + + PR target/123027 + * gcc.target/i386/pr123027.c: New testcase. + * gcc.dg/torture/pr123027.c: Likewise. + +2025-12-09 Nathaniel Shead <nathanieloshead@gmail.com> + + PR c++/122819 + * g++.dg/modules/tpl-friend-22.C: New test. + +2025-12-08 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/46555 + * gcc.dg/tree-ssa/pr46555.c: New test. + +2025-12-08 Harald Anlauf <anlauf@gmx.de> + Steven G. Kargl <kargl@gcc.gnu.org> + + PR fortran/123025 + * gfortran.dg/assumed_charlen_dummy.f90: These tests failed + with the change because of the default -pedantic option + used by the dg.exp mechanisms. Overide this default. + * gfortran.dg/automatic_char_len_1.f90: Ditto. + * gfortran.dg/entry_23.f: Ditto. + * gfortran.dg/finalize_59.f90: Dito. + * gfortran.dg/g77/f90-intrinsic-bit.f: Ditto. + * gfortran.dg/g77/f90-intrinsic-mathematical.f: Ditto. + * gfortran.dg/g77/f90-intrinsic-numeric.f: Ditto. + * gfortran.dg/g77/intrinsic-unix-bessel.f: Ditto. + * gfortran.dg/g77/intrinsic-unix-erf.f: Ditto. + * gfortran.dg/initialization_9.f90: Ditto. + * gfortran.dg/intrinsic_actual_4.f90: Ditto. + * gfortran.dg/namelist_assumed_char.f90: Ditto. + * gfortran.dg/pr15140.f90: Ditto. + +2025-12-08 Egas Ribeiro <egas.g.ribeiro@tecnico.ulisboa.pt> + + PR c++/119343 + * g++.dg/template/sfinae-deleted-pr119343.C: New test. + +2025-12-08 Eric Botcazou <ebotcazou@adacore.com> + + * gcc.dg/tls/data-sections-1.c: New test. + +2025-12-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/123040 + * g++.dg/torture/pr123040.C: New testcase. + +2025-12-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/123038 + * gcc.dg/vect/pr123038.c: New testcase. + +2025-12-08 Tamar Christina <tamar.christina@arm.com> + + PR target/123026 + * gcc.target/aarch64/pr123026.c: New test. + +2025-12-08 H.J. Lu <hjl.tools@gmail.com> + + PR target/122343 + * gcc.target/i386/avx2-vpcmpgtq-1.c: Compile with + -fno-fuse-ops-with-volatile-access. + +2025-12-07 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/reduce3.adb: New test. + +2025-12-07 H.J. Lu <hjl.tools@gmail.com> + + PR target/122343 + * gcc.target/i386/20040112-1.c: Add -fomit-frame-pointer and use + check-function-bodies to check for loop. + * gcc.target/i386/avx-ne-convert-1.c: Compile with + -fno-fuse-ops-with-volatile-access. + * gcc.target/i386/avx10_2-bf16-1.c: Likewise. + * gcc.target/i386/avx10_2-convert-1.c: Likewise. + * gcc.target/i386/avx10_2-satcvt-1.c: Likewise. + * gcc.target/i386/avx512bf16-vcvtneps2bf16-1.c: Likewise. + * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1a.c: Likewise. + * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1b.c: Likewise. + * gcc.target/i386/avx512bitalg-vpshufbitqmb.c: Likewise. + * gcc.target/i386/avx512bw-vpcmpb-1.c: Likewise. + * gcc.target/i386/avx512bw-vpcmpub-1.c: Likewise. + * gcc.target/i386/avx512bw-vpcmpuw-1.c: Likewise. + * gcc.target/i386/avx512bw-vpcmpw-1.c: Likewise. + * gcc.target/i386/avx512dq-vcvtps2qq-1.c: Likewise. + * gcc.target/i386/avx512dq-vcvtps2uqq-1.c: Likewise. + * gcc.target/i386/avx512dq-vcvtqq2pd-1.c: Likewise. + * gcc.target/i386/avx512dq-vcvtqq2ps-1.c: Likewise. + * gcc.target/i386/avx512dq-vcvttps2qq-1.c: Likewise. + * gcc.target/i386/avx512dq-vcvttps2uqq-1.c: Likewise. + * gcc.target/i386/avx512dq-vcvtuqq2pd-1.c: Likewise. + * gcc.target/i386/avx512dq-vcvtuqq2ps-1.c: Likewise. + * gcc.target/i386/avx512dq-vextractf32x8-1.c: Likewise. + * gcc.target/i386/avx512dq-vextractf64x2-1.c: Likewise. + * gcc.target/i386/avx512dq-vextracti64x2-1.c: Likewise. + * gcc.target/i386/avx512dq-vfpclasspd-1.c: Likewise. + * gcc.target/i386/avx512dq-vfpclassps-1.c: Likewise. + * gcc.target/i386/avx512dq-vfpclasssd-1.c: Likewise. + * gcc.target/i386/avx512dq-vfpclassss-1.c: Likewise. + * gcc.target/i386/avx512dq-vpmullq-1.c: Likewise. + * gcc.target/i386/avx512dq-vpmullq-3.c: Likewise. + * gcc.target/i386/avx512f-pr100267-1.c: Likewise. + * gcc.target/i386/avx512f-vcmppd-1.c: Likewise. + * gcc.target/i386/avx512f-vcmpps-1.c: Likewise. + * gcc.target/i386/avx512f-vcvtps2pd-1.c: Likewise. + * gcc.target/i386/avx512f-vcvtsd2si-1.c: Likewise. + * gcc.target/i386/avx512f-vcvtsd2si64-1.c: Likewise. + * gcc.target/i386/avx512f-vcvtsd2usi-1.c: Likewise. + * gcc.target/i386/avx512f-vcvtsd2usi64-1.c: Likewise. + * gcc.target/i386/avx512f-vcvtsi2ss-1.c: Likewise. + * gcc.target/i386/avx512f-vcvtss2si-1.c: Likewise. + * gcc.target/i386/avx512f-vcvtss2si64-1.c: Likewise. + * gcc.target/i386/avx512f-vcvtss2usi-1.c: Likewise. + * gcc.target/i386/avx512f-vcvtss2usi64-1.c: Likewise. + * gcc.target/i386/avx512f-vcvttsd2si-1.c: Likewise. + * gcc.target/i386/avx512f-vcvttsd2si64-1.c: Likewise. + * gcc.target/i386/avx512f-vcvttsd2usi-1.c: Likewise. + * gcc.target/i386/avx512f-vcvttsd2usi64-1.c: Likewise. + * gcc.target/i386/avx512f-vcvttss2si-1.c: Likewise. + * gcc.target/i386/avx512f-vcvttss2si64-1.c: Likewise. + * gcc.target/i386/avx512f-vcvttss2usi-1.c: Likewise. + * gcc.target/i386/avx512f-vcvttss2usi64-1.c: Likewise. + * gcc.target/i386/avx512f-vextractf32x4-1.c: Likewise. + * gcc.target/i386/avx512f-vextractf64x4-1.c: Likewise. + * gcc.target/i386/avx512f-vextracti64x4-1.c: Likewise. + * gcc.target/i386/avx512f-vmovapd-1.c: Likewise. + * gcc.target/i386/avx512f-vmovaps-1.c: Likewise. + * gcc.target/i386/avx512f-vmovdqa64-1.c: Likewise. + * gcc.target/i386/avx512f-vpandnq-1.c: Likewise. + * gcc.target/i386/avx512f-vpbroadcastd-1.c: Likewise. + * gcc.target/i386/avx512f-vpbroadcastq-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpd-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpeqq-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpequq-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpged-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpgeq-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpgeud-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpgeuq-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpled-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpleq-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpleud-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpleuq-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpltd-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpltq-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpltud-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpltuq-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpneqd-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpneqq-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpnequd-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpnequq-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpq-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpud-1.c: Likewise. + * gcc.target/i386/avx512f-vpcmpuq-1.c: Likewise. + * gcc.target/i386/avx512f-vrndscalepd-1.c: Likewise. + * gcc.target/i386/avx512f-vrndscaleps-1.c: Likewise. + * gcc.target/i386/avx512fp16-complex-fma.c: Likewise. + * gcc.target/i386/avx512fp16-vaddph-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvtpd2ph-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvtph2dq-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvtph2pd-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvtph2psx-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvtph2qq-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvtph2udq-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvtph2uqq-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvtph2uw-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvtph2w-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvtps2ph-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvtqq2ph-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvttph2dq-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvttph2qq-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvttph2udq-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvttph2uqq-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvttph2uw-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvttph2w-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vcvtuqq2ph-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vfcmaddcph-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vfcmulcph-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vfmaddcph-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vfmulcph-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vfpclassph-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vfpclasssh-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vmulph-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vrcpph-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vrsqrtph-1a.c: Likewise. + * gcc.target/i386/avx512fp16-vsqrtph-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vaddph-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvtpd2ph-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvtph2dq-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvtph2psx-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvtph2qq-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvtph2udq-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvtph2uqq-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvtph2uw-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvtph2w-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvtps2ph-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvtqq2ph-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvttph2dq-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvttph2udq-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvttph2uw-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvttph2w-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vfcmaddcph-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vfcmulcph-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vfmaddcph-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vfmulcph-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vfpclassph-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vmulph-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vrcpph-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vrsqrtph-1a.c: Likewise. + * gcc.target/i386/avx512fp16vl-vsqrtph-1a.c: Likewise. + * gcc.target/i386/avx512vl-pr100267-1.c: Likewise. + * gcc.target/i386/avx512vl-vcmppd-1.c: Likewise. + * gcc.target/i386/avx512vl-vcmpps-1.c: Likewise. + * gcc.target/i386/avx512vl-vcvtpd2ps-1.c: Likewise. + * gcc.target/i386/avx512vl-vcvtpd2udq-1.c: Likewise. + * gcc.target/i386/avx512vl-vcvttpd2udq-1.c: Likewise. + * gcc.target/i386/avx512vl-vcvttps2udq-1.c: Likewise. + * gcc.target/i386/avx512vl-vextractf32x4-1.c: Likewise. + * gcc.target/i386/avx512vl-vmovapd-1.c: Likewise. + * gcc.target/i386/avx512vl-vmovaps-1.c: Likewise. + * gcc.target/i386/avx512vl-vmovdqa64-1.c: Likewise. + * gcc.target/i386/avx512vl-vpcmpd-1.c: Likewise. + * gcc.target/i386/avx512vl-vpcmpeqq-1.c: Likewise. + * gcc.target/i386/avx512vl-vpcmpequq-1.c: Likewise. + * gcc.target/i386/avx512vl-vpcmpq-1.c: Likewise. + * gcc.target/i386/avx512vl-vpcmpud-1.c: Likewise. + * gcc.target/i386/avx512vl-vpcmpuq-1.c: Likewise. + * gcc.target/i386/pr122343-1a.c: New test. + * gcc.target/i386/pr122343-1b.c: Likewise. + * gcc.target/i386/pr122343-2a.c: Likewise. + * gcc.target/i386/pr122343-2b.c: Likewise. + * gcc.target/i386/pr122343-3.c: Likewise. + * gcc.target/i386/pr122343-4a.c: Likewise. + * gcc.target/i386/pr122343-4b.c: Likewise. + * gcc.target/i386/pr122343-5a.c: Likewise. + * gcc.target/i386/pr122343-5b.c: Likewise. + * gcc.target/i386/pr122343-6a.c: Likewise. + * gcc.target/i386/pr122343-6b.c: Likewise. + * gcc.target/i386/pr122343-7.c: Likewise. + 2025-12-06 Alexandre Oliva <oliva@adacore.com> PR rtl-optimization/122947 diff --git a/gcc/testsuite/g++.dg/lookup/extern-c-redecl3.C b/gcc/testsuite/g++.dg/lookup/extern-c-redecl3.C index 56dcefa..c9c9bd5 100644 --- a/gcc/testsuite/g++.dg/lookup/extern-c-redecl3.C +++ b/gcc/testsuite/g++.dg/lookup/extern-c-redecl3.C @@ -5,17 +5,19 @@ // { dg-final { scan-assembler-not "call\[\t \]+\[^\$\]*?_Z4forkv" { target i?86-*-* x86_64-*-* } } } // { dg-final { scan-assembler "call\[\t \]+_?fork" { target i?86-*-* x86_64-*-* } } } -extern "C" int fork (void); +typedef __typeof (__builtin_fork ()) pid_t; + +extern "C" pid_t fork (void); void foo () { - extern int fork (void); + extern pid_t fork (void); fork (); } extern "C" -int +pid_t fork (void) { return 0; diff --git a/gcc/testsuite/g++.dg/pid_t-1.C b/gcc/testsuite/g++.dg/pid_t-1.C new file mode 100644 index 0000000..cb32eb4 --- /dev/null +++ b/gcc/testsuite/g++.dg/pid_t-1.C @@ -0,0 +1,3 @@ +/* { dg-options "-Wall" } */ + +extern "C" int fork (void); // { dg-warning "conflicts with built-in declaration" "" { target { *-*-solaris2* && ilp32 } } } diff --git a/gcc/testsuite/g++.dg/template/sfinae-deleted-pr119343.C b/gcc/testsuite/g++.dg/template/sfinae-deleted-pr119343.C new file mode 100644 index 0000000..065ad60 --- /dev/null +++ b/gcc/testsuite/g++.dg/template/sfinae-deleted-pr119343.C @@ -0,0 +1,31 @@ +// { dg-do compile { target c++11 } } +// PR c++/119343 - No SFINAE for deleted explicit specializations + +struct true_type { static constexpr bool value = true; }; +struct false_type { static constexpr bool value = false; }; + +struct X { + static void f()=delete; + template<int> static void g(); +}; +template<> void X::g<0>()=delete; +struct Y { + static void f(); + template<int> static void g(); +}; + +template<class T,class=void> +struct has_f : false_type {}; +template<class T> +struct has_f<T,decltype(void(T::f))> : true_type {}; + +static_assert(!has_f<X>::value, ""); +static_assert(has_f<Y>::value, ""); + +template<class T,class=void> +struct has_g0 : false_type {}; +template<class T> +struct has_g0<T,decltype(void(T::template g<0>))> : true_type {}; + +static_assert(!has_g0<X>::value, ""); +static_assert(has_g0<Y>::value, ""); diff --git a/gcc/testsuite/g++.dg/torture/pr123040.C b/gcc/testsuite/g++.dg/torture/pr123040.C new file mode 100644 index 0000000..3ba2d90 --- /dev/null +++ b/gcc/testsuite/g++.dg/torture/pr123040.C @@ -0,0 +1,61 @@ +// { dg-do compile } + +template <int kBytes, typename From, typename To> +void CopyBytes(From from, To to) { + __builtin_memcpy(to, from, kBytes); +} +template <typename From, typename To> void CopySameSize(From *from, To to) { + CopyBytes<sizeof(From)>(from, to); +} +template <typename> using MakeUnsigned = char; +template <typename Lane, int N> struct Simd { + using T = Lane; + static constexpr int kPrivateLanes = N; + template <typename NewT> using Rebind = Simd<NewT, 0>; +}; +template <class D> using TFromD = D::T; +template <class T, class D> using Rebind = D::template Rebind<T>; +template <class D> using RebindToUnsigned = Rebind<MakeUnsigned<D>, D>; +template <typename T, int> struct Vec128 { + using PrivateT = T; + static constexpr int kPrivateN = 6; + T raw[16]; +}; +template <class V> using DFromV = Simd<typename V::PrivateT, V::kPrivateN>; +template <class D> Vec128<TFromD<D>, D::kPrivateLanes> Zero(D); +template <class D> using VFromD = decltype(Zero(D())); +template <class D, class VFrom> VFromD<D> BitCast(D, VFrom v) { + VFromD<D> to; + CopySameSize(&v, to.raw); + return to; +} +template <int N> Vec128<signed char, N> And(Vec128<signed char, N> b) { + Vec128<signed char, N> a; + DFromV<decltype(a)> d; + RebindToUnsigned<decltype(d)> du; + auto au(a); + auto bu = BitCast(du, b); + for (int i = 0; i < N; ++i) + au.raw[i] &= bu.raw[i]; + return au; +} +void Or(Vec128<signed char, 16>); +template <int N> void IfVecThenElse(Vec128<signed char, N> yes) { + Vec128 __trans_tmp_2 = And(yes); + Or(__trans_tmp_2); +} +template <int N> void IfThenElseZero(Vec128<signed char, N> yes) { + IfVecThenElse(yes); +} +Vec128<signed char, 16> Abs_a; +char MaskedAbs___trans_tmp_5; +void MaskedAbs() { + Vec128<signed char, 16> __trans_tmp_4; + for (int i = 0; i < 16; ++i) { + MaskedAbs___trans_tmp_5 = Abs_a.raw[i] ? -Abs_a.raw[i] : 0; + Abs_a.raw[i] = MaskedAbs___trans_tmp_5; + } + __trans_tmp_4 = Abs_a; + Vec128 __trans_tmp_3 = __trans_tmp_4; + IfThenElseZero(__trans_tmp_3); +} diff --git a/gcc/testsuite/g++.target/riscv/rvv/autovec/pr123074.C b/gcc/testsuite/g++.target/riscv/rvv/autovec/pr123074.C new file mode 100644 index 0000000..d203477 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/autovec/pr123074.C @@ -0,0 +1,124 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fpermissive -Wno-return-type" } */ + +namespace std { +template <typename _Iterator> _Iterator __miter_base(_Iterator); +template <typename _Default, typename, template <typename> class> +struct __detector { + using type = _Default; +}; +template <typename _Default, template <typename> class _Op> +using __detected_or = __detector<_Default, void, _Op>; +template <typename _Default, template <typename> class _Op> +using __detected_or_t = typename __detected_or<_Default, _Op>::type; +template <typename _Tp> class allocator { +public: + typedef _Tp value_type; +}; +template <typename> struct pointer_traits { + template <typename _Up> using rebind = _Up *; +}; +} // namespace std +namespace __gnu_cxx { +template <typename _Iterator, typename> class __normal_iterator { +public: + _Iterator base(); +}; +} // namespace __gnu_cxx +namespace std { +template <bool, typename _OutIter, typename _InIter> +void __assign_one(_OutIter __out, _InIter __in) { + *__out = *__in; +} +template <bool _IsMove, typename _BI1, typename _BI2> +__copy_move_backward_a2(_BI1 __first, _BI1 __last, _BI2 __result) { /* { dg-warning "with no type" "" } */ + while (__first != __last) { + --__last; + --__result; + __assign_one<_IsMove>(__result, __last); + } +} +template <bool _IsMove, typename _BI1, typename _BI2> +__copy_move_backward_a1(_BI1 __first, _BI1 __last, _BI2 __result) { /* { dg-warning "with no type" "" } */ + __copy_move_backward_a2<_IsMove>(__first, __last, __result); +} +template <bool _IsMove, typename _II, typename _OI> +__copy_move_backward_a(_II __first, _II __last, _OI __result) { /* { dg-warning "with no type" "" } */ + __copy_move_backward_a1<_IsMove>(__first, __last, __result); +} +template <typename _BI1, typename _BI2> +move_backward(_BI1 __first, _BI1 __last, _BI2 __result) { /* { dg-warning "with no type" "" } */ + __copy_move_backward_a<true>(__first, __miter_base(__last), __result); +} +struct __allocator_traits_base { + template <typename _Tp> using __pointer = typename _Tp::pointer; + template <typename _Tp> using __c_pointer = typename _Tp::const_pointer; +}; +template <typename _Alloc> struct allocator_traits : __allocator_traits_base { + typedef typename _Alloc::value_type value_type; + using pointer = __detected_or_t<value_type *, __pointer>; + template <template <typename> class, typename _Tp> struct _Ptr { + using type = typename pointer_traits<pointer>::rebind<_Tp>; + }; + using const_pointer = typename _Ptr<__c_pointer, value_type>::type; +}; +} // namespace std +namespace __gnu_cxx { +template <typename _Alloc> +struct __alloc_traits : std::allocator_traits<_Alloc> {}; +} // namespace __gnu_cxx +namespace std { +template <typename, typename _Alloc> struct _Vector_base { + typedef __gnu_cxx::__alloc_traits<_Alloc> _Tp_alloc_type; + typedef typename __gnu_cxx::__alloc_traits<_Tp_alloc_type>::pointer pointer; + struct { + pointer _M_finish; + } _M_impl; +}; +template <typename _Tp, typename _Alloc = allocator<_Tp>> +class vector : _Vector_base<_Tp, _Alloc> { + typedef _Vector_base<_Tp, _Alloc> _Base; + typedef typename _Base::_Tp_alloc_type _Alloc_traits; + +public: + typedef _Tp value_type; + typedef typename _Base::pointer pointer; + typedef typename _Alloc_traits::const_pointer const_pointer; + typedef __gnu_cxx::__normal_iterator<pointer, vector> iterator; + typedef __gnu_cxx::__normal_iterator<const_pointer, vector> const_iterator; + iterator begin(); + iterator insert(const_iterator, const value_type &); + struct _Temporary_value {}; + template <typename _Arg> void _M_insert_aux(iterator, _Arg &&); +}; +template <typename _Tp, typename _Alloc> +typename vector<_Tp, _Alloc>::iterator +vector<_Tp, _Alloc>::insert(const_iterator, const value_type &) { + auto __pos = begin(); + _Temporary_value __x_copy; + _M_insert_aux(__pos, __x_copy); +} +template <typename _Tp, typename _Alloc> +template <typename _Arg> +void vector<_Tp, _Alloc>::_M_insert_aux(iterator __position, _Arg &&) { + move_backward(__position.base(), this->_M_impl._M_finish, + this->_M_impl._M_finish); +} +namespace internals { +struct distributing { + distributing &operator=(const distributing &); + int global_row; + *constraints; /* { dg-warning "with no type" "" } */ +}; +distributing &distributing::operator=(const distributing &in) { + global_row = in.global_row; + return; /* { dg-warning "return-statement with no value" "" } */ +} +insert_index(vector<distributing> my_indices) { /* { dg-warning "with no type" "" } */ + typedef vector<distributing>::iterator index_iterator; + index_iterator pos; + distributing row_value; + my_indices.insert(pos, row_value); +} +} // namespace internals +} // namespace std diff --git a/gcc/testsuite/gcc.dg/pid_t-1.c b/gcc/testsuite/gcc.dg/pid_t-1.c new file mode 100644 index 0000000..f4f3f68 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pid_t-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-Wall" } */ +/* { dg-require-fork "" } */ + +/* Compile with -Wall to get a warning if built-in and system pid_t don't + match. */ + +#include <sys/types.h> + +typedef __typeof (__builtin_fork ()) __builtin_pid_t; + +__builtin_pid_t __p_t__; +pid_t *p_t_p; + +void +pt (void) +{ + p_t_p = &__p_t__; +} diff --git a/gcc/testsuite/gcc.dg/pointer-counted-by-pr122982.c b/gcc/testsuite/gcc.dg/pointer-counted-by-pr122982.c new file mode 100644 index 0000000..1bad7f0 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pointer-counted-by-pr122982.c @@ -0,0 +1,19 @@ +/* PR c/122982 */ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ + +int* f (int); + +struct __bounded_ptr { + int k; + int *buf __attribute__ ((counted_by (k))); +}; + +int* +f1 (int n) { return f (n); } + +void h1 (void) +{ + int *p = (struct __bounded_ptr) {3, f1 (3)}.buf; + __builtin_memset (p, 0, 3 * sizeof p); +} diff --git a/gcc/testsuite/gcc.dg/pr123018.c b/gcc/testsuite/gcc.dg/pr123018.c new file mode 100644 index 0000000..f1f701b --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr123018.c @@ -0,0 +1,17 @@ +/* PR c/123018 */ +/* { dg-do compile } */ + +struct A { + int x : 8 __attribute__ ((vector_size (8))); /* { dg-error "bit-field 'x' has invalid type" } */ +}; +struct B { + float x : 8; /* { dg-error "bit-field 'x' has invalid type" } */ +}; +struct C { + int : 8 __attribute__ ((vector_size (8))); /* { dg-error "bit-field '\[^\n\r]*anonymous\[^\n\r]*' has invalid type" } */ + int x; +}; +struct D { + float : 8; /* { dg-error "bit-field '\[^\n\r]*anonymous\[^\n\r]*' has invalid type" } */ + int x; +}; diff --git a/gcc/testsuite/gcc.dg/tls/data-sections-1.c b/gcc/testsuite/gcc.dg/tls/data-sections-1.c new file mode 100644 index 0000000..c829256 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tls/data-sections-1.c @@ -0,0 +1,14 @@ +/* { dg-do run } */ +/* { dg-require-effective-target tls_runtime } */ +/* { dg-options "-fdata-sections" } */ +/* { dg-add-options tls } */ + +__thread int i = 1; + +int main (void) +{ + if (i != 1) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr123027.c b/gcc/testsuite/gcc.dg/torture/pr123027.c new file mode 100644 index 0000000..cba4cc9 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr123027.c @@ -0,0 +1,20 @@ +/* { dg-do run } */ +/* { dg-options "-ffinite-math-only" } */ +/* { dg-add-options ieee } */ + +double a = 0.0; +double b = -0.0; + +int main() +{ + double min1 = a < b ? a : b; + double max1 = a > b ? a : b; + double min2 = b < a ? b : a; + double max2 = b > a ? b : a; + if (__builtin_copysign (1., min1) != -1. + || __builtin_copysign (1., max1) != -1. + || __builtin_copysign (1., min2) != 1. + || __builtin_copysign (1., max2) != 1.) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr46555.c b/gcc/testsuite/gcc.dg/tree-ssa/pr46555.c new file mode 100644 index 0000000..d4de7c2 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr46555.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized-details -fdump-rtl-pro_and_epilogue" } */ +/* PR tree-optimization/46555 */ +/* Here should not remove the forwarder block (or rather recreate it and not + remove it again). This improves expansion to RTL as there is one less copy + (or constant formation) in some cases. In this case we also get the ability + to shrink wrap the function. */ + +int h(void); +int f(int a, int b, int c) +{ + if (a) + return 2; + h(); + if (b) + return 2; + h(); + if (c) + return 2; + h(); + return 4; +} + +/* { dg-final { scan-tree-dump-times "New forwarder block for edge" 1 "optimized" } } */ +/* Make sure we only have a PHI with 2 arguments here, 2 and 4. */ +/* { dg-final { scan-tree-dump "PHI <2..., 4...>|PHI <4..., 2...>" "optimized" } } */ +/* Make sure we can shrink wrap the function now too. */ +/* { dg-final { scan-rtl-dump "Performing shrink-wrapping" "pro_and_epilogue" { target { { { i?86-*-* x86_64-*-* } && { ! ia32 } } || { powerpc*-*-* aarch64*-*-* riscv*-*-* arm*-*-* } } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr123038.c b/gcc/testsuite/gcc.dg/vect/pr123038.c new file mode 100644 index 0000000..bca831f --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr123038.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ + +unsigned char f(int b) +{ + for (int a = 0; a < 10; a += 1) + b = __builtin_ffs(b); + return b; +} diff --git a/gcc/testsuite/gcc.target/aarch64/pr123026.c b/gcc/testsuite/gcc.target/aarch64/pr123026.c new file mode 100644 index 0000000..4dcce8a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr123026.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-additional-options "-O3 -march=armv8-a -std=c99" } */ + +#include <stdbool.h> + +int g; + +__attribute__ ((noipa)) void +foo(bool a) { + for (int i = 0; i < 4; i++) + if (!i || a) + g += 1; +} + +int main() +{ + foo(0); + if (g != 1) + __builtin_abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store.c index 1539f58..39db13b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store.c @@ -46,8 +46,5 @@ ALL_DATA (st2, x2_t) ALL_DATA (st3, x3_t) ALL_DATA (st4, x4_t) -/* FIXME: Currently, st1/2/3/4 are not folded with a pfalse - predicate, which is the reason for the 48 missing cases below. Once - folding is implemented for these intrinsics, the sum should be 60. */ -/* { dg-final { scan-assembler-times {\t.cfi_startproc\n\tret\n} 12 } } */ +/* { dg-final { scan-assembler-times {\t.cfi_startproc\n\tret\n} 60 } } */ /* { dg-final { scan-assembler-times {\t.cfi_startproc\n} 60 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-1.c b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-1.c index 7a98380..5e6f431 100644 --- a/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mavx2 -O2" } */ +/* { dg-options "-mavx2 -O2 -fno-fuse-ops-with-volatile-access" } */ /* { dg-final { scan-assembler "vpcmpgtq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/pr121230.c b/gcc/testsuite/gcc.target/i386/pr121230.c new file mode 100644 index 0000000..67c9c5c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121230.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-O3 -march=athlon-xp -mfpmath=387 -fexcess-precision=standard" } */ + +typedef struct { + float a; + float b; +} f32_2; + +f32_2 add32_2(f32_2 x, f32_2 y) { + return (f32_2){ x.a + y.a, x.b + y.b}; +} + +/* We do not want the vectorizer to vectorize the store and/or the + conversion (with IA32 we do not support V2SF add) given that spills + FP regs to reload them to XMM. */ +/* { dg-final { scan-assembler-not "movss\[ \\t\]+\[0-9\]*\\\(%esp\\\), %xmm" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr123027.c b/gcc/testsuite/gcc.target/i386/pr123027.c new file mode 100644 index 0000000..b7effac --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr123027.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse -mfpmath=sse -ffinite-math-only" } */ + +float foo (float a, float b) +{ + return a < b ? a : b; +} + +float bar (float a, float b) +{ + return a > b ? a : b; +} + +/* { dg-final { scan-assembler-times "minss" 1 } } */ +/* { dg-final { scan-assembler-times "maxss" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-8.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-8.c index 34a2c8e..5dff0d0 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-8.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-8.c @@ -13,5 +13,5 @@ #include "p9-vec-length-8.h" -/* { dg-final { scan-assembler-times {\mlxvl\M} 16 } } */ +/* { dg-final { scan-assembler-times {\mlxvl\M} 14 } } */ /* { dg-final { scan-assembler-times {\mstxvl\M} 7 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pragma-target-1.c b/gcc/testsuite/gcc.target/riscv/pragma-target-1.c new file mode 100644 index 0000000..d1a0600 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pragma-target-1.c @@ -0,0 +1,59 @@ +/* Test for #pragma GCC target and push/pop options support in RISC-V */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O2" } */ + +/* Default compilation options - no vector */ +void default_func(void) { +#ifdef __riscv_vector + __builtin_abort(); /* Should not have vector by default */ +#endif +} + +/* Change target to enable vector */ +#pragma GCC push_options +#pragma GCC target("arch=rv64gcv") +void vector_func(void) { +#ifndef __riscv_vector + __builtin_abort(); /* Should have vector here */ +#endif +} +#pragma GCC pop_options + +/* Back to default - no vector */ +void after_pop_func(void) { +#ifdef __riscv_vector + __builtin_abort(); /* Should not have vector after pop */ +#endif +} + +/* Test multiple push/pop levels */ +#pragma GCC push_options +#pragma GCC target("arch=rv64gc") +void base_func(void) { +#ifdef __riscv_vector + __builtin_abort(); /* Should not have vector */ +#endif +} + +#pragma GCC push_options +#pragma GCC target("arch=rv64gcv") +void nested_vector_func(void) { +#ifndef __riscv_vector + __builtin_abort(); /* Should have vector here */ +#endif +} +#pragma GCC pop_options + +void after_nested_pop_func(void) { +#ifdef __riscv_vector + __builtin_abort(); /* Should not have vector after nested pop */ +#endif +} +#pragma GCC pop_options + +/* Final function should be back to original default */ +void final_func(void) { +#ifdef __riscv_vector + __builtin_abort(); /* Should not have vector */ +#endif +} diff --git a/gcc/testsuite/gcc.target/riscv/pragma-target-2.c b/gcc/testsuite/gcc.target/riscv/pragma-target-2.c new file mode 100644 index 0000000..077bcdd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pragma-target-2.c @@ -0,0 +1,26 @@ +/* Test for #pragma GCC target with tune parameter */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=rocket -O2" } */ + +void default_tune(void) { + /* Default tune is rocket */ +} + +#pragma GCC push_options +#pragma GCC target("tune=sifive-7-series") +void sifive_tune(void) { + /* Tune should be sifive-7-series */ +} +#pragma GCC pop_options + +void back_to_rocket(void) { + /* Tune should be back to rocket */ +} + +#pragma GCC target("arch=rv64gcv;tune=generic") +void combined_options(void) { +#ifndef __riscv_vector + __builtin_abort(); /* Should have vector */ +#endif + /* Tune should be generic */ +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/max-vect-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/max-vect-1.c new file mode 100644 index 0000000..923c1f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/max-vect-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +void __attribute__ (( target ("max-vectorization"))) +foo (char *restrict a, int *restrict b, short *restrict c, + int *restrict d, int stride) +{ + if (stride <= 1) + return; + + for (int i = 0; i < 3; i++) + { + int res = c[i]; + int t = b[d[i]]; + if (a[c[i]] != 0) + res = t * b[d[i]]; + c[i] = res; + } +} + +/* { dg-final { scan-tree-dump "vectorized 1 loops in function" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/max-vect-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/max-vect-2.c new file mode 100644 index 0000000..fc5c2ad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/max-vect-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mmax-vectorization -fdump-tree-vect-details" } */ + +void +foo (char *restrict a, int *restrict b, short *restrict c, + int *restrict d, int stride) +{ + if (stride <= 1) + return; + + for (int i = 0; i < 3; i++) + { + int res = c[i]; + int t = b[d[i]]; + if (a[c[i]] != 0) + res = t * b[d[i]]; + c[i] = res; + } +} + +/* { dg-final { scan-tree-dump "vectorized 1 loops in function" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122635-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122635-1.c new file mode 100644 index 0000000..0beb3d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122635-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -mno-autovec-segment" } */ + +typedef struct { + int a[6]; + float b[3]; +} c; + +int d(c *e) { + int f =0; + for (; f < 3; f++) { + e->a[2 * f] = e->b[f]; + e->a[2 * f + 1] = -e->a[2 * f]; + e->a[2 * f] = f + 3 * e->a[2 * f]; + e->a[2 * f + 1] = f + 3 * e->a[2 * f + 1]; + } + return 0; +} + +/* { dg-final { scan-assembler-not "vsetivli.*zero,0" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122635-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122635-2.c new file mode 100644 index 0000000..0de69b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122635-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -mno-autovec-segment" } */ + +typedef struct { + int A[6]; + float b[]; +} a; + +int b(a *a) { + int b = 0; + for (; b < 3; b++) { + a->A[2 * b] = a->b[b] - b + a->A[2 * b]; + a->A[2 * b + 1] = b * a->A[2 * b + 1]; + } + return 0; +} + +/* { dg-final { scan-assembler-not "vsetivli.*zero,0" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022-2.c new file mode 100644 index 0000000..0562b56 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv_zvl512b -mabi=lp64d -mrvv-vector-bits=zvl -fsigned-char" } */ + +#include "pr123022.c" + +/* { dg-final { scan-assembler-not "vset.*zero,1," } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022.c new file mode 100644 index 0000000..1f5f165 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-require-effective-target rvv_zvl512b_ok } */ +/* { dg-options "-O3 -march=rv64gcv_zvl512b -mabi=lp64d -mrvv-vector-bits=zvl -fsigned-char" } */ +unsigned e[2][2]; +long a; +char c[2]; + +int +main () +{ + long long b; + c[1] = 3; + for (unsigned h = 0; h < 2; h++) + for (int i = c[0]; i < 5; i += 5) + for (int j = 0; j < 219; j++) + a = c[h] ? e[h][h] + 3326195747 : 0; + + b = a; + if (b != 3326195747) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1-run.c new file mode 100644 index 0000000..b3bf8da --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1-run.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +char p[128]; + +bool __attribute__((noipa)) +fand (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r |= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fand (n)) + __builtin_abort (); + + p[0] = 0; + for (int n = 1; n < 77; ++n) + if (fand (n)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fior (n)) + __builtin_abort (); + + p[0] = 1; + for (int n = 1; n < 77; ++n) + if (!fior (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1.c new file mode 100644 index 0000000..b8c4f22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +char p[128]; + +bool __attribute__((noipa)) +fand (int n) +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior (int n) +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r |= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2-run.c new file mode 100644 index 0000000..1a64b2b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2-run.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +short p[128]; + +bool __attribute__((noipa)) +fand (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r |= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fand (n)) + __builtin_abort (); + + p[0] = 0; + for (int n = 1; n < 77; ++n) + if (fand (n)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fior (n)) + __builtin_abort (); + + p[0] = 1; + for (int n = 1; n < 77; ++n) + if (!fior (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2.c new file mode 100644 index 0000000..868f91b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +short p[128]; + +bool __attribute__((noipa)) +fand () +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior () +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r |= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3-run.c new file mode 100644 index 0000000..693a9118 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3-run.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +int p[128]; + +bool __attribute__((noipa)) +fand (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r |= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fand (n)) + __builtin_abort (); + + p[0] = 0; + for (int n = 1; n < 77; ++n) + if (fand (n)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fior (n)) + __builtin_abort (); + + p[0] = 1; + for (int n = 1; n < 77; ++n) + if (!fior (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3.c new file mode 100644 index 0000000..d1a286b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +int p[128]; + +bool __attribute__((noipa)) +fand () +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior () +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r |= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4-run.c new file mode 100644 index 0000000..b55925e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4-run.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +long long p[128]; + +bool __attribute__((noipa)) +fand (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r |= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fand (n)) + __builtin_abort (); + + p[0] = 0; + for (int n = 1; n < 77; ++n) + if (fand (n)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fior (n)) + __builtin_abort (); + + p[0] = 1; + for (int n = 1; n < 77; ++n) + if (!fior (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4.c new file mode 100644 index 0000000..34a44b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +long long p[128]; + +bool __attribute__((noipa)) +fand () +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior () +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r |= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5-run.c new file mode 100644 index 0000000..95570ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5-run.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +char p[128]; + +bool __attribute__((noipa)) +fxort (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fxort (n) != !(n & 1)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n) != (n & 1)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fxort (n)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5.c new file mode 100644 index 0000000..f179970 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +char p[128]; + +bool __attribute__((noipa)) +fxort () +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf () +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6-run.c new file mode 100644 index 0000000..267485b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6-run.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +short p[128]; + +bool __attribute__((noipa)) +fxort (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fxort (n) != !(n & 1)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n) != (n & 1)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fxort (n)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6.c new file mode 100644 index 0000000..8486c6b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +short p[128]; + +bool __attribute__((noipa)) +fxort () +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf () +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7-run.c new file mode 100644 index 0000000..242147b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7-run.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +int p[128]; + +bool __attribute__((noipa)) +fxort (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fxort (n) != !(n & 1)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n) != (n & 1)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fxort (n)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7.c new file mode 100644 index 0000000..cc14996 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +int p[128]; + +bool __attribute__((noipa)) +fxort () +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf () +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8-run.c new file mode 100644 index 0000000..bf73da5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8-run.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +long long p[128]; + +bool __attribute__((noipa)) +fxort (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fxort (n) != !(n & 1)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n) != (n & 1)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fxort (n)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8.c new file mode 100644 index 0000000..6842f39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +long long p[128]; + +bool __attribute__((noipa)) +fxort () +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf () +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c index 14a961d..1b7a0d8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c index 738caa8..8e2c631 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c index 1e7a977..a16623e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c @@ -32,3 +32,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c index 70257d3..be50b83 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c index bced156..fb50bae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c index cfb52fb..d79e0e0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c index 31846ef..6cdaf5d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c index ea28e2b..9e3879a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c index e3cddc4..e3ef3e3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c index c5cce62..20039c7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c @@ -28,4 +28,5 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c index 6ef8681..c973ea7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c index cc78959..e781c62 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h index 764f301..a9bba40 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h @@ -404,6 +404,7 @@ DEF_AVG_CEIL(int32_t, int64_t) DEF_VX_BINARY_CASE_0_WRAP(T, %, rem) \ DEF_VX_BINARY_CASE_0_WRAP(T, ==, eq) \ DEF_VX_BINARY_CASE_0_WRAP(T, !=, ne) \ + DEF_VX_BINARY_CASE_0_WRAP(T, <, lt) \ DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \ DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \ DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h index d4834c7..fad479a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -6566,4 +6566,140 @@ uint64_t TEST_BINARY_DATA(uint64_t, ltu)[][3][N] = }, }; +int8_t TEST_BINARY_DATA(int8_t, lt)[][3][N] = +{ + { + { 127 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 127, 127, 127, 127, + -128, -128, -128, -128, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -128, -128, -128, -128, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, lt)[][3][N] = +{ + { + { 32767 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -32768, -32768, -32768, -32768, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, lt)[][3][N] = +{ + { + { 2147483647 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, lt)[][3][N] = +{ + { + { 9223372036854775807ll }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i16.c new file mode 100644 index 0000000..865a2f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME lt + +DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i32.c new file mode 100644 index 0000000..eeb2a66 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i32.c @@ -0,0 +1,16 @@ + +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME lt + +DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i64.c new file mode 100644 index 0000000..c3a2052 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME lt + +DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i8.c new file mode 100644 index 0000000..92a84f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME lt + +DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gfortran.dg/assumed_charlen_dummy.f90 b/gcc/testsuite/gfortran.dg/assumed_charlen_dummy.f90 index 04f0b9f..2e0e77c 100644 --- a/gcc/testsuite/gfortran.dg/assumed_charlen_dummy.f90 +++ b/gcc/testsuite/gfortran.dg/assumed_charlen_dummy.f90 @@ -1,4 +1,5 @@ ! { dg-do compile } +! { dg-options " " } ! Test the fix for PR fortran/39893. ! Original testcase provided by Deji Akingunola. ! Reduced testcase provided by Dominique d'Humieres. diff --git a/gcc/testsuite/gfortran.dg/automatic_char_len_1.f90 b/gcc/testsuite/gfortran.dg/automatic_char_len_1.f90 index 3ccfcb7..7f102b7 100644 --- a/gcc/testsuite/gfortran.dg/automatic_char_len_1.f90 +++ b/gcc/testsuite/gfortran.dg/automatic_char_len_1.f90 @@ -1,4 +1,5 @@ ! { dg-do compile } +! { dg-options " " } ! PR18082 - Compiler would get stuck in loop, whilst treating ! the assignments. ! Test is one of PR cases. diff --git a/gcc/testsuite/gfortran.dg/entry_23.f b/gcc/testsuite/gfortran.dg/entry_23.f index ebc5f66..d10ea92 100644 --- a/gcc/testsuite/gfortran.dg/entry_23.f +++ b/gcc/testsuite/gfortran.dg/entry_23.f @@ -1,4 +1,5 @@ ! { dg-do run } +! { dg-options " " } ! PR 97799 - this used to segfault intermittently. ! Test case by George Hockney. PROGRAM MAIN diff --git a/gcc/testsuite/gfortran.dg/finalize_59.f90 b/gcc/testsuite/gfortran.dg/finalize_59.f90 index 8be5f71..e9e68d4 100644 --- a/gcc/testsuite/gfortran.dg/finalize_59.f90 +++ b/gcc/testsuite/gfortran.dg/finalize_59.f90 @@ -187,7 +187,7 @@ Program Cds_Principal Type(Uef_Vector) :: Cds_Mod_Les_materiaux Type (Cds_Materiau_Acier_EC) :: acier_ec Class (Cds_Materiau), pointer :: pt_materiau - Character *(8) :: nom_materiau + Character(len=8) :: nom_materiau !------------------------------------------------------------------------------------------------- CaLL Cds_Mod_Les_materiaux%Add (acier_ec) nom_materiau = "12345678" @@ -199,7 +199,7 @@ Function Get_Pt_Materiau_nom (vecteur, nom_materiau) ! Fonction : !-------------------- ! Parametres en entree - Character *(8), Intent (in) :: nom_materiau + Character(len=8), Intent (in) :: nom_materiau Type (Uef_Vector) , Intent (inout) :: vecteur ! Parametres en sortie diff --git a/gcc/testsuite/gfortran.dg/g77/f90-intrinsic-bit.f b/gcc/testsuite/gfortran.dg/g77/f90-intrinsic-bit.f index 0ce45de..2f03db1 100644 --- a/gcc/testsuite/gfortran.dg/g77/f90-intrinsic-bit.f +++ b/gcc/testsuite/gfortran.dg/g77/f90-intrinsic-bit.f @@ -1,4 +1,5 @@ c { dg-do run } +c { dg-options " " } c f90-intrinsic-bit.f c c Test Fortran 90 diff --git a/gcc/testsuite/gfortran.dg/g77/f90-intrinsic-mathematical.f b/gcc/testsuite/gfortran.dg/g77/f90-intrinsic-mathematical.f index d151fd0..f07336e 100644 --- a/gcc/testsuite/gfortran.dg/g77/f90-intrinsic-mathematical.f +++ b/gcc/testsuite/gfortran.dg/g77/f90-intrinsic-mathematical.f @@ -1,4 +1,5 @@ c { dg-do run } +c { dg-options " " } c f90-intrinsic-mathematical.f c c Test Fortran 90 intrinsic mathematical functions - Section 13.10.3 and diff --git a/gcc/testsuite/gfortran.dg/g77/f90-intrinsic-numeric.f b/gcc/testsuite/gfortran.dg/g77/f90-intrinsic-numeric.f index c8d7c56..c01efe6 100644 --- a/gcc/testsuite/gfortran.dg/g77/f90-intrinsic-numeric.f +++ b/gcc/testsuite/gfortran.dg/g77/f90-intrinsic-numeric.f @@ -1,4 +1,5 @@ c { dg-do run } +c { dg-options " " } c f90-intrinsic-numeric.f c c Test Fortran 90 intrinsic numeric functions - Section 13.10.2 and 13.13 diff --git a/gcc/testsuite/gfortran.dg/g77/intrinsic-unix-bessel.f b/gcc/testsuite/gfortran.dg/g77/intrinsic-unix-bessel.f index b388806..406a8e4 100644 --- a/gcc/testsuite/gfortran.dg/g77/intrinsic-unix-bessel.f +++ b/gcc/testsuite/gfortran.dg/g77/intrinsic-unix-bessel.f @@ -1,4 +1,5 @@ c { dg-do run } +c { dg-options " " } c intrinsic-unix-bessel.f c c Test Bessel function intrinsics. diff --git a/gcc/testsuite/gfortran.dg/g77/intrinsic-unix-erf.f b/gcc/testsuite/gfortran.dg/g77/intrinsic-unix-erf.f index 250519a..6ed9590 100644 --- a/gcc/testsuite/gfortran.dg/g77/intrinsic-unix-erf.f +++ b/gcc/testsuite/gfortran.dg/g77/intrinsic-unix-erf.f @@ -1,4 +1,5 @@ c { dg-do run } +c { dg-options " " } c intrinsic-unix-erf.f c c Test Bessel function intrinsics. diff --git a/gcc/testsuite/gfortran.dg/initialization_9.f90 b/gcc/testsuite/gfortran.dg/initialization_9.f90 index d904047..fe7ca63 100644 --- a/gcc/testsuite/gfortran.dg/initialization_9.f90 +++ b/gcc/testsuite/gfortran.dg/initialization_9.f90 @@ -1,4 +1,5 @@ ! { dg-do compile } +! { dg-options " " } ! ! PR fortran/31639 ! Contributed by Martin Michlmayr <tbm AT cyrius DOT com> diff --git a/gcc/testsuite/gfortran.dg/intrinsic_actual_4.f90 b/gcc/testsuite/gfortran.dg/intrinsic_actual_4.f90 index 4521c96..3358b4a 100644 --- a/gcc/testsuite/gfortran.dg/intrinsic_actual_4.f90 +++ b/gcc/testsuite/gfortran.dg/intrinsic_actual_4.f90 @@ -1,4 +1,5 @@ ! { dg-do run } +! { dg-options " " } ! Tests the fix for PR27900, in which an ICE would be caused because ! the actual argument LEN had no type. ! diff --git a/gcc/testsuite/gfortran.dg/namelist_assumed_char.f90 b/gcc/testsuite/gfortran.dg/namelist_assumed_char.f90 index b7d063c..25edf64 100644 --- a/gcc/testsuite/gfortran.dg/namelist_assumed_char.f90 +++ b/gcc/testsuite/gfortran.dg/namelist_assumed_char.f90 @@ -8,7 +8,7 @@ ! Add -std=f95, add bar() ! subroutine foo(c) - character*(*) c + character*(*) c ! { dg-warning "Old-style character length" } namelist /abc/ c ! { dg-error "nonconstant character length in namelist" } end subroutine diff --git a/gcc/testsuite/gfortran.dg/pr15140.f90 b/gcc/testsuite/gfortran.dg/pr15140.f90 index 80c08dd..7f9af4f 100644 --- a/gcc/testsuite/gfortran.dg/pr15140.f90 +++ b/gcc/testsuite/gfortran.dg/pr15140.f90 @@ -1,4 +1,5 @@ ! { dg-do run } +! { dg-options "-std=legacy" } ! PR 15140: we used to fail an assertion, because we don't use the ! argument of the subroutine directly, but instead use a copy of it. function M(NAMES) diff --git a/gcc/testsuite/gnat.dg/reduce3.adb b/gcc/testsuite/gnat.dg/reduce3.adb new file mode 100644 index 0000000..55934d0 --- /dev/null +++ b/gcc/testsuite/gnat.dg/reduce3.adb @@ -0,0 +1,17 @@ +-- { dg-do run } +-- { dg-options "-gnat2022" } + +with Ada.Containers.Vectors; + +procedure Reduce3 is + + package Qs is new + Ada.Containers.Vectors (Index_Type => Positive, Element_Type => Positive); + + V : Qs.Vector; + Sum : Positive; + +begin + V.Append (1); + Sum := V'Reduce ("+", 0); +end; |