diff options
Diffstat (limited to 'gcc/testsuite')
79 files changed, 1493 insertions, 19 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 905bbb0..ff68455 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,70 @@ +2025-06-02 Alexandre Oliva <oliva@adacore.com> + + PR rtl-optimization/120424 + PR middle-end/118939 + * g++.target/arm/pr120424.C: New. + * gnat.dg/controlled9.adb: New. + * gnat.dg/controlled9_pkg.ads: New. + +2025-06-02 Jason Merrill <jason@redhat.com> + + PR c++/107600 + * g++.dg/ext/is_destructible2.C: Add more cases. + +2025-06-02 Dongyan Chen <chendongyan@isrc.iscas.ac.cn> + + * gcc.target/riscv/arch-59.c: New test. + +2025-06-02 Jason Merrill <jason@redhat.com> + + PR c++/120506 + * g++.dg/cpp2a/constinit21.C: New test. + +2025-06-02 Iain Sandoe <iain@sandoe.co.uk> + + PR c++/118903 + * g++.dg/coroutines/pr118903.C: New test. + +2025-06-02 Jason Merrill <jason@redhat.com> + + PR c++/107600 + * g++.dg/ext/is_destructible2.C: New test. + +2025-06-02 Jason Merrill <jason@redhat.com> + + PR c++/107600 + * g++.dg/ext/has_trivial_destructor-3.C: New test. + +2025-06-02 Stafford Horne <shorne@gmail.com> + + * gcc.target/or1k/return-2.c: Fix test. + +2025-06-02 Stafford Horne <shorne@gmail.com> + + * gcc.target/or1k/call-1.c: New test. + * gcc.target/or1k/got-1.c: New test. + +2025-06-02 Christophe Lyon <christophe.lyon@linaro.org> + + * lib/target-supports.exp (check_effective_target_tls_link): New. + * g++.dg/tls/pr102496-1.C: Require tls_link. + * g++.dg/tls/pr77285-1.C: Likewise. + +2025-06-02 Sandra Loosemore <sloosemore@baylibre.com> + + * c-c++-common/gomp/declare-variant-2.c: Update expected output. + * c-c++-common/gomp/metadirective-condition-constexpr.c: New. + * c-c++-common/gomp/metadirective-condition.c: New. + * c-c++-common/gomp/metadirective-error-recovery.c: Update expected + output. + * g++.dg/gomp/metadirective-condition-class.C: New. + * g++.dg/gomp/metadirective-condition-template.C: New. + +2025-06-02 Liao Shihua <shihua@iscas.ac.cn> + + * gcc.target/riscv/rvv/autovec/param-autovec-mode.c: Change + `autovec-mode` to `riscv-autovec-mode` in dg-options. + 2025-06-01 Jerry DeLisle <jvdelisle@gcc.gnu.org> PR libfortran/119856 diff --git a/gcc/testsuite/g++.dg/coroutines/pr118903.C b/gcc/testsuite/g++.dg/coroutines/pr118903.C new file mode 100644 index 0000000..a577a9a --- /dev/null +++ b/gcc/testsuite/g++.dg/coroutines/pr118903.C @@ -0,0 +1,40 @@ +// { dg-additional-options "-fsyntax-only" } + +#include <coroutine> + +struct awaitable { + constexpr bool await_ready() { + return true; + } + void await_suspend(std::coroutine_handle<void>) { + + } + constexpr int await_resume() { + return 42; + } +}; + +struct super_simple_coroutine { + struct promise_type { + constexpr auto initial_suspend() { + return std::suspend_never(); + } + constexpr auto final_suspend() const noexcept { + return std::suspend_never(); + } + constexpr void unhandled_exception() { + // do nothing + } + constexpr auto get_return_object() { + return super_simple_coroutine{}; + } + constexpr void return_void() { + } + }; +}; + +auto fib (float f) -> super_simple_coroutine { + // if `co_await` is part of BodyStatement of a function + // it makes it coroutine + constexpr int x = co_await awaitable{}; // { dg-error {'co_await awaitable..' is not a constant expression} } +} diff --git a/gcc/testsuite/g++.dg/cpp2a/constinit21.C b/gcc/testsuite/g++.dg/cpp2a/constinit21.C new file mode 100644 index 0000000..18bca90 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/constinit21.C @@ -0,0 +1,28 @@ +// PR c++/120506 +// { dg-do compile { target c++20 } } +// Test that we give more information about why the init is non-constant + +struct A +{ + constexpr A(int c) : counter(c) { } + + int counter; +}; + + +struct B : A +{ + constexpr B(int c) : A(c) { } + + int i; // OOPS, not initialized +}; + +struct C +{ + B sem; + + constexpr C(int c) : sem(c) { } +}; + +constinit C s(0); // { dg-error "incompletely initialized" } +// { dg-prune-output "constant" } diff --git a/gcc/testsuite/g++.dg/ext/has_trivial_destructor-3.C b/gcc/testsuite/g++.dg/ext/has_trivial_destructor-3.C new file mode 100644 index 0000000..a179be5 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/has_trivial_destructor-3.C @@ -0,0 +1,21 @@ +// { dg-do compile { target c++11 } } + +struct X; + +template<class T> +struct default_delete +{ + void operator()(T*) { static_assert(sizeof(T), "type is not incomplete"); } +}; + +template<class T, class D = default_delete<T>> +struct unique_ptr +{ + ~unique_ptr() { del(ptr); } + + T* ptr; + D del; +}; + + +constexpr bool b = __has_trivial_destructor(unique_ptr<X>); diff --git a/gcc/testsuite/g++.dg/ext/is_destructible2.C b/gcc/testsuite/g++.dg/ext/is_destructible2.C new file mode 100644 index 0000000..2edf440 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/is_destructible2.C @@ -0,0 +1,24 @@ +// PR c++/107600 +// { dg-additional-options -Wno-c++17-extensions } +// { dg-do compile { target c++11 } } + +struct A +{ + A& operator= (const A&); + virtual ~A() = 0; +}; + +static_assert( __is_destructible(A) ); +static_assert( __is_assignable(A, A) ); +static_assert( not __is_destructible(int()) ); +static_assert( not __is_nothrow_destructible(int()) ); +static_assert( not __is_trivially_destructible(int()) ); +static_assert( __is_destructible(int&) ); +static_assert( __is_destructible(int&&) ); +static_assert( __is_destructible(int(&)[1]) ); +static_assert( __is_destructible(const int(&)[1]) ); +static_assert( __is_destructible(void(&)()) ); +static_assert( not __is_destructible(int[]) ); +static_assert( not __is_destructible(const int[]) ); +static_assert( not __is_destructible(int[][1]) ); +static_assert( not __is_destructible(const int[][1]) ); diff --git a/gcc/testsuite/g++.dg/modules/cpp-1.C b/gcc/testsuite/g++.dg/modules/cpp-1.C index 2ad9637..56ef05fe 100644 --- a/gcc/testsuite/g++.dg/modules/cpp-1.C +++ b/gcc/testsuite/g++.dg/modules/cpp-1.C @@ -1,4 +1,5 @@ // { dg-do preprocess } +// { dg-additional-options -fno-modules } module bob; #if 1 @@ -11,4 +12,4 @@ import gru; EXPORT import mabel; int i; -// { dg-final { scan-file cpp-1.i "cpp-1.C\"\n\n\nmodule bob;\n\nexport import stuart;\n\n\n\nimport gru;\n\n import mabel;\n" } } +// { dg-final { scan-file cpp-1.i "cpp-1.C\"\n\n\n\nmodule bob;\n\nexport import stuart;\n\n\n\nimport gru;\n\n import mabel;\n" } } diff --git a/gcc/testsuite/g++.dg/modules/cpp-3.C b/gcc/testsuite/g++.dg/modules/cpp-3.C index 3aa0c6e..cd776ae 100644 --- a/gcc/testsuite/g++.dg/modules/cpp-3.C +++ b/gcc/testsuite/g++.dg/modules/cpp-3.C @@ -1,4 +1,5 @@ // { dg-do preprocess } +// { dg-additional-options -fno-modules } #define NAME(X) X; diff --git a/gcc/testsuite/g++.dg/modules/cpp-4.C b/gcc/testsuite/g++.dg/modules/cpp-4.C index 6c19431..c423de2 100644 --- a/gcc/testsuite/g++.dg/modules/cpp-4.C +++ b/gcc/testsuite/g++.dg/modules/cpp-4.C @@ -1,3 +1,4 @@ +// { dg-additional-options -fno-modules } // { dg-do preprocess } #if 1 diff --git a/gcc/testsuite/g++.dg/tls/pr102496-1.C b/gcc/testsuite/g++.dg/tls/pr102496-1.C index 8220e1e..e015ae9 100644 --- a/gcc/testsuite/g++.dg/tls/pr102496-1.C +++ b/gcc/testsuite/g++.dg/tls/pr102496-1.C @@ -1,6 +1,6 @@ // PR c++/102496 // { dg-do link { target c++11 } } -// { dg-require-effective-target tls } +// { dg-require-effective-target tls_link } // { dg-add-options tls } // { dg-additional-sources pr102496-2.C } diff --git a/gcc/testsuite/g++.dg/tls/pr77285-1.C b/gcc/testsuite/g++.dg/tls/pr77285-1.C index 7a93414..340c88b 100644 --- a/gcc/testsuite/g++.dg/tls/pr77285-1.C +++ b/gcc/testsuite/g++.dg/tls/pr77285-1.C @@ -1,5 +1,5 @@ // { dg-do link { target c++11 } } -// { dg-require-effective-target tls } +// { dg-require-effective-target tls_link } // { dg-add-options tls } // { dg-additional-sources pr77285-2.C } diff --git a/gcc/testsuite/g++.target/arm/pr120424.C b/gcc/testsuite/g++.target/arm/pr120424.C new file mode 100644 index 0000000..4d0e490 --- /dev/null +++ b/gcc/testsuite/g++.target/arm/pr120424.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv7 -O2 -fstack-clash-protection -fnon-call-exceptions" } */ +/* { dg-final { scan-assembler-not {#-8} } } */ +/* LRA register elimination gets confused when register spilling + causes arm_frame_pointer_required to switch from false to true, and + ends up using a stack slot below sp. */ + +void f() { + int i = 0, j = 0; + asm ("" : : "m" (i), "m" (j)); +} + +void g(void (*fn[])(), int i) +{ + auto fn0 = fn[i+0]; + auto fn1 = fn[i+1]; + auto fn2 = fn[i+2]; + auto fn3 = fn[i+3]; + fn0(); + fn1(); + if (!fn2) + throw i+2; + fn2(); + fn3(); + fn0(); + fn1(); +} + +int +main() +{ + void (*fn[4])() = { f, f, f, f }; + g (fn, 0); +} diff --git a/gcc/testsuite/g++.target/i386/pr103750.C b/gcc/testsuite/g++.target/i386/pr103750.C new file mode 100644 index 0000000..c82c10a --- /dev/null +++ b/gcc/testsuite/g++.target/i386/pr103750.C @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=x86-64-v4 -std=c++17" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +#include <x86intrin.h> + +/* +**_Z8qustrchrPDsS_Ds: +**... +**.L[0-9]+: +** vpcmpeqw \(%[a-x]+\), %ymm0, %k1 +** vpcmpeqw 32\(%[a-x]+\), %ymm0, %k0 +** kortestw %k0, %k1 +** je .L[0-9]+ +**... +*/ + +const char16_t * +qustrchr(char16_t *n, char16_t *e, char16_t c) noexcept +{ + __m256i mch256 = _mm256_set1_epi16(c); + for ( ; n < e; n += 32) { + __m256i data1 = _mm256_loadu_si256(reinterpret_cast<const __m256i *>(n)); + __m256i data2 = _mm256_loadu_si256(reinterpret_cast<const __m256i *>(n) + 1); + __mmask16 mask1 = _mm256_cmpeq_epu16_mask(data1, mch256); + __mmask16 mask2 = _mm256_cmpeq_epu16_mask(data2, mch256); + if (_kortestz_mask16_u8(mask1, mask2)) + continue; + + unsigned idx = _tzcnt_u32(mask1); + if (mask1 == 0) { + idx = __tzcnt_u16(mask2); + n += 16; + } + return n + idx; + } + return e; +} diff --git a/gcc/testsuite/gcc.dg/Wjump-misses-init-3.c b/gcc/testsuite/gcc.dg/Wjump-misses-init-3.c new file mode 100644 index 0000000..c3110c4 --- /dev/null +++ b/gcc/testsuite/gcc.dg/Wjump-misses-init-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-Wc++-compat" } */ + +void f() +{ + goto skip; /* { dg-warning "jump skips variable initialization" } */ + int i = 1; +skip: ; +} + diff --git a/gcc/testsuite/gcc.dg/gnu23-tag-composite-6.c b/gcc/testsuite/gcc.dg/gnu23-tag-composite-6.c index 2411b04..076c066 100644 --- a/gcc/testsuite/gcc.dg/gnu23-tag-composite-6.c +++ b/gcc/testsuite/gcc.dg/gnu23-tag-composite-6.c @@ -1,11 +1,31 @@ /* { dg-do compile } */ /* { dg-options "-std=gnu23" } */ +#define NEST(...) typeof(({ (__VA_ARGS__){ }; })) + int f() { typedef struct foo bar; - struct foo { typeof(({ (struct foo { bar * x; }){ }; })) * x; } *q; - typeof(q->x) p; - 1 ? p : q; + struct foo { NEST(struct foo { bar *x; }) *x; } *q; + typeof(q->x) p0; + typeof(q->x) p1; + 1 ? p0 : q; + 1 ? p1 : q; + 1 ? p0 : p1; +} + +int g() +{ + typedef struct fo2 bar; + struct fo2 { NEST(struct fo2 { NEST(struct fo2 { bar *x; }) * x; }) *x; } *q; + typeof(q->x) p0; + typeof(q->x->x) p1; + typeof(q->x->x->x) p2; + 1 ? p0 : q; + 1 ? p1 : q; + 1 ? p2 : q; + 1 ? p0 : p1; + 1 ? p2 : p1; + 1 ? p0 : p2; } diff --git a/gcc/testsuite/gcc.dg/pr116892.c b/gcc/testsuite/gcc.dg/pr116892.c new file mode 100644 index 0000000..7eb431b --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr116892.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-g -std=gnu23" } */ + +enum fmt_type; + +void foo(const enum fmt_type a); + +enum [[gnu::packed]] fmt_type { + A +} const a; + diff --git a/gcc/testsuite/gcc.dg/tree-ssa/cswtch-6.c b/gcc/testsuite/gcc.dg/tree-ssa/cswtch-6.c new file mode 100644 index 0000000..d765a03 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/cswtch-6.c @@ -0,0 +1,43 @@ +/* PR tree-optimization/120451 */ +/* { dg-do compile { target elf } } */ +/* { dg-options "-O2" } */ + +void foo (int, int); + +__attribute__((noinline, noclone)) void +f1 (int v, int w) +{ + int i, j; + if (w) + { + i = 129; + j = i - 1; + goto lab; + } + switch (v) + { + case 170: + j = 7; + i = 27; + break; + case 171: + i = 8; + j = 122; + break; + case 172: + i = 21; + j = -19; + break; + case 173: + i = 18; + j = 17; + break; + default: + __builtin_abort (); + } + + lab: + foo (i, j); +} + +/* { dg-final { scan-assembler ".rodata.cst16" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/phiprop-2.c b/gcc/testsuite/gcc.dg/tree-ssa/phiprop-2.c new file mode 100644 index 0000000..7181787 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/phiprop-2.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -fdump-tree-phiopt2 -fdump-tree-phiprop1-details" } */ + +/* PR tree-optimization/116824 */ + +int g(int i, int *tt) +{ + const int t = 10; + const int *a; + { + if (t < i) + { + *tt = 1; + a = &t; + } + else + { + *tt = 1; + a = &i; + } + } + return *a; +} + +/* Check that phiprop1 can do the insert of the loads. */ +/* { dg-final { scan-tree-dump-times "Inserting PHI for result of load" 1 "phiprop1"} } */ +/* Should be able to get MIN_EXPR in phiopt2 after cselim and phiprop. */ +/* { dg-final { scan-tree-dump-times "MIN_EXPR " 1 "phiopt2" } } */ diff --git a/gcc/testsuite/gcc.target/or1k/call-1.c b/gcc/testsuite/gcc.target/or1k/call-1.c new file mode 100644 index 0000000..593e402 --- /dev/null +++ b/gcc/testsuite/gcc.target/or1k/call-1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcmodel=large" } */ + +/* Generate local and global function calls. */ + +extern int geti (void); + +__attribute__ ((noinline)) int +calc (int a, int b) +{ + return a * b + 255; +} + +int +main (void) +{ + return geti () + calc (3, 4); +} + +/* Ensure the 2 calls use register not immediate jumps. */ +/* { dg-final { scan-assembler-times "l.movhi\\s+" 2 } } */ +/* { dg-final { scan-assembler-times "l.jalr\\s+" 2 } } */ diff --git a/gcc/testsuite/gcc.target/or1k/got-1.c b/gcc/testsuite/gcc.target/or1k/got-1.c new file mode 100644 index 0000000..5357096 --- /dev/null +++ b/gcc/testsuite/gcc.target/or1k/got-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fPIC -mcmodel=large" } */ + +/* Generate references to the GOT. */ + +extern int geti (void); +extern int j; + +int +calc (int a) +{ + return a * j + geti (); +} + +/* Ensure the 2 references use gotha relocations and that the function call does + not use an immediate jump instruction. */ +/* { dg-final { scan-assembler-times "gotha" 2 } } */ +/* { dg-final { scan-assembler "l.jalr\\s+" } } */ diff --git a/gcc/testsuite/gcc.target/or1k/return-2.c b/gcc/testsuite/gcc.target/or1k/return-2.c index add3720..c072ae2 100644 --- a/gcc/testsuite/gcc.target/or1k/return-2.c +++ b/gcc/testsuite/gcc.target/or1k/return-2.c @@ -16,4 +16,4 @@ struct a getstruct (long aa) { /* Ensure our return value is returned on stack. */ /* { dg-final { scan-assembler-not "r12," } } */ /* { dg-final { scan-assembler "l.or\\s+r11, r3, r3" } } */ -/* { dg-final { scan-assembler-times "l.sw\\s+\\d+.r11.," 3 } } */ +/* { dg-final { scan-assembler-times "l.sw\\s+\\d+.r3.," 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-59.c b/gcc/testsuite/gcc.target/riscv/arch-59.c new file mode 100644 index 0000000..511cf22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-59.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_smcntrpmf -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c index 0750d8e..4685ed2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c @@ -3,13 +3,13 @@ #include "vdiv-template.h" -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvdiv\.vx} 3 } } */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ /* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */ /* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfdiv\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfdiv\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 16 "optimized" } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 6 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c index 31b2284..59c48d2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c @@ -3,8 +3,8 @@ #include "vdiv-template.h" -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvdiv\.vx} 3 } } */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ /* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */ /* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c index 6015af9..b574dc4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c @@ -3,13 +3,13 @@ #include "vdiv-template.h" -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdiv\.vx} 4 } } */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ /* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ /* { dg-final { scan-assembler-times {\tvdivu\.vx} 4 } } */ -/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfdiv\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfdiv\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 16 "optimized" } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 6 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c index ccaa2f8..9b46c6b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c @@ -3,8 +3,8 @@ #include "vdiv-template.h" -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdiv\.vx} 4 } } */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ /* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ /* { dg-final { scan-assembler-times {\tvdivu\.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c new file mode 100644 index 0000000..821e5c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_0(_Float16, +, add) +DEF_VF_MULOP_CASE_0(_Float16, -, sub) + +/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c new file mode 100644 index 0000000..49b4287 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_0(float, +, add) +DEF_VF_MULOP_CASE_0(float, -, sub) + +/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c new file mode 100644 index 0000000..2bb5d89 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_0(double, +, add) +DEF_VF_MULOP_CASE_0(double, -, sub) + +/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c new file mode 100644 index 0000000..cbb43ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=1" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_0(_Float16, +, add) +DEF_VF_MULOP_CASE_0(_Float16, -, sub) + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c new file mode 100644 index 0000000..66ff9b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=1" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_0(float, +, add) +DEF_VF_MULOP_CASE_0(float, -, sub) + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c new file mode 100644 index 0000000..66ff9b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=1" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_0(float, +, add) +DEF_VF_MULOP_CASE_0(float, -, sub) + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c new file mode 100644 index 0000000..45980f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_1(_Float16, +, add, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1(_Float16, -, sub, VF_MULOP_BODY_X16) + +/* { dg-final { scan-assembler {vfmadd.vf} } } */ +/* { dg-final { scan-assembler {vfmsub.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c new file mode 100644 index 0000000..c853620 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_1(float, +, add, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1(float, -, sub, VF_MULOP_BODY_X16) + +/* { dg-final { scan-assembler {vfmadd.vf} } } */ +/* { dg-final { scan-assembler {vfmsub.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c new file mode 100644 index 0000000..d38ae8b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_1(double, +, add, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1(double, -, sub, VF_MULOP_BODY_X16) + +/* { dg-final { scan-assembler {vfmadd.vf} } } */ +/* { dg-final { scan-assembler {vfmsub.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c new file mode 100644 index 0000000..f1ca34e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_1(_Float16, +, add, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1(_Float16, -, sub, VF_MULOP_BODY_X16) + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c new file mode 100644 index 0000000..6730d4b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_1(float, +, add, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1(float, -, sub, VF_MULOP_BODY_X16) + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c new file mode 100644 index 0000000..bcb6a6e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_1(double, +, add, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1(double, -, sub, VF_MULOP_BODY_X16) + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h new file mode 100644 index 0000000..5253978 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h @@ -0,0 +1,61 @@ +#ifndef HAVE_DEFINED_VF_MULOP_H +#define HAVE_DEFINED_VF_MULOP_H + +#include <stdint.h> + +#define DEF_VF_MULOP_CASE_0(T, OP, NAME) \ + void test_vf_mulop_##NAME##_##T##_case_0(T *restrict out, T *restrict in, \ + T x, unsigned n) { \ + for (unsigned i = 0; i < n; i++) \ + out[i] = in[i] OP out[i] * x; \ + } +#define DEF_VF_MULOP_CASE_0_WRAP(T, OP, NAME) DEF_VF_MULOP_CASE_0(T, OP, NAME) +#define RUN_VF_MULOP_CASE_0(T, NAME, out, in, x, n) \ + test_vf_mulop_##NAME##_##T##_case_0(out, in, x, n) +#define RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) \ + RUN_VF_MULOP_CASE_0(T, NAME, out, in, x, n) + +#define VF_MULOP_BODY(op) \ + out[k + 0] = in[k + 0] op tmp * out[k + 0]; \ + out[k + 1] = in[k + 1] op tmp * out[k + 1]; \ + k += 2; + +#define VF_MULOP_BODY_X4(op) \ + VF_MULOP_BODY(op) \ + VF_MULOP_BODY(op) + +#define VF_MULOP_BODY_X8(op) \ + VF_MULOP_BODY_X4(op) \ + VF_MULOP_BODY_X4(op) + +#define VF_MULOP_BODY_X16(op) \ + VF_MULOP_BODY_X8(op) \ + VF_MULOP_BODY_X8(op) + +#define VF_MULOP_BODY_X32(op) \ + VF_MULOP_BODY_X16(op) \ + VF_MULOP_BODY_X16(op) + +#define VF_MULOP_BODY_X64(op) \ + VF_MULOP_BODY_X32(op) \ + VF_MULOP_BODY_X32(op) + +#define VF_MULOP_BODY_X128(op) \ + VF_MULOP_BODY_X64(op) \ + VF_MULOP_BODY_X64(op) + +#define DEF_VF_MULOP_CASE_1(T, OP, NAME, BODY) \ + void test_vf_mulop_##NAME##_##T##_case_1(T *restrict out, T *restrict in, \ + T x, unsigned n) { \ + unsigned k = 0; \ + T tmp = x + 3; \ + \ + while (k < n) { \ + tmp = tmp * 0x3f; \ + BODY(OP) \ + } \ + } +#define DEF_VF_MULOP_CASE_1_WRAP(T, OP, NAME, BODY) \ + DEF_VF_MULOP_CASE_1(T, OP, NAME, BODY) + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_data.h new file mode 100644 index 0000000..c16c1a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_data.h @@ -0,0 +1,413 @@ +#ifndef HAVE_DEFINED_VF_MULOP_DATA_H +#define HAVE_DEFINED_VF_MULOP_DATA_H + +#define N 16 + +#define TEST_MULOP_DATA(T, NAME) test_##T##_##NAME##_data +#define TEST_MULOP_DATA_WRAP(T, NAME) TEST_MULOP_DATA(T, NAME) + + +_Float16 TEST_MULOP_DATA(_Float16, add)[][4][N] = +{ + { + { 0.30f16 }, + { + 1.48f16, 1.48f16, 1.48f16, 1.48f16, + 0.80f16, 0.80f16, 0.80f16, 0.80f16, + 0.62f16, 0.62f16, 0.62f16, 0.62f16, + 1.18f16, 1.18f16, 1.18f16, 1.18f16, + }, + { + 1.25f16, 1.25f16, 1.25f16, 1.25f16, + 1.89f16, 1.89f16, 1.89f16, 1.89f16, + 1.57f16, 1.57f16, 1.57f16, 1.57f16, + 1.21f16, 1.21f16, 1.21f16, 1.21f16, + }, + { + 1.85f16, 1.85f16, 1.85f16, 1.85f16, + 1.37f16, 1.37f16, 1.37f16, 1.37f16, + 1.09f16, 1.09f16, 1.09f16, 1.09f16, + 1.54f16, 1.54f16, 1.54f16, 1.54f16, + } + }, + { + { -0.505f16 }, + { + -2.38f16, -2.38f16, -2.38f16, -2.38f16, + -2.06f16, -2.06f16, -2.06f16, -2.06f16, + -1.69f16, -1.69f16, -1.69f16, -1.69f16, + -1.1f16, -1.1f16, -1.1f16, -1.1f16, + }, + { + -1.77f16, -1.77f16, -1.77f16, -1.77f16, + -1.6f16, -1.6f16, -1.6f16, -1.6f16, + -1.f16, -1.f16, -1.f16, -1.f16, + -1.23f16, -1.23f16, -1.23f16, -1.23f16, + }, + { + -1.49f16, -1.49f16, -1.49f16, -1.49f16, + -1.25f16, -1.25f16, -1.25f16, -1.25f16, + -1.18f16, -1.18f16, -1.18f16, -1.18f16, + -0.479f16, -0.479f16, -0.479f16, -0.479f16, + } + }, + { + { 4.95e-04f16 }, + { + 1.4266e-05f16, 1.4266e-05f16, 1.4266e-05f16, 1.4266e-05f16, + 1.8129e-05f16, 1.8129e-05f16, 1.8129e-05f16, 1.8129e-05f16, + -8.4710e-06f16, -8.4710e-06f16, -8.4710e-06f16, -8.4710e-06f16, + 3.7876e-05f16, 3.7876e-05f16, 3.7876e-05f16, 3.7876e-05f16, + }, + { + 2.2808e-02f16, 2.2808e-02f16, 2.2808e-02f16, 2.2808e-02f16, + 3.9633e-02f16, 3.9633e-02f16, 3.9633e-02f16, 3.9633e-02f16, + 9.9657e-02f16, 9.9657e-02f16, 9.9657e-02f16, 9.9657e-02f16, + 7.7189e-02f16, 7.7189e-02f16, 7.7189e-02f16, 7.7189e-02f16, + }, + { + 2.5547e-05f16, 2.5547e-05f16, 2.5547e-05f16, 2.5547e-05f16, + 3.7732e-05f16, 3.7732e-05f16, 3.7732e-05f16, 3.7732e-05f16, + 4.0820e-05f16, 4.0820e-05f16, 4.0820e-05f16, 4.0820e-05f16, + 7.6054e-05f16, 7.6054e-05f16, 7.6054e-05f16, 7.6054e-05f16, + } + }, +}; + +float TEST_MULOP_DATA(float, add)[][4][N] = +{ + { + { 43.71f }, + { + -410.28f, -410.28f, -410.28f, -410.28f, + -276.91f, -276.91f, -276.91f, -276.91f, + -103.38f, -103.38f, -103.38f, -103.38f, + -378.24f, -378.24f, -378.24f, -378.24f, + }, + { + 9.56f, 9.56f, 9.56f, 9.56f, + 6.39f, 6.39f, 6.39f, 6.39f, + 2.40f, 2.40f, 2.40f, 2.40f, + 8.80f, 8.80f, 8.80f, 8.80f, + }, + { + 7.59f, 7.59f, 7.59f, 7.59f, + 2.40f, 2.40f, 2.40f, 2.40f, + 1.52f, 1.52f, 1.52f, 1.52f, + 6.41f, 6.41f, 6.41f, 6.41f, + } + }, + { + { 2.04f }, + { + -110.22f, -110.22f, -110.22f, -110.22f, + -25.13f, -25.13f, -25.13f, -25.13f, + -108.18f, -108.18f, -108.18f, -108.18f, + -107.14f, -107.14f, -107.14f, -107.14f, + }, + { + 64.82f, 64.82f, 64.82f, 64.82f, + 31.65f, 31.65f, 31.65f, 31.65f, + 87.32f, 87.32f, 87.32f, 87.32f, + 58.70f, 58.70f, 58.70f, 58.70f, + }, + { + 22.01f, 22.01f, 22.01f, 22.01f, + 39.44f, 39.44f, 39.44f, 39.44f, + 69.95f, 69.95f, 69.95f, 69.95f, + 12.61f, 12.61f, 12.61f, 12.61f, + } + }, + { + { 20.35f }, + { + 881.43f, 881.43f, 881.43f, 881.43f, + 3300.17f, 3300.17f, 3300.17f, 3300.17f, + 5217.85f, 5217.85f, 5217.85f, 5217.85f, + 66.57f, 66.57f, 66.57f, 66.57f, + }, + { + 64.82f, 64.82f, 64.82f, 64.82f, + 31.65f, 31.65f, 31.65f, 31.65f, + 87.32f, 87.32f, 87.32f, 87.32f, + 58.70f, 58.70f, 58.70f, 58.70f, + }, + { + 2200.52f, 2200.52f, 2200.52f, 2200.52f, + 3944.25f, 3944.25f, 3944.25f, 3944.25f, + 6994.81f, 6994.81f, 6994.81f, 6994.81f, + 1261.12f, 1261.12f, 1261.12f, 1261.12f, + } + }, +}; + +double TEST_MULOP_DATA(double, add)[][4][N] = +{ + { + { 1.16e+12 }, + { + 1.8757e+45, 1.8757e+45, 1.8757e+45, 1.8757e+45, + 7.5140e+45, 7.5140e+45, 7.5140e+45, 7.5140e+45, + 8.2069e+45, 8.2069e+45, 8.2069e+45, 8.2069e+45, + 4.9456e+45, 4.9456e+45, 4.9456e+45, 4.9456e+45, + }, + { + 9.0242e+32, 9.0242e+32, 9.0242e+32, 9.0242e+32, + 3.6908e+32, 3.6908e+32, 3.6908e+32, 3.6908e+32, + 3.9202e+32, 3.9202e+32, 3.9202e+32, 3.9202e+32, + 5.0276e+32, 5.0276e+32, 5.0276e+32, 5.0276e+32, + }, + { + 2.9201e+45, 2.9201e+45, 2.9201e+45, 2.9201e+45, + 7.9411e+45, 7.9411e+45, 7.9411e+45, 7.9411e+45, + 8.6606e+45, 8.6606e+45, 8.6606e+45, 8.6606e+45, + 5.5275e+45, 5.5275e+45, 5.5275e+45, 5.5275e+45, + } + }, + { + { -7.29e+23 }, + { + -6.4993e+65, -6.4993e+65, -6.4993e+65, -6.4993e+65, + -4.6760e+65, -4.6760e+65, -4.6760e+65, -4.6760e+65, + -8.1564e+65, -8.1564e+65, -8.1564e+65, -8.1564e+65, + -8.2899e+65, -8.2899e+65, -8.2899e+65, -8.2899e+65, + }, + { + -7.7764e+41, -7.7764e+41, -7.7764e+41, -7.7764e+41, + -1.9756e+41, -1.9756e+41, -1.9756e+41, -1.9756e+41, + -4.8980e+41, -4.8980e+41, -4.8980e+41, -4.8980e+41, + -8.1062e+41, -8.1062e+41, -8.1062e+41, -8.1062e+41, + }, + { + -8.2928e+64, -8.2928e+64, -8.2928e+64, -8.2928e+64, + -3.2356e+65, -3.2356e+65, -3.2356e+65, -3.2356e+65, + -4.5850e+65, -4.5850e+65, -4.5850e+65, -4.5850e+65, + -2.3794e+65, -2.3794e+65, -2.3794e+65, -2.3794e+65, + } + }, + { + { 2.02e-03 }, + { + -1.2191e-35, -1.2191e-35, -1.2191e-35, -1.2191e-35, + -1.0471e-36, -1.0471e-36, -1.0471e-36, -1.0471e-36, + -9.7582e-36, -9.7582e-36, -9.7582e-36, -9.7582e-36, + -2.2097e-36, -2.2097e-36, -2.2097e-36, -2.2097e-36, + }, + { + 9.7703e-33, 9.7703e-33, 9.7703e-33, 9.7703e-33, + 4.1632e-33, 4.1632e-33, 4.1632e-33, 4.1632e-33, + 8.1964e-33, 8.1964e-33, 8.1964e-33, 8.1964e-33, + 4.7314e-33, 4.7314e-33, 4.7314e-33, 4.7314e-33, + }, + { + 7.5586e-36, 7.5586e-36, 7.5586e-36, 7.5586e-36, + 7.3684e-36, 7.3684e-36, 7.3684e-36, 7.3684e-36, + 6.8101e-36, 6.8101e-36, 6.8101e-36, 6.8101e-36, + 7.3543e-36, 7.3543e-36, 7.3543e-36, 7.3543e-36, + } + }, +}; + +_Float16 TEST_MULOP_DATA(_Float16, sub)[][4][N] = +{ + { + { 0.676f16 }, + { + 1.39f16, 1.39f16, 1.39f16, 1.39f16, + 1.68f16, 1.68f16, 1.68f16, 1.68f16, + 1.63f16, 1.63f16, 1.63f16, 1.63f16, + 2.12f16, 2.12f16, 2.12f16, 2.12f16, + }, + { + 1.04f16, 1.04f16, 1.04f16, 1.04f16, + 1.64f16, 1.64f16, 1.64f16, 1.64f16, + 1.95f16, 1.95f16, 1.95f16, 1.95f16, + 1.39f16, 1.39f16, 1.39f16, 1.39f16, + }, + { + 0.687f16, 0.687f16, 0.687f16, 0.687f16, + 0.568f16, 0.568f16, 0.568f16, 0.568f16, + 0.315f16, 0.315f16, 0.315f16, 0.315f16, + 1.18f16, 1.18f16, 1.18f16, 1.18f16, + } +}, + { + { -0.324f16 }, + { + -0.679f16, -0.679f16, -0.679f16, -0.679f16, + -0.992f16, -0.992f16, -0.992f16, -0.992f16, + -1.34f16, -1.34f16, -1.34f16, -1.34f16, + -0.297f16, -0.297f16, -0.297f16, -0.297f16, + }, + { + -1.96f16, -1.96f16, -1.96f16, -1.96f16, + -1.36f16, -1.36f16, -1.36f16, -1.36f16, + -1.05f16, -1.05f16, -1.05f16, -1.05f16, + -1.61f16, -1.61f16, -1.61f16, -1.61f16, + }, + { + -1.31f16, -1.31f16, -1.31f16, -1.31f16, + -1.43f16, -1.43f16, -1.43f16, -1.43f16, + -1.68f16, -1.68f16, -1.68f16, -1.68f16, + -0.82f16, -0.82f16, -0.82f16, -0.82f16, + } + }, + { + { 7.08e+01f16 }, + { + 4.49e+03f16, 4.49e+03f16, 4.49e+03f16, 4.49e+03f16, + 7.73e+03f16, 7.73e+03f16, 7.73e+03f16, 7.73e+03f16, + 8.42e+03f16, 8.42e+03f16, 8.42e+03f16, 8.42e+03f16, + 9.12e+03f16, 9.12e+03f16, 9.12e+03f16, 9.12e+03f16, + }, + { + 1.40e+01f16, 1.40e+01f16, 1.40e+01f16, 1.40e+01f16, + 6.80e+01f16, 6.80e+01f16, 6.80e+01f16, 6.80e+01f16, + 9.54e+01f16, 9.54e+01f16, 9.54e+01f16, 9.54e+01f16, + 4.49e+01f16, 4.49e+01f16, 4.49e+01f16, 4.49e+01f16, + }, + { + 3.50e+03f16, 3.50e+03f16, 3.50e+03f16, 3.50e+03f16, + 2.91e+03f16, 2.91e+03f16, 2.91e+03f16, 2.91e+03f16, + 1.66e+03f16, 1.66e+03f16, 1.66e+03f16, 1.66e+03f16, + 5.94e+03f16, 5.94e+03f16, 5.94e+03f16, 5.94e+03f16, + } + }, +}; + +float TEST_MULOP_DATA(float, sub)[][4][N] = +{ + { + {8.51f }, + { + 24.21f, 24.21f, 24.21f, 24.21f, + 40.31f, 40.31f, 40.31f, 40.31f, + 59.68f, 59.68f, 59.68f, 59.68f, + 45.42f, 45.42f, 45.42f, 45.42f, + }, + { + 1.94f, 1.94f, 1.94f, 1.94f, + 4.24f, 4.24f, 4.24f, 4.24f, + 6.48f, 6.48f, 6.48f, 6.48f, + 4.68f, 4.68f, 4.68f, 4.68f, + }, + { + 7.70f, 7.70f, 7.70f, 7.70f, + 4.23f, 4.23f, 4.23f, 4.23f, + 4.54f, 4.54f, 4.54f, 4.54f, + 5.59f, 5.59f, 5.59f, 5.59f, + }, +}, + { + { 85.14f }, + { + 1731.29f, 1731.29f, 1731.29f, 1731.29f, + 3656.53f, 3656.53f, 3656.53f, 3656.53f, + 5565.07f, 5565.07f, 5565.07f, 5565.07f, + 4042.14f, 4042.14f, 4042.14f, 4042.14f, + }, + { + 19.43f, 19.43f, 19.43f, 19.43f, + 42.45f, 42.45f, 42.45f, 42.45f, + 64.83f, 64.83f, 64.83f, 64.83f, + 46.82f, 46.82f, 46.82f, 46.82f, + }, + { + 77.02f, 77.02f, 77.02f, 77.02f, + 42.34f, 42.34f, 42.34f, 42.34f, + 45.44f, 45.44f, 45.44f, 45.44f, + 55.89f, 55.89f, 55.89f, 55.89f, + } + }, + { + { 99.01f }, + { + 6240.43f, 6240.43f, 6240.43f, 6240.43f, + 2179.23f, 2179.23f, 2179.23f, 2179.23f, + 5346.65f, 5346.65f, 5346.65f, 5346.65f, + 2649.91f, 2649.91f, 2649.91f, 2649.91f, + }, + { + 59.46f, 59.46f, 59.46f, 59.46f, + 16.96f, 16.96f, 16.96f, 16.96f, + 52.55f, 52.55f, 52.55f, 52.55f, + 24.70f, 24.70f, 24.70f, 24.70f, + }, + { + 353.30f, 353.30f, 353.30f, 353.30f, + 500.02f, 500.02f, 500.02f, 500.02f, + 143.67f, 143.67f, 143.67f, 143.67f, + 204.36f, 204.36f, 204.36f, 204.36f, + } + }, +}; + +double TEST_MULOP_DATA(double, sub)[][4][N] = +{ + { + { 80.54 }, + { + 5731.60, 5731.60, 5731.60, 5731.60, + 6682.41, 6682.41, 6682.41, 6682.41, + 7737.53, 7737.53, 7737.53, 7737.53, + 4922.68, 4922.68, 4922.68, 4922.68, + }, + { + 67.14, 67.14, 67.14, 67.14, + 78.23, 78.23, 78.23, 78.23, + 94.35, 94.35, 94.35, 94.35, + 49.68, 49.68, 49.68, 49.68, + }, + { + 324.14, 324.14, 324.14, 324.14, + 381.77, 381.77, 381.77, 381.77, + 138.58, 138.58, 138.58, 138.58, + 921.45, 921.45, 921.45, 921.45, + } + }, + { + { 8.05e+01 }, + { + 8.65e+27, 8.65e+27, 8.65e+27, 8.65e+27, + 1.01e+28, 1.01e+28, 1.01e+28, 1.01e+28, + 8.99e+27, 8.99e+27, 8.99e+27, 8.99e+27, + 1.32e+28, 1.32e+28, 1.32e+28, 1.32e+28, + }, + { + 6.71e+25, 6.71e+25, 6.71e+25, 6.71e+25, + 7.82e+25, 7.82e+25, 7.82e+25, 7.82e+25, + 9.44e+25, 9.44e+25, 9.44e+25, 9.44e+25, + 4.97e+25, 4.97e+25, 4.97e+25, 4.97e+25, + }, + { + 3.24e+27, 3.24e+27, 3.24e+27, 3.24e+27, + 3.82e+27, 3.82e+27, 3.82e+27, 3.82e+27, + 1.39e+27, 1.39e+27, 1.39e+27, 1.39e+27, + 9.21e+27, 9.21e+27, 9.21e+27, 9.21e+27, + } + }, + { + { 2.02e-03 }, + { + 2.7308e-35, 2.7308e-35, 2.7308e-35, 2.7308e-35, + 1.5784e-35, 1.5784e-35, 1.5784e-35, 1.5784e-35, + 2.3378e-35, 2.3378e-35, 2.3378e-35, 2.3378e-35, + 1.6918e-35, 1.6918e-35, 1.6918e-35, 1.6918e-35, + }, + { + 9.7703e-33, 9.7703e-33, 9.7703e-33, 9.7703e-33, + 4.1632e-33, 4.1632e-33, 4.1632e-33, 4.1632e-33, + 8.1964e-33, 8.1964e-33, 8.1964e-33, 8.1964e-33, + 4.7314e-33, 4.7314e-33, 4.7314e-33, 4.7314e-33, + }, + { + 7.5586e-36, 7.5586e-36, 7.5586e-36, 7.5586e-36, + 7.3684e-36, 7.3684e-36, 7.3684e-36, 7.3684e-36, + 6.8101e-36, 6.8101e-36, 6.8101e-36, 6.8101e-36, + 7.3543e-36, 7.3543e-36, 7.3543e-36, 7.3543e-36, + } + }, +}; + + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h new file mode 100644 index 0000000..bc6f483d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h @@ -0,0 +1,34 @@ +#ifndef HAVE_DEFINED_VF_MULOP_RUN_H +#define HAVE_DEFINED_VF_MULOP_RUN_H + +#include <math.h> + +#define TYPE_FABS(x, T) \ + (__builtin_types_compatible_p (T, double) ? fabs (x) : fabsf (x)) + +int +main () +{ + unsigned i, k; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + T x = TEST_DATA[i][0][0]; + T *in = TEST_DATA[i][1]; + T *out = TEST_DATA[i][2]; + T *expect = TEST_DATA[i][3]; + + TEST_RUN (T, NAME, out, in, x, N); + + for (k = 0; k < N; k++) + { + T diff = expect[k] - out[k]; + if (TYPE_FABS (diff, T) > .01 * TYPE_FABS (expect[k], T)) + __builtin_abort (); + } + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c new file mode 100644 index 0000000..1bcf9e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME add + +DEF_VF_MULOP_CASE_0_WRAP(T, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c new file mode 100644 index 0000000..199b9ad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME add + +DEF_VF_MULOP_CASE_0_WRAP(T, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c new file mode 100644 index 0000000..3857f58 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME add + +DEF_VF_MULOP_CASE_0_WRAP(T, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c new file mode 100644 index 0000000..671c7d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME sub + +DEF_VF_MULOP_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c new file mode 100644 index 0000000..f896963 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME sub + +DEF_VF_MULOP_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c new file mode 100644 index 0000000..b42ab1e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME sub + +DEF_VF_MULOP_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c index 144d1ba..d88e76b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, &, and) DEF_VX_BINARY_CASE_0_WRAP(T, |, or) DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) +DEF_VX_BINARY_CASE_0_WRAP(T, /, div) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) /* { dg-final { scan-assembler-times {vor.vx} 1 } } */ /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmul.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c index 74d35d1..53189c2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, &, and) DEF_VX_BINARY_CASE_0_WRAP(T, |, or) DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) +DEF_VX_BINARY_CASE_0_WRAP(T, /, div) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) /* { dg-final { scan-assembler-times {vor.vx} 1 } } */ /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmul.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c index ac512ff..5059beb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, &, and) DEF_VX_BINARY_CASE_0_WRAP(T, |, or) DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) +DEF_VX_BINARY_CASE_0_WRAP(T, /, div) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) /* { dg-final { scan-assembler-times {vor.vx} 1 } } */ /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmul.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c index 4f7b675..4bbe5a4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, &, and) DEF_VX_BINARY_CASE_0_WRAP(T, |, or) DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) +DEF_VX_BINARY_CASE_0_WRAP(T, /, div) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) /* { dg-final { scan-assembler-times {vor.vx} 1 } } */ /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmul.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c index 075c8be..0437db4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, &, and) DEF_VX_BINARY_CASE_0_WRAP(T, |, or) DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) +DEF_VX_BINARY_CASE_0_WRAP(T, /, div) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) /* { dg-final { scan-assembler-not {vor.vx} } } */ /* { dg-final { scan-assembler-not {vxor.vx} } } */ /* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c index 595479c..95ed403 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, &, and) DEF_VX_BINARY_CASE_0_WRAP(T, |, or) DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) +DEF_VX_BINARY_CASE_0_WRAP(T, /, div) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) /* { dg-final { scan-assembler-not {vor.vx} } } */ /* { dg-final { scan-assembler-not {vxor.vx} } } */ /* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c index 7b6fcbf..f8912a0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, &, and) DEF_VX_BINARY_CASE_0_WRAP(T, |, or) DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) +DEF_VX_BINARY_CASE_0_WRAP(T, /, div) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) /* { dg-final { scan-assembler-not {vor.vx} } } */ /* { dg-final { scan-assembler-not {vxor.vx} } } */ /* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c index 55fc717..3c8f915 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, &, and) DEF_VX_BINARY_CASE_0_WRAP(T, |, or) DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) +DEF_VX_BINARY_CASE_0_WRAP(T, /, div) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) /* { dg-final { scan-assembler-not {vor.vx} } } */ /* { dg-final { scan-assembler-not {vxor.vx} } } */ /* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c index bec6b3a..f49dae4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, &, and) DEF_VX_BINARY_CASE_0_WRAP(T, |, or) DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) +DEF_VX_BINARY_CASE_0_WRAP(T, /, div) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) /* { dg-final { scan-assembler-not {vor.vx} } } */ /* { dg-final { scan-assembler-not {vxor.vx} } } */ /* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c index 98fce52..8f502a3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, &, and) DEF_VX_BINARY_CASE_0_WRAP(T, |, or) DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) +DEF_VX_BINARY_CASE_0_WRAP(T, /, div) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) /* { dg-final { scan-assembler-not {vor.vx} } } */ /* { dg-final { scan-assembler-not {vxor.vx} } } */ /* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c index 48dd57a..3277bf2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, &, and) DEF_VX_BINARY_CASE_0_WRAP(T, |, or) DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) +DEF_VX_BINARY_CASE_0_WRAP(T, /, div) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) /* { dg-final { scan-assembler-not {vor.vx} } } */ /* { dg-final { scan-assembler-not {vxor.vx} } } */ /* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c index 9bdce82..25ed2ad 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, &, and) DEF_VX_BINARY_CASE_0_WRAP(T, |, or) DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) +DEF_VX_BINARY_CASE_0_WRAP(T, /, div) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) /* { dg-final { scan-assembler-not {vor.vx} } } */ /* { dg-final { scan-assembler-not {vxor.vx} } } */ /* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c index a1b24f7..1e409de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) /* { dg-final { scan-assembler {vor.vx} } } */ /* { dg-final { scan-assembler {vxor.vx} } } */ /* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c index 53bd744..2f242c7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4) /* { dg-final { scan-assembler {vor.vx} } } */ /* { dg-final { scan-assembler {vxor.vx} } } */ /* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c index 73cb89d..f027bd8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY) /* { dg-final { scan-assembler {vor.vx} } } */ /* { dg-final { scan-assembler {vxor.vx} } } */ /* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c index ec20474..c4f55b0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) /* { dg-final { scan-assembler {vor.vx} } } */ /* { dg-final { scan-assembler {vxor.vx} } } */ /* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c index 902ba1e..d6b05bc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X8) DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X8) /* { dg-final { scan-assembler {vor.vx} } } */ /* { dg-final { scan-assembler {vxor.vx} } } */ /* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c index e57cee6..e1c043f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4) /* { dg-final { scan-assembler {vor.vx} } } */ /* { dg-final { scan-assembler {vxor.vx} } } */ /* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c index 3b4138d..1beb914 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY) /* { dg-final { scan-assembler {vor.vx} } } */ /* { dg-final { scan-assembler {vxor.vx} } } */ /* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c index 0ad52b2..0291517 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) /* { dg-final { scan-assembler {vor.vx} } } */ /* { dg-final { scan-assembler {vxor.vx} } } */ /* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c index 5e04050..c22c82d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X8) DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X8) /* { dg-final { scan-assembler {vor.vx} } } */ /* { dg-final { scan-assembler {vxor.vx} } } */ /* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c index 13a9fe2..dc35600 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4) /* { dg-final { scan-assembler {vor.vx} } } */ /* { dg-final { scan-assembler {vxor.vx} } } */ /* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c index ca515b4..cee1e3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY) /* { dg-final { scan-assembler-not {vor.vx} } } */ /* { dg-final { scan-assembler-not {vxor.vx} } } */ /* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c index 70e1abc..74fd2fb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c @@ -12,6 +12,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -20,3 +21,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) /* { dg-final { scan-assembler {vor.vx} } } */ /* { dg-final { scan-assembler {vxor.vx} } } */ /* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h index c7289ac..ed8c562 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -2554,4 +2554,200 @@ int64_t TEST_BINARY_DATA(int64_t, mul)[][3][N] = }, }; +int8_t TEST_BINARY_DATA(int8_t, div)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { -128 }, + { + -128, -128, -128, -128, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, div)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { -32768 }, + { + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, div)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { -2147483648 }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, div)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 9223372036854775807ll }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { -9223372036854775808ull }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i16.c new file mode 100644 index 0000000..64cf31c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i32.c new file mode 100644 index 0000000..2fe6623 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i64.c new file mode 100644 index 0000000..03dbe03 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i8.c new file mode 100644 index 0000000..e54e5bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gfortran.dg/coarray_data_2.f90 b/gcc/testsuite/gfortran.dg/coarray_data_2.f90 new file mode 100644 index 0000000..bda57f3 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/coarray_data_2.f90 @@ -0,0 +1,14 @@ +! { dg-do compile } +! { dg-additional-options "-fcoarray=lib -Warray-temporaries" } +! +! PR fortran/99838 - ICE due to missing locus with data statement for coarray +! +! Contributed by Gerhard Steinmetz + +program p + type t + integer :: a + end type + type(t) :: x(3)[*] + data x%a /1, 2, 3/ ! { dg-warning "Creating array temporary" } +end diff --git a/gcc/testsuite/gnat.dg/controlled9.adb b/gcc/testsuite/gnat.dg/controlled9.adb new file mode 100644 index 0000000..fb7acce --- /dev/null +++ b/gcc/testsuite/gnat.dg/controlled9.adb @@ -0,0 +1,10 @@ +-- { dg-do run } +-- { dg-options "-O1 -fstack-check" } +-- from PR middle-end/118939 + +with Controlled9_Pkg; +procedure Controlled9 is + S : constant Controlled9_Pkg.T_Access := new Controlled9_Pkg.T; +begin + null; +end Controlled9; diff --git a/gcc/testsuite/gnat.dg/controlled9_pkg.ads b/gcc/testsuite/gnat.dg/controlled9_pkg.ads new file mode 100644 index 0000000..d0e7c28 --- /dev/null +++ b/gcc/testsuite/gnat.dg/controlled9_pkg.ads @@ -0,0 +1,5 @@ +with Ada.Finalization; +package Controlled9_Pkg is + type T is new Ada.Finalization.Controlled with null record; + type T_Access is access all T; +end Controlled9_Pkg; diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 75d723c..dfffe3a 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1098,6 +1098,16 @@ proc check_effective_target_tls {} { }] } +# Return 1 if we can link using TLS, 0 otherwise. + +proc check_effective_target_tls_link {} { + return [check_no_compiler_messages tls_link executable { + __thread int i; + int main (void) { return i; } + void g (int j) { i = j; } + }] +} + # Return 1 if *native* thread local storage (TLS) is supported, 0 otherwise. proc check_effective_target_tls_native {} { |