diff options
Diffstat (limited to 'gcc/testsuite')
25 files changed, 757 insertions, 120 deletions
diff --git a/gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C b/gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C new file mode 100644 index 0000000..90160a5 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C @@ -0,0 +1,17 @@ +// PR c++/119981 +// { dg-do compile { target c++20 } } + +template<template<class> class P> +struct mp_copy_if{}; + +template<auto Fn> +struct g { + template<class> struct fn{}; +}; + +template<typename> +void test3() { + mp_copy_if<g<[]{}>::template fn> b; +} + +template void test3<int>(); diff --git a/gcc/testsuite/g++.target/riscv/pr119832.C b/gcc/testsuite/g++.target/riscv/pr119832.C new file mode 100644 index 0000000..f4dc480 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/pr119832.C @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gcv -mabi=lp64 -ffast-math" } */ + +struct ac { + ~ac(); + void u(); +}; +struct ae { + int s; + float *ag; +}; + +float c; + +void ak(ae *al, int n) { + ac d; + for (int i;i<n;++i) { + float a = 0; + for (long j; j < al[i].s; j++) + a += al[i].ag[j]; + c = a; + d.u(); + } +} + +/* { dg-final { scan-assembler-not "frrm\t" } } */ +/* { dg-final { scan-assembler-not "fsrm\t" } } */ diff --git a/gcc/testsuite/gcc.dg/torture/pr120006.c b/gcc/testsuite/gcc.dg/torture/pr120006.c new file mode 100644 index 0000000..c067f0e --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr120006.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-additional-options "-fipa-pta" } */ + +char *b; +int f = 1; + +char *xstrdup(char *i) { + char *c = __builtin_strdup(i); + if (!c) + __builtin_exit(1); + return c; +} + +int main() { + char g; + char h[8]; + + for (int i = 0; i < 2; i++) { + char c = *__builtin_strdup(""); + b = &g; + + if (f) { + h[0] = '-'; + h[1] = 'a'; + h[2] = '\0'; + b = xstrdup(h); + } + } + if (__builtin_strcmp(b, "-a") != 0) + __builtin_abort(); +} diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c index d84acee..8be9878 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c @@ -11,8 +11,8 @@ to change decisions in switch expansion which in turn can expose new jump threading opportunities. Skip the later tests on aarch64. */ /* { dg-final { scan-tree-dump-not "Jumps threaded" "dom3" { target { ! aarch64*-*-* } } } } */ -/* { dg-final { scan-tree-dump "Jumps threaded: 9" "thread2" { target { ! aarch64*-*-* } } } } */ -/* { dg-final { scan-tree-dump "Jumps threaded: 17" "thread2" { target { aarch64*-*-* } } } } */ +/* { dg-final { scan-tree-dump "Jumps threaded: 10" "thread2" { target { ! aarch64*-*-* } } } } */ +/* { dg-final { scan-tree-dump "Jumps threaded: 14" "thread2" { target { aarch64*-*-* } } } } */ enum STATE { S0=0, diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-thread-23.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-thread-23.c new file mode 100644 index 0000000..930360a --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-thread-23.c @@ -0,0 +1,19 @@ +/* PR120003 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-cddce3-details" } */ + +extern _Bool g(int); + +_Bool f() +{ + _Bool retval = 0; + for(int i=0; i<1000000; ++i) + retval = retval || g(i); + return retval; +} + +/* Jump threading after loop optimization should get the counting loop + separated from the loop until retval is true and CD-DCE elide it. + It's difficult to check for the fact that a true retval terminates + the loop so check CD-DCE eliminates one loop instead. */ +/* { dg-final { scan-tree-dump "fix_loop_structure: removing loop" "cddce3" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr115258.c b/gcc/testsuite/gcc.target/aarch64/pr115258.c index 9a489d4..f60b50a 100644 --- a/gcc/testsuite/gcc.target/aarch64/pr115258.c +++ b/gcc/testsuite/gcc.target/aarch64/pr115258.c @@ -1,4 +1,4 @@ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -mcmodel=small" } */ /* { dg-final { check-function-bodies "**" "" "" } } */ /* diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_arith_6.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_arith_6.c index 4085ab1..d5a12f1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/cond_arith_6.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_arith_6.c @@ -8,7 +8,8 @@ f (float *x) x[i] -= 1.0f; } -/* { dg-final { scan-assembler {\tld1w\tz} } } */ +/* { dg-final { scan-assembler {\tld1w\tz} { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler {\tldr\tq} { target aarch64_little_endian } } } */ /* { dg-final { scan-assembler {\tfcmgt\tp} } } */ /* { dg-final { scan-assembler {\tfsub\tz} } } */ /* { dg-final { scan-assembler {\tst1w\tz} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/ldst_ptrue_128_to_neon.c b/gcc/testsuite/gcc.target/aarch64/sve/ldst_ptrue_128_to_neon.c new file mode 100644 index 0000000..43d36e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/ldst_ptrue_128_to_neon.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=128" } */ +/* { dg-require-effective-target aarch64_little_endian } */ + +#include <arm_sve.h> + +#define TEST(TYPE, TY, B) \ + sv##TYPE \ + ld1_##TY##B (TYPE *x) \ + { \ + svbool_t pg = svptrue_b##B (); \ + return svld1_##TY##B (pg, x); \ + } \ + \ + void \ + st1_##TY##B (TYPE *x, sv##TYPE data) \ + { \ + svbool_t pg = svptrue_b##B (); \ + svst1_##TY##B (pg, x, data); \ + } \ + \ + sv##TYPE \ + ld1_vol_##TY##B (volatile sv##TYPE *ptr) \ + { \ + return *ptr; \ + } \ + \ + void \ + st1_vol_##TY##B (volatile sv##TYPE *ptr, sv##TYPE x) \ + { \ + *ptr = x; \ + } + +TEST (bfloat16_t, bf, 16) +TEST (float16_t, f, 16) +TEST (float32_t, f, 32) +TEST (float64_t, f, 64) +TEST (int8_t, s, 8) +TEST (int16_t, s, 16) +TEST (int32_t, s, 32) +TEST (int64_t, s, 64) +TEST (uint8_t, u, 8) +TEST (uint16_t, u, 16) +TEST (uint32_t, u, 32) +TEST (uint64_t, u, 64) + +/* { dg-final { scan-assembler-times {\tldr\tq0, \[x0\]} 24 } } */ +/* { dg-final { scan-assembler-times {\tstr\tq0, \[x0\]} 24 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_128.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_128.c index 87d528c..ac5f981 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_128.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_4_128.c @@ -11,104 +11,91 @@ /* ** callee_s8: -** ptrue (p[0-7])\.b, vl16 -** ld1b z0\.b, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (s8, __SVInt8_t) /* ** callee_u8: -** ptrue (p[0-7])\.b, vl16 -** ld1b z0\.b, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (u8, __SVUint8_t) /* ** callee_mf8: -** ptrue (p[0-7])\.b, vl16 -** ld1b z0\.b, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (mf8, __SVMfloat8_t) /* ** callee_s16: -** ptrue (p[0-7])\.b, vl16 -** ld1h z0\.h, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (s16, __SVInt16_t) /* ** callee_u16: -** ptrue (p[0-7])\.b, vl16 -** ld1h z0\.h, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (u16, __SVUint16_t) /* ** callee_f16: -** ptrue (p[0-7])\.b, vl16 -** ld1h z0\.h, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (f16, __SVFloat16_t) /* ** callee_bf16: -** ptrue (p[0-7])\.b, vl16 -** ld1h z0\.h, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (bf16, __SVBfloat16_t) /* ** callee_s32: -** ptrue (p[0-7])\.b, vl16 -** ld1w z0\.s, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (s32, __SVInt32_t) /* ** callee_u32: -** ptrue (p[0-7])\.b, vl16 -** ld1w z0\.s, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (u32, __SVUint32_t) /* ** callee_f32: -** ptrue (p[0-7])\.b, vl16 -** ld1w z0\.s, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (f32, __SVFloat32_t) /* ** callee_s64: -** ptrue (p[0-7])\.b, vl16 -** ld1d z0\.d, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (s64, __SVInt64_t) /* ** callee_u64: -** ptrue (p[0-7])\.b, vl16 -** ld1d z0\.d, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (u64, __SVUint64_t) /* ** callee_f64: -** ptrue (p[0-7])\.b, vl16 -** ld1d z0\.d, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (f64, __SVFloat64_t) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_128.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_128.c index 347a16c..2fab6fe 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_128.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_5_128.c @@ -13,104 +13,91 @@ /* ** callee_s8: -** ptrue (p[0-7])\.b, vl16 -** ld1b z0\.b, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (s8, svint8_t) /* ** callee_u8: -** ptrue (p[0-7])\.b, vl16 -** ld1b z0\.b, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (u8, svuint8_t) /* ** callee_mf8: -** ptrue (p[0-7])\.b, vl16 -** ld1b z0\.b, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (mf8, svmfloat8_t) /* ** callee_s16: -** ptrue (p[0-7])\.b, vl16 -** ld1h z0\.h, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (s16, svint16_t) /* ** callee_u16: -** ptrue (p[0-7])\.b, vl16 -** ld1h z0\.h, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (u16, svuint16_t) /* ** callee_f16: -** ptrue (p[0-7])\.b, vl16 -** ld1h z0\.h, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (f16, svfloat16_t) /* ** callee_bf16: -** ptrue (p[0-7])\.b, vl16 -** ld1h z0\.h, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (bf16, svbfloat16_t) /* ** callee_s32: -** ptrue (p[0-7])\.b, vl16 -** ld1w z0\.s, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (s32, svint32_t) /* ** callee_u32: -** ptrue (p[0-7])\.b, vl16 -** ld1w z0\.s, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (u32, svuint32_t) /* ** callee_f32: -** ptrue (p[0-7])\.b, vl16 -** ld1w z0\.s, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (f32, svfloat32_t) /* ** callee_s64: -** ptrue (p[0-7])\.b, vl16 -** ld1d z0\.d, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (s64, svint64_t) /* ** callee_u64: -** ptrue (p[0-7])\.b, vl16 -** ld1d z0\.d, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (u64, svuint64_t) /* ** callee_f64: -** ptrue (p[0-7])\.b, vl16 -** ld1d z0\.d, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ CALLEE (f64, svfloat64_t) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_3_128.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_3_128.c index d99ce12..29bdaf3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_3_128.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_3_128.c @@ -473,17 +473,16 @@ SEL2 (struct, pst_uniform4) ** sub sp, sp, #144 ** add (x[0-9]+), sp, #?31 ** and x7, \1, #?(?:-32|4294967264) -** ptrue (p[0-7])\.b, vl16 -** st1w z0\.s, \2, \[x7\] -** add (x[0-9]+), x7, #?32 +** mov (x[0-9]+), x7 +** str q0, \[\2\], 32 ** ( -** str z1, \[\3\] -** str z2, \[\3, #1, mul vl\] +** str z1, \[\2\] +** str z2, \[\2, #1, mul vl\] ** | -** stp q1, q2, \[\3\] +** stp q1, q2, \[\2\] ** ) -** str z3, \[\3, #2, mul vl\] -** st1w z4\.s, \2, \[x7, #6, mul vl\] +** str z3, \[\2, #2, mul vl\] +** str q4, \[x7, 96\] ** add sp, sp, #?144 ** ret */ @@ -516,20 +515,12 @@ SEL2 (struct, pst_mixed1) ** test_pst_mixed1: ** sub sp, sp, #176 ** str p0, \[sp\] -** ptrue p0\.b, vl16 -** st1h z0\.h, p0, \[sp, #1, mul vl\] -** st1h z1\.h, p0, \[sp, #2, mul vl\] -** st1w z2\.s, p0, \[sp, #3, mul vl\] -** st1d z3\.d, p0, \[sp, #4, mul vl\] +** stp q0, q1, \[sp, 16\] +** stp q2, q3, \[sp, 48\] ** str p1, \[sp, #40, mul vl\] ** str p2, \[sp, #41, mul vl\] -** st1b z4\.b, p0, \[sp, #6, mul vl\] -** st1h z5\.h, p0, \[sp, #7, mul vl\] -** ... -** st1w z6\.s, p0, [^\n]* -** ... -** st1d z7\.d, p0, [^\n]* -** ... +** stp q4, q5, \[sp, 96\] +** stp q6, q7, \[sp, 128\] ** str p3, \[sp, #80, mul vl\] ** mov (x7, sp|w7, wsp) ** add sp, sp, #?176 @@ -557,15 +548,11 @@ SEL2 (struct, pst_mixed2) ** test_pst_mixed2: ** sub sp, sp, #128 ** str p0, \[sp\] -** ptrue (p[03])\.b, vl16 -** add (x[0-9]+), sp, #?2 -** st1b z0\.b, \1, \[\2\] +** str q0, \[sp, 2\] ** str p1, \[sp, #9, mul vl\] -** add (x[0-9]+), sp, #?20 -** st1b z1\.b, \1, \[\3\] +** str q1, \[sp, 20\] ** str p2, \[sp, #18, mul vl\] -** add (x[0-9]+), sp, #?38 -** st1b z2\.b, \1, \[\4\] +** str q2, \[sp, 38\] ** ( ** str z3, \[sp, #4, mul vl\] ** str z4, \[sp, #5, mul vl\] @@ -595,8 +582,7 @@ SEL2 (struct, pst_big1) /* ** test_pst_big1_a: { target lp64 } -** ptrue (p[0-7])\.b, vl16 -** ld1b z0\.b, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ /* @@ -760,8 +746,7 @@ test_pst_big3_d (struct pst_big3 x) /* ** test_pst_big3_e: { target lp64 } -** ptrue (p[0-7])\.b, vl16 -** ld1b z0\.b, \1/z, \[x0, #1, mul vl\] +** ldr q0, \[x0, 16\] ** ret */ /* @@ -780,8 +765,7 @@ test_pst_big3_e (struct pst_big3 x) /* ** test_pst_big3_f: { target lp64 } -** ptrue (p[0-7])\.b, vl16 -** ld1b z0\.b, \1/z, \[x0, #5, mul vl\] +** ldr q0, \[x0, 80\] ** ret */ /* @@ -1035,8 +1019,7 @@ SEL2 (struct, nonpst6) /* ** test_nonpst6: { target lp64 } -** ptrue (p[0-3])\.b, vl16 -** ld1d z0\.d, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ /* @@ -1063,8 +1046,7 @@ SEL2 (struct, nonpst7) /* ** test_nonpst7: { target lp64 } -** ptrue (p[0-3])\.b, vl16 -** ld1d z0\.d, \1/z, \[x0\] +** ldr q0, \[x0\] ** ret */ /* diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-1.c b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-1.c new file mode 100644 index 0000000..086d1ea --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-1.c @@ -0,0 +1,7 @@ +/* { dg-do run { target { ! avr_tiny } } } */ +/* { dg-additional-options "-std=gnu99" } */ + +typedef __UINT8_TYPE__ TYP; +#define AS __flashx + +#include "pr119989.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-2.c b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-2.c new file mode 100644 index 0000000..d053ab9 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-2.c @@ -0,0 +1,7 @@ +/* { dg-do run { target { ! avr_tiny } } } */ +/* { dg-additional-options "-std=gnu99" } */ + +typedef __UINT16_TYPE__ TYP; +#define AS __flashx + +#include "pr119989.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-3.c b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-3.c new file mode 100644 index 0000000..1a5e8f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-3.c @@ -0,0 +1,7 @@ +/* { dg-do run { target { ! avr_tiny } } } */ +/* { dg-additional-options "-std=gnu99" } */ + +__extension__ typedef __uint24 TYP; +#define AS __flashx + +#include "pr119989.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-4.c b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-4.c new file mode 100644 index 0000000..63fb52c --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-4.c @@ -0,0 +1,7 @@ +/* { dg-do run { target { ! avr_tiny } } } */ +/* { dg-additional-options "-std=gnu99" } */ + +typedef __UINT32_TYPE__ TYP; +#define AS __flashx + +#include "pr119989.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c new file mode 100644 index 0000000..4553517 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c @@ -0,0 +1,7 @@ +/* { dg-do run { target { ! avr_tiny } } } */ +/* { dg-additional-options "-std=gnu99" } */ + +typedef __UINT8_TYPE__ TYP; +#define AS __memx + +#include "pr119989.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-2.c b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-2.c new file mode 100644 index 0000000..b28c497 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-2.c @@ -0,0 +1,7 @@ +/* { dg-do run { target { ! avr_tiny } } } */ +/* { dg-additional-options "-std=gnu99" } */ + +typedef __UINT16_TYPE__ TYP; +#define AS __memx + +#include "pr119989.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-3.c b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-3.c new file mode 100644 index 0000000..bb20053 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-3.c @@ -0,0 +1,7 @@ +/* { dg-do run { target { ! avr_tiny } } } */ +/* { dg-additional-options "-std=gnu99" } */ + +__extension__ typedef __uint24 TYP; +#define AS __memx + +#include "pr119989.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-4.c b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-4.c new file mode 100644 index 0000000..05a3ee7 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-4.c @@ -0,0 +1,7 @@ +/* { dg-do run { target { ! avr_tiny } } } */ +/* { dg-additional-options "-std=gnu99" } */ + +typedef __UINT32_TYPE__ TYP; +#define AS __memx + +#include "pr119989.h" diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989.h b/gcc/testsuite/gcc.target/avr/torture/pr119989.h new file mode 100644 index 0000000..12b5449 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr119989.h @@ -0,0 +1,37 @@ +const AS TYP some_data[] = { 1, 2, 3, 4, 5 }; +const AS TYP *IP; + +TYP DT, a, b; + +__attribute__((noipa)) +void do_test1 (void) +{ + DT = *IP; + DT = *IP--; +} + +__attribute__((noipa)) +void do_test2 (void) +{ + DT = *IP; + __asm volatile ("" ::: "memory"); // Prevents unwanted optimization + DT = *IP--; +} + +TYP difference(void) +{ + IP = &some_data[3]; + do_test1(); + a = DT; + IP = &some_data[3]; + do_test2(); + b = DT; + return a - b; // Expected: 0 +} + +int main (void) +{ + if (difference () != 0) + __builtin_exit (__LINE__); + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-19.c b/gcc/testsuite/gcc.target/riscv/predef-19.c index 2b90702..ca3d57a 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-19.c +++ b/gcc/testsuite/gcc.target/riscv/predef-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=rv64gc_zve32x -mabi=lp64d -mcmodel=medlow -misa-spec=2.2" } */ +/* { dg-options "-O2 -march=rv64im_zve32x -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */ int main () { @@ -15,50 +15,30 @@ int main () { #error "__riscv_i" #endif -#if !defined(__riscv_c) -#error "__riscv_c" -#endif - #if defined(__riscv_e) #error "__riscv_e" #endif -#if !defined(__riscv_a) -#error "__riscv_a" -#endif - #if !defined(__riscv_m) #error "__riscv_m" #endif -#if !defined(__riscv_f) -#error "__riscv_f" -#endif - -#if !defined(__riscv_d) -#error "__riscv_d" -#endif - -#if defined(__riscv_v) -#error "__riscv_v" +#if !defined(__riscv_zicsr) +#error "__riscv_zicsr" #endif -#if defined(__riscv_zvl128b) -#error "__riscv_zvl128b" +#if !defined(_riscv_zmmul) +#error "__riscv_zmmul" #endif -#if defined(__riscv_zvl64b) -#error "__riscv_zvl64b" +#if !defined(__riscv_zve32x) +#error "__riscv_zve32x" #endif #if !defined(__riscv_zvl32b) #error "__riscv_zvl32b" #endif -#if !defined(__riscv_zve32x) -#error "__riscv_zve32x" -#endif - #if !defined(__riscv_vector) #error "__riscv_vector" #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c new file mode 100644 index 0000000..7667e56 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c @@ -0,0 +1,88 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sifive_vector.h" + +typedef _Float16 float16_t; +typedef float float32_t; +typedef double float64_t; + +/* +** test_sf_vc_v_fv_u16mf4: +** ... +** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+ +** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl); +} + +/* +** test_sf_vc_v_fv_se_u16mf4: +** ... +** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+ +** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl); +} + +/* +** test_sf_vc_fv_se_u16mf2: +** ... +** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+ +** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) { + __riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl); +} + +/* +** test_sf_vc_v_fvv_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl); +} + +/* +** test_sf_vc_v_fvv_se_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl); +} + +/* +** test_sf_vc_fvv_se_u32m8: +** ... +** vsetivli\s+zero+,0+,e32+,m8,ta,ma+ +** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl); +} + + +/* +** test_sf_vc_fvw_se_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, size_t vl) { + __riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl); +} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c new file mode 100644 index 0000000..5528cc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sifive_vector.h" + + +/* +** test_sf_vc_v_i_u16m4: +** ... +** vsetivli\s+zero+,0+,e16+,m4,ta,ma+ +** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) { + return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl); +} + +/* +** test_sf_vc_v_i_se_u16m4: +** ... +** vsetivli\s+zero+,0+,e16+,m4,ta,ma+ +** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) { + return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl); +} + +/* +** test_sf_vc_i_se_u16mf4: +** ... +** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+ +** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+ +** ... +*/ +void test_sf_vc_i_se_u16mf4(size_t vl) { + __riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl); +} + +/* +** test_sf_vc_v_iv_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint32m2_t test_sf_vc_v_iv_u32m2(vuint32m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u32m2(1, vs2, 4, vl); +} + +/* +** test_sf_vc_v_iv_se_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint32m2_t test_sf_vc_v_iv_se_u32m2(vuint32m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u32m2(1, vs2, 4, vl); +} + +/* +** test_sf_vc_iv_se_u16m2: +** ... +** vsetivli\s+zero+,0+,e16+,m2,ta,ma+ +** sf\.vc\.iv\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +void test_sf_vc_iv_se_u16m2(vuint16m2_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u16m2(1, 3, vs2, 4, vl); +} + +/* +** test_sf_vc_v_ivv_u8m8: +** ... +** vsetivli\s+zero+,0+,e8+,m8,ta,ma+ +** sf\.vc\.v\.ivv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint8m8_t test_sf_vc_v_ivv_u8m8(vuint8m8_t vd, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u8m8(1, vd, vs2, 4, vl); +} + +/* +** test_sf_vc_v_ivv_se_u8m8: +** ... +** vsetivli\s+zero+,0+,e8+,m8,ta,ma+ +** sf\.vc\.v\.ivv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint8m8_t test_sf_vc_v_ivv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u8m8(1, vd, vs2, 4, vl); +} + +/* +** test_sf_vc_ivv_se_u64m1: +** ... +** vsetivli\s+zero+,0+,e64+,m1,ta,ma+ +** sf\.vc\.ivv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +void test_sf_vc_ivv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u64m1(1, vd, vs2, 4, vl); +} + +/* +** test_sf_vc_v_ivw_u8mf4: +** ... +** vsetivli\s+zero+,0+,e8+,mf4,ta,ma+ +** sf\.vc\.v\.ivw\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint16mf2_t test_sf_vc_v_ivw_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u8mf4(1, vd, vs2, 4, vl); +} + +/* +** test_sf_vc_v_ivw_se_u8mf4: +** ... +** vsetivli\s+zero+,0+,e8+,mf4,ta,ma+ +** sf\.vc\.v\.ivw\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint16mf2_t test_sf_vc_v_ivw_se_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u8mf4(1, vd, vs2, 4, vl); +} + +void test_sf_vc_ivw_se_u32m4(vuint64m8_t vd, vuint32m4_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u32m4(1, vd, vs2, 4, vl); +} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_v.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_v.c new file mode 100644 index 0000000..e3022c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_v.c @@ -0,0 +1,107 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sifive_vector.h" + + +/* +** test_sf_vc_v_vv_u8mf8: +** ... +** vsetivli\s+zero+,0+,e8+,mf8,ta,ma+ +** sf\.vc\.v\.vv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint8mf8_t test_sf_vc_v_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t rs1, size_t vl) { + return __riscv_sf_vc_v_vv_u8mf8(1, vs2, rs1, vl); +} + +/* +** test_sf_vc_v_vv_se_u8mf8: +** ... +** vsetivli\s+zero+,0+,e8+,mf8,ta,ma+ +** sf\.vc\.v\.vv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint8mf8_t test_sf_vc_v_vv_se_u8mf8(vuint8mf8_t vs2, vuint8mf8_t rs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u8mf8(1, vs2, rs1, vl); +} + +/* +** test_sf_vc_vv_se_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.vv\t[0-9]+,[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +void test_sf_vc_vv_se_u16m1(vuint16m1_t vs2, vuint16m1_t rs1, size_t vl) { + __riscv_sf_vc_vv_se_u16m1(1, 3, vs2, rs1, vl); +} + +/* +** test_sf_vc_v_vvv_u32mf2: +** ... +** vsetivli\s+zero+,0+,e32+,mf2,ta,ma+ +** sf\.vc\.v\.vvv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint32mf2_t test_sf_vc_v_vvv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t rs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u32mf2(1, vd, vs2, rs1, vl); +} + +/* +** test_sf_vc_v_vvv_se_u32mf2: +** ... +** vsetivli\s+zero+,0+,e32+,mf2,ta,ma+ +** sf\.vc\.v\.vvv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint32mf2_t test_sf_vc_v_vvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t rs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u32mf2(1, vd, vs2, rs1, vl); +} + +/* +** test_sf_vc_vvv_se_u64m1: +** ... +** vsetivli\s+zero+,0+,e64+,m1,ta,ma+ +** sf\.vc\.vvv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +void test_sf_vc_vvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t rs1, size_t vl) { + __riscv_sf_vc_vvv_se_u64m1(1, vd, vs2, rs1, vl); +} + + +/* +** test_sf_vc_v_vvw_u8m1: +** ... +** vsetivli\s+zero+,0+,e8+,m1,ta,ma+ +** sf\.vc\.v\.vvw\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint16m2_t test_sf_vc_v_vvw_u8m1(vuint16m2_t vd, vuint8m1_t vs2, vuint8m1_t rs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u8m1(1, vd, vs2, rs1, vl); +} + +/* +** test_sf_vc_v_vvw_se_u8m1: +** ... +** vsetivli\s+zero+,0+,e8+,m1,ta,ma+ +** sf\.vc\.v\.vvw\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint16m2_t test_sf_vc_v_vvw_se_u8m1(vuint16m2_t vd, vuint8m1_t vs2, vuint8m1_t rs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u8m1(1, vd, vs2, rs1, vl); +} + +/* +** test_sf_vc_vvw_se_u16mf2: +** ... +** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+ +** sf\.vc\.vvw\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +void test_sf_vc_vvw_se_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, vuint16mf2_t rs1, size_t vl) { + __riscv_sf_vc_vvw_se_u16mf2(1, vd, vs2, rs1, vl); +} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_x.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_x.c new file mode 100644 index 0000000..10c92c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_x.c @@ -0,0 +1,138 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sifive_vector.h" + +/* +** test_sf_vc_v_x_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.v\.x\t[0-9]+,[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint32m1_t test_sf_vc_v_x_u32m1(uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_x_u32m1(1, 2, xs1, vl); +} + +/* +** test_sf_vc_v_x_se_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.v\.x\t[0-9]+,[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint32m1_t test_sf_vc_v_x_se_u32m1(uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u32m1(1, 2, xs1, vl); +} + +/* +** test_sf_vc_x_se_u16m8: +** ... +** vsetivli\s+zero+,0+,e16+,m8,ta,ma+ +** sf\.vc\.x\t[0-9]+,[0-9]+,[0-9]+,a[0-9]+ +** ... +*/ +void test_sf_vc_x_se_u16m8(uint16_t xs1, size_t vl) { + __riscv_sf_vc_x_se_u16m8(1, 2, 3, xs1, vl); +} + +/* +** test_sf_vc_v_xv_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.v\.xv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint32m2_t test_sf_vc_v_xv_u32m2(vuint32m2_t vs2, uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_xv_u32m2(1, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xv_se_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.v\.xv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint32m2_t test_sf_vc_v_xv_se_u32m2(vuint32m2_t vs2, uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u32m2(1, vs2, xs1, vl); +} + +/* +** test_sf_vc_xv_se_u16m4: +** ... +** vsetivli\s+zero+,0+,e16+,m4,ta,ma+ +** sf\.vc\.xv\t[0-9]+,[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +void test_sf_vc_xv_se_u16m4(vuint16m4_t vs2, uint16_t xs1, size_t vl) { + __riscv_sf_vc_xv_se_u16m4(1, 3, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xvv_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.v\.xvv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint16m1_t test_sf_vc_v_xvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, uint16_t xs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u16m1(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xvv_se_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.v\.xvv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint16m1_t test_sf_vc_v_xvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, uint16_t xs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u16m1(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_xvv_se_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.xvv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +void test_sf_vc_xvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, uint32_t xs1, size_t vl) { + __riscv_sf_vc_xvv_se_u32m2(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xvw_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.v\.xvw\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint64m2_t test_sf_vc_v_xvw_u32m1(vuint64m2_t vd, vuint32m1_t vs2, uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u32m1(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xvw_se_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.v\.xvw\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint64m2_t test_sf_vc_v_xvw_se_u32m1(vuint64m2_t vd, vuint32m1_t vs2, uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u32m1(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_xvw_se_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.xvw\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +void test_sf_vc_xvw_se_u32m1(vuint64m2_t vd, vuint32m1_t vs2, uint32_t xs1, size_t vl) { + __riscv_sf_vc_xvw_se_u32m1(1, vd, vs2, xs1, vl); +} + |