diff options
Diffstat (limited to 'gcc/testsuite')
195 files changed, 1632 insertions, 315 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 131f605..b683608 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,1168 @@ +2025-03-25 Bob Dubner <rdubner@symas.com> + Richard Biener <rguenth@suse.de> + Jakub Jelinek <jakub@redhat.com> + James K. Lowden <jklowden@cobolworx.com> + Robert Dubner <rdubher@symas.com> + + * cobol.dg/literal1.cob: New testcase. + * cobol.dg/output1.cob: Likewise + * cobol.dg/data1.cob: New file. + +2025-03-25 Marek Polacek <polacek@redhat.com> + + PR c++/101881 + * g++.dg/ext/vector44.C: New test. + +2025-03-25 Simon Martin <simon@nasilyan.com> + + PR c++/114525 + * g++.dg/expr/cond18.C: New test. + +2025-03-25 yxj-github-437 <2457369732@qq.com> + + * g++.dg/cpp2a/lambda-uneval25.C: New test. + +2025-03-25 Richard Earnshaw <rearnsha@arm.com> + + * gcc.target/arm/mtp_1.c: Require arm32. + * gcc.target/arm/mtp_2.c: Likewise. + * gcc.target/arm/mtp_3.c: Likewise. + * gcc.target/arm/mtp_4.c: Likewise. + +2025-03-25 Sandra Loosemore <sloosemore@baylibre.com> + Tobias Burnus <tburnus@baylibre.com> + + * c-c++-common/gomp/append-args-1.c: Adjust expected behavior. + * c-c++-common/gomp/append-args-interop.c: New. + * c-c++-common/gomp/dispatch-11.c: Adjust expected behavior. + * g++.dg/gomp/append-args-1.C: Likewise. + * gfortran.dg/gomp/append-args-interop.f90: New. + * gfortran.dg/gomp/declare-variant-mod-2.f90: Adjust expected behavior. + +2025-03-25 Richard Earnshaw <rearnsha@arm.com> + + * gcc.target/arm/ftest-armv4t-thumb.c: Expect __ARM_FEATURE_CLZ to be + defined. Remove redundant dg-skip-if rules. + * gcc.target/arm/ftest-armv5t-thumb.c: Likewise. + * gcc.target/arm/ftest-armv5te-thumb.c: Likewise. + * gcc.target/arm/ftest-armv6-thumb.c: Likewise. + * gcc.target/arm/ftest-armv6k-thumb.c: Likewise. + * gcc.target/arm/ftest-armv6z-thumb.c: Likewise. + * gcc.target/arm/ftest-armv7em-thumb.c: Remove redundant dg-skip-if + rules. Add a require-effective-target for armv7em. + * gcc.target/arm/ftest-armv7a-arm.c: Likewise. + * gcc.target/arm/ftest-armv7a-thumb.c: Likewise. + * gcc.target/arm/ftest-armv7r-arm.c: Likewise. + * gcc.target/arm/ftest-armv7r-thumb.c: Likewise. + * gcc.target/arm/ftest-armv7ve-arm.c: Likewise. + * gcc.target/arm/ftest-armv7ve-thumb.c: Likewise. + * gcc.target/arm/ftest-armv8a-arm.c: Likewise. + * gcc.target/arm/ftest-armv8a-thumb.c: Likewise. + * gcc.target/arm/ftest-armv4-arm.c: Remove redundant dg-skip-if rules. + * gcc.target/arm/ftest-armv4t-arm.c: Likewise. + * gcc.target/arm/ftest-armv5t-arm.c: Likewise. + * gcc.target/arm/ftest-armv5te-arm.c: Likewise. + * gcc.target/arm/ftest-armv6-arm.c: Likewise. + * gcc.target/arm/ftest-armv6k-arm.c: Likewise. + * gcc.target/arm/ftest-armv6m-thumb.c: Likewise. + * gcc.target/arm/ftest-armv6t2-arm.c: Likewise. + * gcc.target/arm/ftest-armv6t2-thumb.c: Likewise. + * gcc.target/arm/ftest-armv6z-arm.c: Likewise. + +2025-03-25 Jakub Jelinek <jakub@redhat.com> + + PR target/96226 + PR target/119428 + * gcc.c-torture/execute/pr119428.c: New test. + +2025-03-25 Vineet Gupta <vineetg@rivosinc.com> + + PR target/119224 + * gcc.target/riscv/rvv/autovec/pr117722.c: Adjust output insn. + * gcc.target/riscv/rvv/autovec/pr119224.c: Add new test. + +2025-03-25 Paul-Antoine Arras <parras@baylibre.com> + + * gfortran.dg/gomp/interop-5.f90: Declare omp_interop_kind explicitly + instead of use'ing omp_lib. Update scan-dumps to allow for 4-byte + pointers. + +2025-03-25 Richard Earnshaw <rearnsha@arm.com> + + * gcc.target/arm/lto/pr96939_0.c (dg-options): Delete. Move the + options from here ... + (dg-lto-options): ... to here. + +2025-03-25 Richard Earnshaw <rearnsha@arm.com> + + * gcc.target/arm/vect-early-break-cbranch.c: Allow BEQ as well as BNE. + +2025-03-25 Richard Earnshaw <rearnsha@arm.com> + + * gcc.target/arm/pr65647.c (dg-options): Add -std=gnu17. + +2025-03-25 Christophe Lyon <christophe.lyon@linaro.org> + + * gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c: Remove + dg-do directive. + * gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vld1x2.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vld1x3.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vld1x4.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vqrshrn_high_n.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vqrshrun_high_n.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vqshrn_high_n.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vqshrun_high_n.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vst1x2.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vst1x3.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vst1x4.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vzip_half.c: Likewise. + +2025-03-25 Christophe Lyon <christophe.lyon@linaro.org> + + * gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c: + Remove dg-options. + * gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c: + Likewise. + +2025-03-25 Christophe Lyon <christophe.lyon@linaro.org> + + * gcc.target/aarch64/advsimd-intrinsics/bf16_dup.c: Remove + dg-options. + +2025-03-25 Christophe Lyon <christophe.lyon@linaro.org> + + * gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect.inc: + Move to gcc.target/aarch64/simd/. + * gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_1.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_2.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_3.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_4.c: Likewise. + * gcc.target/aarch64/simd/saturating_arithmetic_autovect.inc: New file. + * gcc.target/aarch64/simd/saturating_arithmetic_autovect_1.c: New file. + * gcc.target/aarch64/simd/saturating_arithmetic_autovect_2.c: New file. + * gcc.target/aarch64/simd/saturating_arithmetic_autovect_3.c: New file. + * gcc.target/aarch64/simd/saturating_arithmetic_autovect_4.c: New file. + +2025-03-25 Christophe Lyon <christophe.lyon@linaro.org> + + * lib/target-supports.exp + (check_effective_target_arm_v8_1_lob_ok): Remove duplicate + -mcpu=unset. + +2025-03-25 Richard Earnshaw <rearnsha@arm.com> + + * gcc.target/arm/pr42575.c: Skip test if thumb1. + +2025-03-25 Richard Earnshaw <rearnsha@arm.com> + + PR middle-end/117811 + * gcc.dg/torture/pr117811.c: New test. + +2025-03-25 Jakub Jelinek <jakub@redhat.com> + + PR ipa/119376 + * g++.dg/torture/musttail1.C: New test. + * g++.dg/opt/musttail2.C: New test. + +2025-03-25 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/119449 + * gm2/pim/pass/minmaxreal.mod: New test. + * gm2/pim/pass/minmaxreal2.mod: New test. + * gm2/pim/pass/minmaxreal3.mod: New test. + +2025-03-25 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c: Modify testcase. + +2025-03-24 Jason Merrill <jason@redhat.com> + + * g++.dg/cpp26/pack-indexing16.C: New test. + +2025-03-24 Iain Buclaw <ibuclaw@gdcproject.org> + + * gdc.dg/Wbuiltin_declaration_mismatch2.d: Split test into ... + * gdc.dg/Wbuiltin_declaration_mismatch3.d: New test. + * gdc.dg/Wbuiltin_declaration_mismatch4.d: New test. + * gdc.dg/Wbuiltin_declaration_mismatch5.d: New test. + * gdc.dg/Wbuiltin_declaration_mismatch6.d: New test. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/execute/torture/issue-3502.rs: New test. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove entries. + * rust/compile/redef_error2.rs: Modify expected error. + * rust/compile/redef_error5.rs: Likewise. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove self-path2.rs + * rust/compile/self-path2.rs: Adjust expected errors. + +2025-03-24 Ryutaro Okada <1015ryu88@gmail.com> + + * rust/compile/extern_generics.rs: New test. + +2025-03-24 Liam Naddell <liamnprg@gmail.com> + + * rust/compile/issue-3315-1.rs: Add test for module with same name + as builtin + * rust/compile/issue-3315-2.rs: Test with utilization of i32 + type + * rust/compile/nr2/exclude: issue-3315-2.rs Does not work with + NR2.0 + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/compile.exp: Adjust to cover tests in the + torture subdirectory. + * rust/compile/nr2/exclude: Add entries. + +2025-03-24 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/nr2/exclude: Remove two mangling tests from exclusion + file. + +2025-03-24 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/nr2/exclude: Remove issue-1786 and issue-3033 from + exclusion list. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/execute/torture/issue-3126.rs: New test. + +2025-03-24 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/enum_variant_name.rs: New test. + +2025-03-24 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/nr2/exclude: Remove test. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/execute/crate-metavar1.rs: New test. + * rust/compile/crate-metavar1.rs: New test. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/compile/try-expr1.rs: New test. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/macros/mbe/macro43.rs: Adjust expected errors. + * rust/compile/macros/mbe/macro44.rs: Likewise. + * rust/compile/nested_macro_use2.rs: Likewise. + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/compile/issue-2015.rs: New test. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/additional-trait-bounds2.rs: Adjust expected + errors. + * rust/compile/const_generics_4.rs: Likewise. + * rust/compile/const_generics_7.rs: Likewise. + * rust/compile/generic-default1.rs: Likewise. + * rust/compile/generics5.rs: Likewise. + * rust/compile/generics9.rs: Likewise. + * rust/compile/issue-2423.rs: Likewise. + * rust/compile/method2.rs: Likewise. + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/compile/derive-hash1.rs: New test. + * rust/compile/nr2/exclude: Add testcase to exclusion list. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/macros/mbe/macro-expand-module.rs: New test. + +2025-03-24 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/compile/derive-eq-invalid.rs: Declare StructuralPartialEq. + * rust/compile/derive-partialeq1.rs: Likewise. + * rust/execute/torture/derive-partialeq1.rs: Likewise. + +2025-03-24 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/compile/derive-eq-invalid.rs: Mark PartialEq def as a lang item. + * rust/compile/derive-partialeq1.rs: New test. + * rust/execute/torture/derive-partialeq1.rs: New test. + * rust/compile/nr2/exclude: Exclude all of them. + +2025-03-24 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/compile/derive-eq-invalid.rs: New test. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Benjamin Thos <benjamin.thos@epita.fr> + + * rust/compile/implicit_returns_err3.rs: Change test to be valid. + * rust/compile/torture/if.rs: Likewise. + * rust/compile/if-without-else.rs: New test. + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/generics4.rs: cleanup + * rust/compile/generics6.rs: likewise + * rust/compile/type-bindings1.rs: likewise + * rust/compile/unconstrained_type_param.rs: likewise + * rust/compile/issue-2035.rs: New test. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/issue-3022.rs: New test. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/issue-3031.rs: New test. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/issue-2369.rs: New test. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/execute/torture/enum_intrinsics2.rs: New test. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/execute/torture/enum_intrinsics1.rs: New test. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/nr2/exclude: nr2 cant handle this + * rust/compile/issue-3403.rs: New test. + +2025-03-24 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/compile/for-loop1.rs: New test. + * rust/compile/for-loop2.rs: New test. + * rust/execute/torture/for-loop1.rs: New test. + * rust/execute/torture/for-loop2.rs: New test. + * rust/compile/nr2/exclude: Exclude for-loop1.rs + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/nr2/exclude: nr2 cant handle this + * rust/compile/issue-3402-1.rs: New test. + * rust/compile/issue-3402-2.rs: New test. + +2025-03-24 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/compile/derive-default1.rs: New test. + * rust/execute/torture/derive-default1.rs: New test. + * rust/compile/nr2/exclude: Exclude them. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/execute/torture/issue-3381.rs: New test. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/nr2/exclude: nr2 cant handle this. + * rust/compile/issue-3382.rs: New test. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/reference1.rs: fix error message + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Remove entries. + +2025-03-24 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/compile/derive-debug1.rs: New test. + * rust/compile/nr2/exclude: Exclude it. + +2025-03-24 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/compile/structural-eq-peq.rs: New test. + +2025-03-24 Liam Naddell <liamnprg@gmail.com> + + * rust/compile/macros/builtin/option_env1.rs: Add success case for option_env + * rust/compile/macros/builtin/option_env2.rs: Add failure case for option_env + * rust/execute/torture/builtin_macro_option_env.rs: Add + execution case for option_env + * rust/compile/macros/builtin/option_env3.rs: New file. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/nr2/exclude: nr2 cant handle this + * rust/compile/issue-3174.rs: New test. + +2025-03-24 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/nr2/exclude: Remove some tests. + +2025-03-24 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/nr2/exclude: Remove passing tests. + +2025-03-24 Philip Herron <herron.philip@googlemail.com> + + * rust/compile/nr2/exclude: these tests now work it seems + +2025-03-24 Owen Avery <powerboat9.gamer@gmail.com> + + * rust/compile/nr2/exclude: Add entries. + +2025-03-24 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/compile/try-trait.rs: New test. + +2025-03-24 Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com> + + * rust/compile/nr2/exclude: Remove break-rust3.rs from exclude list. + +2025-03-24 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/compile/derive_macro6.rs: Add lang item attribute to Copy trait. + +2025-03-24 lishin <lishin1008@gmail.com> + + * rust/compile/issue-2954.rs: New test. + +2025-03-24 Arthur Cohen <arthur.cohen@embecosm.com> + + * rust/compile/nr2/exclude: Some parts of nr2.0 can't handle auto traits yet. + * rust/compile/auto_traits3.rs: Removed in favor of... + * rust/compile/auto_traits2.rs: ...this one. + * rust/compile/auto_traits4.rs: New test. + +2025-03-24 Richard Earnshaw <rearnsha@arm.com> + + * gcc.target/arm/unaligned-memcpy-4.c: Tighten scan-assembler-not + pattern. + +2025-03-24 Thomas Schwinge <tschwinge@baylibre.com> + + * gcc.target/nvptx/march-map=sm_30.c: Adjust. + * gcc.target/nvptx/march-map=sm_32.c: Likewise. + * gcc.target/nvptx/march-map=sm_35.c: Likewise. + * gcc.target/nvptx/march-map=sm_37.c: Likewise. + * gcc.target/nvptx/march-map=sm_50.c: Likewise. + * gcc.target/nvptx/march=sm_30.c: Likewise. + * gcc.target/nvptx/march=sm_35.c: Likewise. + * gcc.target/nvptx/march=sm_37.c: Likewise. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + * gcc.target/i386/avx10-check.h: Change to avx10.1. + * gcc.target/i386/avx10_1-1.c: Add warning check. + * gcc.target/i386/avx10_1-10.c: Ditto. + * gcc.target/i386/avx10_1-11.c: Ditto. + * gcc.target/i386/avx10_1-12.c: Ditto. + * gcc.target/i386/avx10_1-13.c: Ditto. + * gcc.target/i386/avx10_1-15.c: Ditto. + * gcc.target/i386/avx10_1-16.c: Ditto. + * gcc.target/i386/avx10_1-18.c: Ditto. + * gcc.target/i386/avx10_1-19.c: Ditto. + * gcc.target/i386/avx10_1-2.c: Ditto. + * gcc.target/i386/avx10_1-20.c: Ditto. + * gcc.target/i386/avx10_1-21.c: Ditto. + * gcc.target/i386/avx10_1-22.c: Ditto. + * gcc.target/i386/avx10_1-23.c: Ditto. + * gcc.target/i386/avx10_1-26.c: Ditto. + * gcc.target/i386/avx10_1-3.c: Ditto. + * gcc.target/i386/avx10_1-4.c: Ditto. + * gcc.target/i386/avx10_1-7.c: Ditto. + * gcc.target/i386/avx10_1-8.c: Ditto. + * gcc.target/i386/avx10_1-9.c: Ditto. + * gcc.target/i386/noevex512-1.c: Ditto. + * gcc.target/i386/noevex512-2.c: Ditto. + * gcc.target/i386/pr111068.c: Ditto. + * gcc.target/i386/pr111907.c: Ditto. + * gcc.target/i386/pr117240_avx512f.c: Ditto. + * gcc.target/i386/pr117304-1.c: Ditto. + * gcc.target/i386/pr117946.c: Ditto. + * gcc.target/i386/avx10_1-24.c: Removed. + * gcc.target/i386/avx10_1-25.c: Removed. + * gcc.target/i386/avx10_1-5.c: Removed. + * gcc.target/i386/avx10_1-6.c: Removed. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + * g++.dg/other/i386-2.C: Use -mavx10.2. + * g++.dg/other/i386-3.C: Ditto. + * gcc.target/i386/avx-1.c: Ditto. + * gcc.target/i386/avx10_2-512-bf16-1.c: Ditto. + * gcc.target/i386/avx10_2-512-bf16-vector-cmp-1.c: Ditto. + * gcc.target/i386/avx10_2-512-bf16-vector-fma-1.c: Ditto. + * gcc.target/i386/avx10_2-512-bf16-vector-operations-1.c: Ditto. + * gcc.target/i386/avx10_2-512-bf16-vector-smaxmin-1.c: Ditto. + * gcc.target/i386/avx10_2-512-convert-1.c: Ditto. + * gcc.target/i386/avx10_2-512-media-1.c: Ditto. + * gcc.target/i386/avx10_2-512-minmax-1.c: Ditto. + * gcc.target/i386/avx10_2-512-movrs-1.c: Ditto. + * gcc.target/i386/avx10_2-512-satcvt-1.c: Ditto. + * gcc.target/i386/avx10_2-512-vaddbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcmpbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvt2ph2bf8-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvt2ph2bf8s-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvt2ph2hf8-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvt2ph2hf8s-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvt2ps2phx-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtbf162ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtbf162iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtbiasph2bf8-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtbiasph2bf8s-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtbiasph2hf8-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtbiasph2hf8s-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvthf82ph-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtph2bf8-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtph2bf8s-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtph2hf8-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtph2hf8s-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtph2ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtph2iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtps2ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtps2iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttbf162ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttbf162iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttpd2dqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttpd2qqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttpd2udqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttpd2uqqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttph2ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttps2dqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttps2ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttps2iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttps2qqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttps2udqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttps2uqqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vdivbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vdpphps-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vfmaddXXXbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vfmsubXXXbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vfnmaddXXXbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vfnmsubXXXbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vfpclassbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vgetexpbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vgetmantbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vmaxbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vminbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vminmaxbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vminmaxpd-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vminmaxph-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vminmaxps-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vmpsadbw-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vmulbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vpdpbssd-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vpdpbssds-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vpdpbsud-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vpdpbsuds-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vpdpbuud-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vpdpbuuds-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vpdpwsud-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vpdpwsuds-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vpdpwusd-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vpdpwusds-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vpdpwuud-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vpdpwuuds-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vrcpbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vreducebf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vrndscalebf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vrsqrtbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vscalefbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vsqrtbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vsubbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-bf16-1.c: Ditto. + * gcc.target/i386/avx10_2-bf16-vector-cmp-1.c: Ditto. + * gcc.target/i386/avx10_2-bf16-vector-fma-1.c: Ditto. + * gcc.target/i386/avx10_2-bf16-vector-operations-1.c: Ditto. + * gcc.target/i386/avx10_2-bf16-vector-smaxmin-1.c: Ditto. + * gcc.target/i386/avx10_2-builtin-1.c: Ditto. + * gcc.target/i386/avx10_2-builtin-2.c: Ditto. + * gcc.target/i386/avx10_2-comibf-1.c: Ditto. + * gcc.target/i386/avx10_2-comibf-2.c: Ditto. + * gcc.target/i386/avx10_2-comibf-3.c: Ditto. + * gcc.target/i386/avx10_2-comibf-4.c: Ditto. + * gcc.target/i386/avx10_2-compare-1.c: Ditto. + * gcc.target/i386/avx10_2-compare-1b.c: Ditto. + * gcc.target/i386/avx10_2-convert-1.c: Ditto. + * gcc.target/i386/avx10_2-media-1.c: Ditto. + * gcc.target/i386/avx10_2-minmax-1.c: Ditto. + * gcc.target/i386/avx10_2-movrs-1.c: Ditto. + * gcc.target/i386/avx10_2-partial-bf16-vector-fast-math-1.c: Ditto. + * gcc.target/i386/avx10_2-partial-bf16-vector-fma-1.c: Ditto. + * gcc.target/i386/avx10_2-partial-bf16-vector-operations-1.c: Ditto. + * gcc.target/i386/avx10_2-partial-bf16-vector-smaxmin-1.c: Ditto. + * gcc.target/i386/avx10_2-satcvt-1.c: Ditto. + * gcc.target/i386/avx10_2-vaddbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vcmpbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vcomisbf16-1.c: Ditto. + * gcc.target/i386/avx10_2-vcomisbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvt2ph2bf8-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvt2ph2bf8s-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvt2ph2hf8-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvt2ph2hf8s-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvt2ps2phx-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvtbf162ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvtbf162iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvtbiasph2bf8-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvtbiasph2bf8s-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvtbiasph2hf8-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvtbiasph2hf8s-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvthf82ph-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvtph2bf8-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvtph2bf8s-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvtph2hf8-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvtph2hf8s-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvtph2ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvtph2iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvtps2ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvtps2iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttbf162ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttbf162iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttpd2dqs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttpd2qqs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttpd2udqs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttpd2uqqs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttph2ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttph2iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttps2dqs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttps2ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttps2iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttps2qqs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttps2udqs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttps2uqqs-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttsd2sis-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttsd2usis-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttss2sis-2.c: Ditto. + * gcc.target/i386/avx10_2-vcvttss2usis-2.c: Ditto. + * gcc.target/i386/avx10_2-vdivbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vdpphps-2.c: Ditto. + * gcc.target/i386/avx10_2-vfmaddXXXbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vfmsubXXXbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vfnmaddXXXbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vfnmsubXXXbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vfpclassbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vgetexpbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vgetmantbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vmaxbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vminbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vminmaxbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vminmaxpd-2.c: Ditto. + * gcc.target/i386/avx10_2-vminmaxph-2.c: Ditto. + * gcc.target/i386/avx10_2-vminmaxps-2.c: Ditto. + * gcc.target/i386/avx10_2-vminmaxsd-2.c: Ditto. + * gcc.target/i386/avx10_2-vminmaxsh-2.c: Ditto. + * gcc.target/i386/avx10_2-vminmaxss-2.c: Ditto. + * gcc.target/i386/avx10_2-vmovd-1.c: Ditto. + * gcc.target/i386/avx10_2-vmovd-2.c: Ditto. + * gcc.target/i386/avx10_2-vmovw-1.c: Ditto. + * gcc.target/i386/avx10_2-vmovw-2.c: Ditto. + * gcc.target/i386/avx10_2-vmpsadbw-2.c: Ditto. + * gcc.target/i386/avx10_2-vmulbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vpdpbssd-2.c: Ditto. + * gcc.target/i386/avx10_2-vpdpbssds-2.c: Ditto. + * gcc.target/i386/avx10_2-vpdpbsud-2.c: Ditto. + * gcc.target/i386/avx10_2-vpdpbsuds-2.c: Ditto. + * gcc.target/i386/avx10_2-vpdpbuud-2.c: Ditto. + * gcc.target/i386/avx10_2-vpdpbuuds-2.c: Ditto. + * gcc.target/i386/avx10_2-vpdpwsud-2.c: Ditto. + * gcc.target/i386/avx10_2-vpdpwsuds-2.c: Ditto. + * gcc.target/i386/avx10_2-vpdpwusd-2.c: Ditto. + * gcc.target/i386/avx10_2-vpdpwusds-2.c: Ditto. + * gcc.target/i386/avx10_2-vpdpwuud-2.c: Ditto. + * gcc.target/i386/avx10_2-vpdpwuuds-2.c: Ditto. + * gcc.target/i386/avx10_2-vrcpbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vreducebf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vrndscalebf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vrsqrtbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vscalefbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vsqrtbf16-2.c: Ditto. + * gcc.target/i386/avx10_2-vsubbf16-2.c: Ditto. + * gcc.target/i386/funcspec-56.inc: Ditto. + * gcc.target/i386/part-vect-vec_cmpbf.c: Ditto. + * gcc.target/i386/pr117495.c: Ditto. + * gcc.target/i386/pr118815.c: Ditto. + * gcc.target/i386/sm4-avx10_2-1.c: Ditto. + * gcc.target/i386/sm4-avx10_2-512-1.c: Ditto. + * gcc.target/i386/sm4key4-avx10_2-512-2.c: Ditto. + * gcc.target/i386/sm4rnds4-avx10_2-512-2.c: Ditto. + * gcc.target/i386/sse-12.c: Ditto. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Ditto. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/vnniint16-auto-vectorize-3.c: Ditto. + * gcc.target/i386/vnniint16-auto-vectorize-4.c: Ditto. + * gcc.target/i386/vnniint8-auto-vectorize-3.c: Ditto. + * gcc.target/i386/vnniint8-auto-vectorize-4.c: Ditto. + * gcc.target/i386/avx10-check.h: Remove avx10.2-512 and + use avx10.2. + * gcc.target/i386/sm4-check.h: Ditto. + * lib/target-supports.exp: Ditto. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add -mavx10.2 and new builtin test. + * gcc.target/i386/avx-2.c: Ditto. + * gcc.target/i386/sse-13.c: Add new tests. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Ditto. + * gcc.target/i386/avx10_2-rounding-1.c: New test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/sse-14.c: Add new macro test. + * gcc.target/i386/sse-22.c: Ditto. + * gcc.target/i386/avx10_2-rounding-1.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/sse-14.c: Add new macro test. + * gcc.target/i386/sse-22.c: Ditto. + * gcc.target/i386/avx10_2-rounding-1.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-1.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-1.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-1.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-2.c: New test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-2.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-2.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-3.c: New test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-3.c: New test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-3.c: New test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-3.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-3.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-3.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-3.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-3.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-3.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-3.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-3.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-3.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + Revert: + 2025-03-24 Hu, Lin1 <lin1.hu@intel.com> + + * gcc.target/i386/avx-1.c: Add new builtin test. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Add new macro test. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/avx10_2-rounding-3.c: Add test. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + * gcc.target/i386/avx10_2-512-vcvtph2ibs-2.c: Adjust condition + for rounding test. + * gcc.target/i386/avx10_2-512-vcvtph2iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtps2ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvtps2iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttpd2dqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttpd2qqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttpd2udqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttpd2uqqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttph2ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttps2dqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttps2ibs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttps2iubs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttps2qqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttps2udqs-2.c: Ditto. + * gcc.target/i386/avx10_2-512-vcvttps2uqqs-2.c: Ditto. + * gcc.target/i386/avx-1.c: Remove rounding tests. + * gcc.target/i386/avx10_2-satcvt-1.c: Ditto. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Ditto. + * gcc.target/i386/sse-23.c: Ditto. + +2025-03-24 Haochen Jiang <haochen.jiang@intel.com> + + * gcc.target/i386/avx-1.c: Remove rounding tests. + * gcc.target/i386/avx10_2-convert-1.c: Ditto. + * gcc.target/i386/avx10_2-minmax-1.c: Ditto. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Ditto. + * gcc.target/i386/sse-23.c: Ditto. + 2025-03-23 Nathaniel Shead <nathanieloshead@gmail.com> PR c++/119154 diff --git a/gcc/testsuite/c-c++-common/gomp/append-args-1.c b/gcc/testsuite/c-c++-common/gomp/append-args-1.c index 2a47063..e03b8de 100644 --- a/gcc/testsuite/c-c++-common/gomp/append-args-1.c +++ b/gcc/testsuite/c-c++-common/gomp/append-args-1.c @@ -23,25 +23,19 @@ float base0(); float repl1(omp_interop_t, omp_interop_t); #pragma omp declare variant(repl1) match(construct={dispatch}) append_args(interop(target), interop(targetsync)) float base1(); -/* { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'repl1', except when specifying all 2 objects in the 'interop' clause of the 'dispatch' directive" "" { target c } .-2 } */ -/* { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'float repl1\\(omp_interop_t, omp_interop_t\\)', except when specifying all 2 objects in the 'interop' clause of the 'dispatch' directive" "" { target c++ } .-3 } */ void repl2(int *, int *, omp_interop_t, omp_interop_t); #pragma omp declare variant(repl2) match(construct={dispatch}) adjust_args(need_device_ptr : y) \ append_args(interop(target, targetsync, prefer_type(1)), \ interop(prefer_type({fr(3), attr("ompx_nop")},{fr(2)},{attr("ompx_all")}))) void base2(int *x, int *y); -/* { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'repl2', except when specifying all 2 objects in the 'interop' clause of the 'dispatch' directive" "" { target c } .-3 } */ -/* { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'void repl2\\(int\\*, int\\*, omp_interop_t, omp_interop_t\\)', except when specifying all 2 objects in the 'interop' clause of the 'dispatch' directive" "" { target c++ } .-4 } */ void repl3(int, omp_interop_t, ...); #pragma omp declare variant(repl3) match(construct={dispatch}) \ append_args(interop(prefer_type("cuda", "hsa"))) void base3(int, ...); -/* { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'repl3', except when specifying all 1 objects in the 'interop' clause of the 'dispatch' directive" "" { target c } .-2 } */ -/* { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'void repl3\\(int, omp_interop_t, \\.\\.\\.\\)', except when specifying all 1 objects in the 'interop' clause of the 'dispatch' directive" "" { target c++ } .-3 } */ -/* { dg-note "'declare variant' candidate 'repl3' declared here" "" { target c } .-4 } */ -/* { dg-note "'declare variant' candidate 'void repl3\\(int, omp_interop_t, \\.\\.\\.\\)' declared here" "" { target c++ } .-5 } */ +/* { dg-note "'declare variant' candidate 'repl3' declared here" "" { target c } .-2 } */ +/* { dg-note "'declare variant' candidate 'void repl3\\(int, omp_interop_t, \\.\\.\\.\\)' declared here" "" { target c++ } .-3 } */ float repl4(short, short, omp_interop_t, short); #pragma omp declare variant(repl4) match(construct={dispatch}) append_args(interop(target)) append_args(interop(targetsync)) /* { dg-error "too many 'append_args' clauses" } */ @@ -75,15 +69,12 @@ test (int *a, int *b) #pragma omp dispatch interop ( obj1 ) x = base1 (); - /* { dg-note "required by 'dispatch' construct" "" { target *-*-* } .-2 } */ #pragma omp dispatch interop ( obj1 ) base2 (a, b); - /* { dg-note "required by 'dispatch' construct" "" { target *-*-* } .-2 } */ #pragma omp dispatch base3 (5, 1, 2, 3); - /* { dg-note "required by 'dispatch' construct" "" { target *-*-* } .-2 } */ #pragma omp dispatch interop (obj2) base3 (5, 1, 2, 3); @@ -92,7 +83,6 @@ test (int *a, int *b) base3 (5, 1, 2, 3); /* { dg-error "number of list items in 'interop' clause \\(2\\) exceeds the number of 'append_args' items \\(1\\) for 'declare variant' candidate 'repl3'" "" { target c } .-2 } */ /* { dg-error "number of list items in 'interop' clause \\(2\\) exceeds the number of 'append_args' items \\(1\\) for 'declare variant' candidate 'void repl3\\(int, omp_interop_t, \\.\\.\\.\\)'" "" { target c++ } .-3 } */ - /* { dg-note "required by 'dispatch' construct" "" { target *-*-* } .-4 } */ return x; } diff --git a/gcc/testsuite/c-c++-common/gomp/append-args-interop.c b/gcc/testsuite/c-c++-common/gomp/append-args-interop.c new file mode 100644 index 0000000..9494625 --- /dev/null +++ b/gcc/testsuite/c-c++-common/gomp/append-args-interop.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-fdump-tree-gimple" } */ + +/* Test that interop objects are implicitly created/destroyed when a dispatch + construct doesn't provide enough of them to satisfy the declare variant + append_args clause. */ + +/* The following definitions are in omp_lib, which cannot be included + in gcc/testsuite/ */ + +#if __cplusplus >= 201103L +# define __GOMP_UINTPTR_T_ENUM : __UINTPTR_TYPE__ +#else +# define __GOMP_UINTPTR_T_ENUM +#endif + +typedef enum omp_interop_t __GOMP_UINTPTR_T_ENUM +{ + omp_interop_none = 0, + __omp_interop_t_max__ = __UINTPTR_MAX__ +} omp_interop_t; + +float repl1(omp_interop_t, omp_interop_t, omp_interop_t); + +#pragma omp declare variant(repl1) match(construct={dispatch}) append_args(interop(target), interop(targetsync), interop (target)) +float base1(); + +float +test (int *a, int *b) +{ + omp_interop_t obj1; + float x; + + /* repl1 takes 3 interop arguments, one will come from the dispatch + construct and the other 2 will be consed up. */ + #pragma omp dispatch interop ( obj1 ) + x = base1 (); + + return x; +} + +/* { dg-final { scan-tree-dump "__builtin_GOMP_interop \\(D\.\[0-9\]+, 2, interopobjs\.\[0-9\]+, tgt_tgtsync\.\[0-9\]+," "gimple" } } */ +/* { dg-final { scan-tree-dump "__builtin_GOMP_interop \\(D\.\[0-9\]+, 0, 0B, 0B, 0B, 0, 0B, 2, interopobjs\.\[0-9\]+," "gimple" } } */ +/* { dg-final { scan-tree-dump "repl1 \\(obj1, interop\.\[0-9\]+, interop\.\[0-9\]+\\)" "gimple" } } */ diff --git a/gcc/testsuite/c-c++-common/gomp/dispatch-11.c b/gcc/testsuite/c-c++-common/gomp/dispatch-11.c index e59985a..79dcd0a 100644 --- a/gcc/testsuite/c-c++-common/gomp/dispatch-11.c +++ b/gcc/testsuite/c-c++-common/gomp/dispatch-11.c @@ -87,12 +87,9 @@ test (int *a, int *b) base3 (a, b); /* { dg-error "number of list items in 'interop' clause \\(2\\) exceeds the number of 'append_args' items \\(1\\) for 'declare variant' candidate 'repl3'" "" { target c } .-2 } */ /* { dg-error "number of list items in 'interop' clause \\(2\\) exceeds the number of 'append_args' items \\(1\\) for 'declare variant' candidate 'void repl3\\(int\\*, int\\*, omp_interop_t\\)'" "" { target c++ } .-3 } */ - /* { dg-note "required by 'dispatch' construct" "" { target *-*-* } .-4 } */ #pragma omp dispatch interop(obj3) base3 (a, b); - /* { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'repl3'" "" { target c } 28 } */ - /* { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'void repl3\\(int\\*, int\\*, omp_interop_t\\)'" "" { target c++ } 28 } */ return x + y; } diff --git a/gcc/testsuite/cobol.dg/data1.cob b/gcc/testsuite/cobol.dg/data1.cob new file mode 100644 index 0000000..5830195 --- /dev/null +++ b/gcc/testsuite/cobol.dg/data1.cob @@ -0,0 +1,14 @@ +*> { dg-do run } +*> { dg-output {1.2345678E\+07(\n|\r\n|\r)} } +*> { dg-output {1.2345678E\+07(\n|\r\n|\r)} } + IDENTIFICATION DIVISION. + PROGRAM-ID. data1. + DATA DIVISION. + WORKING-STORAGE SECTION. + 01 FLOATLONG FLOAT-LONG VALUE 12345678. + 01 FLOATEXT FLOAT-EXTENDED VALUE 12345678. + PROCEDURE DIVISION. + DISPLAY FLOATLONG + DISPLAY FLOATEXT + GOBACK. + END PROGRAM data1. diff --git a/gcc/testsuite/cobol.dg/literal1.cob b/gcc/testsuite/cobol.dg/literal1.cob new file mode 100644 index 0000000..43369e0 --- /dev/null +++ b/gcc/testsuite/cobol.dg/literal1.cob @@ -0,0 +1,14 @@ +*> { dg-do run } +*> Make sure we properly round to integer when computing the initial +*> binary representation of a literal +IDENTIFICATION DIVISION. +PROGRAM-ID. literal1. +DATA DIVISION. +WORKING-STORAGE SECTION. + 77 VAR8 PIC 999V9(8) COMP-5 . + 77 VAR555 PIC 999V99999999 COMP-5 VALUE 555.55555555. + PROCEDURE DIVISION. + MOVE 555.55555555 TO VAR8 + ADD 0.00000001 TO VAR555 GIVING VAR8 ROUNDED + IF VAR8 NOT EQUAL TO 555.55555556 STOP RUN ERROR 1. + END PROGRAM literal1. diff --git a/gcc/testsuite/cobol.dg/output1.cob b/gcc/testsuite/cobol.dg/output1.cob new file mode 100644 index 0000000..9475bde --- /dev/null +++ b/gcc/testsuite/cobol.dg/output1.cob @@ -0,0 +1,14 @@ +*> { dg-do run } +*> { dg-output {-0.00012(\n|\r\n|\r)} } +*> { dg-output {0.00012(\n|\r\n|\r)} } +*> { dg-output {1234.66(\n|\r\n|\r)} } +*> { dg-output {-99.8(\n|\r\n|\r)} } +IDENTIFICATION DIVISION. +PROGRAM-ID. output1. +ENVIRONMENT DIVISION. +PROCEDURE DIVISION. + DISPLAY -0.00012 + DISPLAY 0.00012 + DISPLAY 1234.66 + DISPLAY -99.8 + STOP RUN. diff --git a/gcc/testsuite/g++.dg/cpp2a/lambda-uneval25.C b/gcc/testsuite/g++.dg/cpp2a/lambda-uneval25.C new file mode 100644 index 0000000..7fdd44d --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/lambda-uneval25.C @@ -0,0 +1,11 @@ +// { dg-do compile { target c++20 } } + +template <class T> +void foo(T x) { + sizeof []<int=0>(T=x) { return 0; }(); // { dg-error "may not appear" } + sizeof [](T=x) { return 0; }(); // { dg-error "may not appear" } +}; + +void test() { + foo(0); +} diff --git a/gcc/testsuite/g++.dg/expr/cond18.C b/gcc/testsuite/g++.dg/expr/cond18.C new file mode 100644 index 0000000..326985e --- /dev/null +++ b/gcc/testsuite/g++.dg/expr/cond18.C @@ -0,0 +1,36 @@ +/* PR c++/114525 */ +/* { dg-do run } */ + +struct Foo { + int x; +}; + +Foo& get (Foo& v) { + return v; +} + +int main () { + bool cond = true; + + /* Testcase from PR; v.x would wrongly remain equal to 1. */ + Foo v_ko; + v_ko.x = 1; + (cond ? get (v_ko) : get (v_ko)).*(&Foo::x) = 2; + if (v_ko.x != 2) + __builtin_abort (); + + /* Those would already work, i.e. x be changed to 2. */ + Foo v_ok_1; + v_ok_1.x = 1; + (cond ? get (v_ok_1) : get (v_ok_1)).x = 2; + if (v_ok_1.x != 2) + __builtin_abort (); + + Foo v_ok_2; + v_ok_2.x = 1; + get (v_ok_2).*(&Foo::x) = 2; + if (v_ok_2.x != 2) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/g++.dg/ext/vector44.C b/gcc/testsuite/g++.dg/ext/vector44.C new file mode 100644 index 0000000..cb24ef6 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/vector44.C @@ -0,0 +1,5 @@ +// PR c++/101881 +// { dg-do compile { target c++11 } } + +template<int N> using A = int __attribute__((vector_size(N)))*; +void foo(A<4>) {} diff --git a/gcc/testsuite/g++.dg/gomp/append-args-1.C b/gcc/testsuite/g++.dg/gomp/append-args-1.C index 7ff4023..25ea4c2 100644 --- a/gcc/testsuite/g++.dg/gomp/append-args-1.C +++ b/gcc/testsuite/g++.dg/gomp/append-args-1.C @@ -20,8 +20,6 @@ template<typename T> float base1(T); -/* { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'float repl1\\(T, T2, T2\\) \\\[with T = omp_interop_t; T2 = omp_interop_t\\\]', except when specifying all 2 objects in the 'interop' clause of the 'dispatch' directive" "" { target *-*-* } .-5 } */ -/* { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'float repl1\\(T, T2, T2\\) \\\[with T = float; T2 = omp_interop_t\\\]', except when specifying all 2 objects in the 'interop' clause of the 'dispatch' directive" "" { target *-*-* } .-6 } */ @@ -45,8 +43,6 @@ void repl99(T); append_args(interop(target, targetsync, prefer_type("cuda"))) void base99(); -/* { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'void repl99\\(T\\) \\\[with T = omp_interop_t\\\]', except when specifying all 1 objects in the 'interop' clause of the 'dispatch' directive" "" { target *-*-* } .-3 } */ - template<typename T, typename T2, typename T3> @@ -57,9 +53,6 @@ void repl2(T, T2, T3, T3); template<typename T, typename T2> void base2(T x, T2 y); -/* { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'void repl2\\(T, T2, T3, T3\\) \\\[with T = int\\*; T2 = int\\*; T3 = omp_interop_t\\\]', except when specifying all 2 objects in the 'interop' clause of the 'dispatch' directive" "" { target *-*-* } .-5 } */ -/* { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'void repl2\\(T, T2, T3, T3\\) \\\[with T = int\\*; T2 = omp_interop_t; T3 = omp_interop_t\\\]', except when specifying all 2 objects in the 'interop' clause of the 'dispatch' directive" "" { target *-*-* } .-6 } */ - template<typename T,typename T3> void tooFewRepl(T, T, T3); @@ -83,7 +76,6 @@ void repl3(T, T2, ...); template<typename T> void base3(T, ...); -/* { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'void repl3\\(T, T2, \.\.\.\\) \\\[with T = int\\*; T2 = omp_interop_t\\\]', except when specifying all 1 objects in the 'interop' clause of the 'dispatch' directive" "" { target *-*-* } .-4 } */ @@ -104,23 +96,18 @@ test (int *a, int *b) #pragma omp dispatch base99 (); - /* { dg-note "required by 'dispatch' construct" "" { target *-*-* } .-2 } */ - #pragma omp dispatch interop ( obj1 ) + #pragma omp dispatch interop ( obj1 ) // { dg-message "sorry" } base2<int *, omp_interop_t> (b, omp_interop_none); - /* { dg-note "required by 'dispatch' construct" "" { target *-*-* } .-2 } */ - #pragma omp dispatch interop ( obj1 ) + #pragma omp dispatch interop ( obj1 ) // { dg-message "sorry" } base2<int *, int *> (b, a); - /* { dg-note "required by 'dispatch' construct" "" { target *-*-* } .-2 } */ #pragma omp dispatch interop ( obj1 ) x = base1<omp_interop_t> (omp_interop_none); - /* { dg-note "required by 'dispatch' construct" "" { target *-*-* } .-2 } */ #pragma omp dispatch interop ( obj1 ) x = base1<float> (1.0f); - /* { dg-note "required by 'dispatch' construct" "" { target *-*-* } .-2 } */ #pragma omp dispatch tooFewBase<int*,int*>(a,b); @@ -130,7 +117,6 @@ test (int *a, int *b) #pragma omp dispatch base3<int*>(a, 1, 2, "abc"); - /* { dg-note "required by 'dispatch' construct" "" { target *-*-* } .-2 } */ return x; } diff --git a/gcc/testsuite/g++.dg/opt/musttail2.C b/gcc/testsuite/g++.dg/opt/musttail2.C new file mode 100644 index 0000000..ee55c1a --- /dev/null +++ b/gcc/testsuite/g++.dg/opt/musttail2.C @@ -0,0 +1,14 @@ +// PR ipa/119376 +// { dg-do compile { target musttail } } +// { dg-options "-O2 -fno-early-inlining -fdump-tree-optimized" } +// { dg-final { scan-tree-dump-times " \[^\n\r]* = foo \\\(\[^\n\r]*\\\); \\\[tail call\\\] \\\[must tail call\\\]" 1 "optimized" } } + +struct S { S () {} }; +char *foo (S); + +char * +bar (S) +{ + S t; + [[clang::musttail]] return foo (t); +} diff --git a/gcc/testsuite/g++.dg/torture/musttail1.C b/gcc/testsuite/g++.dg/torture/musttail1.C new file mode 100644 index 0000000..12012ad --- /dev/null +++ b/gcc/testsuite/g++.dg/torture/musttail1.C @@ -0,0 +1,15 @@ +// PR ipa/119376 +// { dg-do compile { target musttail } } +// { dg-additional-options "-ffat-lto-objects -fdump-tree-optimized" } +/* { dg-final { scan-tree-dump-times " \[^\n\r]* = foo \\\(\[^\n\r]*\\\); \\\[tail call\\\] \\\[must tail call\\\]" 1 "optimized" } } */ + +struct S { int s; }; +int foo (int); + +int +bar (int a) +{ + S b = {a}; + b.s++; + [[gnu::musttail]] return foo (a); +} diff --git a/gcc/testsuite/gcc.c-torture/execute/pr119428.c b/gcc/testsuite/gcc.c-torture/execute/pr119428.c new file mode 100644 index 0000000..33a93f4 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr119428.c @@ -0,0 +1,18 @@ +/* PR target/119428 */ + +__attribute__((noipa)) void +foo (unsigned int x, unsigned char *y) +{ + y += x >> 3; + *y &= (unsigned char) ~(1 << (x & 0x07)); +} + +int +main () +{ + unsigned char buf[8]; + __builtin_memset (buf, 0xff, 8); + foo (8, buf); + if (buf[1] != 0xfe) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.dg/ipa/ipa-icf-40.c b/gcc/testsuite/gcc.dg/ipa/ipa-icf-40.c new file mode 100644 index 0000000..ab328ba --- /dev/null +++ b/gcc/testsuite/gcc.dg/ipa/ipa-icf-40.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-ipa-icf-optimized" } */ + +int c0 = 0; +typedef int v4si __attribute__((vector_size(4*sizeof(int)))); +v4si a; +int f() +{ + return a[c0]; +} +int g() +{ + return a[c0]; +} + +/* { dg-final { scan-ipa-dump "optimized: Semantic equality hit:f/\[0-9+\]+->g/\[0-9+\]+" "icf" } } */ diff --git a/gcc/testsuite/gcc.dg/torture/pr117811.c b/gcc/testsuite/gcc.dg/torture/pr117811.c new file mode 100644 index 0000000..13d7e13 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr117811.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ + +#include <string.h> + +typedef int v4 __attribute__((vector_size (4 * sizeof (int)))); + +void __attribute__((noclone,noinline)) do_shift (v4 *vec, int shift) +{ + v4 t = *vec; + + if (shift > 0) + { + t = t >> shift; + } + + *vec = t; +} + +int main () +{ + v4 vec = {0x1000000, 0x2000, 0x300, 0x40}; + v4 vec2 = {0x100000, 0x200, 0x30, 0x4}; + do_shift (&vec, 4); + if (memcmp (&vec, &vec2, sizeof (v4)) != 0) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_dup.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_dup.c index c42c7ac..da9370b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_dup.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_dup.c @@ -1,6 +1,6 @@ /* { dg-do assemble { target { aarch64*-*-* } } } */ +/* { dg-skip-if "no optimizations" { *-*-* } { "-O0" } { "" } } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ -/* { dg-options "-O2" } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ /* { dg-additional-options "-save-temps" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c index 3a5efa5..7478323 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c index 16a986a..ebae422 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c index 4b0e242..dd62e32b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c index 0bebec7..70279d2 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c index 68ce599..2e8205d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c index 1b5a09b..eae7189 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c index 766c783..f23900e 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c index 8f5c14b..a735602 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c index ccfecf42..2792c2c1 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c index 161c7a0..6b4e028 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c index 2d3cd8a..cf44631 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c index 0d35385..c95a455 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c index ca23e3f..a801785 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c index f51cac3..9d17b05 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c index 57901c8..94e2f5d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c index 3218873..a1c8c50 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c index af6a5b6..9620001 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c index 2084c30..05cda23 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c index ebfd62a..f567e9b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c index a27871b..842005b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c index 0642ae0..1e23056 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c index 5ae28fc..719769a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c index 2d197b4..77b226b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c index 540b637..32a7f92 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c index 2173a0e..a24f787 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c index 5f17dbe..7a7617d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c index 426700c..7c6ad5a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c index 1583202..afe6c03 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c index 3413de0..6c988e6 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c index 25265d1..87dcfe5 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c index 9ce9558..944b325 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c index f0adb09..2756d0e 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c index 74c4e60..874726d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c index d308c35..4ee9dc7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c index b393767..ef61a24 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c index 247f7c9..8e725c7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c index 6e2ee50..f09cab0 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c index 27502c2..668be0f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c index e5f57f1..d3aeb69 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c index 188f60c..c66ee58 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c index cfc33c2..dd2dfbd 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c index 9965654..21055db 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c index 6bff954..c6d8481 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c index c7b3d17..a8bb322 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c index e3c5d3a..a2300b4 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c index d5807d7..1de5551 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c index a904e5e..a5b346f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c index ef0132a..d20e2dc 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c index f4f7b37..474cd20 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c index 7b5b16f..b564749 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c index db56171..1e5c289 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c index 6cda3b6..3ee2194 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c index cae69a3..175bcf2 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c index dec8d85..ef5acbb 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c index 94c333e..2f9855c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c index 0048b5b..f159ac2 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c index 0a95cea..39d92ec 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c index 97d5fba..fe605b5 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c index 3b1b273..597a2e0 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c index 5ff0d22..d58cad8 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c index 105d236..a2a246d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c index 290c5b1..a4905b1 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c index e367dad..8e443bd 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c index d66adcd..63b793bc 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c index 0229099..b1238de 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c index c0103fb..99c3e95 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c index 6a99109..c5b458b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c index c9d553a..789d9e2 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c index 1ac6b67..aae9a94 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c index 00c95d3..363d25f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c index f01aefb..72416dc 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c index ea751da..57ff684 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c index 77021be..d2486f1 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c index 6e56ff1..0892ce7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c @@ -1,5 +1,4 @@ /* We haven't implemented these intrinsics for arm yet. */ -/* { dg-do run } */ /* { dg-skip-if "unimplemented" { arm*-*-* } } */ /* { dg-options "-O3" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c index 42aeadf..9465e4a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c @@ -1,5 +1,4 @@ /* We haven't implemented these intrinsics for arm yet. */ -/* { dg-do run } */ /* { dg-skip-if "unimplemented" { arm*-*-* } } */ /* { dg-options "-O3" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c index 694fda8..a1461fd 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c @@ -1,5 +1,4 @@ /* We haven't implemented these intrinsics for arm yet. */ -/* { dg-do run } */ /* { dg-skip-if "unimplemented" { arm*-*-* } } */ /* { dg-options "-O3" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c index 182463e..763eb47 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c index 4db4b84..5242d55 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c index ce9872f..3b12e62 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c index 39c4897..bcb56fe 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c index d8efbca..9ee302f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c index f6b0216..e70bc6c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c index b7c5101..1910d9f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c index c454a53..3ab5432 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c index 18d1767..8f1d012 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-skip-if "" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c index 6c51d04..f434564 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-skip-if "" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c index 1719d56..d470308 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c index 09684d2..85fe687 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c index 4cd5c37..fe7cc84 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c index 51bbead..1b5b869 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c index f90a36d..2a4f24f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c index 140647b..d1fd316 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c index 66c744c..1c85773 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c index 90a5be8..d2df24c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c index 421d827..37ce039 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c index c8df677..df3b83d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrn_high_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrn_high_n.c index 6ebe074..07d873d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrn_high_n.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrn_high_n.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrun_high_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrun_high_n.c index 49d319d..e8f464d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrun_high_n.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrun_high_n.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrn_high_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrn_high_n.c index 8d06f11..5a3ea62 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrn_high_n.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrn_high_n.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrun_high_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrun_high_n.c index e8235fe..80c66fd 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrun_high_n.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrun_high_n.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c index 3740d6a..f0d0da7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c index 3e6b24e..9dd8981 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c index fc02b6b..9593b18 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c index bcf47f6..6b40e29 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c index 3c4649e..691fcd7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c index 7a4620b..1c596b0 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c index 4a7b721..6cbcf7c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c index 9af357d..7accb45 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c index eb4b27d..bc841b5 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c index 3fa9749..856a661 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c index eb4b27d..bc841b5 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c index 7c0e619..02d8bb7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c index a9753a4..b32c44c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c index 82249a7..77f9460 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c index 7d03827..89b910c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c index 69be40a..3cf5eb3 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c @@ -1,5 +1,4 @@ /* We haven't implemented these intrinsics for arm yet. */ -/* { dg-do run } */ /* { dg-skip-if "unimplemented" { arm*-*-* } } */ /* { dg-options "-O3" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c index 4d42bcc..c05f8e7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c @@ -1,5 +1,4 @@ /* We haven't implemented these intrinsics for arm yet. */ -/* { dg-do run } */ /* { dg-skip-if "unimplemented" { arm*-*-* } } */ /* { dg-options "-O3" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c index ddc7fa5..a9867c3 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c @@ -1,5 +1,4 @@ /* We haven't implemented these intrinsics for arm yet. */ -/* { dg-do run } */ /* { dg-skip-if "unimplemented" { arm*-*-* } } */ /* { dg-options "-O3" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c index a7aba11..d24a599 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c index 6debfe5..c9485c3 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c index fe35e15..12ae8b0 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c index 5914192..65bc140 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect.inc b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect.inc index 1fadfd5..1fadfd5 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect.inc +++ b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect.inc diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_1.c b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_1.c index 2b72be7..2b72be7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_1.c diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_2.c b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_2.c index 0640361..0640361 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_2.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_2.c diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_3.c b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_3.c index ea6e0c7..ea6e0c7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_3.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_3.c diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_4.c b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_4.c index 0139063..0139063 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_4.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_4.c diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c index 447a8ec..63d57d4 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv4" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v4_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v4 } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c index 28fd2f7..d33beef 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv4t" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v4t_arm_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v4t } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c index 78878f7..8f43801 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv4t" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v4t_thumb_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v4t } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c index 8191299..cc139f1 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5t" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v5t_arm_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v5t } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c index b25d17d..1432018 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5t" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v5t_thumb_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v5t } */ @@ -14,4 +12,9 @@ #define NEED_ARM_ARCH_ISA_THUMB #define VALUE_ARM_ARCH_ISA_THUMB 1 +/* Not in the Thumb ISA, but does exist in Arm state. A call to the library + function should result in using that instruction in Arm state. */ +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + #include "ftest-support.h" diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c index e0c0d5c..2917ee6 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5te" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v5te_arm_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v5te } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c index 27a64a2..768dbaa 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5te" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v5te_thumb_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v5te } */ @@ -14,4 +12,9 @@ #define NEED_ARM_ARCH_ISA_THUMB #define VALUE_ARM_ARCH_ISA_THUMB 1 +/* Not in the Thumb ISA, but does exist in Arm state. A call to the library + function should result in using that instruction in Arm state. */ +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + #include "ftest-support.h" diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c index 5d447c3..648acb1 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v6_arm_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v6 } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c index 15a6d75..02360ee 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v6_thumb_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v6 } */ @@ -14,4 +12,9 @@ #define NEED_ARM_ARCH_ISA_THUMB #define VALUE_ARM_ARCH_ISA_THUMB 1 +/* Not in the Thumb ISA, but does exist in Arm state. A call to the library + function should result in using that instruction in Arm state. */ +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + #include "ftest-support.h" diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c index 0656e8f..ccc4e03 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6k" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v6k_arm_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v6k } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c index b3b6ecf..2c5490f 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6k" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v6k_thumb_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v6k } */ @@ -14,4 +12,9 @@ #define NEED_ARM_ARCH_ISA_THUMB #define VALUE_ARM_ARCH_ISA_THUMB 1 +/* Not in the Thumb ISA, but does exist in Arm state. A call to the library + function should result in using that instruction in Arm state. */ +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + #include "ftest-support.h" diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c index 27f71be..46cf957 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6-m" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v6m_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v6m } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c index 259d2b5..d24b08c 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6t2" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v6t2_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v6t2 } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c index e624ec5..27d2ccb 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6t2" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v6t2_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v6t2 } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c index 6e3a966..7de37ee 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6z" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v6z_arm_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v6z } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c index 23a4fcd..d3e0393 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6z" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v6z_thumb_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v6z } */ @@ -14,4 +12,9 @@ #define NEED_ARM_ARCH_ISA_THUMB #define VALUE_ARM_ARCH_ISA_THUMB 1 +/* Not in the Thumb ISA, but does exist in Arm state. A call to the library + function should result in using that instruction in Arm state. */ +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + #include "ftest-support.h" diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c index 43f52fe..ec70bc5 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-a" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v7a_ok } /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v7a } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c index 717f44c..d0ae786 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-a" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v7a_ok } /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v7a } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c index 688d766..353dbadc 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7e-m" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-require-effective-target arm_arch_v7em_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v7em } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c index 24b93ea..2809050 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-r" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v7r_ok } /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v7r } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c index a7c3772..7ee7981 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-r" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v7r_ok } /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v7r } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c index 72c4c1f..e6e6862 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7ve" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v7ve_ok } /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v7ve } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c index 772405b..5a2ffd8 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7ve" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v7ve_ok } /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v7ve } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c index feab5ee..40d2437 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv8-a" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v8a_ok } /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v8a } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c index 28d54bf..9f13069 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv8-a" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v8a_ok } /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v8a } */ diff --git a/gcc/testsuite/gcc.target/arm/lto/pr96939_0.c b/gcc/testsuite/gcc.target/arm/lto/pr96939_0.c index 21d2c1d..8dfbc06 100644 --- a/gcc/testsuite/gcc.target/arm/lto/pr96939_0.c +++ b/gcc/testsuite/gcc.target/arm/lto/pr96939_0.c @@ -1,8 +1,7 @@ /* PR target/96939 */ /* { dg-lto-do link } */ /* { dg-require-effective-target arm_arch_v8a_link } */ -/* { dg-options "-mcpu=unset -march=armv8-a+simd -mfpu=auto" } */ -/* { dg-lto-options { { -flto -O2 } } } */ +/* { dg-lto-options { { -flto -O2 -mcpu=unset -march=armv8-a+simd -mfpu=auto} } } */ extern unsigned crc (unsigned, const void *); typedef unsigned (*fnptr) (unsigned, const void *); diff --git a/gcc/testsuite/gcc.target/arm/mtp_1.c b/gcc/testsuite/gcc.target/arm/mtp_1.c index 678d27d..f78ceb8 100644 --- a/gcc/testsuite/gcc.target/arm/mtp_1.c +++ b/gcc/testsuite/gcc.target/arm/mtp_1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target tls_native } */ +/* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mtp=cp15" } */ #include "mtp.c" diff --git a/gcc/testsuite/gcc.target/arm/mtp_2.c b/gcc/testsuite/gcc.target/arm/mtp_2.c index bcb308f..1368fe4 100644 --- a/gcc/testsuite/gcc.target/arm/mtp_2.c +++ b/gcc/testsuite/gcc.target/arm/mtp_2.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target tls_native } */ +/* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mtp=tpidrprw" } */ #include "mtp.c" diff --git a/gcc/testsuite/gcc.target/arm/mtp_3.c b/gcc/testsuite/gcc.target/arm/mtp_3.c index 7d5cea3..2ef2e95 100644 --- a/gcc/testsuite/gcc.target/arm/mtp_3.c +++ b/gcc/testsuite/gcc.target/arm/mtp_3.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target tls_native } */ +/* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mtp=tpidruro" } */ #include "mtp.c" diff --git a/gcc/testsuite/gcc.target/arm/mtp_4.c b/gcc/testsuite/gcc.target/arm/mtp_4.c index 068078d..121fc83 100644 --- a/gcc/testsuite/gcc.target/arm/mtp_4.c +++ b/gcc/testsuite/gcc.target/arm/mtp_4.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target tls_native } */ +/* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mtp=tpidrurw" } */ #include "mtp.c" diff --git a/gcc/testsuite/gcc.target/arm/pr42575.c b/gcc/testsuite/gcc.target/arm/pr42575.c index 1998e32..3906c77 100644 --- a/gcc/testsuite/gcc.target/arm/pr42575.c +++ b/gcc/testsuite/gcc.target/arm/pr42575.c @@ -1,4 +1,5 @@ /* { dg-options "-O2" } */ +/* { dg-skip-if "Thumb1 lacks UMULL" { arm_thumb1 } } */ /* Make sure RA does good job allocating registers and avoids unnecessary moves. */ /* { dg-final { scan-assembler-not "mov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr65647.c b/gcc/testsuite/gcc.target/arm/pr65647.c index e0c534b..663157c 100644 --- a/gcc/testsuite/gcc.target/arm/pr65647.c +++ b/gcc/testsuite/gcc.target/arm/pr65647.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_arch_v6m_ok } */ -/* { dg-options "-O3 -w -fpermissive" } */ +/* { dg-options "-O3 -w -fpermissive -std=gnu17" } */ /* { dg-add-options arm_arch_v6m } */ a, b, c, e, g = &e, h, i = 7, l = 1, m, n, o, q = &m, r, s = &r, u, w = 9, x, diff --git a/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c b/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c index 4dc0edd..045f143 100644 --- a/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c +++ b/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c @@ -18,7 +18,7 @@ int b[N] = {0}; ** vmov r[0-9]+, s[0-9]+ @ int ** ( ** cmp r[0-9]+, #0 -** bne \.L[0-9]+ +** b(ne|eq) \.L[0-9]+ ** | ** cbn?z r[0-9]+, \.L.+ ** ) @@ -43,7 +43,7 @@ void f1 () ** vmov r[0-9]+, s[0-9]+ @ int ** ( ** cmp r[0-9]+, #0 -** bne \.L[0-9]+ +** b(ne|eq) \.L[0-9]+ ** | ** cbn?z r[0-9]+, \.L.+ ** ) @@ -68,7 +68,7 @@ void f2 () ** vmov r[0-9]+, s[0-9]+ @ int ** ( ** cmp r[0-9]+, #0 -** bne \.L[0-9]+ +** b(ne|eq) \.L[0-9]+ ** | ** cbn?z r[0-9]+, \.L.+ ** ) @@ -94,7 +94,7 @@ void f3 () ** vmov r[0-9]+, s[0-9]+ @ int ** ( ** cmp r[0-9]+, #0 -** bne \.L[0-9]+ +** b(ne|eq) \.L[0-9]+ ** | ** cbn?z r[0-9]+, \.L.+ ** ) @@ -119,7 +119,7 @@ void f4 () ** vmov r[0-9]+, s[0-9]+ @ int ** ( ** cmp r[0-9]+, #0 -** bne \.L[0-9]+ +** b(ne|eq) \.L[0-9]+ ** | ** cbn?z r[0-9]+, \.L.+ ** ) @@ -144,7 +144,7 @@ void f5 () ** vmov r[0-9]+, s[0-9]+ @ int ** ( ** cmp r[0-9]+, #0 -** bne \.L[0-9]+ +** b(ne|eq) \.L[0-9]+ ** | ** cbn?z r[0-9]+, \.L.+ ** ) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c index e932362..ff103d0 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c @@ -86,9 +86,9 @@ avx10_2_vcvtbiasph2bf8_test (void) void extern avx10_2_vcvtbiasph2bf8s_test (void) { - x256i = _mm512_cvtbiassph_bf8 (x512i, x512h); - x256i = _mm512_mask_cvtbiassph_bf8 (x256i, m32, x512i, x512h); - x256i = _mm512_maskz_cvtbiassph_bf8 (m32, x512i, x512h); + x256i = _mm512_cvts_biasph_bf8 (x512i, x512h); + x256i = _mm512_mask_cvts_biasph_bf8 (x256i, m32, x512i, x512h); + x256i = _mm512_maskz_cvts_biasph_bf8 (m32, x512i, x512h); } void extern @@ -102,9 +102,9 @@ avx10_2_vcvtbiasph2hf8_test (void) void extern avx10_2_vcvtbiasph2hf8s_test (void) { - x256i = _mm512_cvtbiassph_hf8 (x512i, x512h); - x256i = _mm512_mask_cvtbiassph_hf8 (x256i, m32, x512i, x512h); - x256i = _mm512_maskz_cvtbiassph_hf8 (m32, x512i, x512h); + x256i = _mm512_cvts_biasph_hf8 (x512i, x512h); + x256i = _mm512_mask_cvts_biasph_hf8 (x256i, m32, x512i, x512h); + x256i = _mm512_maskz_cvts_biasph_hf8 (m32, x512i, x512h); } void extern @@ -118,9 +118,9 @@ avx10_2_vcvt2ph2bf8_test (void) void extern avx10_2_vcvt2ph2bf8s_test (void) { - x512i = _mm512_cvts2ph_bf8 (x512h, x512h); - x512i = _mm512_mask_cvts2ph_bf8 (x512i, m64, x512h, x512h); - x512i = _mm512_maskz_cvts2ph_bf8 (m64, x512h, x512h); + x512i = _mm512_cvts_2ph_bf8 (x512h, x512h); + x512i = _mm512_mask_cvts_2ph_bf8 (x512i, m64, x512h, x512h); + x512i = _mm512_maskz_cvts_2ph_bf8 (m64, x512h, x512h); } void extern @@ -134,9 +134,9 @@ avx10_2_vcvt2ph2hf8_test (void) void extern avx10_2_vcvt2ph2hf8s_test (void) { - x512i = _mm512_cvts2ph_hf8 (x512h, x512h); - x512i = _mm512_mask_cvts2ph_hf8 (x512i, m64, x512h, x512h); - x512i = _mm512_maskz_cvts2ph_hf8 (m64, x512h, x512h); + x512i = _mm512_cvts_2ph_hf8 (x512h, x512h); + x512i = _mm512_mask_cvts_2ph_hf8 (x512i, m64, x512h, x512h); + x512i = _mm512_maskz_cvts_2ph_hf8 (m64, x512h, x512h); } void extern @@ -158,9 +158,9 @@ avx10_2_vcvtph2bf8_test (void) void extern avx10_2_vcvtph2bf8s_test (void) { - x256i = _mm512_cvtsph_bf8 (x512h); - x256i = _mm512_mask_cvtsph_bf8 (x256i, m32, x512h); - x256i = _mm512_maskz_cvtsph_bf8 (m32, x512h); + x256i = _mm512_cvts_ph_bf8 (x512h); + x256i = _mm512_mask_cvts_ph_bf8 (x256i, m32, x512h); + x256i = _mm512_maskz_cvts_ph_bf8 (m32, x512h); } void extern @@ -174,9 +174,9 @@ avx10_2_vcvtph2hf8_test (void) void extern avx10_2_vcvtph2hf8s_test (void) { - x256i = _mm512_cvtsph_hf8 (x512h); - x256i = _mm512_mask_cvtsph_hf8 (x256i, m32, x512h); - x256i = _mm512_maskz_cvtsph_hf8 (m32, x512h); + x256i = _mm512_cvts_ph_hf8 (x512h); + x256i = _mm512_mask_cvts_ph_hf8 (x256i, m32, x512h); + x256i = _mm512_maskz_cvts_ph_hf8 (m32, x512h); } void extern diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2bf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2bf8s-2.c index aa8545c..33d9c0c 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2bf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2bf8s-2.c @@ -64,16 +64,16 @@ TEST (void) CALC(res_ref, src1.a, src2.a); - res1.x = INTRINSIC (_cvts2ph_bf8) (src1.x, src2.x); + res1.x = INTRINSIC (_cvts_2ph_bf8) (src1.x, src2.x); if (UNION_CHECK (AVX512F_LEN, i_b) (res1, res_ref)) abort (); - res2.x = INTRINSIC (_mask_cvts2ph_bf8) (res2.x, mask, src1.x, src2.x); + res2.x = INTRINSIC (_mask_cvts_2ph_bf8) (res2.x, mask, src1.x, src2.x); MASK_MERGE (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN, i_b) (res2, res_ref)) abort (); - res3.x = INTRINSIC (_maskz_cvts2ph_bf8) (mask, src1.x, src2.x); + res3.x = INTRINSIC (_maskz_cvts_2ph_bf8) (mask, src1.x, src2.x); MASK_ZERO (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN, i_b) (res3, res_ref)) abort (); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2hf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2hf8s-2.c index afed1d1..b9fdfac 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2hf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2hf8s-2.c @@ -64,16 +64,16 @@ TEST (void) CALC(res_ref, src1.a, src2.a); - res1.x = INTRINSIC (_cvts2ph_hf8) (src1.x, src2.x); + res1.x = INTRINSIC (_cvts_2ph_hf8) (src1.x, src2.x); if (UNION_CHECK (AVX512F_LEN, i_b) (res1, res_ref)) abort (); - res2.x = INTRINSIC (_mask_cvts2ph_hf8) (res2.x, mask, src1.x, src2.x); + res2.x = INTRINSIC (_mask_cvts_2ph_hf8) (res2.x, mask, src1.x, src2.x); MASK_MERGE (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN, i_b) (res2, res_ref)) abort (); - res3.x = INTRINSIC (_maskz_cvts2ph_hf8) (mask, src1.x, src2.x); + res3.x = INTRINSIC (_maskz_cvts_2ph_hf8) (mask, src1.x, src2.x); MASK_ZERO (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN, i_b) (res3, res_ref)) abort (); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8s-2.c index 88ced07..93de7ea 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8s-2.c @@ -61,16 +61,16 @@ TEST (void) CALC (res_ref, src1.a, src2.a); - res1.x = INTRINSIC (_cvtbiassph_bf8) (src1.x, src2.x); + res1.x = INTRINSIC (_cvts_biasph_bf8) (src1.x, src2.x); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res1, res_ref)) abort (); - res2.x = INTRINSIC (_mask_cvtbiassph_bf8) (res2.x, mask, src1.x, src2.x); + res2.x = INTRINSIC (_mask_cvts_biasph_bf8) (res2.x, mask, src1.x, src2.x); MASK_MERGE (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res2, res_ref)) abort (); - res3.x = INTRINSIC (_maskz_cvtbiassph_bf8) (mask, src1.x, src2.x); + res3.x = INTRINSIC (_maskz_cvts_biasph_bf8) (mask, src1.x, src2.x); MASK_ZERO (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res3, res_ref)) abort (); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2hf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2hf8s-2.c index 1a8b4d6..0333f08 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2hf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2hf8s-2.c @@ -60,16 +60,16 @@ TEST (void) CALC (res_ref, src1.a, src2.a); - res1.x = INTRINSIC (_cvtbiassph_hf8) (src1.x, src2.x); + res1.x = INTRINSIC (_cvts_biasph_hf8) (src1.x, src2.x); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res1, res_ref)) abort (); - res2.x = INTRINSIC (_mask_cvtbiassph_hf8) (res2.x, mask, src1.x, src2.x); + res2.x = INTRINSIC (_mask_cvts_biasph_hf8) (res2.x, mask, src1.x, src2.x); MASK_MERGE (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res2, res_ref)) abort (); - res3.x = INTRINSIC (_maskz_cvtbiassph_hf8) (mask, src1.x, src2.x); + res3.x = INTRINSIC (_maskz_cvts_biasph_hf8) (mask, src1.x, src2.x); MASK_ZERO (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res3, res_ref)) abort (); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2bf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2bf8s-2.c index f4853ce..c22e1aa 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2bf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2bf8s-2.c @@ -60,16 +60,16 @@ TEST (void) CALC(res_ref, src.a); - res1.x = INTRINSIC (_cvtsph_bf8) (src.x); + res1.x = INTRINSIC (_cvts_ph_bf8) (src.x); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res1, res_ref)) abort (); - res2.x = INTRINSIC (_mask_cvtsph_bf8) (res2.x, mask, src.x); + res2.x = INTRINSIC (_mask_cvts_ph_bf8) (res2.x, mask, src.x); MASK_MERGE (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res2, res_ref)) abort (); - res3.x = INTRINSIC (_maskz_cvtsph_bf8) (mask, src.x); + res3.x = INTRINSIC (_maskz_cvts_ph_bf8) (mask, src.x); MASK_ZERO (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res3, res_ref)) abort (); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2hf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2hf8s-2.c index 43610bf..e6872e8 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2hf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2hf8s-2.c @@ -60,16 +60,16 @@ TEST (void) CALC(res_ref, src.a); - res1.x = INTRINSIC (_cvtsph_hf8) (src.x); + res1.x = INTRINSIC (_cvts_ph_hf8) (src.x); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res1, res_ref)) abort (); - res2.x = INTRINSIC (_mask_cvtsph_hf8) (res2.x, mask, src.x); + res2.x = INTRINSIC (_mask_cvts_ph_hf8) (res2.x, mask, src.x); MASK_MERGE (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res2, res_ref)) abort (); - res3.x = INTRINSIC (_maskz_cvtsph_hf8) (mask, src.x); + res3.x = INTRINSIC (_maskz_cvts_ph_hf8) (mask, src.x); MASK_ZERO (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res3, res_ref)) abort (); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c index d057c83..1db5a89 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c @@ -9,6 +9,7 @@ #endif #include "avx10-helper.h" #include <limits.h> +#include <string.h> #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" @@ -37,7 +38,7 @@ TEST (void) UNION_TYPE (AVX512F_LEN, h) s; UNION_TYPE (AVX512F_LEN, i_w) res1, res2, res3; MASK_TYPE mask = MASK_VALUE; - short res_ref[SIZE] = { 0 }; + short res_ref[SIZE] = { 0 }, res_ref2[SIZE] = { 0 }; int i, sign = 1; for (i = 0; i < SIZE; i++) @@ -54,11 +55,7 @@ TEST (void) res3.x = INTRINSIC (_maskz_ipcvtts_ph_epu8) (mask, s.x); CALC (s.a, res_ref); - -#if AVX512F_LEN == 512 - res1.x = INTRINSIC (_ipcvtts_roundph_epu8) (s.x, 8); - res2.x = INTRINSIC (_mask_ipcvtts_roundph_epu8) (res2.x, mask, s.x, 8); - res3.x = INTRINSIC (_maskz_ipcvtts_roundph_epu8) (mask, s.x, 8); + memcpy(res_ref2, res_ref, sizeof(res_ref)); if (UNION_CHECK (AVX512F_LEN, i_w) (res1, res_ref)) abort (); @@ -70,5 +67,24 @@ TEST (void) MASK_ZERO (i_w) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN, i_w) (res3, res_ref)) abort (); + +#if AVX512F_LEN == 512 + for (i = 0; i < SIZE; i++) + res2.a[i] = DEFAULT_VALUE; + + res1.x = INTRINSIC (_ipcvtts_roundph_epu8) (s.x, 8); + res2.x = INTRINSIC (_mask_ipcvtts_roundph_epu8) (res2.x, mask, s.x, 8); + res3.x = INTRINSIC (_maskz_ipcvtts_roundph_epu8) (mask, s.x, 8); + + if (UNION_CHECK (AVX512F_LEN, i_w) (res1, res_ref2)) + abort (); + + MASK_MERGE (i_w) (res_ref2, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_w) (res2, res_ref2)) + abort (); + + MASK_ZERO (i_w) (res_ref2, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_w) (res3, res_ref2)) + abort (); #endif } diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-convert-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-convert-1.c index 62791d0..3d5e921 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-convert-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-convert-1.c @@ -138,13 +138,13 @@ avx10_2_vcvtbiasph2bf8_test (void) void extern avx10_2_vcvtbiasph2bf8s_test (void) { - x128i = _mm_cvtbiassph_bf8 (x128i, x128h); - x128i = _mm_mask_cvtbiassph_bf8 (x128i, m8, x128i, x128h); - x128i = _mm_maskz_cvtbiassph_bf8 (m8, x128i, x128h); + x128i = _mm_cvts_biasph_bf8 (x128i, x128h); + x128i = _mm_mask_cvts_biasph_bf8 (x128i, m8, x128i, x128h); + x128i = _mm_maskz_cvts_biasph_bf8 (m8, x128i, x128h); - x128i = _mm256_cvtbiassph_bf8 (x256i, x256h); - x128i = _mm256_mask_cvtbiassph_bf8 (x128i, m16, x256i, x256h); - x128i = _mm256_maskz_cvtbiassph_bf8 (m16, x256i, x256h); + x128i = _mm256_cvts_biasph_bf8 (x256i, x256h); + x128i = _mm256_mask_cvts_biasph_bf8 (x128i, m16, x256i, x256h); + x128i = _mm256_maskz_cvts_biasph_bf8 (m16, x256i, x256h); } void extern @@ -162,13 +162,13 @@ avx10_2_vcvtbiasph2hf8_test (void) void extern avx10_2_vcvtbiasph2hf8s_test (void) { - x128i = _mm_cvtbiassph_hf8 (x128i, x128h); - x128i = _mm_mask_cvtbiassph_hf8 (x128i, m8, x128i, x128h); - x128i = _mm_maskz_cvtbiassph_hf8 (m8, x128i, x128h); + x128i = _mm_cvts_biasph_hf8 (x128i, x128h); + x128i = _mm_mask_cvts_biasph_hf8 (x128i, m8, x128i, x128h); + x128i = _mm_maskz_cvts_biasph_hf8 (m8, x128i, x128h); - x128i = _mm256_cvtbiassph_hf8 (x256i, x256h); - x128i = _mm256_mask_cvtbiassph_hf8 (x128i, m16, x256i, x256h); - x128i = _mm256_maskz_cvtbiassph_hf8 (m16, x256i, x256h); + x128i = _mm256_cvts_biasph_hf8 (x256i, x256h); + x128i = _mm256_mask_cvts_biasph_hf8 (x128i, m16, x256i, x256h); + x128i = _mm256_maskz_cvts_biasph_hf8 (m16, x256i, x256h); } void extern @@ -185,12 +185,12 @@ avx10_2_vcvt2ph2bf8_test (void) void extern avx10_2_vcvt2ph2bf8s_test (void) { - x128i = _mm_cvts2ph_bf8 (x128h, x128h); - x128i = _mm_mask_cvts2ph_bf8 (x128i, m16, x128h, x128h); - x128i = _mm_maskz_cvts2ph_bf8 (m16, x128h, x128h); - x256i = _mm256_cvts2ph_bf8 (x256h, x256h); - x256i = _mm256_mask_cvts2ph_bf8 (x256i, m32, x256h, x256h); - x256i = _mm256_maskz_cvts2ph_bf8 (m32, x256h, x256h); + x128i = _mm_cvts_2ph_bf8 (x128h, x128h); + x128i = _mm_mask_cvts_2ph_bf8 (x128i, m16, x128h, x128h); + x128i = _mm_maskz_cvts_2ph_bf8 (m16, x128h, x128h); + x256i = _mm256_cvts_2ph_bf8 (x256h, x256h); + x256i = _mm256_mask_cvts_2ph_bf8 (x256i, m32, x256h, x256h); + x256i = _mm256_maskz_cvts_2ph_bf8 (m32, x256h, x256h); } void extern @@ -207,12 +207,12 @@ avx10_2_vcvt2ph2hf8_test (void) void extern avx10_2_vcvt2ph2hf8s_test (void) { - x128i = _mm_cvts2ph_hf8 (x128h, x128h); - x128i = _mm_mask_cvts2ph_hf8 (x128i, m16, x128h, x128h); - x128i = _mm_maskz_cvts2ph_hf8 (m16, x128h, x128h); - x256i = _mm256_cvts2ph_hf8 (x256h, x256h); - x256i = _mm256_mask_cvts2ph_hf8 (x256i, m32, x256h, x256h); - x256i = _mm256_maskz_cvts2ph_hf8 (m32, x256h, x256h); + x128i = _mm_cvts_2ph_hf8 (x128h, x128h); + x128i = _mm_mask_cvts_2ph_hf8 (x128i, m16, x128h, x128h); + x128i = _mm_maskz_cvts_2ph_hf8 (m16, x128h, x128h); + x256i = _mm256_cvts_2ph_hf8 (x256h, x256h); + x256i = _mm256_mask_cvts_2ph_hf8 (x256i, m32, x256h, x256h); + x256i = _mm256_maskz_cvts_2ph_hf8 (m32, x256h, x256h); } void extern @@ -242,13 +242,13 @@ avx10_2_vcvtph2bf8_test (void) void extern avx10_2_vcvtph2bf8s_test (void) { - x128i = _mm_cvtsph_bf8 (x128h); - x128i = _mm_mask_cvtsph_bf8 (x128i, m8, x128h); - x128i = _mm_maskz_cvtsph_bf8 (m8, x128h); + x128i = _mm_cvts_ph_bf8 (x128h); + x128i = _mm_mask_cvts_ph_bf8 (x128i, m8, x128h); + x128i = _mm_maskz_cvts_ph_bf8 (m8, x128h); - x128i = _mm256_cvtsph_bf8 (x256h); - x128i = _mm256_mask_cvtsph_bf8 (x128i, m16, x256h); - x128i = _mm256_maskz_cvtsph_bf8 (m16, x256h); + x128i = _mm256_cvts_ph_bf8 (x256h); + x128i = _mm256_mask_cvts_ph_bf8 (x128i, m16, x256h); + x128i = _mm256_maskz_cvts_ph_bf8 (m16, x256h); } void extern @@ -266,13 +266,13 @@ avx10_2_vcvtph2hf8_test (void) void extern avx10_2_vcvtph2hf8s_test (void) { - x128i = _mm_cvtsph_hf8 (x128h); - x128i = _mm_mask_cvtsph_hf8 (x128i, m8, x128h); - x128i = _mm_maskz_cvtsph_hf8 (m8, x128h); + x128i = _mm_cvts_ph_hf8 (x128h); + x128i = _mm_mask_cvts_ph_hf8 (x128i, m8, x128h); + x128i = _mm_maskz_cvts_ph_hf8 (m8, x128h); - x128i = _mm256_cvtsph_hf8 (x256h); - x128i = _mm256_mask_cvtsph_hf8 (x128i, m16, x256h); - x128i = _mm256_maskz_cvtsph_hf8 (m16, x256h); + x128i = _mm256_cvts_ph_hf8 (x256h); + x128i = _mm256_mask_cvts_ph_hf8 (x128i, m16, x256h); + x128i = _mm256_maskz_cvts_ph_hf8 (m16, x256h); } void extern diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c index f255ceb..493dab0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c @@ -18,6 +18,6 @@ int pixel_sad_n(unsigned char *pix1, unsigned char *pix2, int n) return sum; } -/* { dg-final { scan-assembler {vminu\.v} } } */ -/* { dg-final { scan-assembler {vmaxu\.v} } } */ -/* { dg-final { scan-assembler {vsub\.v} } } */ +/* { dg-final { scan-assembler {vrsub\.v} } } */ +/* { dg-final { scan-assembler {vmax\.v} } } */ +/* { dg-final { scan-assembler {vwsubu\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr119224.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr119224.c new file mode 100644 index 0000000..fa3386c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr119224.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -ffast-math -march=rv64gcv_zvl256b -mabi=lp64d -mtune=generic-ooo -mrvv-vector-bits=zvl" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O2" "-Og" "-Os" "-Oz" } } */ + +/* A core routine of x264 which should not spill for OoO VLS build. */ + +inline int abs(int i) +{ + return (i < 0 ? -i : i); +} + +int x264_sad_16x16(unsigned char *p1, int st1, unsigned char *p2, int st2) +{ + int sum = 0; + + for(int y = 0; y < 16; y++) + { + for(int x = 0; x < 16; x++) + sum += abs (p1[x] - p2[x]); + p1 += st1; p2 += st2; + } + + return sum; +} + +/* { dg-final { scan-assembler-not {addi\t[a-x0-9]+,sp} } } */ +/* { dg-final { scan-assembler-not {addi\tsp,sp} } } */ diff --git a/gcc/testsuite/gfortran.dg/gomp/append-args-interop.f90 b/gcc/testsuite/gfortran.dg/gomp/append-args-interop.f90 new file mode 100644 index 0000000..11a0f01 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/gomp/append-args-interop.f90 @@ -0,0 +1,27 @@ +! { dg-do compile } +! { dg-additional-options "-fdump-tree-gimple" } + +! Test that interop objects are implicitly created/destroyed when a dispatch +! construct doesn't provide enough of them to satisfy the declare variant +! append_args clause. + +module m + use omp_lib, only: omp_interop_kind +contains +subroutine g(x,y,z) + integer(omp_interop_kind) :: x, y, z + value :: y +end +subroutine f() + !$omp declare variant(f: g) append_args(interop(target), interop(prefer_type("cuda","hip"), targetsync), interop(target,targetsync,prefer_type({attr("ompx_foo")}))) match(construct={dispatch}) +end +end + +use m +!$omp dispatch device(99) + call f() +end + +! { dg-final { scan-tree-dump "__builtin_GOMP_interop \\(99, 3, interopobjs\.\[0-9\]+, tgt_tgtsync\.\[0-9\]+, pref_type\.\[0-9\]+, " "gimple" } } +! { dg-final { scan-tree-dump "__builtin_GOMP_interop \\(99, 0, 0B, 0B, 0B, 0, 0B, 3, interopobjs\.\[0-9\]+," "gimple" } } +! { dg-final { scan-tree-dump "g \\(&interop\.\[0-9\]+, interop\.\[0-9\]+, &interop\.\[0-9\]+\\)" "gimple" } } diff --git a/gcc/testsuite/gfortran.dg/gomp/declare-variant-mod-2.f90 b/gcc/testsuite/gfortran.dg/gomp/declare-variant-mod-2.f90 index f75b49c..ab44050 100644 --- a/gcc/testsuite/gfortran.dg/gomp/declare-variant-mod-2.f90 +++ b/gcc/testsuite/gfortran.dg/gomp/declare-variant-mod-2.f90 @@ -9,12 +9,6 @@ ! { dg-error "'x' at .1. is specified more than once" "" { target *-*-* } 17 } -! { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'm2_f1', except when specifying all 1 objects in the 'interop' clause of the 'dispatch' directive" "" { target *-*-* } 27 } -! { dg-note "required by 'dispatch' construct" "" { target *-*-* } 33 } -! { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'm2_f2', except when specifying all 2 objects in the 'interop' clause of the 'dispatch' directive" "" { target *-*-* } 27 } -! { dg-note "required by 'dispatch' construct" "" { target *-*-* } 37 } -! { dg-message "sorry, unimplemented: 'append_args' clause not yet supported for 'm2_f3', except when specifying all 3 objects in the 'interop' clause of the 'dispatch' directive" "" { target *-*-* } 27 } -! { dg-note "required by 'dispatch' construct" "" { target *-*-* } 43 } ! Check that module-file handling works for declare_variant ! and its match/adjust_args/append_args clauses diff --git a/gcc/testsuite/gfortran.dg/gomp/interop-5.f90 b/gcc/testsuite/gfortran.dg/gomp/interop-5.f90 index a6a2d71..a08eeb8 100644 --- a/gcc/testsuite/gfortran.dg/gomp/interop-5.f90 +++ b/gcc/testsuite/gfortran.dg/gomp/interop-5.f90 @@ -1,7 +1,13 @@ ! { dg-additional-options "-fdump-tree-omplower" } subroutine sub1 (a1, a2, a3, a4) - use omp_lib, only: omp_interop_kind + use iso_c_binding + implicit none + + ! The following definitions are in omp_lib, which cannot be included + ! in gcc/testsuite/ + integer, parameter :: omp_interop_kind = c_intptr_t + integer(omp_interop_kind) :: a1 ! by ref integer(omp_interop_kind), optional :: a2 ! as pointer integer(omp_interop_kind), allocatable :: a3 ! ref to pointer @@ -9,13 +15,13 @@ subroutine sub1 (a1, a2, a3, a4) integer(omp_interop_kind) :: b !$omp interop init(target : a1, a2, a3, a4, b) - ! { dg-final { scan-tree-dump-times "void \\* interopobjs\.\[0-9\]+\\\[5\\\];\[\r\n ]*integer\\(kind=4\\) tgt_tgtsync\.\[0-9\]+\\\[5\\\];\[\r\n ]*integer\\(kind=8\\) \\* & a3\.\[0-9\]+;\[\r\n ]*integer\\(kind=8\\) \\* D\.\[0-9\]+;\[\r\n ]*integer\\(kind=8\\) \\* a2\.\[0-9\]+;\[\r\n ]*integer\\(kind=8\\) & a1\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[0\\\] = &b;\[\r\n ]*tgt_tgtsync\.\[0-9\]+\\\[0\\\] = 1;\[\r\n ]*interopobjs\.\[0-9\]+\\\[1\\\] = &a4;\[\r\n ]*tgt_tgtsync\.\[0-9\]+\\\[1\\\] = 1;\[\r\n ]*a3\.\[0-9\]+ = a3;\[\r\n ]*D\.\[0-9\]+ = \\*a3\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[2\\\] = D\.\[0-9\]+;\[\r\n ]*tgt_tgtsync\.\[0-9\]+\\\[2\\\] = 1;\[\r\n ]*a2\.\[0-9\]+ = a2;\[\r\n ]*interopobjs\.\[0-9\]+\\\[3\\\] = a2\.\[0-9\]+;\[\r\n ]*tgt_tgtsync\.\[0-9\]+\\\[3\\\] = 1;\[\r\n ]*a1\.\[0-9\]+ = a1;\[\r\n ]*interopobjs\.\[0-9\]+\\\[4\\\] = a1\.\[0-9\]+;\[\r\n ]*tgt_tgtsync\.\[0-9\]+\\\[4\\\] = 1;\[\r\n ]*__builtin_GOMP_interop \\(-5, 5, &interopobjs\.\[0-9\]+, &tgt_tgtsync\.\[0-9\]+, 0B, 0, 0B, 0, 0B, 0, 0B\\);" 1 "omplower" } } + ! { dg-final { scan-tree-dump-times "void \\* interopobjs\.\[0-9\]+\\\[5\\\];\[\r\n ]*integer\\(kind=4\\) tgt_tgtsync\.\[0-9\]+\\\[5\\\];\[\r\n ]*integer\\(kind=\[48\]\\) \\* & a3\.\[0-9\]+;\[\r\n ]*integer\\(kind=\[48\]\\) \\* D\.\[0-9\]+;\[\r\n ]*integer\\(kind=\[48\]\\) \\* a2\.\[0-9\]+;\[\r\n ]*integer\\(kind=\[48\]\\) & a1\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[0\\\] = &b;\[\r\n ]*tgt_tgtsync\.\[0-9\]+\\\[0\\\] = 1;\[\r\n ]*interopobjs\.\[0-9\]+\\\[1\\\] = &a4;\[\r\n ]*tgt_tgtsync\.\[0-9\]+\\\[1\\\] = 1;\[\r\n ]*a3\.\[0-9\]+ = a3;\[\r\n ]*D\.\[0-9\]+ = \\*a3\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[2\\\] = D\.\[0-9\]+;\[\r\n ]*tgt_tgtsync\.\[0-9\]+\\\[2\\\] = 1;\[\r\n ]*a2\.\[0-9\]+ = a2;\[\r\n ]*interopobjs\.\[0-9\]+\\\[3\\\] = a2\.\[0-9\]+;\[\r\n ]*tgt_tgtsync\.\[0-9\]+\\\[3\\\] = 1;\[\r\n ]*a1\.\[0-9\]+ = a1;\[\r\n ]*interopobjs\.\[0-9\]+\\\[4\\\] = a1\.\[0-9\]+;\[\r\n ]*tgt_tgtsync\.\[0-9\]+\\\[4\\\] = 1;\[\r\n ]*__builtin_GOMP_interop \\(-5, 5, &interopobjs\.\[0-9\]+, &tgt_tgtsync\.\[0-9\]+, 0B, 0, 0B, 0, 0B, 0, 0B\\);" 1 "omplower" } } !$omp interop use(a1, a2, a3, a4, b) - ! { dg-final { scan-tree-dump-times "void \\* interopobjs\.\[0-9\]+\\\[5\\\];\[\r\n ]*integer\\(kind=8\\) b\.\[0-9\]+;\[\r\n ]*void \\* b\.\[0-9\]+;\[\r\n ]*integer\\(kind=8\\) a4\.\[0-9\]+;\[\r\n ]*void \\* a4\.\[0-9\]+;\[\r\n ]*integer\\(kind=8\\) \\* & a3\.\[0-9\]+;\[\r\n ]*integer\\(kind=8\\) \\* D\.\[0-9\]+;\[\r\n ]*integer\\(kind=8\\) D\.\[0-9\]+;\[\r\n ]*void \\* D\.\[0-9\]+;\[\r\n ]*integer\\(kind=8\\) \\* a2\.\[0-9\]+;\[\r\n ]*integer\\(kind=8\\) D\.\[0-9\]+;\[\r\n ]*void \\* D\.\[0-9\]+;\[\r\n ]*integer\\(kind=8\\) & a1\.\[0-9\]+;\[\r\n ]*integer\\(kind=8\\) D\.\[0-9\]+;\[\r\n ]*void \\* D\.\[0-9\]+;\[\r\n ]*b\.\[0-9\]+ = b;\[\r\n ]*b\.\[0-9\]+ = \\(void \\*\\) b\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[0\\\] = b\.\[0-9\]+;\[\r\n ]*a4\.\[0-9\]+ = a4;\[\r\n ]*a4\.\[0-9\]+ = \\(void \\*\\) a4\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[1\\\] = a4\.\[0-9\]+;\[\r\n ]*a3\.\[0-9\]+ = a3;\[\r\n ]*D\.\[0-9\]+ = \\*a3\.\[0-9\]+;\[\r\n ]*D\.\[0-9\]+ = \\*D\.\[0-9\]+;\[\r\n ]*D\.\[0-9\]+ = \\(void \\*\\) D\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[2\\\] = D\.\[0-9\]+;\[\r\n ]*a2\.\[0-9\]+ = a2;\[\r\n ]*D\.\[0-9\]+ = \\*a2\.\[0-9\]+;\[\r\n ]*D\.\[0-9\]+ = \\(void \\*\\) D\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[3\\\] = D\.\[0-9\]+;\[\r\n ]*a1\.\[0-9\]+ = a1;\[\r\n ]*D\.\[0-9\]+ = \\*a1\.\[0-9\]+;\[\r\n ]*D\.\[0-9\]+ = \\(void \\*\\) D\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[4\\\] = D\.\[0-9\]+;\[\r\n ]*__builtin_GOMP_interop \\(-5, 0, 0B, 0B, 0B, 5, &interopobjs\.\[0-9\]+, 0, 0B, 0, 0B\\);" 1 "omplower" } } + ! { dg-final { scan-tree-dump-times "void \\* interopobjs\.\[0-9\]+\\\[5\\\];\[\r\n ]*integer\\(kind=\[48\]\\) b\.\[0-9\]+;\[\r\n ]*void \\* b\.\[0-9\]+;\[\r\n ]*integer\\(kind=\[48\]\\) a4\.\[0-9\]+;\[\r\n ]*void \\* a4\.\[0-9\]+;\[\r\n ]*integer\\(kind=\[48\]\\) \\* & a3\.\[0-9\]+;\[\r\n ]*integer\\(kind=\[48\]\\) \\* D\.\[0-9\]+;\[\r\n ]*integer\\(kind=\[48\]\\) D\.\[0-9\]+;\[\r\n ]*void \\* D\.\[0-9\]+;\[\r\n ]*integer\\(kind=\[48\]\\) \\* a2\.\[0-9\]+;\[\r\n ]*integer\\(kind=\[48\]\\) D\.\[0-9\]+;\[\r\n ]*void \\* D\.\[0-9\]+;\[\r\n ]*integer\\(kind=\[48\]\\) & a1\.\[0-9\]+;\[\r\n ]*integer\\(kind=\[48\]\\) D\.\[0-9\]+;\[\r\n ]*void \\* D\.\[0-9\]+;\[\r\n ]*b\.\[0-9\]+ = b;\[\r\n ]*b\.\[0-9\]+ = \\(void \\*\\) b\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[0\\\] = b\.\[0-9\]+;\[\r\n ]*a4\.\[0-9\]+ = a4;\[\r\n ]*a4\.\[0-9\]+ = \\(void \\*\\) a4\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[1\\\] = a4\.\[0-9\]+;\[\r\n ]*a3\.\[0-9\]+ = a3;\[\r\n ]*D\.\[0-9\]+ = \\*a3\.\[0-9\]+;\[\r\n ]*D\.\[0-9\]+ = \\*D\.\[0-9\]+;\[\r\n ]*D\.\[0-9\]+ = \\(void \\*\\) D\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[2\\\] = D\.\[0-9\]+;\[\r\n ]*a2\.\[0-9\]+ = a2;\[\r\n ]*D\.\[0-9\]+ = \\*a2\.\[0-9\]+;\[\r\n ]*D\.\[0-9\]+ = \\(void \\*\\) D\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[3\\\] = D\.\[0-9\]+;\[\r\n ]*a1\.\[0-9\]+ = a1;\[\r\n ]*D\.\[0-9\]+ = \\*a1\.\[0-9\]+;\[\r\n ]*D\.\[0-9\]+ = \\(void \\*\\) D\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[4\\\] = D\.\[0-9\]+;\[\r\n ]*__builtin_GOMP_interop \\(-5, 0, 0B, 0B, 0B, 5, &interopobjs\.\[0-9\]+, 0, 0B, 0, 0B\\);" 1 "omplower" } } !$omp interop destroy(a1, a2, a3, a4, b) - ! { dg-final { scan-tree-dump-times "void \\* interopobjs\.\[0-9\]+\\\[5\\\];\[\r\n ]*integer\\(kind=8\\) \\* & a3\.\[0-9\]+;\[\r\n ]*integer\\(kind=8\\) \\* D\.\[0-9\]+;\[\r\n ]*integer\\(kind=8\\) \\* a2\.\[0-9\]+;\[\r\n ]*integer\\(kind=8\\) & a1\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[0\\\] = &b;\[\r\n ]*interopobjs\.\[0-9\]+\\\[1\\\] = &a4;\[\r\n ]*a3\.\[0-9\]+ = a3;\[\r\n ]*D\.\[0-9\]+ = \\*a3\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[2\\\] = D\.\[0-9\]+;\[\r\n ]*a2\.\[0-9\]+ = a2;\[\r\n ]*interopobjs\.\[0-9\]+\\\[3\\\] = a2\.\[0-9\]+;\[\r\n ]*a1\.\[0-9\]+ = a1;\[\r\n ]*interopobjs\.\[0-9\]+\\\[4\\\] = a1\.\[0-9\]+;\[\r\n ]*__builtin_GOMP_interop \\(-5, 0, 0B, 0B, 0B, 0, 0B, 5, &interopobjs\.\[0-9\]+, 0, 0B\\);" 1 "omplower" } } + ! { dg-final { scan-tree-dump-times "void \\* interopobjs\.\[0-9\]+\\\[5\\\];\[\r\n ]*integer\\(kind=\[48\]\\) \\* & a3\.\[0-9\]+;\[\r\n ]*integer\\(kind=\[48\]\\) \\* D\.\[0-9\]+;\[\r\n ]*integer\\(kind=\[48\]\\) \\* a2\.\[0-9\]+;\[\r\n ]*integer\\(kind=\[48\]\\) & a1\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[0\\\] = &b;\[\r\n ]*interopobjs\.\[0-9\]+\\\[1\\\] = &a4;\[\r\n ]*a3\.\[0-9\]+ = a3;\[\r\n ]*D\.\[0-9\]+ = \\*a3\.\[0-9\]+;\[\r\n ]*interopobjs\.\[0-9\]+\\\[2\\\] = D\.\[0-9\]+;\[\r\n ]*a2\.\[0-9\]+ = a2;\[\r\n ]*interopobjs\.\[0-9\]+\\\[3\\\] = a2\.\[0-9\]+;\[\r\n ]*a1\.\[0-9\]+ = a1;\[\r\n ]*interopobjs\.\[0-9\]+\\\[4\\\] = a1\.\[0-9\]+;\[\r\n ]*__builtin_GOMP_interop \\(-5, 0, 0B, 0B, 0B, 0, 0B, 5, &interopobjs\.\[0-9\]+, 0, 0B\\);" 1 "omplower" } } end subroutine diff --git a/gcc/testsuite/gm2/pim/pass/minmaxreal.mod b/gcc/testsuite/gm2/pim/pass/minmaxreal.mod new file mode 100644 index 0000000..2871f46 --- /dev/null +++ b/gcc/testsuite/gm2/pim/pass/minmaxreal.mod @@ -0,0 +1,7 @@ +MODULE minmaxreal ; + +CONST + min = MIN (REAL) ; + max = MAX (REAL) ; + +END minmaxreal. diff --git a/gcc/testsuite/gm2/pim/pass/minmaxreal2.mod b/gcc/testsuite/gm2/pim/pass/minmaxreal2.mod new file mode 100644 index 0000000..120c1b7 --- /dev/null +++ b/gcc/testsuite/gm2/pim/pass/minmaxreal2.mod @@ -0,0 +1,8 @@ +MODULE minmaxreal2 ; + +VAR + min, max: REAL ; +BEGIN + min := MIN (REAL) ; + max := MAX (REAL) +END minmaxreal2. diff --git a/gcc/testsuite/gm2/pim/pass/minmaxreal3.mod b/gcc/testsuite/gm2/pim/pass/minmaxreal3.mod new file mode 100644 index 0000000..30b5d1b --- /dev/null +++ b/gcc/testsuite/gm2/pim/pass/minmaxreal3.mod @@ -0,0 +1,10 @@ +MODULE minmaxreal3 ; + +FROM SYSTEM IMPORT REAL64 ; + +VAR + min, max: REAL64 ; +BEGIN + min := MIN (REAL64) ; + max := MAX (REAL64) +END minmaxreal3. diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index e875e35..e90c090 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -13504,7 +13504,7 @@ proc check_effective_target_arm_v8_1_lob_ok { } { asm goto ("le lr, %l0" : : : "lr" : loop); return i != 10; } - } "-mcpu=unset -mcpu=unset -march=armv8.1-m.main -mthumb" ] + } "-mcpu=unset -march=armv8.1-m.main -mthumb" ] } } |