diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
196 files changed, 4331 insertions, 325 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_1.c b/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_1.c new file mode 100644 index 0000000..e49ace1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_1.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.2-a+fp16" } */ + +/* +** test_fcmp_store: +** fcmp h0, h1 +** cset w0, eq +** ret +*/ +int +test_fcmp_store(_Float16 a, _Float16 b) +{ + return a == b; +} + +/* +** test_fcmpe_store: +** fcmpe h0, h1 +** cset w0, mi +** ret +*/ +int +test_fcmpe_store(_Float16 a, _Float16 b) +{ + return a < b; +} + +/* +** test_fcmp_branch: +** fcmp h0, h1 +** ... +*/ +_Float16 +test_fcmp_branch(_Float16 a, _Float16 b) +{ + if (a == b) + return a * b; + return a; +} + +/* +** test_fcmpe_branch: +** fcmpe h0, h1 +** ... +*/ +_Float16 +test_fcmpe_branch(_Float16 a, _Float16 b) +{ + if (a < b) + return a * b; + return a; +} + +/* { dg-final { check-function-bodies "**" "" "" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_2.c b/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_2.c new file mode 100644 index 0000000..0ff7cda --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.2-a+nofp16" } */ + +#include "_Float16_cmp_1.c" + +/* { dg-final { scan-assembler-not {\tfcmp\th[0-9]+} } } */ +/* { dg-final { scan-assembler-not {\tfcmpe\th[0-9]+} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr-ungated.c b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-ungated.c new file mode 100644 index 0000000..d67a426 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-ungated.c @@ -0,0 +1,13 @@ +/* Test that __arm_[r,w]sr intrinsics aren't gated (by default). */ + +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a" } */ + +#include <arm_acle.h> + +uint64_t +foo (uint64_t a) +{ + __arm_wsr64 ("zcr_el1", a); + return __arm_rsr64 ("smcr_el1"); +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c index 0892ce7..a653296 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c @@ -1,7 +1,3 @@ -/* We haven't implemented these intrinsics for arm yet. */ -/* { dg-skip-if "unimplemented" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <arm_neon.h> #include "arm-neon-ref.h" @@ -39,7 +35,6 @@ VARIANT (int32, 2, _s32) \ VARIANT (int64, 1, _s64) \ VARIANT (poly8, 8, _p8) \ VARIANT (poly16, 4, _p16) \ -VARIANT (float16, 4, _f16) \ VARIANT (float32, 2, _f32) \ VARIANT (uint8, 16, q_u8) \ VARIANT (uint16, 8, q_u16) \ @@ -51,17 +46,30 @@ VARIANT (int32, 4, q_s32) \ VARIANT (int64, 2, q_s64) \ VARIANT (poly8, 16, q_p8) \ VARIANT (poly16, 8, q_p16) \ -VARIANT (float16, 8, q_f16) \ VARIANT (float32, 4, q_f32) +#if defined (__ARM_FP16_FORMAT_IEEE) \ + || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \ + || defined (__aarch64__) +#define VARIANTS_F16(VARIANT) \ + VARIANT (float16, 4, _f16) \ + VARIANT (float16, 8, q_f16) +#else +#define VARIANTS_F16(VARIANTS_F16) +#endif + #ifdef __aarch64__ #define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) \ +VARIANT (poly64, 1, _p64) \ +VARIANT (poly64, 2, q_p64) \ VARIANT (mfloat8, 8, _mf8) \ VARIANT (mfloat8, 16, q_mf8) \ VARIANT (float64, 1, _f64) \ VARIANT (float64, 2, q_f64) #else -#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) +#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) #endif /* Tests of vld1_x2 and vld1q_x2. */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c index 9465e4a..832ee75 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c @@ -1,7 +1,3 @@ -/* We haven't implemented these intrinsics for arm yet. */ -/* { dg-skip-if "unimplemented" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <arm_neon.h> #include "arm-neon-ref.h" @@ -40,7 +36,6 @@ VARIANT (int32, 2, _s32) \ VARIANT (int64, 1, _s64) \ VARIANT (poly8, 8, _p8) \ VARIANT (poly16, 4, _p16) \ -VARIANT (float16, 4, _f16) \ VARIANT (float32, 2, _f32) \ VARIANT (uint8, 16, q_u8) \ VARIANT (uint16, 8, q_u16) \ @@ -52,17 +47,30 @@ VARIANT (int32, 4, q_s32) \ VARIANT (int64, 2, q_s64) \ VARIANT (poly8, 16, q_p8) \ VARIANT (poly16, 8, q_p16) \ -VARIANT (float16, 8, q_f16) \ VARIANT (float32, 4, q_f32) +#if defined (__ARM_FP16_FORMAT_IEEE) \ + || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \ + || defined (__aarch64__) +#define VARIANTS_F16(VARIANT) \ + VARIANT (float16, 4, _f16) \ + VARIANT (float16, 8, q_f16) +#else +#define VARIANTS_F16(VARIANTS_F16) +#endif + #ifdef __aarch64__ #define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) \ +VARIANT (poly64, 1, _p64) \ +VARIANT (poly64, 2, q_p64) \ VARIANT (mfloat8, 8, _mf8) \ VARIANT (mfloat8, 16, q_mf8) \ VARIANT (float64, 1, _f64) \ VARIANT (float64, 2, q_f64) #else -#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) +#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) #endif diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c index a1461fd..e5f55f0 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c @@ -1,7 +1,3 @@ -/* We haven't implemented these intrinsics for arm yet. */ -/* { dg-skip-if "unimplemented" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <stdbool.h> #include <arm_neon.h> #include "arm-neon-ref.h" @@ -42,8 +38,6 @@ VARIANT (int32, 2, _s32) \ VARIANT (int64, 1, _s64) \ VARIANT (poly8, 8, _p8) \ VARIANT (poly16, 4, _p16) \ -VARIANT (poly64, 1, _p64) \ -VARIANT (float16, 4, _f16) \ VARIANT (float32, 2, _f32) \ VARIANT (uint8, 16, q_u8) \ VARIANT (uint16, 8, q_u16) \ @@ -55,18 +49,30 @@ VARIANT (int32, 4, q_s32) \ VARIANT (int64, 2, q_s64) \ VARIANT (poly8, 16, q_p8) \ VARIANT (poly16, 8, q_p16) \ -VARIANT (poly64, 2, q_p64) \ -VARIANT (float16, 8, q_f16) \ VARIANT (float32, 4, q_f32) +#if defined (__ARM_FP16_FORMAT_IEEE) \ + || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \ + || defined (__aarch64__) +#define VARIANTS_F16(VARIANT) \ + VARIANT (float16, 4, _f16) \ + VARIANT (float16, 8, q_f16) +#else +#define VARIANTS_F16(VARIANTS_F16) +#endif + #ifdef __aarch64__ #define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) \ +VARIANT (poly64, 1, _p64) \ +VARIANT (poly64, 2, q_p64) \ VARIANT (mfloat8, 8, _mf8) \ VARIANT (mfloat8, 16, q_mf8) \ VARIANT (float64, 1, _f64) \ VARIANT (float64, 2, q_f64) #else -#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) +#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) #endif /* Tests of vld1_x4 and vld1q_x4. */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c index 3cf5eb3..8399290 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c @@ -1,7 +1,3 @@ -/* We haven't implemented these intrinsics for arm yet. */ -/* { dg-skip-if "unimplemented" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <arm_neon.h> #include "arm-neon-ref.h" @@ -39,7 +35,6 @@ VARIANT (int32, 2, _s32) \ VARIANT (int64, 1, _s64) \ VARIANT (poly8, 8, _p8) \ VARIANT (poly16, 4, _p16) \ -VARIANT (float16, 4, _f16) \ VARIANT (float32, 2, _f32) \ VARIANT (uint8, 16, q_u8) \ VARIANT (uint16, 8, q_u16) \ @@ -51,17 +46,30 @@ VARIANT (int32, 4, q_s32) \ VARIANT (int64, 2, q_s64) \ VARIANT (poly8, 16, q_p8) \ VARIANT (poly16, 8, q_p16) \ -VARIANT (float16, 8, q_f16) \ VARIANT (float32, 4, q_f32) +#if defined (__ARM_FP16_FORMAT_IEEE) \ + || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \ + || defined (__aarch64__) +#define VARIANTS_F16(VARIANT) \ + VARIANT (float16, 4, _f16) \ + VARIANT (float16, 8, q_f16) +#else +#define VARIANTS_F16(VARIANTS_F16) +#endif + #ifdef __aarch64__ #define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) \ +VARIANT (poly64, 1, _p64) \ +VARIANT (poly64, 2, q_p64) \ VARIANT (mfloat8, 8, _mf8) \ VARIANT (mfloat8, 16, q_mf8) \ VARIANT (float64, 1, _f64) \ VARIANT (float64, 2, q_f64) #else -#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) +#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) #endif /* Tests of vst1_x2 and vst1q_x2. */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c index c05f8e7..e7d9e02 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c @@ -1,7 +1,3 @@ -/* We haven't implemented these intrinsics for arm yet. */ -/* { dg-skip-if "unimplemented" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <arm_neon.h> #include "arm-neon-ref.h" @@ -40,7 +36,6 @@ VARIANT (int32, 2, _s32) \ VARIANT (int64, 1, _s64) \ VARIANT (poly8, 8, _p8) \ VARIANT (poly16, 4, _p16) \ -VARIANT (float16, 4, _f16) \ VARIANT (float32, 2, _f32) \ VARIANT (uint8, 16, q_u8) \ VARIANT (uint16, 8, q_u16) \ @@ -52,17 +47,30 @@ VARIANT (int32, 4, q_s32) \ VARIANT (int64, 2, q_s64) \ VARIANT (poly8, 16, q_p8) \ VARIANT (poly16, 8, q_p16) \ -VARIANT (float16, 8, q_f16) \ VARIANT (float32, 4, q_f32) +#if defined (__ARM_FP16_FORMAT_IEEE) \ + || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \ + || defined (__aarch64__) +#define VARIANTS_F16(VARIANT) \ + VARIANT (float16, 4, _f16) \ + VARIANT (float16, 8, q_f16) +#else +#define VARIANTS_F16(VARIANTS_F16) +#endif + #ifdef __aarch64__ #define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) \ +VARIANT (poly64, 1, _p64) \ +VARIANT (poly64, 2, q_p64) \ VARIANT (mfloat8, 8, _mf8) \ VARIANT (mfloat8, 16, q_mf8) \ VARIANT (float64, 1, _f64) \ VARIANT (float64, 2, q_f64) #else -#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) +#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) #endif /* Tests of vst1_x3 and vst1q_x3. */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c index a9867c3..83b0567 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c @@ -1,7 +1,3 @@ -/* We haven't implemented these intrinsics for arm yet. */ -/* { dg-skip-if "unimplemented" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <arm_neon.h> #include "arm-neon-ref.h" @@ -41,8 +37,6 @@ VARIANT (int32, 2, _s32) \ VARIANT (int64, 1, _s64) \ VARIANT (poly8, 8, _p8) \ VARIANT (poly16, 4, _p16) \ -VARIANT (poly64, 1, _p64) \ -VARIANT (float16, 4, _f16) \ VARIANT (float32, 2, _f32) \ VARIANT (uint8, 16, q_u8) \ VARIANT (uint16, 8, q_u16) \ @@ -54,18 +48,30 @@ VARIANT (int32, 4, q_s32) \ VARIANT (int64, 2, q_s64) \ VARIANT (poly8, 16, q_p8) \ VARIANT (poly16, 8, q_p16) \ -VARIANT (poly64, 2, q_p64) \ -VARIANT (float16, 8, q_f16) \ VARIANT (float32, 4, q_f32) +#if defined (__ARM_FP16_FORMAT_IEEE) \ + || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \ + || defined (__aarch64__) +#define VARIANTS_F16(VARIANT) \ + VARIANT (float16, 4, _f16) \ + VARIANT (float16, 8, q_f16) +#else +#define VARIANTS_F16(VARIANTS_F16) +#endif + #ifdef __aarch64__ #define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) \ +VARIANT (poly64, 1, _p64) \ +VARIANT (poly64, 2, q_p64) \ VARIANT (mfloat8, 8, _mf8) \ VARIANT (mfloat8, 16, q_mf8) \ VARIANT (float64, 1, _f64) \ VARIANT (float64, 2, q_f64) #else -#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) +#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) #endif /* Tests of vst1_x4 and vst1q_x4. */ diff --git a/gcc/testsuite/gcc.target/aarch64/bic-1.c b/gcc/testsuite/gcc.target/aarch64/bic-1.c new file mode 100644 index 0000000..65e1514 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/bic-1.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* PR rtl-optmization/111949 */ + +/* +**func1: +** bic w([0-9]+), w0, w1 +** and w0, w\1, 1 +** ret +*/ + +unsigned func1(unsigned a, bool b) +{ + int c = a & b; + return (c ^ a)&1; +} + +/* +**func2: +** bic w([0-9]+), w1, w0 +** and w0, w\1, 255 +** ret +*/ +unsigned func2(bool a, bool b) +{ + return ~a & b; +} + +/* +**func3: +** bic w([0-9]+), w1, w0 +** and w0, w\1, 1 +** ret +*/ +bool func3(bool a, unsigned char b) +{ + return !a & b; +} diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt-le-1.c b/gcc/testsuite/gcc.target/aarch64/popcnt-le-1.c index b4141da..843fdac 100644 --- a/gcc/testsuite/gcc.target/aarch64/popcnt-le-1.c +++ b/gcc/testsuite/gcc.target/aarch64/popcnt-le-1.c @@ -8,7 +8,7 @@ /* ** le32: ** sub w([0-9]+), w0, #1 -** tst w0, w\1 +** tst (?:w0, w\1|w\1, w0) ** cset w0, eq ** ret */ @@ -20,7 +20,7 @@ unsigned le32 (const unsigned int a) { /* ** gt32: ** sub w([0-9]+), w0, #1 -** tst w0, w\1 +** tst (?:w0, w\1|w\1, w0) ** cset w0, ne ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt-le-3.c b/gcc/testsuite/gcc.target/aarch64/popcnt-le-3.c index b811e6f..3b558e9 100644 --- a/gcc/testsuite/gcc.target/aarch64/popcnt-le-3.c +++ b/gcc/testsuite/gcc.target/aarch64/popcnt-le-3.c @@ -8,7 +8,7 @@ /* ** le16: ** sub w([0-9]+), w0, #1 -** and w([0-9]+), w0, w\1 +** and w([0-9]+), (?:w0, w\1|w\1, w0) ** tst w\2, 65535 ** cset w0, eq ** ret @@ -21,7 +21,7 @@ unsigned le16 (const unsigned short a) { /* ** gt16: ** sub w([0-9]+), w0, #1 -** and w([0-9]+), w0, w\1 +** and w([0-9]+), (?:w0, w\1|w\1, w0) ** tst w\2, 65535 ** cset w0, ne ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/pr100056.c b/gcc/testsuite/gcc.target/aarch64/pr100056.c index 0b77824..70499772 100644 --- a/gcc/testsuite/gcc.target/aarch64/pr100056.c +++ b/gcc/testsuite/gcc.target/aarch64/pr100056.c @@ -1,7 +1,9 @@ /* PR target/100056 */ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-final { scan-assembler-not {\t[us]bfiz\tw[0-9]+, w[0-9]+, 11} } } */ +/* { dg-final { scan-assembler-not {\t[us]bfiz\tw[0-9]+, w[0-9]+, 11} { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\t[us]bfiz\tw[0-9]+, w[0-9]+, 11} 2 } } */ +/* { dg-final { scan-assembler-times {\tadd\tw[0-9]+, w[0-9]+, w[0-9]+, uxtb\n} 2 } } */ int or_shift_u8 (unsigned char i) diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c index dcac6d5..3799fb4 100644 --- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c +++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c @@ -315,3 +315,18 @@ #ifndef __ARM_FEATURE_FP8DOT2 #error Foo #endif + +#pragma GCC target "arch=armv9.4-a" +#ifdef __ARM_FEATURE_FAMINMAX +#error Foo +#endif + +#pragma GCC target "arch=armv9.5-a" +#ifndef __ARM_FEATURE_FAMINMAX +#error Foo +#endif + +#pragma GCC target "arch=armv8-a+faminmax" +#ifndef __ARM_FEATURE_FAMINMAX +#error Foo +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/gomp/gomp.exp b/gcc/testsuite/gcc.target/aarch64/sve/gomp/gomp.exp new file mode 100644 index 0000000..376985d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/gomp/gomp.exp @@ -0,0 +1,46 @@ +# Copyright (C) 2006-2025 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an AArch64 target. +if {![istarget aarch64*-*-*] } then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +if ![check_effective_target_fopenmp] { + return +} + +if { [check_effective_target_aarch64_sve] } { + set sve_flags "" +} else { + set sve_flags "-march=armv8.2-a+sve" +} + +# Main loop. +dg-runtest [lsort [find $srcdir/$subdir *.c]] "$sve_flags -fopenmp" "" + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-device.c b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-device.c new file mode 100644 index 0000000..75dd39b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-device.c @@ -0,0 +1,201 @@ +/* { dg-do compile } */ +/* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */ + +#include <arm_sve.h> + +#define N __ARM_FEATURE_SVE_BITS + +int64_t __attribute__ ((noipa)) +target_device_ptr_vla (svbool_t vp, svint32_t *vptr) +{ + + int a[N], b[N], c[N]; + svint32_t va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } +/* { dg-error {SVE type 'svint32_t \*' not allowed in 'target' device clauses} "" { target *-*-* } .+1 } */ +#pragma omp target data use_device_ptr (vptr) map (to: b, c) +/* { dg-error {SVE type 'svint32_t \*' not allowed in 'target' device clauses} "" { target *-*-* } .+1 } */ +#pragma omp target is_device_ptr (vptr) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vb = *vptr; + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+2 } */ + /* { dg-error "cannot reference 'svbool_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vc = svld1_s32 (vp, c); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +int64_t __attribute__ ((noipa)) +target_device_addr_vla (svbool_t vp, svint32_t *vptr) +{ + + int a[N], b[N], c[N]; + svint32_t va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'target' device clauses" "" { target *-*-* } .+1 } */ +#pragma omp target data use_device_addr (vb) map (to: b, c) +/* { dg-error {SVE type 'svint32_t \*' not allowed in 'target' device clauses} "" { target *-*-* } .+1 } */ +#pragma omp target is_device_ptr (vptr) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vb = *vptr; + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+2 } */ + /* { dg-error "cannot reference 'svbool_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vc = svld1_s32 (vp, c); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +int64_t __attribute__ ((noipa)) +target_has_device_addr_vla (svbool_t vp, svint32_t *vptr) +{ + + int a[N], b[N], c[N]; + svint32_t va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'target' device clauses" "" { target *-*-* } .+1 } */ +#pragma omp target data use_device_addr (vb) map (to: b, c) +/* { dg-error "SVE type 'svint32_t' not allowed in 'target' device clauses" "" { target *-*-* } .+1 } */ +#pragma omp target has_device_addr (vb) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svbool_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vb = svld1_s32 (vp, b); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vc = svld1_s32 (vp, c); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +#define FIXED_ATTR __attribute__ ((arm_sve_vector_bits (N))) + +typedef __SVInt32_t v8si FIXED_ATTR; +typedef svbool_t v8bi FIXED_ATTR; + +int64_t __attribute__ ((noipa)) +target_device_ptr_vls (v8bi vp, v8si *vptr) +{ + + int a[N], b[N], c[N]; + v8si va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +#pragma omp target data use_device_ptr (vptr) map (to: b, c) +#pragma omp target is_device_ptr (vptr) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + vb = *vptr; + vc = svld1_s32 (vp, c); + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +int64_t __attribute__ ((noipa)) +target_device_addr_vls (v8bi vp, v8si *vptr) +{ + + int a[N], b[N], c[N]; + v8si va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +#pragma omp target data use_device_addr (vb) map (to: b, c) +#pragma omp target is_device_ptr (vptr) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + vb = *vptr; + vc = svld1_s32 (vp, c); + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +int64_t __attribute__ ((noipa)) +target_has_device_addr_vls (v8bi vp, v8si *vptr) +{ + + int a[N], b[N], c[N]; + v8si va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +#pragma omp target data use_device_addr (vb) map (to: b, c) +#pragma omp target has_device_addr (vb) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + vb = svld1_s32 (vp, b); + vc = svld1_s32 (vp, c); + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-link.c b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-link.c new file mode 100644 index 0000000..2f6184b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-link.c @@ -0,0 +1,57 @@ +/* { dg-do compile } */ +/* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */ + +#include <arm_sve.h> + +#define N __ARM_FEATURE_SVE_BITS +#define FIXED_ATTR __attribute__((arm_sve_vector_bits (N))) + +typedef __SVInt32_t v8si FIXED_ATTR; + +static v8si local_vec; +#pragma omp declare target link(local_vec) + +v8si global_vec; +#pragma omp declare target link(global_vec) + +/* { dg-error {SVE type 'svint32_t' does not have a fixed size} "" { target *-*-* } .+1 } */ +static svint32_t slocal_vec; + +/* { dg-error {'slocal_vec' does not have a mappable type in 'link' clause} "" { target *-*-* } .+1 } */ +#pragma omp declare target link(slocal_vec) + +void +one_get_inc2_local_vec_vls () +{ + v8si res, res2, tmp; + +#pragma omp target map(from: res, res2) + { + res = local_vec; + local_vec = svadd_s32_z (svptrue_b32 (), local_vec, local_vec); + res2 = local_vec; + } + + tmp = svadd_s32_z (svptrue_b32 (), res, res); + svbool_t p = svcmpne_s32 (svptrue_b32 (), tmp, res2); + if (svptest_any (svptrue_b32 (), p)) + __builtin_abort (); +} + +void +one_get_inc3_global_vec_vls () +{ + v8si res, res2, tmp; + +#pragma omp target map(from: res, res2) + { + res = global_vec; + global_vec = svadd_s32_z (svptrue_b32 (), global_vec, global_vec); + res2 = global_vec; + } + + tmp = svadd_s32_z (svptrue_b32 (), res, res); + svbool_t p = svcmpne_s32 (svptrue_b32 (), tmp, res2); + if (svptest_any (svptrue_b32 (), p)) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/gomp/target.c b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target.c new file mode 100644 index 0000000..812183d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target.c @@ -0,0 +1,2049 @@ +/* { dg-do compile } */ +/* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */ + +#include <arm_sve.h> + +#define N __ARM_FEATURE_SVE_BITS +#define FIXED_ATTR __attribute__((arm_sve_vector_bits (N))) + +typedef svint32_t v8si FIXED_ATTR; +typedef svbool_t v8bi FIXED_ATTR; + +void +target_vla1 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla1 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla1 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla1 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla1 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls1 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls1 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls1 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls1 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls1 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla2 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target parallel + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla2 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla2 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla2 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla2 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target parallel + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls2 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target parallel + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls2 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target parallel map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls2 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target parallel map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls2 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target parallel map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target parallel map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls2 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target parallel + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla3 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target parallel loop + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla3 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla3 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla3 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla3 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target parallel loop + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls3 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target parallel loop + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls3 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target parallel loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls3 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target parallel loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls3 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target parallel loop map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target parallel loop map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls3 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target parallel loop + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target parallel loop map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla4 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target simd + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla4 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla4 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla4 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla4 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target simd + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls4 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target simd + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls4 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls4 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls4 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target simd map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target simd map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls4 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target simd + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla5 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla5 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla5 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla5 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla5 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls5 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls5 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls5 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls5 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target teams map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls5 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla6 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams loop + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla6 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla6 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla6 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla6 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams loop + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls6 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams loop + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls6 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls6 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls6 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target teams loop map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams loop map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls6 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams loop + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target teams loop map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla7 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams distribute + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla7 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla7 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla7 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla7 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams distribute + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls7 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams distribute + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls7 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams distribute map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls7 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams distribute map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls7 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target teams distribute map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams distribute map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls7 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams distribute + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target teams distribute map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla8 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams distribute simd + for (i = 0; i < 8; i++) + { + svint32_t va; + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla8 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla8 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla8 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla8 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams distribute simd + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls8 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams distribute simd + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls8 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams distribute simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls8 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams distribute simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls8 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target teams distribute simd map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams distribute simd map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls8 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams distribute simd + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target teams distribute simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_10.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_10.c new file mode 100644 index 0000000..b7a7bc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_10.c @@ -0,0 +1,24 @@ +/* Fix for PR119351 alignment peeling with vectors and VLS. */ +/* { dg-do compile } */ +/* { dg-options "-Ofast -msve-vector-bits=256 --param aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */ + +#define N 512 +#define START 0 +#define END 505 + +int x[N] __attribute__((aligned(32))); + +int __attribute__((noipa)) +foo (int start) +{ + for (unsigned int i = start; i < END; ++i) + { + if (x[i] == 0) + return i; + } + return -1; +} + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ +/* { dg-final { scan-tree-dump "pfa_iv_offset" "vect" } } */ +/* { dg-final { scan-tree-dump "Alignment of access forced using peeling" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_10_run.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_10_run.c new file mode 100644 index 0000000..6169aeb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_10_run.c @@ -0,0 +1,17 @@ +/* Fix for PR119351 alignment peeling with vectors and VLS. */ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only" } */ +/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw } } */ +/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw } } */ + +#include "peel_ind_10.c" + +int __attribute__ ((optimize (1))) +main (void) +{ + int res = foo (START); + asm volatile (""); + if (res != START) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5.c new file mode 100644 index 0000000..a03bb1d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5.c @@ -0,0 +1,24 @@ +/* Fix for PR119351 alignment peeling with vectors and VLS. */ +/* { dg-do compile } */ +/* { dg-options "-Ofast -msve-vector-bits=256 --param aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */ + +#define N 512 +#define START 2 +#define END 505 + +int x[N] __attribute__((aligned(32))); + +int __attribute__((noipa)) +foo (void) +{ + for (signed int i = START; i < END; ++i) + { + if (x[i] == 0) + return i; + } + return -1; +} + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ +/* { dg-final { scan-tree-dump "pfa_iv_offset" "vect" } } */ +/* { dg-final { scan-tree-dump "Alignment of access forced using peeling" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5_run.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5_run.c new file mode 100644 index 0000000..f26befe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5_run.c @@ -0,0 +1,17 @@ +/* Fix for PR119351 alignment peeling with vectors and VLS. */ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only" } */ +/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw } } */ +/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw } } */ + +#include "peel_ind_5.c" + +int __attribute__ ((optimize (1))) +main (void) +{ + int res = foo (); + asm volatile (""); + if (res != START) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6.c new file mode 100644 index 0000000..9bfd1a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6.c @@ -0,0 +1,24 @@ +/* Fix for PR119351 alignment peeling with vectors and VLS. */ +/* { dg-do compile } */ +/* { dg-options "-Ofast -msve-vector-bits=256 --param aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */ + +#define N 512 +#define START 1 +#define END 505 + +int x[N] __attribute__((aligned(32))); + +int __attribute__((noipa)) +foo (int start) +{ + for (unsigned int i = start; i < END; ++i) + { + if (x[i] == 0) + return i; + } + return -1; +} + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ +/* { dg-final { scan-tree-dump "pfa_iv_offset" "vect" } } */ +/* { dg-final { scan-tree-dump "Alignment of access forced using peeling" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6_run.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6_run.c new file mode 100644 index 0000000..4fdf3e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6_run.c @@ -0,0 +1,17 @@ +/* Fix for PR119351 alignment peeling with vectors and VLS. */ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only" } */ +/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw } } */ +/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw } } */ + +#include "peel_ind_6.c" + +int __attribute__ ((optimize (1))) +main (void) +{ + int res = foo (START); + asm volatile (""); + if (res != START) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7.c new file mode 100644 index 0000000..0182e13 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7.c @@ -0,0 +1,24 @@ +/* Fix for PR119351 alignment peeling with vectors and VLS. */ +/* { dg-do compile } */ +/* { dg-options "-Ofast -msve-vector-bits=256 --param aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */ + +#define N 512 +#define START 1 +#define END 505 + +int x[N] __attribute__((aligned(32))); + +int __attribute__((noipa)) +foo (void) +{ + for (unsigned int i = START; i < END; ++i) + { + if (x[i] == 0) + return i; + } + return -1; +} + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ +/* { dg-final { scan-tree-dump "pfa_iv_offset" "vect" } } */ +/* { dg-final { scan-tree-dump "Alignment of access forced using peeling" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7_run.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7_run.c new file mode 100644 index 0000000..05608dd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7_run.c @@ -0,0 +1,17 @@ +/* Fix for PR119351 alignment peeling with vectors and VLS. */ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only" } */ +/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw } } */ +/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw } } */ + +#include "peel_ind_7.c" + +int __attribute__ ((optimize (1))) +main (void) +{ + int res = foo (); + asm volatile (""); + if (res != START) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8.c new file mode 100644 index 0000000..043348b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8.c @@ -0,0 +1,24 @@ +/* Fix for PR119351 alignment peeling with vectors and VLS. */ +/* { dg-do compile } */ +/* { dg-options "-Ofast -msve-vector-bits=256 --param aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */ + +#define N 512 +#define START 1 +#define END 505 + +int x[N] __attribute__((aligned(32))); + +int __attribute__((noipa)) +foo (void) +{ + for (unsigned int i = START; i < END; i*=2) + { + if (x[i] == 0) + return i; + } + return -1; +} + +/* { dg-final { scan-tree-dump-not "LOOP VECTORIZED" "vect" } } */ +/* { dg-final { scan-tree-dump-not "pfa_iv_offset" "vect" } } */ +/* { dg-final { scan-tree-dump-not "Alignment of access forced using peeling" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8_run.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8_run.c new file mode 100644 index 0000000..aa86122 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8_run.c @@ -0,0 +1,17 @@ +/* Fix for PR119351 alignment peeling with vectors and VLS. */ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only" } */ +/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw } } */ +/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw } } */ + +#include "peel_ind_8.c" + +int __attribute__ ((optimize (1))) +main (void) +{ + int res = foo (); + asm volatile (""); + if (res != START) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9.c new file mode 100644 index 0000000..cc904e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9.c @@ -0,0 +1,25 @@ +/* Fix for PR119351 alignment peeling with vectors and VLS. */ +/* { dg-do compile } */ +/* { dg-options "-Ofast -msve-vector-bits=256 --param aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */ + +#define N 512 +#define START 1 +#define END 505 + +int x[N] __attribute__((aligned(32))); + +int __attribute__((noipa)) +foo (void) +{ + for (int *p = x + START; p < x + END; p++) + { + if (*p == 0) + return START; + } + return -1; +} + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ +/* Peels using a scalar loop. */ +/* { dg-final { scan-tree-dump-not "pfa_iv_offset" "vect" } } */ +/* { dg-final { scan-tree-dump "Alignment of access forced using peeling" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9_run.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9_run.c new file mode 100644 index 0000000..767f8bd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9_run.c @@ -0,0 +1,17 @@ +/* Fix for PR119351 alignment peeling with vectors and VLS. */ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only" } */ +/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw } } */ +/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw } } */ + +#include "peel_ind_9.c" + +int __attribute__ ((optimize (1))) +main (void) +{ + int res = foo (); + asm volatile (""); + if (res != START) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr119351.c b/gcc/testsuite/gcc.target/aarch64/sve/pr119351.c new file mode 100644 index 0000000..85aab35 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr119351.c @@ -0,0 +1,39 @@ +/* Fix for PR119351 alignment peeling with vectors and VLS. */ +/* { dg-do compile } */ +/* { dg-options "-Ofast -msve-vector-bits=256 --param aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */ +/* { dg-final { check-function-bodies "**" "" ""} } */ + +#define N 512 +#define START 1 +#define END 505 + +int x[N] __attribute__((aligned(32))); + +/* +** foo: +** ... +** ld1w z[0-9]+.s, p[0-9]+/z, \[x[0-9], x[0-9], lsl 2\] +** cmple p[0-9]+.s, p[0-9]+/z, z[0-9]+.s, #0 +** ptest p[0-9]+, p[0-9]+.b +** ... +*/ + +int __attribute__((noipa)) +foo (void) +{ + int z = 0; + for (unsigned int i = START; i < END; ++i) + { + z++; + if (x[i] > 0) + continue; + + return z; + } + return -1; +} + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ +/* { dg-final { scan-tree-dump "pfa_iv_offset" "vect" } } */ +/* { dg-final { scan-tree-dump "Alignment of access forced using peeling" "vect" } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr119351_run.c b/gcc/testsuite/gcc.target/aarch64/sve/pr119351_run.c new file mode 100644 index 0000000..d36ab0e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr119351_run.c @@ -0,0 +1,20 @@ +/* Fix for PR119351 alignment peeling with vectors and VLS. */ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only" } */ +/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw } } */ +/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw } } */ + +#include "pr119351.c" + +int __attribute__ ((optimize (1))) +main (void) +{ + x[0] = 1; + x[1] = 21; + x[2] = 39; + x[3] = 59; + int res = foo (); + if (res != 4) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-1.c b/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-1.c index a7d2795..c9a8b82 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-1.c @@ -19,6 +19,6 @@ void f10(double * restrict z, double * restrict w, double * restrict x, double * } } -/* { dg-final { scan-assembler-not {\tbic\t} { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not {\tbic\t} } } */ +/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfcmgt\tp[0-9]+\.d, p[0-9]+/z, z[0-9]+\.d, #0} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-4.c b/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-4.c index 20cbd75..1845bd3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-4.c @@ -8,6 +8,6 @@ void f13(double * restrict z, double * restrict w, double * restrict x, double * } } -/* { dg-final { scan-assembler-not {\tbic\t} { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not {\tbic\t} } } */ +/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfcmuo\tp[0-9]+\.d, p[0-9]+/z, z[0-9]+\.d, z[0-9]+\.d} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c index 33b9f0f..b8afea7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c @@ -16,7 +16,8 @@ f (TYPE *x, TYPE *y, unsigned short n, unsigned short m) /* { dg-final { scan-assembler {\tldr\tw[0-9]+} } } */ /* { dg-final { scan-assembler {\tstr\tw[0-9]+} } } */ /* Should multiply by (257-1)*4 rather than (VF-1)*4 or (VF-2)*4. */ -/* { dg-final { scan-assembler-times {\tadd\tx[0-9]+, x[0-9]+, x[0-9]+, lsl 10\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tubfiz\tx[0-9]+, x2, 10, 16\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tubfiz\tx[0-9]+, x3, 10, 16\n} 1 } } */ /* { dg-final { scan-assembler-not {\tcmp\tx[0-9]+, 0} } } */ /* { dg-final { scan-assembler-not {\tcmp\tw[0-9]+, 0} } } */ /* { dg-final { scan-assembler-not {\tcsel\tx[0-9]+} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c index 71b826a..d2e74f9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c @@ -16,7 +16,8 @@ f (TYPE *x, TYPE *y, int n, int m) /* { dg-final { scan-assembler {\tldr\tw[0-9]+} } } */ /* { dg-final { scan-assembler {\tstr\tw[0-9]+} } } */ /* Should multiply by (257-1)*4 rather than (VF-1)*4. */ -/* { dg-final { scan-assembler-times {\t(?:lsl\tx[0-9]+, x[0-9]+, 10|sbfiz\tx[0-9]+, x[0-9]+, 10, 32)\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsbfiz\tx[0-9]+, x2, 10, 32\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsbfiz\tx[0-9]+, x3, 10, 32\n} 1 } } */ /* { dg-final { scan-assembler {\tcmp\tw2, 0} } } */ /* { dg-final { scan-assembler {\tcmp\tw3, 0} } } */ /* { dg-final { scan-assembler-times {\tcsel\tx[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-nested-offset-long.c b/gcc/testsuite/gcc.target/alpha/memcpy-nested-offset-long.c new file mode 100644 index 0000000..631d14f --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memcpy-nested-offset-long.c @@ -0,0 +1,76 @@ +/* { dg-do compile } */ +/* { dg-options "" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef unsigned int __attribute__ ((mode (DI))) int64_t; +typedef unsigned int __attribute__ ((mode (SI))) int32_t; + +typedef union + { + int32_t l[8]; + } +val; + +typedef struct + { + int32_t l[2]; + val v; + } +tre; + +typedef struct + { + int32_t l[3]; + tre t; + } +due; + +typedef struct + { + val v; + int64_t q; + int32_t l[2]; + due d; + } +uno; + +void +memcpy_nested_offset_long (uno *u) +{ + u->d.t.v = u->v; +} + +/* Expect assembly such as: + + ldq $4,0($16) + ldq $3,8($16) + ldq $2,16($16) + srl $4,32,$7 + ldq $1,24($16) + srl $3,32,$6 + stl $4,68($16) + srl $2,32,$5 + stl $7,72($16) + srl $1,32,$4 + stl $3,76($16) + stl $6,80($16) + stl $2,84($16) + stl $5,88($16) + stl $1,92($16) + stl $4,96($16) + + that is with four quadword loads at offsets 0, 8, 16, 24 each and + eight longword stores at offsets 68, 72, 76, 80, 84, 88, 92, 96 each. */ + +/* { dg-final { scan-assembler-times "\\sldq\\s\\\$\[0-9\]+,0\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sldq\\s\\\$\[0-9\]+,8\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sldq\\s\\\$\[0-9\]+,16\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sldq\\s\\\$\[0-9\]+,24\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl\\s\\\$\[0-9\]+,68\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl\\s\\\$\[0-9\]+,72\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl\\s\\\$\[0-9\]+,76\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl\\s\\\$\[0-9\]+,80\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl\\s\\\$\[0-9\]+,84\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl\\s\\\$\[0-9\]+,88\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl\\s\\\$\[0-9\]+,92\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl\\s\\\$\[0-9\]+,96\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-nested-offset-quad.c b/gcc/testsuite/gcc.target/alpha/memcpy-nested-offset-quad.c new file mode 100644 index 0000000..1d2227e --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memcpy-nested-offset-quad.c @@ -0,0 +1,64 @@ +/* { dg-do compile } */ +/* { dg-options "" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef unsigned int __attribute__ ((mode (DI))) int64_t; +typedef unsigned int __attribute__ ((mode (SI))) int32_t; + +typedef union + { + int32_t l[8]; + } +val; + +typedef struct + { + int32_t l[2]; + val v; + } +tre; + +typedef struct + { + int32_t l[3]; + tre t; + } +due; + +typedef struct + { + val v; + int64_t q; + int32_t l[3]; + due d; + } +uno; + +void +memcpy_nested_offset_quad (uno *u) +{ + u->d.t.v = u->v; +} + +/* Expect assembly such as: + + ldq $4,0($16) + ldq $3,8($16) + ldq $2,16($16) + ldq $1,24($16) + stq $4,72($16) + stq $3,80($16) + stq $2,88($16) + stq $1,96($16) + + that is with four quadword loads at offsets 0, 8, 16, 24 each + and four quadword stores at offsets 72, 80, 88, 96 each. */ + +/* { dg-final { scan-assembler-times "\\sldq\\s\\\$\[0-9\]+,0\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sldq\\s\\\$\[0-9\]+,8\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sldq\\s\\\$\[0-9\]+,16\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sldq\\s\\\$\[0-9\]+,24\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq\\s\\\$\[0-9\]+,72\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq\\s\\\$\[0-9\]+,80\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq\\s\\\$\[0-9\]+,88\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq\\s\\\$\[0-9\]+,96\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/ivopts.c b/gcc/testsuite/gcc.target/arm/ivopts.c index d7d72a5..582fdab 100644 --- a/gcc/testsuite/gcc.target/arm/ivopts.c +++ b/gcc/testsuite/gcc.target/arm/ivopts.c @@ -11,6 +11,6 @@ tr5 (short array[], int n) } /* { dg-final { scan-tree-dump-times "PHI <" 1 "ivopts"} } */ -/* { dg-final { object-size text <= 20 { target { arm_thumb2_no_arm_v8_1_lob } } } } */ +/* { dg-final { object-size text <= 20 { target { arm_thumb2_no_arm_v8_1m_lob } } } } */ /* { dg-final { object-size text <= 32 { target { arm_nothumb && { ! arm_iwmmxt_ok } } } } } */ /* { dg-final { object-size text <= 36 { target { arm_nothumb && arm_iwmmxt_ok } } } } */ diff --git a/gcc/testsuite/gcc.target/arm/lob1.c b/gcc/testsuite/gcc.target/arm/lob1.c index c8ce653..f42a367 100644 --- a/gcc/testsuite/gcc.target/arm/lob1.c +++ b/gcc/testsuite/gcc.target/arm/lob1.c @@ -1,7 +1,7 @@ /* Check that GCC generates Armv8.1-M low over head loop instructions for some simple loops. */ /* { dg-do run } */ -/* { dg-require-effective-target arm_v8_1_lob_ok } */ +/* { dg-require-effective-target arm_v8_1m_lob_hw } */ /* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "-mcpu=*" } } */ /* { dg-options "-march=armv8.1-m.main -mthumb -O3 --save-temps" } */ #include <stdlib.h> diff --git a/gcc/testsuite/gcc.target/arm/lob6.c b/gcc/testsuite/gcc.target/arm/lob6.c index 4fe116e..e19635b 100644 --- a/gcc/testsuite/gcc.target/arm/lob6.c +++ b/gcc/testsuite/gcc.target/arm/lob6.c @@ -1,7 +1,7 @@ /* Check that GCC generates Armv8.1-M low over head loop instructions with some less trivial loops and the result is correct. */ /* { dg-do run } */ -/* { dg-require-effective-target arm_v8_1_lob_ok } */ +/* { dg-require-effective-target arm_v8_1m_lob_hw } */ /* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "-mcpu=*" } } */ /* { dg-options "-march=armv8.1-m.main -mthumb -O3 --save-temps" } */ #include <stdlib.h> diff --git a/gcc/testsuite/gcc.target/arm/mve/mve.exp b/gcc/testsuite/gcc.target/arm/mve/mve.exp index a5d8511..9dc56c9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/mve.exp +++ b/gcc/testsuite/gcc.target/arm/mve/mve.exp @@ -35,6 +35,7 @@ global dg_runtest_extra_prunes set dg_runtest_extra_prunes "" lappend dg_runtest_extra_prunes "warning: switch '-m(cpu|arch)=.*' conflicts with switch '-m(cpu|arch)=.*'" +set saved-dg-do-what-default ${dg-do-what-default} set dg-do-what-default "assemble" # Initialize `dg'. @@ -53,6 +54,8 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/general-c/*.\[cCS\]]] \ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ "" $DEFAULT_CFLAGS +set dg-do-what-default ${saved-dg-do-what-default} + # All done. set dg_runtest_extra_prunes "" dg-finish diff --git a/gcc/testsuite/gcc.target/arm/short-vfp-1.c b/gcc/testsuite/gcc.target/arm/short-vfp-1.c index 18d38a5..418fc27 100644 --- a/gcc/testsuite/gcc.target/arm/short-vfp-1.c +++ b/gcc/testsuite/gcc.target/arm/short-vfp-1.c @@ -1,45 +1,75 @@ /* { dg-do compile } */ -/* { dg-require-effective-target arm_vfp_ok } -/* { dg-add-options arm_vfp } */ +/* { dg-require-effective-target arm_arch_v7a_fp_hard_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v7a_fp_hard } */ +/* { dg-final { check-function-bodies "**" "" } } */ +/* +** test_sisf: +** vcvt.s32.f32 (s[0-9]+), s0 +** vmov r0, \1 @ int +** bx lr +*/ int test_sisf (float x) { return (int)x; } +/* +** test_hisf: +** vcvt.s32.f32 (s[0-9]+), s0 +** vmov (r[0-9]+), \1 @ int +** sxth r0, \2 +** bx lr +*/ short test_hisf (float x) { return (short)x; } +/* +** test_sfsi: +** vmov (s[0-9]+), r0 @ int +** vcvt.f32.s32 s0, \1 +** bx lr +*/ float test_sfsi (int x) { return (float)x; } +/* +** test_sfhi: +** vmov (s[0-9]+), r0 @ int +** vcvt.f32.s32 s0, \1 +** bx lr +*/ float test_sfhi (short x) { return (float)x; } +/* +** test_hisi: +** sxth r0, r0 +** bx lr +*/ short test_hisi (int x) { return (short)x; } +/* +** test_sihi: +** bx lr +*/ int test_sihi (short x) { return (int)x; } - -/* { dg-final { scan-assembler-times {vcvt\.s32\.f32\ts[0-9]+,s[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {vcvt\.f32\.s32\ts[0-9]+,s[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {vmov\tr[0-9]+,s[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {vmov\ts[0-9]+,r[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {sxth\tr[0-9]+,r[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c index 9272e4c..41ee994 100644 --- a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c +++ b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target arm_thumb2_ok_no_arm_v8_1_lob } */ +/* { dg-require-effective-target arm_thumb2_ok_no_arm_v8_1m_lob } */ /* { dg-options "-O" } */ unsigned short foo (unsigned short x, unsigned short c) diff --git a/gcc/testsuite/gcc.target/i386/apx-interrupt-1.c b/gcc/testsuite/gcc.target/i386/apx-interrupt-1.c index fefe2e6..fa1acc7 100644 --- a/gcc/testsuite/gcc.target/i386/apx-interrupt-1.c +++ b/gcc/testsuite/gcc.target/i386/apx-interrupt-1.c @@ -66,7 +66,7 @@ void foo (void *frame) /* { dg-final { scan-assembler-times {\t\.cfi_offset 132, -120} 1 } } */ /* { dg-final { scan-assembler-times {\t\.cfi_offset 131, -128} 1 } } */ /* { dg-final { scan-assembler-times {\t\.cfi_offset 130, -136} 1 } } */ -/* { dg-final { scan-assembler-times ".cfi_restore" 15} } */ +/* { dg-final { scan-assembler-times ".cfi_restore" 31 } } */ /* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)ax" 1 } } */ /* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ /* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)cx" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd.c b/gcc/testsuite/gcc.target/i386/apx-ndd.c index ce77630..2b2f4fc 100644 --- a/gcc/testsuite/gcc.target/i386/apx-ndd.c +++ b/gcc/testsuite/gcc.target/i386/apx-ndd.c @@ -188,16 +188,13 @@ FOO2 (int64_t, imul, *) /* { dg-final { scan-assembler-times "not(?:l|w|q)\[^\n\r]%(?:|r|e)di, %(?:|r|e)ax" 4 } } */ /* { dg-final { scan-assembler-times "andb\[^\n\r]*1, \\(%(?:r|e)di\\), %al" 1 } } */ /* { dg-final { scan-assembler-times "and(?:l|w|q)\[^\n\r]*1, \\(%(?:r|e)di\\), %(?:|r|e)ax" 3 } } */ -/* { dg-final { scan-assembler-times "and(?:l|w|q)\[^\n\r]%(?:|r|e)di, %(?:|r|e)si, %(?:|r|e)ax" 2 } } */ -/* { dg-final { scan-assembler-times "and(?:l|w|q)\[^\n\r]%(?:|r|e)si, %(?:|r|e)di, %(?:|r|e)ax" 2 } } */ +/* { dg-final { scan-assembler-times "and(?:l|w|q)\[^\n\r]%(?:|r|e)si, %(?:|r|e)di, %(?:|r|e)ax" 4 } } */ /* { dg-final { scan-assembler-times "orb\[^\n\r]*1, \\(%(?:r|e)di\\), %al" 2} } */ /* { dg-final { scan-assembler-times "or(?:l|w|q)\[^\n\r]*1, \\(%(?:r|e)di\\), %(?:|r|e)ax" 6 } } */ -/* { dg-final { scan-assembler-times "or(?:l|w|q)\[^\n\r]%(?:|r|e)di, %(?:|r|e)si, %(?:|r|e)ax" 4 } } */ -/* { dg-final { scan-assembler-times "or(?:l|w|q)\[^\n\r]%(?:|r|e)si, %(?:|r|e)di, %(?:|r|e)ax" 4 } } */ +/* { dg-final { scan-assembler-times "or(?:l|w|q)\[^\n\r]%(?:|r|e)si, %(?:|r|e)di, %(?:|r|e)ax" 8 } } */ /* { dg-final { scan-assembler-times "xorb\[^\n\r]*1, \\(%(?:r|e)di\\), %al" 1 } } */ /* { dg-final { scan-assembler-times "xor(?:l|w|q)\[^\n\r]*1, \\(%(?:r|e)di\\), %(?:|r|e)ax" 3 } } */ -/* { dg-final { scan-assembler-times "xor(?:l|w|q)\[^\n\r]%(?:|r|e)di, %(?:|r|e)si, %(?:|r|e)ax" 2 } } */ -/* { dg-final { scan-assembler-times "xor(?:l|w|q)\[^\n\r]%(?:|r|e)si, %(?:|r|e)di, %(?:|r|e)ax" 2 } } */ +/* { dg-final { scan-assembler-times "xor(?:l|w|q)\[^\n\r]%(?:|r|e)si, %(?:|r|e)di, %(?:|r|e)ax" 4 } } */ /* { dg-final { scan-assembler-times "sal(?:b|l|w|q)\[^\n\r]*1, \\(%(?:r|e)di\\), %(?:|r|e)a(?:x|l)" 4 } } */ /* { dg-final { scan-assembler-times "sal(?:l|w|q)\[^\n\r]*7, %(?:|r|e)di, %(?:|r|e)ax" 4 } } */ /* { dg-final { scan-assembler-times "sar(?:b|l|w|q)\[^\n\r]*1, \\(%(?:r|e)di\\), %(?:|r|e)a(?:x|l)" 4 } } */ diff --git a/gcc/testsuite/gcc.target/i386/apx-nf-pr119539.c b/gcc/testsuite/gcc.target/i386/apx-nf-pr119539.c new file mode 100644 index 0000000..5dfec55 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-nf-pr119539.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mapx-features=nf -march=x86-64 -O2" } */ +/* { dg-final { scan-assembler-times "\{nf\} rol" 2 } } */ + +long int f1 (int x) { return ~(1ULL << (x & 0x3f)); } +long int f2 (char x) { return ~(1ULL << (x & 0x3f)); } diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr96891-3.c b/gcc/testsuite/gcc.target/i386/avx512f-pr96891-3.c index 5b26081..5eb60d9 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-pr96891-3.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-pr96891-3.c @@ -1,11 +1,10 @@ /* { dg-do compile } */ /* { dg-options "-mavx512vl -mavx512bw -mavx512dq -O2 -masm=att -mstv -mno-stackrealign" } */ /* { dg-final { scan-assembler-not {not[bwlqd]\]} } } */ -/* { dg-final { scan-assembler-times {(?n)vpcmp[bwdq][ \t]*\$5} 4} } */ -/* { dg-final { scan-assembler-times {(?n)vpcmp[bwdq][ \t]*\$6} 4} } */ +/* { dg-final { scan-assembler-times {(?n)vpcmp[bwdq][ \t]*\$5} 2} } */ +/* { dg-final { scan-assembler-times {(?n)vpcmp[bwdq][ \t]*\$6} 3} } */ /* { dg-final { scan-assembler-times {(?n)vpcmp[bwdq][ \t]*\$[37]} 4} } */ -/* { dg-final { scan-assembler-times {(?n)vcmpp[sd][ \t]*\$5} 2} } */ -/* { dg-final { scan-assembler-times {(?n)vcmpp[sd][ \t]*\$6} 2} } */ +/* { dg-final { scan-assembler-times {(?n)vcmpp[sd][ \t]*\$6} 1} } */ /* { dg-final { scan-assembler-times {(?n)vcmpp[sd][ \t]*\$7} 2} } */ #include<immintrin.h> @@ -20,20 +19,14 @@ FOO (__m128i,, epi8, __mmask16, 128, 1); FOO (__m128i,, epi16, __mmask8, 128, 1); -FOO (__m128i,, epi32, __mmask8, 128, 1); -FOO (__m128i,, epi64, __mmask8, 128, 1); FOO (__m256i, 256, epi8, __mmask32, 256, 2); FOO (__m256i, 256, epi16, __mmask16, 256, 2); FOO (__m256i, 256, epi32, __mmask8, 256, 2); -FOO (__m256i, 256, epi64, __mmask8, 256, 2); FOO (__m512i, 512, epi8, __mmask64, 512, 3); FOO (__m512i, 512, epi16, __mmask32, 512, 3); FOO (__m512i, 512, epi32, __mmask16, 512, 3); FOO (__m512i, 512, epi64, __mmask8, 512, 3); -FOO (__m128,, ps, __mmask8, 128, 1); -FOO (__m128d,, pd, __mmask8, 128, 1); FOO (__m256, 256, ps, __mmask8, 256, 2); -FOO (__m256d, 256, pd, __mmask8, 256, 2); FOO (__m512, 512, ps, __mmask16, 512, 3); FOO (__m512d, 512, pd, __mmask8, 512, 3); diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtuq-1.c b/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtuq-1.c index ef6a525..37ca646 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtuq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtuq-1.c @@ -12,5 +12,5 @@ void extern avx512f_test (void) { m = _mm512_cmpgt_epu64_mask (x, x); - m = _mm512_mask_cmpgt_epu64_mask (3, x, x); + m = _mm512_mask_cmpgt_epu64_mask (5, x, x); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-pr103750-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-pr103750-1.c new file mode 100644 index 0000000..a15fae8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-pr103750-1.c @@ -0,0 +1,79 @@ +/* PR target/103750 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512vl" } */ +/* { dg-final { scan-assembler-not "and" } } */ + +#include <immintrin.h> +extern __m128i* pi128; +extern __m256i* pi256; + +extern __m128* ps128; +extern __m256* ps256; + +extern __m128d* pd128; +extern __m256d* pd256; + +extern char a; +void +foo () +{ + __mmask8 mask1 = _mm_cmpeq_epu32_mask (pi128[0], pi128[1]); + a = mask1 & 15; +} + +void +foo1 () +{ + __mmask8 mask1 = _mm_cmpeq_epu64_mask (pi128[0], pi128[1]); + a = mask1 & 3; +} + +void +foo2 () +{ + __mmask8 mask1 = _mm256_cmpeq_epu64_mask (pi256[0], pi256[1]); + a = mask1 & 15; +} + +void +sign_foo () +{ + __mmask8 mask1 = _mm_cmpeq_epi32_mask (pi128[0], pi128[1]); + a = mask1 & 15; +} + +void +sign_foo1 () +{ + __mmask8 mask1 = _mm_cmpeq_epi64_mask (pi128[0], pi128[1]); + a = mask1 & 3; +} + + +void +sign_foo2 () +{ + __mmask8 mask1 = _mm256_cmpeq_epi64_mask (pi256[0], pi256[1]); + a = mask1 & 15; +} + +void +float_foo () +{ + __mmask8 mask1 = _mm_cmp_ps_mask (ps128[0], ps128[1], 1); + a = mask1 & 15; +} + +void +double_foo () +{ + __mmask8 mask1 = _mm_cmp_pd_mask (pd128[0], pd128[1], 1); + a = mask1 & 3; +} + +void +double_foo2 () +{ + __mmask8 mask1 = _mm256_cmp_pd_mask (pd256[0], pd256[1], 1); + a = mask1 & 15; +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpeqq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpeqq-1.c index 69b200a..a798d06 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpeqq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpeqq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpeq_epi64_mask (x128, x128); m = _mm256_cmpeq_epi64_mask (x256, x256); - m = _mm_mask_cmpeq_epi64_mask (3, x128, x128); - m = _mm256_mask_cmpeq_epi64_mask (3, x256, x256); + m = _mm_mask_cmpeq_epi64_mask (5, x128, x128); + m = _mm256_mask_cmpeq_epi64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpequq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpequq-1.c index c925d32..736763f 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpequq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpequq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpeq_epu64_mask (x128, x128); m = _mm256_cmpeq_epu64_mask (x256, x256); - m = _mm_mask_cmpeq_epu64_mask (3, x128, x128); - m = _mm256_mask_cmpeq_epu64_mask (3, x256, x256); + m = _mm_mask_cmpeq_epu64_mask (5, x128, x128); + m = _mm256_mask_cmpeq_epu64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeq-1.c index ef40e41..19110a5 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpge_epi64_mask (x128, x128); m = _mm256_cmpge_epi64_mask (x256, x256); - m = _mm_mask_cmpge_epi64_mask (3, x128, x128); - m = _mm256_mask_cmpge_epi64_mask (3, x256, x256); + m = _mm_mask_cmpge_epi64_mask (5, x128, x128); + m = _mm256_mask_cmpge_epi64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeuq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeuq-1.c index 1f7dd49..d82f8e5 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeuq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeuq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpge_epu64_mask (x128, x128); m = _mm256_cmpge_epu64_mask (x256, x256); - m = _mm_mask_cmpge_epu64_mask (3, x128, x128); - m = _mm256_mask_cmpge_epu64_mask (3, x256, x256); + m = _mm_mask_cmpge_epu64_mask (5, x128, x128); + m = _mm256_mask_cmpge_epu64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtq-1.c index 26cac3a..79f9430 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpgt_epi64_mask (x128, x128); m = _mm256_cmpgt_epi64_mask (x256, x256); - m = _mm_mask_cmpgt_epi64_mask (3, x128, x128); - m = _mm256_mask_cmpgt_epi64_mask (3, x256, x256); + m = _mm_mask_cmpgt_epi64_mask (5, x128, x128); + m = _mm256_mask_cmpgt_epi64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtuq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtuq-1.c index 10717cd..bef015f 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtuq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtuq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpgt_epu64_mask (x128, x128); m = _mm256_cmpgt_epu64_mask (x256, x256); - m = _mm_mask_cmpgt_epu64_mask (3, x128, x128); - m = _mm256_mask_cmpgt_epu64_mask (3, x256, x256); + m = _mm_mask_cmpgt_epu64_mask (5, x128, x128); + m = _mm256_mask_cmpgt_epu64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleq-1.c index 110ff70..9974aa5 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmple_epi64_mask (x128, x128); m = _mm256_cmple_epi64_mask (x256, x256); - m = _mm_mask_cmple_epi64_mask (3, x128, x128); - m = _mm256_mask_cmple_epi64_mask (3, x256, x256); + m = _mm_mask_cmple_epi64_mask (5, x128, x128); + m = _mm256_mask_cmple_epi64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleuq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleuq-1.c index e3faf41..0a5a513 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleuq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleuq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmple_epu64_mask (x128, x128); m = _mm256_cmple_epu64_mask (x256, x256); - m = _mm_mask_cmple_epu64_mask (3, x128, x128); - m = _mm256_mask_cmple_epu64_mask (3, x256, x256); + m = _mm_mask_cmple_epu64_mask (5, x128, x128); + m = _mm256_mask_cmple_epu64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltq-1.c index 1b8f7f1..5f40c79 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmplt_epi64_mask (x128, x128); m = _mm256_cmplt_epi64_mask (x256, x256); - m = _mm_mask_cmplt_epi64_mask (3, x128, x128); - m = _mm256_mask_cmplt_epi64_mask (3, x256, x256); + m = _mm_mask_cmplt_epi64_mask (5, x128, x128); + m = _mm256_mask_cmplt_epi64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltuq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltuq-1.c index 5c2f025..afda5e7 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltuq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltuq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmplt_epu64_mask (x128, x128); m = _mm256_cmplt_epu64_mask (x256, x256); - m = _mm_mask_cmplt_epu64_mask (3, x128, x128); - m = _mm256_mask_cmplt_epu64_mask (3, x256, x256); + m = _mm_mask_cmplt_epu64_mask (5, x128, x128); + m = _mm256_mask_cmplt_epu64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpneqq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpneqq-1.c index f48de10..5ef2548 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpneqq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpneqq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpneq_epi64_mask (x128, x128); m = _mm256_cmpneq_epi64_mask (x256, x256); - m = _mm_mask_cmpneq_epi64_mask (3, x128, x128); - m = _mm256_mask_cmpneq_epi64_mask (3, x256, x256); + m = _mm_mask_cmpneq_epi64_mask (5, x128, x128); + m = _mm256_mask_cmpneq_epi64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpnequq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpnequq-1.c index 726a887..4a9aacf 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpnequq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpnequq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpneq_epu64_mask (x128, x128); m = _mm256_cmpneq_epu64_mask (x256, x256); - m = _mm_mask_cmpneq_epu64_mask (3, x128, x128); - m = _mm256_mask_cmpneq_epu64_mask (3, x256, x256); + m = _mm_mask_cmpneq_epu64_mask (5, x128, x128); + m = _mm256_mask_cmpneq_epu64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/blendv-to-maxmin.c b/gcc/testsuite/gcc.target/i386/blendv-to-maxmin.c new file mode 100644 index 0000000..042eb7d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/blendv-to-maxmin.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v3 -O2 -mfpmath=sse" } */ +/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */ + +double +foo (double a) +{ + if (a > 0.0) + return a; + return 0.0; +} + diff --git a/gcc/testsuite/gcc.target/i386/blendv-to-pand.c b/gcc/testsuite/gcc.target/i386/blendv-to-pand.c new file mode 100644 index 0000000..2896a2b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/blendv-to-pand.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3 -mfpmath=sse" } */ +/* { dg-final { scan-assembler-not "vblendv" } } */ + +void +foo (float* a, float* b, float* c, float* __restrict d, int n) +{ + for (int i = 0; i != n; i++) + { + c[i] *= 2.0f; + if (a[i] > b[i]) + d[i] = 0.0f; + else + d[i] = c[i]; + } +} diff --git a/gcc/testsuite/gcc.target/i386/pr111673.c b/gcc/testsuite/gcc.target/i386/pr111673.c index b9ceacf..0f08ba89 100644 --- a/gcc/testsuite/gcc.target/i386/pr111673.c +++ b/gcc/testsuite/gcc.target/i386/pr111673.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O2 -fdump-rtl-pro_and_epilogue" } */ +/* { dg-options "-O2 -fdump-rtl-pro_and_epilogue -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr115910.c b/gcc/testsuite/gcc.target/i386/pr115910.c new file mode 100644 index 0000000..5f1cd9a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr115910.c @@ -0,0 +1,20 @@ +/* PR target/115910 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=x86-64 -mtune=generic -masm=att" } */ +/* { dg-final { scan-assembler-times {\timulq\t} 2 } } */ +/* { dg-final { scan-assembler-times {\tshrq\t\$33,} 2 } } */ +/* { dg-final { scan-assembler-not {\tsarl\t} } } */ + +int +foo (int x) +{ + if (x < 0) + __builtin_unreachable (); + return x / 3U; +} + +int +bar (int x) +{ + return x / 3U; +} diff --git a/gcc/testsuite/gcc.target/i386/pr119386-1.c b/gcc/testsuite/gcc.target/i386/pr119386-1.c new file mode 100644 index 0000000..9a0dc64 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119386-1.c @@ -0,0 +1,10 @@ +/* PR target/119386 */ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -pg" } */ +/* { dg-final { scan-assembler "call\[ \t\]+mcount@PLT" } } */ + +int +main () +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr119386-2.c b/gcc/testsuite/gcc.target/i386/pr119386-2.c new file mode 100644 index 0000000..3ea978e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119386-2.c @@ -0,0 +1,12 @@ +/* PR target/119386 */ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fno-plt -pg" } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*mcount@GOTPCREL\\(" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*mcount@GOT\\(" { target ia32 } } } */ + + +int +main () +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr119386-3.c b/gcc/testsuite/gcc.target/i386/pr119386-3.c new file mode 100644 index 0000000..287410b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119386-3.c @@ -0,0 +1,10 @@ +/* PR target/119386 */ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -pg -mnop-mcount" } */ +/* { dg-final { scan-assembler ".byte\[ \t\]+0x0f, 0x1f, 0x44, 0x00, 0x00" } } */ + +int +main () +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr119784a.c b/gcc/testsuite/gcc.target/i386/pr119784a.c new file mode 100644 index 0000000..8a119d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119784a.c @@ -0,0 +1,96 @@ +/* { dg-do compile { target { *-*-linux* && lp64 } } } */ +/* { dg-options "-O2 -fno-pic -mtune=generic -mgeneral-regs-only -mapxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* start must save and restore all caller saved registers. */ + +/* +**start: +**.LFB[0-9]+: +** .cfi_startproc +** subq \$248, %rsp +**... +** movq %rax, \(%rsp\) +** movq %rdx, 8\(%rsp\) +** movq %rcx, 16\(%rsp\) +** movq %rbx, 24\(%rsp\) +** movq %rsi, 32\(%rsp\) +** movq %rdi, 40\(%rsp\) +**... +** movq %rbp, 48\(%rsp\) +** movq %r8, 56\(%rsp\) +** movq %r9, 64\(%rsp\) +** movq %r10, 72\(%rsp\) +** movq %r11, 80\(%rsp\) +** movq %r12, 88\(%rsp\) +** movq %r13, 96\(%rsp\) +** movq %r14, 104\(%rsp\) +** movq %r15, 112\(%rsp\) +** movq %r16, 120\(%rsp\) +** movq %r17, 128\(%rsp\) +** movq %r18, 136\(%rsp\) +** movq %r19, 144\(%rsp\) +** movq %r20, 152\(%rsp\) +** movq %r21, 160\(%rsp\) +** movq %r22, 168\(%rsp\) +** movq %r23, 176\(%rsp\) +** movq %r24, 184\(%rsp\) +** movq %r25, 192\(%rsp\) +** movq %r26, 200\(%rsp\) +** movq %r27, 208\(%rsp\) +** movq %r28, 216\(%rsp\) +** movq %r29, 224\(%rsp\) +** movq %r30, 232\(%rsp\) +** movq %r31, 240\(%rsp\) +**... +** call \*code\(%rip\) +** movq \(%rsp\), %rax +** movq 8\(%rsp\), %rdx +** movq 16\(%rsp\), %rcx +** movq 24\(%rsp\), %rbx +** movq 32\(%rsp\), %rsi +** movq 40\(%rsp\), %rdi +** movq 48\(%rsp\), %rbp +** movq 56\(%rsp\), %r8 +** movq 64\(%rsp\), %r9 +** movq 72\(%rsp\), %r10 +** movq 80\(%rsp\), %r11 +** movq 88\(%rsp\), %r12 +** movq 96\(%rsp\), %r13 +** movq 104\(%rsp\), %r14 +** movq 112\(%rsp\), %r15 +** movq 120\(%rsp\), %r16 +** movq 128\(%rsp\), %r17 +** movq 136\(%rsp\), %r18 +** movq 144\(%rsp\), %r19 +** movq 152\(%rsp\), %r20 +** movq 160\(%rsp\), %r21 +** movq 168\(%rsp\), %r22 +** movq 176\(%rsp\), %r23 +** movq 184\(%rsp\), %r24 +** movq 192\(%rsp\), %r25 +** movq 200\(%rsp\), %r26 +** movq 208\(%rsp\), %r27 +** movq 216\(%rsp\), %r28 +** movq 224\(%rsp\), %r29 +** movq 232\(%rsp\), %r30 +** movq 240\(%rsp\), %r31 +** addq \$248, %rsp +**... +** ret +** .cfi_endproc +**... +*/ + +#define DONT_SAVE_REGS __attribute__((no_callee_saved_registers)) +#define SAVE_REGS __attribute__((no_caller_saved_registers)) + +typedef DONT_SAVE_REGS void (*op_t)(void); + +extern op_t code[]; + +SAVE_REGS void start() +{ + code[0](); +} diff --git a/gcc/testsuite/gcc.target/i386/pr119784b.c b/gcc/testsuite/gcc.target/i386/pr119784b.c new file mode 100644 index 0000000..c676197 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119784b.c @@ -0,0 +1,87 @@ +/* { dg-do compile { target { *-*-linux* && x32 } } } */ +/* { dg-options "-O2 -fno-pic -mtune=generic -mgeneral-regs-only -mapxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* start must save and restore all caller saved registers. */ + +/* +**start: +**.LFB[0-9]+: +** .cfi_startproc +** subl \$248, %esp +**... +** movq %rax, \(%rsp\) +** movq %rdx, 8\(%rsp\) +** movq %rcx, 16\(%rsp\) +** movq %rbx, 24\(%rsp\) +** movq %rsi, 32\(%rsp\) +** movq %rdi, 40\(%rsp\) +**... +** movq %rbp, 48\(%rsp\) +** movq %r8, 56\(%rsp\) +** movq %r9, 64\(%rsp\) +** movq %r10, 72\(%rsp\) +** movq %r11, 80\(%rsp\) +** movq %r12, 88\(%rsp\) +** movq %r13, 96\(%rsp\) +** movq %r14, 104\(%rsp\) +** movq %r15, 112\(%rsp\) +** movq %r16, 120\(%rsp\) +** movq %r17, 128\(%rsp\) +** movq %r18, 136\(%rsp\) +** movq %r19, 144\(%rsp\) +** movq %r20, 152\(%rsp\) +** movq %r21, 160\(%rsp\) +** movq %r22, 168\(%rsp\) +** movq %r23, 176\(%rsp\) +** movq %r24, 184\(%rsp\) +** movq %r25, 192\(%rsp\) +** movq %r26, 200\(%rsp\) +** movq %r27, 208\(%rsp\) +** movq %r28, 216\(%rsp\) +** movq %r29, 224\(%rsp\) +** movq %r30, 232\(%rsp\) +** movq %r31, 240\(%rsp\) +**... +** movl code\(%rip\), %ebp +** call \*%rbp +** movq \(%rsp\), %rax +** movq 8\(%rsp\), %rdx +** movq 16\(%rsp\), %rcx +** movq 24\(%rsp\), %rbx +** movq 32\(%rsp\), %rsi +** movq 40\(%rsp\), %rdi +** movq 48\(%rsp\), %rbp +** movq 56\(%rsp\), %r8 +** movq 64\(%rsp\), %r9 +** movq 72\(%rsp\), %r10 +** movq 80\(%rsp\), %r11 +** movq 88\(%rsp\), %r12 +** movq 96\(%rsp\), %r13 +** movq 104\(%rsp\), %r14 +** movq 112\(%rsp\), %r15 +** movq 120\(%rsp\), %r16 +** movq 128\(%rsp\), %r17 +** movq 136\(%rsp\), %r18 +** movq 144\(%rsp\), %r19 +** movq 152\(%rsp\), %r20 +** movq 160\(%rsp\), %r21 +** movq 168\(%rsp\), %r22 +** movq 176\(%rsp\), %r23 +** movq 184\(%rsp\), %r24 +** movq 192\(%rsp\), %r25 +** movq 200\(%rsp\), %r26 +** movq 208\(%rsp\), %r27 +** movq 216\(%rsp\), %r28 +** movq 224\(%rsp\), %r29 +** movq 232\(%rsp\), %r30 +** movq 240\(%rsp\), %r31 +** addl \$248, %esp +**... +** ret +** .cfi_endproc +**... +*/ + +#include "pr119784a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr119919.c b/gcc/testsuite/gcc.target/i386/pr119919.c new file mode 100644 index 0000000..ed64656 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119919.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -fdump-tree-vect-details" } */ +int a[9*9]; +bool b[9]; +void test() +{ + for (int i = 0; i < 9; i++) + { + b[i] = a[i*9] != 0; + } +} + +/* { dg-final { scan-tree-dump "loop vectorized using 8 byte vectors" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr67215-1.c b/gcc/testsuite/gcc.target/i386/pr67215-1.c index fd37f8e..ab69550 100644 --- a/gcc/testsuite/gcc.target/i386/pr67215-1.c +++ b/gcc/testsuite/gcc.target/i386/pr67215-1.c @@ -13,8 +13,8 @@ foo (void) arr[i] = bar (128); } -/* { dg-final { scan-assembler "call\[ \t\]*.bar@GOTPCREL" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "call\[ \t\]*.bar@GOT\\(" { target ia32 } } } */ -/* { dg-final { scan-assembler-not "mov(l|q)\[ \t\]*.bar@GOTPCREL" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-not "movl\[ \t\]*.bar@GOT\\(" { target ia32 } } } */ -/* { dg-final { scan-assembler-not "call\[ \t\]*.bar@PLT" } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*bar@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*bar@GOT\\(" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "mov(l|q)\[ \t\]+bar@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "movl\[ \t\]+bar@GOT\\(" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "call\[ \t\]+\\*bar@PLT" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr67215-2.c b/gcc/testsuite/gcc.target/i386/pr67215-2.c index ebf2919..9fd7469 100644 --- a/gcc/testsuite/gcc.target/i386/pr67215-2.c +++ b/gcc/testsuite/gcc.target/i386/pr67215-2.c @@ -13,8 +13,8 @@ foo (void) arr[i] = bar (128); } -/* { dg-final { scan-assembler "call\[ \t\]*.bar@GOTPCREL" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "call\[ \t\]*.bar@GOT\\(" { target ia32 } } } */ -/* { dg-final { scan-assembler-not "mov(l|q)\[ \t\]*.bar@GOTPCREL" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-not "movl\[ \t\]*.bar@GOT\\(" { target ia32 } } } */ -/* { dg-final { scan-assembler-not "call\[ \t\]*.bar@PLT" } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*bar@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*bar@GOT\\(" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "mov(l|q)\[ \t\]+bar@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "movl\[ \t\]+bar@GOT\\(" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "call\[ \t\]+\\*bar@PLT" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr82142a.c b/gcc/testsuite/gcc.target/i386/pr82142a.c index a40c038..a536150 100644 --- a/gcc/testsuite/gcc.target/i386/pr82142a.c +++ b/gcc/testsuite/gcc.target/i386/pr82142a.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O2 -mno-avx -msse2" } */ +/* { dg-options "-O2 -mno-avx -msse2 -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr82142b.c b/gcc/testsuite/gcc.target/i386/pr82142b.c index b1bf12d..d18b7c4 100644 --- a/gcc/testsuite/gcc.target/i386/pr82142b.c +++ b/gcc/testsuite/gcc.target/i386/pr82142b.c @@ -1,5 +1,5 @@ /* { dg-do compile { target ia32 } } */ -/* { dg-options "-O2 -mno-avx -msse2" } */ +/* { dg-options "-O2 -mno-avx -msse2 -mno-stackrealign -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr89618-2.c b/gcc/testsuite/gcc.target/i386/pr89618-2.c index c414053..11d658f 100644 --- a/gcc/testsuite/gcc.target/i386/pr89618-2.c +++ b/gcc/testsuite/gcc.target/i386/pr89618-2.c @@ -19,5 +19,9 @@ void foo (int n, int *off, double *a) } /* Make sure the cost model selects SSE vectors rather than AVX to avoid - too many scalar ops for the address computes in the loop. */ -/* { dg-final { scan-tree-dump "loop vectorized using 16 byte vectors" "vect" { target { ! ia32 } } } } */ + too many scalar ops for the address computes in the loop. + + Since open-coded scatters are costed wrong, we no longer vectorize after fixing + COND_EXPR costs. See PR119902. */ +/* { dg-final { scan-tree-dump "loop vectorized using 16 byte vectors" "vect" { target { ! ia32 } xfail *-*-* } } } */ +/* { dg-final { scan-tree-dump-not "loop vectorized using 32 byte vectors" "vect" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/recip-vec-divf-fma.c b/gcc/testsuite/gcc.target/i386/recip-vec-divf-fma.c new file mode 100644 index 0000000..ad9e07b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/recip-vec-divf-fma.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -mfma -mavx2" } */ +/* { dg-final { scan-assembler-times {(?n)vfn?m(add|sub)[1-3]*ps} 2 } } */ + +typedef float v4sf __attribute__((vector_size(16))); +/* (a - (rcp(b) * a * b)) * rcp(b) + rcp(b) * a */ + +v4sf +foo (v4sf a, v4sf b) +{ + return a / b; +} diff --git a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp index f56d2f1..9df3f29 100644 --- a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp +++ b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp @@ -35,7 +35,7 @@ dg-init # If the target hardware supports LSX, the default action is "run", otherwise # just "compile". -global dg-do-what-default +set saved-dg-do-what-default ${dg-do-what-default} if {[check_effective_target_loongarch_sx_hw]} then { set dg-do-what-default run } else { @@ -45,6 +45,7 @@ if {[check_effective_target_loongarch_sx_hw]} then { #Main loop. dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lsx/*.\[cS\]]] \ " -mlsx" $DEFAULT_CFLAGS +set dg-do-what-default ${saved-dg-do-what-default} dg-finish @@ -52,7 +53,7 @@ dg-init # If the target hardware supports LASX, the default action is "run", otherwise # just "compile". -global dg-do-what-default +set saved-dg-do-what-default ${dg-do-what-default} if {[check_effective_target_loongarch_asx_hw]} then { set dg-do-what-default run } else { @@ -61,5 +62,6 @@ if {[check_effective_target_loongarch_asx_hw]} then { dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lasx/*.\[cS\]]] \ " -mlasx" $DEFAULT_CFLAGS +set dg-do-what-default ${saved-dg-do-what-default} # All done. dg-finish diff --git a/gcc/testsuite/gcc.target/mips/clear-cache-1.c b/gcc/testsuite/gcc.target/mips/clear-cache-1.c index f1554f5..cd11c66 100644 --- a/gcc/testsuite/gcc.target/mips/clear-cache-1.c +++ b/gcc/testsuite/gcc.target/mips/clear-cache-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-msynci isa_rev>=2" } */ /* { dg-final { scan-assembler "\tsynci\t" } } */ -/* { dg-final { scan-assembler "\tjr.hb\t" } } */ +/* { dg-final { scan-assembler "\tjrc?.hb\t" } } */ /* { dg-final { scan-assembler-not "_flush_cache|mips_sync_icache|_cacheflush" } } */ NOMIPS16 void f() diff --git a/gcc/testsuite/gcc.target/mips/memcpy-2.c b/gcc/testsuite/gcc.target/mips/memcpy-2.c new file mode 100644 index 0000000..df0cd18 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/memcpy-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "isa_rev<=5 -fdump-rtl-expand" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-Os" } { "" } } */ + +__attribute__((nomips16)) +void +f1 (char *p) +{ + __builtin_memcpy (p, "12345", 5); +} + +/* { dg-final { scan-rtl-dump "mem/u.*mem/u" "expand" } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/alloca-2-O0_-mfake-ptx-alloca.c b/gcc/testsuite/gcc.target/nvptx/alloca-2-O0_-mfake-ptx-alloca.c index 4cc4d0c..92562cd 100644 --- a/gcc/testsuite/gcc.target/nvptx/alloca-2-O0_-mfake-ptx-alloca.c +++ b/gcc/testsuite/gcc.target/nvptx/alloca-2-O0_-mfake-ptx-alloca.c @@ -1,4 +1,4 @@ -/* { dg-do link } */ +/* { dg-do run } */ /* { dg-options {-O0 -mno-soft-stack} } */ /* { dg-additional-options -march=sm_30 } */ /* { dg-additional-options -mfake-ptx-alloca } */ @@ -13,6 +13,7 @@ main(void) /* { dg-final { scan-assembler-times {(?n)^\.extern \.func \(\.param\.u64 %value_out\) __GCC_nvptx__PTX_alloca_not_supported \(\.param\.u64 %in_ar0\);$} 1 } } */ -/* { dg-message __GCC_nvptx__PTX_alloca_not_supported {unresolved symbol} { target *-*-* } 0 } */ +/* { dg-bogus __GCC_nvptx__PTX_alloca_not_supported {unresolved symbol} { target *-*-* } 0 } */ -/* { dg-final output-exists-not } */ +/* { dg-output {GCC/nvptx: sorry, unimplemented: dynamic stack allocation not supported[\r\n]+} } + { dg-shouldfail __GCC_nvptx__PTX_alloca_not_supported } */ diff --git a/gcc/testsuite/gcc.target/nvptx/decl.c b/gcc/testsuite/gcc.target/nvptx/decl.c index 190a64d..45dd699 100644 --- a/gcc/testsuite/gcc.target/nvptx/decl.c +++ b/gcc/testsuite/gcc.target/nvptx/decl.c @@ -13,8 +13,8 @@ int Foo () } /* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.visible .global \[^,\r\n\]*glob_export" } } */ -/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.visible .const \[^,\r\n\]*cst_export" } } */ +/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.visible .global \[^,\r\n\]*cst_export" } } */ /* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.global \[^,\r\n\]*glob_local" } } */ -/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.const \[^,\r\n\]*cst_local" } } */ +/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.global \[^,\r\n\]*cst_local" } } */ /* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.extern .global \[^,\r\n\]*glob_import" } } */ -/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.extern .const \[^,\r\n\]*cst_import" } } */ +/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.extern .global \[^,\r\n\]*cst_import" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c b/gcc/testsuite/gcc.target/powerpc/power11-3.c index fa1aedd..56bf881 100644 --- a/gcc/testsuite/gcc.target/powerpc/power11-3.c +++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-ifunc "" } */ /* Check if we can set the power11 target via a target_clones attribute. */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-25.c b/gcc/testsuite/gcc.target/riscv/arch-25.c index 3be4ade..9201883 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-25.c +++ b/gcc/testsuite/gcc.target/riscv/arch-25.c @@ -2,4 +2,4 @@ /* { dg-options "-march=rv64i_zcf -mabi=lp64" } */ int foo() {} /* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64ic_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-1.c b/gcc/testsuite/gcc.target/riscv/attribute-c-1.c new file mode 100644 index 0000000..5627e16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32i_zca -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_c2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-2.c b/gcc/testsuite/gcc.target/riscv/attribute-c-2.c new file mode 100644 index 0000000..4c7d5f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32if_zca -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_zicsr2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-3.c b/gcc/testsuite/gcc.target/riscv/attribute-c-3.c new file mode 100644 index 0000000..7ff68f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32if_zca_zcf -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-4.c b/gcc/testsuite/gcc.target/riscv/attribute-c-4.c new file mode 100644 index 0000000..ef59b65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-4.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32ifd_zca_zcf -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-5.c b/gcc/testsuite/gcc.target/riscv/attribute-c-5.c new file mode 100644 index 0000000..14e9551 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32ifd_zca_zcf_zcd -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-6.c b/gcc/testsuite/gcc.target/riscv/attribute-c-6.c new file mode 100644 index 0000000..30cda55 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-6.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64i_zca -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_c2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-7.c b/gcc/testsuite/gcc.target/riscv/attribute-c-7.c new file mode 100644 index 0000000..b06388b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-7.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64ifd_zca -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_d2p2_zicsr2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-8.c b/gcc/testsuite/gcc.target/riscv/attribute-c-8.c new file mode 100644 index 0000000..fa76050 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-8.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64ifd_zca_zcd -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c index e477414..fc86dbe 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c index 7008eb5..4504158 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c index 89ebaaf..4ffc051 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c index cacbcaa..7ee8de2 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/bext-ext-2.c b/gcc/testsuite/gcc.target/riscv/bext-ext-2.c new file mode 100644 index 0000000..aa170d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/bext-ext-2.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct obstack; +struct bitmap_head_def; +typedef struct bitmap_head_def *bitmap; +struct obstack +{ + long chunk_size; + struct _obstack_chunk *chunk; + char *object_base; + char *next_free; + char *chunk_limit; + long int temp; + int alignment_mask; + + + + struct _obstack_chunk *(*chunkfun) (void *, long); + void (*freefun) (void *, struct _obstack_chunk *); + void *extra_arg; + unsigned use_extra_arg:1; + unsigned maybe_empty_object:1; + + + + unsigned alloc_failed:1; + + +}; + +typedef unsigned long BITMAP_WORD; +typedef struct bitmap_obstack { + struct bitmap_element_def *elements; + struct bitmap_head_def *heads; + struct obstack obstack; +} bitmap_obstack; +typedef struct bitmap_element_def { + struct bitmap_element_def *next; + struct bitmap_element_def *prev; + unsigned int indx; + BITMAP_WORD bits[((128 + (8 + * 8 * 1u) - 1) / (8 + * 8 * 1u))]; +} bitmap_element; +bitmap_element *bitmap_find_bit (bitmap, unsigned int); + + +int +bitmap_bit_p (bitmap head, int bit) +{ + bitmap_element *ptr; + unsigned bit_num; + unsigned word_num; + + ptr = bitmap_find_bit (head, bit); + if (ptr == 0) + return 0; + + bit_num = bit % (8 + * 8 * 1u); + word_num = bit / (8 + * 8 * 1u) % ((128 + (8 + * 8 * 1u) - 1) / (8 + * 8 * 1u)); + + return (ptr->bits[word_num] >> bit_num) & 1; +} + +/* { dg-final { scan-assembler-times "bext\t" 1 } } */ +/* { dg-final { scan-assembler-not "slr\t"} } */ +/* { dg-final { scan-assembler-not "andi\t"} } */ + diff --git a/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c b/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c index e2369fc..326d5dc 100644 --- a/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c +++ b/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c @@ -10,10 +10,10 @@ func (int a, int b); **sum: ** ... ** cm.mvsa01 s1,s2 -** call func +** call func(?:@plt)? ** mv s0,a0 ** cm.mva01s s1,s2 -** call func +** call func(?:@plt)? ** ... */ int diff --git a/gcc/testsuite/gcc.target/riscv/cpymem-64.c b/gcc/testsuite/gcc.target/riscv/cpymem-64.c index 37b8ef0..c91b015 100644 --- a/gcc/testsuite/gcc.target/riscv/cpymem-64.c +++ b/gcc/testsuite/gcc.target/riscv/cpymem-64.c @@ -95,7 +95,7 @@ COPY_ALIGNED_N(11) /* **copy_15: ** ... -** (call|tail)\tmemcpy +** (call|tail)\tmemcpy(?:@plt)? ** ... */ COPY_N(15) @@ -116,7 +116,7 @@ COPY_ALIGNED_N(15) /* **copy_27: ** ... -** (call|tail)\tmemcpy +** (call|tail)\tmemcpy(?:@plt)? ** ... */ COPY_N(27) diff --git a/gcc/testsuite/gcc.target/riscv/fmax-snan.c b/gcc/testsuite/gcc.target/riscv/fmax-snan.c index aabaad5..a1f6149 100644 --- a/gcc/testsuite/gcc.target/riscv/fmax-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fmax-snan.c @@ -10,4 +10,4 @@ fmax (double x, double y) /* { dg-final { scan-assembler-not "\tfmax\\.d\t" } } */ /* { dg-final { scan-assembler-not "\tfge\\.d\t" } } */ -/* { dg-final { scan-assembler "\t(call|tail)\tfmax\t" } } */ +/* { dg-final { scan-assembler "\t(call|tail)\tfmax(?:@plt)?\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c b/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c index f74a817..1daf3e9 100644 --- a/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c @@ -10,4 +10,4 @@ fmaxf (float x, float y) /* { dg-final { scan-assembler-not "\tfmax\\.s\t" } } */ /* { dg-final { scan-assembler-not "\tfge\\.s\t" } } */ -/* { dg-final { scan-assembler "\t(call|tail)\tfmaxf\t" } } */ +/* { dg-final { scan-assembler "\t(call|tail)\tfmaxf(?:@plt)?\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fmin-snan.c b/gcc/testsuite/gcc.target/riscv/fmin-snan.c index 3b2e8c3..cc0e16c 100644 --- a/gcc/testsuite/gcc.target/riscv/fmin-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fmin-snan.c @@ -10,4 +10,4 @@ fmin (double x, double y) /* { dg-final { scan-assembler-not "\tfmin\\.d\t" } } */ /* { dg-final { scan-assembler-not "\tfle\\.d\t" } } */ -/* { dg-final { scan-assembler "\t(call|tail)\tfmin\t" } } */ +/* { dg-final { scan-assembler "\t(call|tail)\tfmin(?:@plt)?\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fminf-snan.c b/gcc/testsuite/gcc.target/riscv/fminf-snan.c index d28822e..598644e 100644 --- a/gcc/testsuite/gcc.target/riscv/fminf-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fminf-snan.c @@ -10,4 +10,4 @@ fminf (float x, float y) /* { dg-final { scan-assembler-not "\tfmin\\.s\t" } } */ /* { dg-final { scan-assembler-not "\tfle\\.s\t" } } */ -/* { dg-final { scan-assembler "\t(call|tail)\tfminf\t" } } */ +/* { dg-final { scan-assembler "\t(call|tail)\tfminf(?:@plt)?\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv32.c b/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv32.c new file mode 100644 index 0000000..4f48cff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv32.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32g_zicfiss -fcf-protection=return -mabi=ilp32d " } */ + +void foo() {} + +/* { dg-final { scan-assembler-times ".p2align\t2" 3 } } */ +/* { dg-final { scan-assembler-not ".p2align\t3" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv64.c b/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv64.c new file mode 100644 index 0000000..1bfd127 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv64.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g_zicfiss -fcf-protection=return -mabi=lp64d " } */ + +void foo() {} + +/* { dg-final { scan-assembler-times ".p2align\t3" 3 } } */ +/* { dg-final { scan-assembler-not ".p2align\t2" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c b/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c new file mode 100644 index 0000000..1ee7f6c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -mcmodel=large" } */ + +int foo(int x, int y) +{ + switch(x){ + case 0: + return 123 + y; + case 1: + return 456 + y; + case 2: + return 789 - y; + case 3: + return 12 * y; + case 4: + return 13 % y; + case 5: + return 11 *y; + } + return 0; +} + + +/* { dg-final { scan-assembler-not "\.section \.rodata" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/large-model.c b/gcc/testsuite/gcc.target/riscv/large-model.c index 244d14e..d5ef7a0 100644 --- a/gcc/testsuite/gcc.target/riscv/large-model.c +++ b/gcc/testsuite/gcc.target/riscv/large-model.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64 -fno-section-anchors -mcmodel=large" } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -fno-section-anchors -mcmodel=large -fno-pie" } */ /* { dg-skip-if "" { *-*-* } {"-O0"} } */ int a, b; int foo1() diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c index 2903c88..c2a374f 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c @@ -1,6 +1,6 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { rv64 } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ -/* { dg-options "-mcpu=xiangshan-nanhu" { target { rv64 } } } */ +/* { dg-options "-mcpu=xiangshan-nanhu" } */ /* XiangShan Nanhu => rv64imafdc_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd _zkne_zknh_zksed_zksh_svinval_zicbom_zicboz */ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c new file mode 100644 index 0000000..cb28baf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c908" { target { rv64 } } } */ +/* XuanTie C908 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_ +zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_sstc_svinval_svnapot_svpbmt_xtheadba_ +xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_ +xtheadmemidx_xtheadmempair_xtheadsync */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_sstc) \ + && defined(__riscv_svinval) \ + && defined(__riscv_svnapot) \ + && defined(__riscv_svpbmt) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c new file mode 100644 index 0000000..1b1ee18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c908v" { target { rv64 } } } */ +/* XuanTie C908v => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_ +zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_sstc_svinval_svnapot_svpbmt_xtheadba_ +xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_ +xtheadmemidx_xtheadmempair_xtheadsync_xtheadvdot */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_v) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_sstc) \ + && defined(__riscv_svinval) \ + && defined(__riscv_svnapot) \ + && defined(__riscv_svpbmt) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync) \ + && defined (__riscv__xtheadvdot)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c new file mode 100644 index 0000000..1e27665 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c910" { target { rv64 } } } */ +/* XuanTie C910 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_xtheadba_ +xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_ +xtheadmemidx_xtheadmempair_xtheadsync */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfh) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c new file mode 100644 index 0000000..6a54f09 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c910v2" { target { rv64 } } } */ +/* XuanTie C910v2 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_ +zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_ +zbb_zbc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_ +xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicond) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei ) \ + && defined(__riscv_zihintntl) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zawrs) \ + && defined(__riscv_zfa) \ + && defined(__riscv_zfbfmin) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zca) \ + && defined(__riscv_zcb) \ + && defined(__riscv_zcd) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c new file mode 100644 index 0000000..6bcd687 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c920" { target { rv64 } } } */ +/* XuanTie c920 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync_xtheadvector */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfh) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync) \ + && defined(__riscv_xtheadvector)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c new file mode 100644 index 0000000..36a6267 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c920v2" { target { rv64 } } } */ +/* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync_xtheadvdot */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_v) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicond) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei ) \ + && defined(__riscv_zihintntl) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zawrs) \ + && defined(__riscv_zfa) \ + && defined(__riscv_zfbfmin) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zca) \ + && defined(__riscv_zcb) \ + && defined(__riscv_zcd) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_zvfbfmin) \ + && defined(__riscv_zvfbfwma) \ + && defined(__riscv_zvfh) \ + && defined(__riscv_sscofpmf) \ + && defined(__riscv_sstc) \ + && defined(__riscv_svinval) \ + && defined(__riscv_svnapot) \ + && defined(__riscv_svpbmt) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadsync) \ + && defined(__riscv_xtheadvdot)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/pr108016.c b/gcc/testsuite/gcc.target/riscv/pr108016.c new file mode 100644 index 0000000..b60df42 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr108016.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +unsigned int addu (unsigned int a, unsigned int b) +{ + unsigned int out; + unsigned int overflow = __builtin_add_overflow (a, b, &out); + return overflow & out; +} + +int addi (int a, int b) +{ + int out; + int overflow = __builtin_add_overflow (a, b, &out); + return overflow & out; +} + +unsigned int subu (unsigned int a, unsigned int b) +{ + unsigned int out; + unsigned int overflow = __builtin_sub_overflow (a, b, &out); + return overflow & out; +} + +int subi (int a, int b) +{ + int out; + int overflow = __builtin_sub_overflow (a, b, &out); + return overflow & out; +} + +/* { dg-final { scan-assembler-not "sext\.w\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr118410-1.c b/gcc/testsuite/gcc.target/riscv/pr118410-1.c new file mode 100644 index 0000000..4a8b847 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr118410-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gcb -mabi=lp64d" { target { rv64} } } */ +/* { dg-options "-march=rv32gcb -mabi=ilp32" { target { rv32} } } */ + +long orlow(long x) { return x | ((1L << 24) - 1); } + +/* { dg-final { scan-assembler-times "orn\t" 1 } } */ +/* { dg-final { scan-assembler-not "addi\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr118410-2.c b/gcc/testsuite/gcc.target/riscv/pr118410-2.c new file mode 100644 index 0000000..b63a1d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr118410-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gcb -mabi=lp64d" { target { rv64} } } */ +/* { dg-options "-march=rv32gcb -mabi=ilp32" { target { rv32} } } */ + +long xorlow(long x) { return x ^ ((1L << 24) - 1); } + +/* { dg-final { scan-assembler-times "xnor\t" 1 } } */ +/* { dg-final { scan-assembler-not "addi\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/predef-1.c b/gcc/testsuite/gcc.target/riscv/predef-1.c index 250812a..551346e 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-1.c +++ b/gcc/testsuite/gcc.target/riscv/predef-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32i -mabi=ilp32 -mcmodel=medlow" } */ +/* { dg-options "-march=rv32i -mabi=ilp32 -mcmodel=medlow -fno-pie" } */ int main () { #if !defined(__riscv) diff --git a/gcc/testsuite/gcc.target/riscv/predef-4.c b/gcc/testsuite/gcc.target/riscv/predef-4.c index ba8b5c7..7b3c054 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-4.c +++ b/gcc/testsuite/gcc.target/riscv/predef-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64ia -mabi=lp64 -mcmodel=medlow" } */ +/* { dg-options "-march=rv64ia -mabi=lp64 -mcmodel=medlow -fno-pie" } */ int main () { #if !defined(__riscv) diff --git a/gcc/testsuite/gcc.target/riscv/predef-7.c b/gcc/testsuite/gcc.target/riscv/predef-7.c index 833e2be..36caf8e 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-7.c +++ b/gcc/testsuite/gcc.target/riscv/predef-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32em -mabi=ilp32e -mno-div -mcmodel=medlow" } */ +/* { dg-options "-march=rv32em -mabi=ilp32e -mno-div -mcmodel=medlow -fno-pie" } */ int main () { #if !defined(__riscv) diff --git a/gcc/testsuite/gcc.target/riscv/predef-9.c b/gcc/testsuite/gcc.target/riscv/predef-9.c index b173d5d..fa072ad 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-9.c +++ b/gcc/testsuite/gcc.target/riscv/predef-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64em -mabi=lp64e -mno-div -mcmodel=medlow" } */ +/* { dg-options "-march=rv64em -mabi=lp64e -mno-div -mcmodel=medlow -fno-pie" } */ /* { dg-warning "LP64E ABI is marked for deprecation in GCC" "" { target *-*-* } 0 } */ /* { dg-note "if you need LP64E please notify the GCC project via PR116152" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c b/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c index 0af4d71..fd845f5 100644 --- a/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c @@ -244,9 +244,9 @@ test_f0 () /* **foo: ** cm.push {ra}, -16 -** call f1 +** call f1(?:@plt)? ** cm.pop {ra}, 16 -** tail f2 +** tail f2(?:@plt)? */ void foo (void) @@ -258,7 +258,7 @@ foo (void) /* **test_popretz: ** cm.push {ra}, -16 -** call f1 +** call f1(?:@plt)? ** li a0,0 ** cm.popret {ra}, 16 */ diff --git a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c b/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c index 723889f4..d90f4f4 100644 --- a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c @@ -244,9 +244,9 @@ test_f0 () /* **foo: ** cm.push {ra}, -16 -** call f1 +** call f1(?:@plt)? ** cm.pop {ra}, 16 -** tail f2 +** tail f2(?:@plt)? */ void foo (void) @@ -258,7 +258,7 @@ foo (void) /* **test_popretz: ** cm.push {ra}, -16 -** call f1 +** call f1(?:@plt)? ** li a0,0 ** cm.popret {ra}, 16 */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f16.c deleted file mode 100644 index e4ff310..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f16.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (float, _Float16) - -/* { dg-final { scan-assembler-times {\tvfwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f32.c deleted file mode 100644 index 7d2b448..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f32.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (double, float) - -/* { dg-final { scan-assembler-times {\tvfwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i16.c deleted file mode 100644 index dc7e1da..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i16.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (int32_t, int16_t) - -/* { dg-final { scan-assembler-times {\tvwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i32.c deleted file mode 100644 index de1072f..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i32.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (int64_t, int32_t) - -/* { dg-final { scan-assembler-times {\tvwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i8.c deleted file mode 100644 index 8de5ef4..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i8.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (int16_t, int8_t) - -/* { dg-final { scan-assembler-times {\tvwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u16.c deleted file mode 100644 index a4aafd2..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u16.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (uint32_t, uint16_t) - -/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u32.c deleted file mode 100644 index 0deeaa0..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u32.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (uint64_t, uint32_t) - -/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u8.c deleted file mode 100644 index a6afcd0..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u8.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (uint16_t, uint8_t) - -/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c new file mode 100644 index 0000000..d02a8e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ + +#include <stdint-gcc.h> + +#define TEST_TYPE(TYPE1, TYPE2) \ + __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 ( \ + TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3, \ + TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b, \ + TYPE2 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; i++) \ + { \ + dst[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b[i] : dst[i]; \ + dst2[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) b[i] : dst2[i]; \ + dst3[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) a[i] : dst3[i]; \ + dst4[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b2[i] : dst4[i]; \ + } \ + } + +#define TEST_ALL() \ + TEST_TYPE (int16_t, int8_t) \ + TEST_TYPE (uint16_t, uint8_t) \ + TEST_TYPE (int32_t, int16_t) \ + TEST_TYPE (uint32_t, uint16_t) \ + TEST_TYPE (int64_t, int32_t) \ + TEST_TYPE (uint64_t, uint32_t) \ + TEST_TYPE (float, _Float16) \ + TEST_TYPE (double, float) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvwmul\.vv} 12 } } */ +/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 12 } } */ +/* { dg-final { scan-assembler-times {\tvfwmul\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.h deleted file mode 100644 index 974846f..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef COND_WIDEN_COMPLICATE_3_H -#define COND_WIDEN_COMPLICATE_3_H - -#include <stdint-gcc.h> - -#define TEST_TYPE(TYPE1, TYPE2) \ - __attribute__ ((noipa)) void vwadd_##TYPE1##_##TYPE2 ( \ - TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3, \ - TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b, \ - TYPE2 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n) \ - { \ - for (int i = 0; i < n; i++) \ - { \ - dst[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b[i] : dst[i]; \ - dst2[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) b[i] : dst2[i]; \ - dst3[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) a[i] : dst3[i]; \ - dst4[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b2[i] : dst4[i]; \ - } \ - } - -#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c index 493dab0..0267078 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c @@ -18,6 +18,5 @@ int pixel_sad_n(unsigned char *pix1, unsigned char *pix2, int n) return sum; } -/* { dg-final { scan-assembler {vrsub\.v} } } */ /* { dg-final { scan-assembler {vmax\.v} } } */ -/* { dg-final { scan-assembler {vwsubu\.v} } } */ +/* { dg-final { scan-assembler-times {vwsubu\.v} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c index 638e90f..69a94d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d -mrvv-vector-bits=zvl" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c index 380d0c1..5e0f136 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d -mrvv-vector-bits=zvl" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c index 9ed72a6..a3c0a6d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d -msave-restore" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c index b6b708f..b1cf6aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c index 13e3328..8838f0d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c index 39c8c00..77f1c7c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d -msave-restore" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar1 (vint8m1_t a); void bar2 (); @@ -51,7 +51,7 @@ foo1 (vint8m1_t a) ** vs1r\.v\tv30,0\(sp\) ** sub\tsp,sp,t0 ** vs1r\.v\tv31,0\(sp\) -** call\tbar2 +** call\tbar2(?:@plt)? ** csrr\tt0,vlenb ** vl1re64\.v\tv31,0\(sp\) ** add\tsp,sp,t0 @@ -96,8 +96,8 @@ foo2 (vint8m1_t a) ** foo3: ** call\tt0,__riscv_save_0 ** vl1re8\.v\tv8,0\(a0\) -** call\tbar1 -** call\tbar2 +** call\tbar1(?:@plt)? +** call\tbar2(?:@plt)? ** tail\t__riscv_restore_0 */ void diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c index 5f8f96f..37127a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar1 (vint8m1_t a); void bar2 (); @@ -10,7 +10,7 @@ void bar2 (); /* ** foo1: ** cm.push\t{ra},\s*-16 -** call\tbar1 +** call\tbar1(?:@plt)? ** cm.popret\t{ra},\s*16 */ void @@ -53,7 +53,7 @@ foo1 (vint8m1_t a) ** vs1r\.v\tv30,0\(sp\) ** sub\tsp,sp,t0 ** vs1r\.v\tv31,0\(sp\) -** call\tbar2 +** call\tbar2(?:@plt)? ** csrr\tt0,vlenb ** vl1re64\.v\tv31,0\(sp\) ** add\tsp,sp,t0 @@ -97,7 +97,7 @@ foo2 (vint8m1_t a) ** foo3: ** cm.push\t{ra},\s*-16 ** vl1re8\.v\tv8,0\(a0\) -** call\tbar1 +** call\tbar1(?:@plt)? ** cm.popret\t{ra},\s*16 */ void diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c index a9f3855..a8daeeb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar1 (vint8m1_t a); void bar2 (); @@ -11,7 +11,7 @@ void bar2 (); ** foo1: ** addi\tsp,sp,-16 ** sd\tra,8\(sp\) -** call\tbar1 +** call\tbar1(?:@plt)? ** ld\tra,8\(sp\) ** addi\tsp,sp,16 ** jr\tra @@ -57,7 +57,7 @@ foo1 (vint8m1_t a) ** vs1r\.v\tv30,0\(sp\) ** sub\tsp,sp,t0 ** vs1r\.v\tv31,0\(sp\) -** call\tbar2 +** call\tbar2(?:@plt)? ** csrr\tt0,vlenb ** vl1re64\.v\tv31,0\(sp\) ** add\tsp,sp,t0 @@ -105,7 +105,7 @@ foo2 (vint8m1_t a) ** addi\tsp,sp,-16 ** sd\tra,8\(sp\) ** vl1re8\.v\tv8,0\(a0\) -** call\tbar1 +** call\tbar1(?:@plt)? ** ld\tra,8\(sp\) ** addi\tsp,sp,16 ** jr\tra diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c index fe3a1ef..f8143b9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c @@ -4,7 +4,7 @@ /* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-options " -march=rv64gcv_zvfh -mabi=lp64d -O2" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" int8_t a[1]; uint16_t b[1]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c index 60fdfc4..05628d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c @@ -4,7 +4,7 @@ /* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-options " -march=rv64gcv_zvfh -mabi=lp64d -O2 --param=vsetvl-strategy=optim -fno-schedule-insns -fno-schedule-insns2 -fno-schedule-fusion " } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void __attribute__ ((noipa)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c index 28766ce..3180f71 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vint64m1_t f1 (vint64m1_t vd, vint64m1_t vs2, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c index 975f755..31b68c4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d -O0" { target { rv64 } } } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O0" { target { rv32 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vint64m1_t f1 (vint64m1_t vd, vint64m1_t vs2, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c index 8cfe965..f7c9ad1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vfloat16m1_t f0 (vfloat16m1_t vs2, vfloat16m1_t vs1, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c index 9edd6cb..3534720 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c @@ -21,7 +21,7 @@ f1 (void *a, void *b) /* Tiny __builtin_memcmp should use libc. ** f2: ** li\s+a\d,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f2 (void *a, void *b) @@ -79,7 +79,7 @@ f5 (void *a, void *b) /* Don't inline if the length is too large for one operation. ** f6: ** li\s+a2,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f6 (void *a, void *b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c index 82aa307..c1c1aae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c @@ -8,7 +8,7 @@ /* Tiny __builtin_memcmp should use libc. ** f1: ** li\s+a\d,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f1 (void *a, void *b) @@ -36,7 +36,7 @@ f2 (void *a, void *b) /* Don't inline if the length is too large for one operation. ** f3: ** li\s+a2,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f3 (void *a, void *b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c index e2dd6a1..ad87038 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c @@ -8,7 +8,7 @@ /* Tiny __builtin_memcmp should use libc. ** f1: ** li\s+a\d,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f1 (void *a, void *b) @@ -53,7 +53,7 @@ f3 (void *a, void *b) /* Don't inline if the length is too large for one operation. ** f4: ** li\s+a2,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f4 (void *a, void *b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c index 654c800..5e35204 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2 -fno-pie" } */ /* { dg-add-options riscv_v } */ /* { dg-final { check-function-bodies "**" "" } } */ @@ -109,4 +109,4 @@ void f3 () memcpy (&a_a, &a_b, sizeof a_a); } -/* { dg-final { scan-assembler-not {\m(tail|call)\s+memcpy\M} } } */ +/* { dg-final { scan-assembler-not {\m(tail|call)\s+memcpy(?:@plt)?\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c index 03e633b..44bf3d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c @@ -52,7 +52,7 @@ f3 (char *a, char const *b) /* Don't vectorise if the move is too large for one operation ** f4: ** li\s+a2,\d+ -** tail\s+memmove +** tail\s+memmove(?:@plt)? */ char * f4 (char *a, char const *b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110943.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110943.c index 8a6c00f..a08ac6e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110943.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110943.c @@ -2,7 +2,7 @@ /* { dg-options "-O3 -march=rv64gcv -mabi=lp64d" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" /* ** foo9: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c index 3e43c94..a0ed793 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-O3 -ansi -pedantic-errors -std=gnu99" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" size_t __attribute__ ((noinline)) sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c index 9bfa39c..4f375e5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c @@ -93,9 +93,9 @@ test_5 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count) /* ** test_6: ** ... -** call\s+__extendhfsf2 +** call\s+__extendhfsf2(?:@plt)? ** ... -** call\s+__truncsfhf2 +** call\s+__truncsfhf2(?:@plt)? ** ... */ void diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114639-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114639-1.c index 3ad91db..c5b35c8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114639-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114639-1.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" extern size_t get_vl (); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c index d552eb5..e9e41f7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target riscv_v_ok } */ /* { dg-add-options riscv_v } */ -/* { dg-additional-options "-std=gnu99" } */ +/* { dg-additional-options "-std=gnu99 -Wno-pedantic" } */ #include "pr115068.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c index af2cba6..ce9a389 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c @@ -1,9 +1,9 @@ /* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options riscv_v } */ -/* { dg-additional-options "-std=gnu99" } */ +/* { dg-additional-options "-std=gnu99 -Wno-pedantic" } */ #include <stdint.h> -#include <riscv_vector.h> +#include "riscv_vector.h" vfloat64m8_t test_vfwadd_wf_f64m8_m (vbool8_t vm, vfloat64m8_t vs2, float rs1, size_t vl) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c index dabb8ae..7b6eefe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O1" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" _Float16 a[10]; void func(){ int placeholder0 = 10; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117544.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117544.c index af3532a..81e0ec3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117544.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117544.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar() __attribute__((riscv_vector_cc)); vint32m1_t foo(vint32m1_t a, vint32m1_t b) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c index 81e3a6e..4904c92 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { rv64 } } } */ /* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" _Float16 a (uint64_t); int8_t b () { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c index adb54d6..d62751e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vfloat32m2_t foo (vfloat16m1_t a, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c index a22d366..490445f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c @@ -94,7 +94,7 @@ f6 (void *a, int const b) /* Don't vectorise if the move is too large for one operation. ** f7: ** li\s+a2,\d+ -** tail\s+memset +** tail\s+memset(?:@plt)? */ void * f7 (void *a, int const b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c index a108868..876929e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c @@ -44,7 +44,7 @@ f2 (void *a, int const b) /* Don't vectorise if the move is too large for requested lmul. ** f3: ** li\s+a2,\d+ -** tail\s+memset +** tail\s+memset(?:@plt)? */ void * f3 (void *a, int const b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c index 460a8f2..a185916 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c @@ -62,7 +62,7 @@ f3 (void *a, int const b) /* Don't vectorise if the move is too large for requested lmul. ** f4: ** li\s+a2,\d+ -** tail\s+memset +** tail\s+memset(?:@plt)? */ void * f4 (void *a, int const b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c index 7e5758b..375d316 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c @@ -18,7 +18,7 @@ void f (char*); ** ... ** addi\ta0,sp,15 ** andi\ta0,a0,-16 -** call\tf +** call\tf(?:@plt)? ** ... ** lw\tra,12\(sp\) ** lw\ts0,8\(sp\) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c index 4253729..6bb7e1c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) { return __riscv_vlmul_ext_v_i16mf4_i16m8(op1); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c index 606854b..a278709 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=rv64gcv -mabi=lp64d" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vuint64m1_t test_vssubu_vx_u64m1(vuint64m1_t op1) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c index 78abd09..2f8c146 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=rv32gcv -mabi=ilp32d" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vuint64m1_t test_vssubu_vx_u64m1(vuint64m1_t op1) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c index 6e027a5..43be202 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c @@ -1,9 +1,9 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ +/* { dg-do compile { target { { ! riscv_abi_e } && rv64 } } } */ /* { dg-add-options riscv_v } */ -/* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns -fno-schedule-insns2 -Wno-pedantic" } */ #include <stdint.h> -#include <riscv_vector.h> +#include "riscv_vector.h" /* ** vwadd_wx_i64m8_m: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c index bf95e1c..64666d3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c @@ -21,6 +21,12 @@ void f2 (void * restrict in, void * restrict out, int l, int n, int m) } } +/* The second check is XFAILed because we currently don't lift + vsetvls into non-transparent (in LCM parlance) blocks. + See PR119547. + In this test it is still possible because the conflicting + register only ever feeds vsetvls. */ + /* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } xfail { *-*-* } } } } */ /* { dg-final { scan-assembler-times {addi\s+[a-x0-9]+,\s*[a-x0-9]+,\s*44} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c index 871cf65..f594217 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void f (vint32m1_t *in, vint64m2_t *out, vbool32_t *m, int b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c index b76760b..48f200f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c @@ -2,7 +2,7 @@ /* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w -std=gnu17" } */ /* { dg-skip-if "" { *-*-* } { "-flto" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" static inline __attribute__(()) int vaddq_f32(); static inline __attribute__(()) int vload_tillz_f32(int nlane) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c index ddf53ca..0dbf34a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c @@ -43,6 +43,6 @@ void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond) } } -/* { dg-final { scan-assembler-times {vsetvli} 15 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 14 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c index 7096159e..3867681 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" size_t foo () { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c index c155f56..3acbc73 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O2 -fdump-rtl-vsetvl-details" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" uint64_t a[2], b[2]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c index 04a8ff2..2b2fe27 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -fno-schedule-insns -fdump-rtl-vsetvl-details" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vuint16m1_t foo (vuint16m1_t a, vuint16m1_t b, size_t avl) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c index dfaf82c..ad27c38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32d -O2 -save-temps" { target { rv32 } } } */ /* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O2 -save-temps" { target { rv64 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void foo (float *a, int b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c index a7cd8c5..c8056a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gc_zfh_xtheadvector -mabi=lp64d -O2 -save-temps" { target { rv64 } } } */ #include <math.h> -#include <riscv_vector.h> +#include "riscv_vector.h" static vfloat32m8_t atan2_ps(vfloat32m8_t a, vfloat32m8_t b, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c index aebb0e3..b3c3428 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { rv64 } } } */ /* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O2" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vfloat16m4_t foo (float *ptr, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c new file mode 100644 index 0000000..42fa43e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +struct a +{ + int b[]; +} c (vint32m4_t), d; + +char e; +char *f; + +void g () +{ + int h; + vint32m4_t i; + vint8m1_t j = __riscv_vlse8_v_i8m1 (&e, d.b[3], h); + vint16m2_t k = __riscv_vwadd_vx_i16m2 (j, 0, h); + i = __riscv_vwmacc_vx_i32m4 (i, f[0], k, h); + c (i); +} + +/* { dg-final { scan-assembler-not {th\.vsext\.vf2} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c new file mode 100644 index 0000000..d622b72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +struct a +{ + int b[]; +} c (vuint32m4_t), d; + +char e; +char *f; + +void g () +{ + int h; + vuint32m4_t i; + vuint8m1_t j = __riscv_vlse8_v_u8m1 (&e, d.b[3], h); + vuint16m2_t k = __riscv_vwaddu_vx_u16m2 (j, 0, h); + i = __riscv_vwmaccu_vx_u32m4 (i, f[0], k, h); + c (i); +} + +/* { dg-final { scan-assembler-not {th\.vzext\.vf2} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c index c0d643d..929de16 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c @@ -15,7 +15,7 @@ ** li\s+[atx][0-9]+,\s*-1 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 ** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c index 470e6b7..a540198 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c @@ -15,7 +15,7 @@ ** li\s+[atx][0-9]+,\s*-1 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 ** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c index bb94775..e3fe6c7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c @@ -15,7 +15,7 @@ ** li\s+[atx][0-9]+,\s*-1 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 ** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c index cc598eb..f42ffea 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c @@ -15,7 +15,7 @@ ** li\s+[atx][0-9]+,\s*-1 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 ** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c new file mode 100644 index 0000000..303f3cb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long long sub (unsigned long long a, unsigned long long b) +{ + b = (b << 50) >> 49; + unsigned int x = a + b; + return x; +} + +/* { dg-final { scan-assembler-not {\msh1add} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c new file mode 100644 index 0000000..883cce2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c @@ -0,0 +1,21 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-options "-march=rv64gc_zba -mabi=lp64d -O2" } */ + +struct { + unsigned a : 14; + unsigned b : 3; +} c; + +unsigned long long d; +void e (unsigned long long *f, long p2) { *f = p2; } +signed g; +long i; + +int main () { + c.b = 4; + i = -(-c.a - (3023282U + c.a + g)); + e (&d, i); + if (d != 3023282) + __builtin_abort (); + __builtin_exit (0); +} diff --git a/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c b/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c index f7d8f44..be304e7 100644 --- a/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c +++ b/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c @@ -10,7 +10,7 @@ bar (); **fool_rv32e: ** cm.push {ra}, -32 ** ... -** call bar +** call bar(?:@plt)? ** ... ** lw a[0-5],32\(sp\) ** ... diff --git a/gcc/testsuite/gcc.target/s390/pr119873-1.c b/gcc/testsuite/gcc.target/s390/pr119873-1.c new file mode 100644 index 0000000..7a9a988 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr119873-1.c @@ -0,0 +1,11 @@ +/* PR target/119873 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +const char *foo (void *, void *, void *, void *, unsigned long, unsigned long); + +const char * +bar (void *a, void *b, void *c, void *d, unsigned long e, unsigned long f) +{ + [[gnu::musttail]] return foo (a, b, c, d, e, f); +} diff --git a/gcc/testsuite/gcc.target/s390/pr119873-2.c b/gcc/testsuite/gcc.target/s390/pr119873-2.c new file mode 100644 index 0000000..f275253 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr119873-2.c @@ -0,0 +1,17 @@ +/* PR target/119873 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +const char *foo (void *, void *, void *, void *, unsigned long, unsigned long); + +const char * +bar (void *a, void *b, void *c, void *d, unsigned long e, unsigned long f) +{ + [[gnu::musttail]] return foo (a, b, c, d, e + 1, f); /* { dg-error "cannot tail-call: target is not able to optimize the call into a sibling call" } */ +} + +const char * +baz (void *a, void *b, void *c, void *d, unsigned long e, unsigned long f) +{ + [[gnu::musttail]] return foo (a, b, c, d, f, e); /* { dg-error "cannot tail-call: target is not able to optimize the call into a sibling call" } */ +} diff --git a/gcc/testsuite/gcc.target/s390/pr119873-3.c b/gcc/testsuite/gcc.target/s390/pr119873-3.c new file mode 100644 index 0000000..048fcaa --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr119873-3.c @@ -0,0 +1,27 @@ +/* PR target/119873 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +extern int foo (int, int, int, long long, int); + +int +bar (int u, int v, int w, long long x, int y) +{ + [[gnu::musttail]] return foo (u, v, w, x, y); +} + +extern int baz (int, int, int, int, int); + +int +qux (int u, int v, int w, int x, int y) +{ + [[gnu::musttail]] return baz (u, v, w, x, y); +} + +extern int corge (int, int, int, int, unsigned short); + +int +garply (int u, int v, int w, int x, unsigned short y) +{ + [[gnu::musttail]] return corge (u, v, w, x, y); +} diff --git a/gcc/testsuite/gcc.target/s390/pr119873-4.c b/gcc/testsuite/gcc.target/s390/pr119873-4.c new file mode 100644 index 0000000..384170c --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr119873-4.c @@ -0,0 +1,27 @@ +/* PR target/119873 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +extern int foo (int, int, int, long long, int); + +int +bar (int u, int v, int w, long long x, int y) +{ + [[gnu::musttail]] return foo (u, v, w, x + 1, y - 1); /* { dg-error "cannot tail-call: target is not able to optimize the call into a sibling call" } */ +} + +extern int baz (int, int, int, int, int); + +int +qux (int u, int v, int w, int x, int y) +{ + [[gnu::musttail]] return baz (u, v, w, x, y + 1); /* { dg-error "cannot tail-call: target is not able to optimize the call into a sibling call" } */ +} + +extern int corge (int, int, int, int, unsigned short); + +int +garply (int u, int v, int w, int x, unsigned short y) +{ + [[gnu::musttail]] return corge (u, v, w, x, y + 1); /* { dg-error "cannot tail-call: target is not able to optimize the call into a sibling call" } */ +} diff --git a/gcc/testsuite/gcc.target/s390/pr119873-5.c b/gcc/testsuite/gcc.target/s390/pr119873-5.c new file mode 100644 index 0000000..b5a7950 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr119873-5.c @@ -0,0 +1,11 @@ +/* PR target/119873 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -m31 -mzarch" } */ + +extern void foo (int x, int y, int z, long long w, int v); + +void +bar (int x, int y, int z, long long w, int v) +{ + [[gnu::musttail]] return foo (x, y, z, w, v); +} diff --git a/gcc/testsuite/gcc.target/sh/pr111814.c b/gcc/testsuite/gcc.target/sh/pr111814.c new file mode 100644 index 0000000..a88e5d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr111814.c @@ -0,0 +1,7 @@ +/* Verify that __builtin_nan("") produces a constant matches + architecture specification. */ +/* { dg-do compile } */ + +double d = __builtin_nan (""); + +/* { dg-final { scan-assembler "\t.long\t-1\n\t.long\t2146959359\n" } } */ |