diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
1871 files changed, 41165 insertions, 10472 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr-2.c b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-2.c index cca8892..5527297 100644 --- a/gcc/testsuite/gcc.target/aarch64/acle/rwsr-2.c +++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-2.c @@ -9,14 +9,14 @@ void test_leading_zeros () { - __uint64_t b = __arm_rsr64 ("S1_2_C03_C04_5"); /* { dg-error "invalid system register name 's1_2_c03_c04_5'" } */ + uint64_t b = __arm_rsr64 ("S1_2_C03_C04_5"); /* { dg-error "invalid system register name 's1_2_c03_c04_5'" } */ __arm_wsr64 ("S1_2_C03_C04_5", b); /* { dg-error "invalid system register name 's1_2_c03_c04_5'" } */ } void test_bounds () { - __uint64_t b; + uint64_t b; b = __arm_rsr64 ("s4_2_c3_c4_5"); /* { dg-error "invalid system register name 's4_2_c3_c4_5'" } */ b = __arm_rsr64 ("s1_8_c3_c4_5"); /* { dg-error "invalid system register name 's1_8_c3_c4_5'" } */ b = __arm_rsr64 ("s1_2_c16_c4_5"); /* { dg-error "invalid system register name 's1_2_c16_c4_5'" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c index 6feb0be..f63eb43 100644 --- a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c +++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c @@ -171,6 +171,6 @@ set_wsrf64 (double a) */ void set_custom () { - __uint64_t b = __arm_rsr64 ("S1_2_C3_C4_5"); + uint64_t b = __arm_rsr64 ("S1_2_C3_C4_5"); __arm_wsr64 ("S1_2_C3_C4_5", b); } diff --git a/gcc/testsuite/gcc.target/aarch64/acle/uhadd_1.c b/gcc/testsuite/gcc.target/aarch64/acle/uhadd_1.c new file mode 100644 index 0000000..f1748a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/uhadd_1.c @@ -0,0 +1,34 @@ +/* Test if SIMD fused unsigned halving adds are generated */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_neon.h> + +#define FUSED_SIMD_UHADD(vectype, q, ts, mask) \ + vectype simd_uhadd ## q ## _ ## ts ## _1 (vectype a) \ + { \ + vectype v1 = vand ## q ## _ ## ts (a, vdup ## q ## _n_ ## ts (mask)); \ + vectype v2 = vdup ## q ## _n_ ## ts (mask); \ + return vshr ## q ## _n_ ## ts (vadd ## q ## _ ## ts (v1, v2), 1); \ + } \ + \ + vectype simd_uhadd ## q ## _ ## ts ## _2 (vectype a, vectype b) \ + { \ + vectype v1 = vand ## q ## _ ## ts (a, vdup ## q ## _n_ ## ts (mask)); \ + vectype v2 = vand ## q ## _ ## ts (b, vdup ## q ## _n_ ## ts (mask)); \ + return vshr ## q ## _n_ ## ts (vadd ## q ## _ ## ts (v1, v2), 1); \ + } + +FUSED_SIMD_UHADD (uint8x8_t, , u8, 0x7f) +FUSED_SIMD_UHADD (uint8x16_t, q, u8, 0x7f) +FUSED_SIMD_UHADD (uint16x4_t, , u16, 0x7fff) +FUSED_SIMD_UHADD (uint16x8_t, q, u16, 0x7fff) +FUSED_SIMD_UHADD (uint32x2_t, , u32, 0x7fffffff) +FUSED_SIMD_UHADD (uint32x4_t, q, u32, 0x7fffffff) + +/* { dg-final { scan-assembler-times {\tuhadd\tv[0-9]+\.8b,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuhadd\tv[0-9]+\.16b,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuhadd\tv[0-9]+\.4h,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuhadd\tv[0-9]+\.8h,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuhadd\tv[0-9]+\.2s,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuhadd\tv[0-9]+\.4s,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/and-be.c b/gcc/testsuite/gcc.target/aarch64/and-be.c new file mode 100644 index 0000000..7457dd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/and-be.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbig-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef float v4sf __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + + +/* +** f_v4hi: +** movi v([0-9]+).2s, 0xff, msl 8 +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 4, 1, 6, 3 }); +} + +/* +** g_v4hi: +** mvni v([0-9]+).2s, 0xff, msl 8 +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v4hi +g_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 0, 5, 2, 7 }); +} + +/* +** f_v8hi: +** ... +** and v0.16b, (?:v0.16b, v[0-9]+.16b|v[0-9]+.16b, v0.16b) +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return __builtin_shuffle (x, (v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 8, 2, 9, 4, 10, 12, 11 }); +} + +/* +** f_v4si: +** movi v([0-9]+).2d, 0xffffffff00000000 +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4si +f_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 0, 4, 2, 5 }); +} + +/* +** g_v4si: +** movi v([0-9]+).2d, 0xffffffff +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4si +g_v4si (v4si x) +{ + return __builtin_shuffle ((v4si){ 0, 0, 0, 0 }, x, (v4si){ 1, 5, 3, 7 }); +} + +/* +** h_v4si: +** movi v([0-9]+).2d, 0xffffffff +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4si +h_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 7, 1, 6, 3 }); +} + +/* +** f_v4sf: +** movi v([0-9]+).2d, 0xffffffff00000000 +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4sf +f_v4sf (v4sf x) +{ + return __builtin_shuffle (x, (v4sf){ 0, 0, 0, 0 }, (v4si){ 0, 6, 2, 7 }); +} + +/* +** f_v8qi: +** movi d([0-9]+), 0xff00ff00ff000000 +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return __builtin_shuffle (x, (v8qi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8qi){ 0, 8, 2, 9, 4, 10, 12, 11 }); +} + +/* +** f_v16qi: +** ... +** and v0.16b, (?:v0.16b, v[0-9]+.16b|v[0-9]+.16b, v0.16b) +** ret +*/ +v16qi +f_v16qi (v16qi x) +{ + return __builtin_shuffle ( + x, (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + (v16qi){ 16, 1, 17, 3, 18, 5, 19, 7, 20, 9, 21, 11, 22, 13, 23, 24 }); +} diff --git a/gcc/testsuite/gcc.target/aarch64/and-le.c b/gcc/testsuite/gcc.target/aarch64/and-le.c new file mode 100644 index 0000000..398813b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/and-le.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlittle-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef float v4sf __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + + +/* +** f_v4hi: +** mvni v([0-9]+).2s, 0xff, msl 8 +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 4, 1, 6, 3 }); +} + +/* +** g_v4hi: +** movi v([0-9]+).2s, 0xff, msl 8 +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v4hi +g_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 0, 5, 2, 7 }); +} + +/* +** f_v8hi: +** ... +** and v0.16b, (?:v0.16b, v[0-9]+.16b|v[0-9]+.16b, v0.16b) +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return __builtin_shuffle (x, (v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 8, 2, 9, 4, 10, 12, 11 }); +} + +/* +** f_v4si: +** movi v([0-9]+).2d, 0xffffffff +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4si +f_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 0, 4, 2, 5 }); +} + +/* +** g_v4si: +** movi v([0-9]+).2d, 0xffffffff00000000 +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4si +g_v4si (v4si x) +{ + return __builtin_shuffle ((v4si){ 0, 0, 0, 0 }, x, (v4si){ 1, 5, 3, 7 }); +} + +/* +** h_v4si: +** movi v([0-9]+).2d, 0xffffffff00000000 +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4si +h_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 7, 1, 6, 3 }); +} + +/* +** f_v4sf: +** movi v([0-9]+).2d, 0xffffffff +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4sf +f_v4sf (v4sf x) +{ + return __builtin_shuffle (x, (v4sf){ 0, 0, 0, 0 }, (v4si){ 0, 6, 2, 7 }); +} + +/* +** f_v8qi: +** movi d([0-9]+), 0xff00ff00ff +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return __builtin_shuffle (x, (v8qi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8qi){ 0, 8, 2, 9, 4, 10, 12, 11 }); +} + +/* +** f_v16qi: +** ... +** and v0.16b, (?:v0.16b, v[0-9]+.16b|v[0-9]+.16b, v0.16b) +** ret +*/ +v16qi +f_v16qi (v16qi x) +{ + return __builtin_shuffle ( + x, (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + (v16qi){ 16, 1, 17, 3, 18, 5, 19, 7, 20, 9, 21, 11, 22, 13, 23, 24 }); +} diff --git a/gcc/testsuite/gcc.target/aarch64/asm-hard-reg-1.c b/gcc/testsuite/gcc.target/aarch64/asm-hard-reg-1.c new file mode 100644 index 0000000..7441dd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-hard-reg-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* Ensure that we error out in case no hard regs are available for an operand + with constraint y. The position/order of the y-constrained operand does not + matter. */ + +void +test (void) +{ + int x, a, b, c, d, e, f, g, h; + + __asm__ __volatile__ ("" : + "={v0}" (a), + "={v1}" (b), + "={v2}" (c), + "={v3}" (d), + "={v4}" (e), + "={v5}" (f), + "={v6}" (g), + "={v7}" (h)); + + __asm__ __volatile__ ("" : /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + "=y" (x), + "={v0}" (a), + "={v1}" (b), + "={v2}" (c), + "={v3}" (d), + "={v4}" (e), + "={v5}" (f), + "={v6}" (g), + "={v7}" (h)); + + __asm__ __volatile__ ("" : /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + "={v0}" (a), + "={v1}" (b), + "={v2}" (c), + "={v3}" (d), + "=y" (x), + "={v4}" (e), + "={v5}" (f), + "={v6}" (g), + "={v7}" (h)); + + __asm__ __volatile__ ("" : /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + "={v0}" (a), + "={v1}" (b), + "={v2}" (c), + "={v3}" (d), + "={v4}" (e), + "={v5}" (f), + "={v6}" (g), + "={v7}" (h), + "=y" (x)); +} diff --git a/gcc/testsuite/gcc.target/aarch64/asm-hard-reg-2.c b/gcc/testsuite/gcc.target/aarch64/asm-hard-reg-2.c new file mode 100644 index 0000000..7434063 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-hard-reg-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8-a+sve" } */ + +/* Test register pairs. */ + +#include <arm_sve.h> + +void +test (void) +{ + svuint32x2_t x, y; + svuint32x4_t z; + + __asm__ __volatile__ ("" : "={z4}" (x), "={z6}" (y)); + __asm__ __volatile__ ("" : "={z5}" (x), "={z6}" (y)); /* { dg-error "multiple outputs to hard register: v6" } */ + __asm__ __volatile__ ("" : "={z4}" (z), "={z6}" (y)); /* { dg-error "multiple outputs to hard register: v6" } */ +} diff --git a/gcc/testsuite/gcc.target/aarch64/autovec_param_asimd-only_2.c b/gcc/testsuite/gcc.target/aarch64/autovec_param_asimd-only_2.c new file mode 100644 index 0000000..6aeac0b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/autovec_param_asimd-only_2.c @@ -0,0 +1,4 @@ +/* { dg-options "-mautovec-preference=asimd-only" } */ + +void +foo (void) {} diff --git a/gcc/testsuite/gcc.target/aarch64/autovec_param_default_2.c b/gcc/testsuite/gcc.target/aarch64/autovec_param_default_2.c new file mode 100644 index 0000000..589cc50 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/autovec_param_default_2.c @@ -0,0 +1,4 @@ +/* { dg-options "-mautovec-preference=default" } */ + +void +foo (void) {} diff --git a/gcc/testsuite/gcc.target/aarch64/autovec_param_prefer-asimd_2.c b/gcc/testsuite/gcc.target/aarch64/autovec_param_prefer-asimd_2.c new file mode 100644 index 0000000..ad89786 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/autovec_param_prefer-asimd_2.c @@ -0,0 +1,4 @@ +/* { dg-options "-mautovec-preference=prefer-asimd" } */ + +void +foo (void) {} diff --git a/gcc/testsuite/gcc.target/aarch64/autovec_param_prefer-sve_2.c b/gcc/testsuite/gcc.target/aarch64/autovec_param_prefer-sve_2.c new file mode 100644 index 0000000..2acea69 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/autovec_param_prefer-sve_2.c @@ -0,0 +1,4 @@ +/* { dg-options "-mautovec-preference=prefer-sve" } */ + +void +foo (void) {} diff --git a/gcc/testsuite/gcc.target/aarch64/autovec_param_sve-only_2.c b/gcc/testsuite/gcc.target/aarch64/autovec_param_sve-only_2.c new file mode 100644 index 0000000..a7df0eb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/autovec_param_sve-only_2.c @@ -0,0 +1,4 @@ +/* { dg-options "-mautovec-preference=sve-only" } */ + +void +foo (void) {} diff --git a/gcc/testsuite/gcc.target/aarch64/avoid-store-forwarding-be.c b/gcc/testsuite/gcc.target/aarch64/avoid-store-forwarding-be.c new file mode 100644 index 0000000..2e8946b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/avoid-store-forwarding-be.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target aarch64_big_endian } */ +/* { dg-options "-O2 -favoid-store-forwarding" } */ + +typedef union { + char arr[2]; + short value; +} DataUnion; + +short __attribute__ ((noinline)) +ssll (DataUnion *data, char x, char y) +{ + data->arr[0] = x; + data->arr[1] = y; + return data->value; +} + +int main () { + DataUnion data = {}; + short value = ssll (&data, 0, 1); + if (value != 1) + __builtin_abort (); +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/aarch64/bti-1.c b/gcc/testsuite/gcc.target/aarch64/bti-1.c index 5a556b0..53dc2d3 100644 --- a/gcc/testsuite/gcc.target/aarch64/bti-1.c +++ b/gcc/testsuite/gcc.target/aarch64/bti-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* -Os to create jump table. */ -/* { dg-options "-Os" } */ +/* { dg-options "-Os -dA" } */ /* { dg-require-effective-target lp64 } */ /* If configured with --enable-standard-branch-protection, don't use command line option. */ @@ -44,8 +44,8 @@ f_jump_table (int y, int n) return (y == 0)? y+1:4; } /* f_jump_table should have PACIASP and AUTIASP. */ -/* { dg-final { scan-assembler-times "hint\t25" 1 } } */ -/* { dg-final { scan-assembler-times "hint\t29" 1 } } */ +/* { dg-final { scan-assembler-times "hint\t25 // paciasp" 1 } } */ +/* { dg-final { scan-assembler-times "hint\t29 // autiasp" 1 } } */ int f_label_address () @@ -59,6 +59,7 @@ lab2: addr = &&lab1; return 2; } -/* { dg-final { scan-assembler-times "hint\t34" 1 } } */ -/* { dg-final { scan-assembler-times "hint\t36" 12 } } */ -/* { dg-final { scan-assembler ".note.gnu.property" { target *-*-linux* } } } */ +/* { dg-final { scan-assembler-times "hint\t34 // bti c" 1 } } */ +/* { dg-final { scan-assembler-times "hint\t36 // bti j" 12 } } */ +/* { dg-final { scan-assembler "\.section\t\.note\.gnu\.property" { target *-*-linux* } } } */ +/* { dg-final { scan-assembler "\.word\t0x7\t\/\/ GNU_PROPERTY_AARCH64_FEATURE_1_AND \\(BTI, PAC, GCS\\)" { target *-*-linux* } } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/aarch64/build-attributes/aarch64-build-attributes.exp b/gcc/testsuite/gcc.target/aarch64/build-attributes/aarch64-build-attributes.exp new file mode 100644 index 0000000..c106c93 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/build-attributes/aarch64-build-attributes.exp @@ -0,0 +1,35 @@ +# Copyright (C) 2024-2025 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an AArch64 target. +if ![istarget aarch64*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ + "" "" + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/aarch64/build-attributes/build-attribute-bti.c b/gcc/testsuite/gcc.target/aarch64/build-attributes/build-attribute-bti.c new file mode 100644 index 0000000..363a6de --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/build-attributes/build-attribute-bti.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { aarch64*-*-linux* && { aarch64_gas_has_build_attributes } } } } */ +/* { dg-options "-mbranch-protection=bti -dA" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler "\.aeabi_subsection aeabi_feature_and_bits, optional, ULEB128" } } */ +/* { dg-final { scan-assembler "\.aeabi_attribute Tag_Feature_BTI, 1\t\/\/ Tag_Feature_BTI: true" } } */ +/* { dg-final { scan-assembler-not "\.section\t\.note\.gnu\.property" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/build-attributes/build-attribute-gcs.c b/gcc/testsuite/gcc.target/aarch64/build-attributes/build-attribute-gcs.c new file mode 100644 index 0000000..5368915 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/build-attributes/build-attribute-gcs.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { aarch64*-*-linux* && { aarch64_gas_has_build_attributes } } } } */ +/* { dg-options "-mbranch-protection=gcs -dA" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler "\.aeabi_subsection aeabi_feature_and_bits, optional, ULEB128" } } */ +/* { dg-final { scan-assembler "\.aeabi_attribute Tag_Feature_GCS, 1\t\/\/ Tag_Feature_GCS: true" } } */ +/* { dg-final { scan-assembler-not "\.section\t\.note\.gnu\.property" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/build-attributes/build-attribute-pac.c b/gcc/testsuite/gcc.target/aarch64/build-attributes/build-attribute-pac.c new file mode 100644 index 0000000..79d36c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/build-attributes/build-attribute-pac.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { aarch64*-*-linux* && { aarch64_gas_has_build_attributes } } } } */ +/* { dg-options "-mbranch-protection=pac-ret -dA" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler "\.aeabi_subsection aeabi_feature_and_bits, optional, ULEB128" } } */ +/* { dg-final { scan-assembler "\.aeabi_attribute Tag_Feature_PAC, 1\t\/\/ Tag_Feature_PAC: true" } } */ +/* { dg-final { scan-assembler-not "\.section\t\.note\.gnu\.property" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/build-attributes/build-attribute-standard.c b/gcc/testsuite/gcc.target/aarch64/build-attributes/build-attribute-standard.c new file mode 100644 index 0000000..7ffa717 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/build-attributes/build-attribute-standard.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { aarch64*-*-linux* && aarch64_gas_has_build_attributes } } } */ +/* { dg-options "-mbranch-protection=standard -dA" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler "\.aeabi_subsection aeabi_feature_and_bits, optional, ULEB128" } } */ +/* { dg-final { scan-assembler "\.aeabi_attribute Tag_Feature_BTI, 1\t\/\/ Tag_Feature_BTI: true" } } */ +/* { dg-final { scan-assembler "\.aeabi_attribute Tag_Feature_PAC, 1\t\/\/ Tag_Feature_PAC: true" } } */ +/* { dg-final { scan-assembler "\.aeabi_attribute Tag_Feature_GCS, 1\t\/\/ Tag_Feature_GCS: true" } } */ +/* { dg-final { scan-assembler-not "\.section\t\.note\.gnu\.property" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/build-attributes/no-build-attribute-bti.c b/gcc/testsuite/gcc.target/aarch64/build-attributes/no-build-attribute-bti.c new file mode 100644 index 0000000..013c76e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/build-attributes/no-build-attribute-bti.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { aarch64*-*-linux* && { ! aarch64_gas_has_build_attributes } } } } */ +/* { dg-options "-mbranch-protection=bti -dA" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler-not "\.aeabi_subsection" } } */ +/* { dg-final { scan-assembler-not "\.aeabi_attribute" } } */ +/* { dg-final { scan-assembler "\.section\t\.note\.gnu\.property" } } */ +/* { dg-final { scan-assembler "\.word\t0x1\t\/\/ GNU_PROPERTY_AARCH64_FEATURE_1_AND \\(BTI\\)" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/aarch64/build-attributes/no-build-attribute-gcs.c b/gcc/testsuite/gcc.target/aarch64/build-attributes/no-build-attribute-gcs.c new file mode 100644 index 0000000..954bf3a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/build-attributes/no-build-attribute-gcs.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { aarch64*-*-linux* && { ! aarch64_gas_has_build_attributes } } } } */ +/* { dg-options "-mbranch-protection=gcs -dA" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler-not "\.aeabi_subsection" } } */ +/* { dg-final { scan-assembler-not "\.aeabi_attribute" } } */ +/* { dg-final { scan-assembler "\.section\t\.note\.gnu\.property" } } */ +/* { dg-final { scan-assembler "\.word\t0x4\t\/\/ GNU_PROPERTY_AARCH64_FEATURE_1_AND \\(GCS\\)" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/aarch64/build-attributes/no-build-attribute-pac.c b/gcc/testsuite/gcc.target/aarch64/build-attributes/no-build-attribute-pac.c new file mode 100644 index 0000000..10195ec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/build-attributes/no-build-attribute-pac.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { aarch64*-*-linux* && { ! aarch64_gas_has_build_attributes } } } } */ +/* { dg-options "-mbranch-protection=pac-ret -dA" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler-not "\.aeabi_subsection" } } */ +/* { dg-final { scan-assembler-not "\.aeabi_attribute" } } */ +/* { dg-final { scan-assembler "\.section\t\.note\.gnu\.property" } } */ +/* { dg-final { scan-assembler "\.word\t0x2\t\/\/ GNU_PROPERTY_AARCH64_FEATURE_1_AND \\(PAC\\)" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/aarch64/build-attributes/no-build-attribute-standard.c b/gcc/testsuite/gcc.target/aarch64/build-attributes/no-build-attribute-standard.c new file mode 100644 index 0000000..52cad28 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/build-attributes/no-build-attribute-standard.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { aarch64*-*-linux* && { ! aarch64_gas_has_build_attributes } } } } */ +/* { dg-options "-mbranch-protection=standard -dA" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler-not "\.aeabi_subsection" } } */ +/* { dg-final { scan-assembler-not "\.aeabi_attribute" } } */ +/* { dg-final { scan-assembler "\.section\t\.note\.gnu\.property" } } */ +/* { dg-final { scan-assembler "\.word\t0x7\t\/\/ GNU_PROPERTY_AARCH64_FEATURE_1_AND \\(BTI, PAC, GCS\\)" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/aarch64/cmpbr.c b/gcc/testsuite/gcc.target/aarch64/cmpbr.c new file mode 100644 index 0000000..34630f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cmpbr.c @@ -0,0 +1,1824 @@ +// Test that the instructions added by FEAT_CMPBR are emitted +// { dg-do compile } +// { dg-do-if assemble { target aarch64_asm_cmpbr_ok } } +// { dg-options "-march=armv9.5-a+cmpbr -O2" } +// { dg-final { check-function-bodies "**" "*/" "" { target *-*-* } {\.L[0-9]+} } } + +#include <stdint.h> + +typedef uint8_t u8; +typedef int8_t i8; + +typedef uint16_t u16; +typedef int16_t i16; + +typedef uint32_t u32; +typedef int32_t i32; + +typedef uint64_t u64; +typedef int64_t i64; + +int taken(); +int not_taken(); + +#define COMPARE(ty, name, op, rhs) \ + int ty##_x0_##name##_##rhs(ty x0, ty x1) { \ + return __builtin_expect(x0 op rhs, 0) ? taken() : not_taken(); \ + } + +#define COMPARE_ALL(unsigned_ty, signed_ty, rhs) \ + COMPARE(unsigned_ty, eq, ==, rhs); \ + COMPARE(unsigned_ty, ne, !=, rhs); \ + \ + COMPARE(unsigned_ty, ult, <, rhs); \ + COMPARE(unsigned_ty, ule, <=, rhs); \ + COMPARE(unsigned_ty, ugt, >, rhs); \ + COMPARE(unsigned_ty, uge, >=, rhs); \ + \ + COMPARE(signed_ty, slt, <, rhs); \ + COMPARE(signed_ty, sle, <=, rhs); \ + COMPARE(signed_ty, sgt, >, rhs); \ + COMPARE(signed_ty, sge, >=, rhs); + +// ==== CBB<cc> (register) ==== +COMPARE_ALL(u8, i8, x1); + +// ==== CBH<cc> (register) ==== +COMPARE_ALL(u16, i16, x1); + +// ==== CB<cc> (register) ==== +COMPARE_ALL(u32, i32, x1); +COMPARE_ALL(u64, i64, x1); + +// ==== CB<cc> (immediate) ==== +COMPARE_ALL(u32, i32, 42); +COMPARE_ALL(u64, i64, 42); + +// ==== Special cases ==== +// Comparisons against the immediate 0 can be done for all types, +// because we can use the wzr/xzr register as one of the operands. +// However, we should prefer to use CBZ/CBNZ or TBZ/TBNZ when possible, +// because they have larger range. +COMPARE_ALL(u8, i8, 0); +COMPARE_ALL(u16, i16, 0); +COMPARE_ALL(u32, i32, 0); +COMPARE_ALL(u64, i64, 0); + +// CBB and CBH cannot have immediate operands. +// Instead we have to do a MOV+CB. +COMPARE_ALL(u8, i8, 42); +COMPARE_ALL(u16, i16, 42); + +// 64 is out of the range for immediate operands (0 to 63). +// * For 8/16-bit types, use a MOV+CB as above. +// * For 32/64-bit types, use a CMP+B<cc> instead, +// because B<cc> has a longer range than CB<cc>. +COMPARE_ALL(u8, i8, 64); +COMPARE_ALL(u16, i16, 64); +COMPARE_ALL(u32, i32, 64); +COMPARE_ALL(u64, i64, 64); + +// 4098 is out of the range for CMP (0 to 4095, optionally shifted by left by 12 +// bits), but it can be materialized in a single MOV. +COMPARE_ALL(u16, i16, 4098); +COMPARE_ALL(u32, i32, 4098); +COMPARE_ALL(u64, i64, 4098); + +// If the branch destination is out of range (1KiB), we have to generate an +// extra B instruction (which can handle larger displacements) and branch around +// it + +// clang-format off +#define STORE_1() z = 0; +#define STORE_2() STORE_1() STORE_1() +#define STORE_4() STORE_2() STORE_2() +#define STORE_8() STORE_4() STORE_4() +#define STORE_16() STORE_8() STORE_8() +#define STORE_32() STORE_16() STORE_16() +#define STORE_64() STORE_32() STORE_32() +#define STORE_128() STORE_64() STORE_64() +#define STORE_256() STORE_128() STORE_128() +// clang-format on + +#define FAR_BRANCH(ty, rhs) \ + int far_branch_##ty##_x0_eq_##rhs(ty x0, ty x1) { \ + volatile int z = 0; \ + if (__builtin_expect(x0 == rhs, 1)) { \ + STORE_256(); \ + } \ + return taken(); \ + } + +FAR_BRANCH(u8, x1); +FAR_BRANCH(u16, x1); +FAR_BRANCH(u32, x1); +FAR_BRANCH(u64, x1); + +FAR_BRANCH(u8, 42); +FAR_BRANCH(u16, 42); +FAR_BRANCH(u32, 42); +FAR_BRANCH(u64, 42); + +/* +** u8_x0_eq_x1: +** cbbeq (?:w1, w0|w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u8_x0_ne_x1: +** cbbne (?:w1, w0|w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u8_x0_ult_x1: +** (?:cbbhi w1, w0|cbblo w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u8_x0_ule_x1: +** (?:cbbhs w1, w0|cbbls w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u8_x0_ugt_x1: +** (?:cbblo w1, w0|cbbhi w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u8_x0_uge_x1: +** (?:cbbls w1, w0|cbbhs w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i8_x0_slt_x1: +** (?:cbbgt w1, w0|cbblt w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i8_x0_sle_x1: +** (?:cbbge w1, w0|cbble w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i8_x0_sgt_x1: +** (?:cbblt w1, w0|cbbgt w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i8_x0_sge_x1: +** (?:cbble w1, w0|cbbge w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u16_x0_eq_x1: +** cbheq (?:w1, w0|w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u16_x0_ne_x1: +** cbhne (?:w1, w0|w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u16_x0_ult_x1: +** (?:cbhhi w1, w0|cbhlo w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u16_x0_ule_x1: +** (?:cbhhs w1, w0|cbhls w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u16_x0_ugt_x1: +** (?:cbhlo w1, w0|cbhhi w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u16_x0_uge_x1: +** (?:cbhls w1, w0|cbhhs w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i16_x0_slt_x1: +** (?:cbhgt w1, w0|cbhlt w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i16_x0_sle_x1: +** (?:cbhge w1, w0|cbhle w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i16_x0_sgt_x1: +** (?:cbhlt w1, w0|cbhgt w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i16_x0_sge_x1: +** (?:cbhle w1, w0|cbhge w0, w1), .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_eq_x1: +** cbeq w0, w1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_ne_x1: +** cbne w0, w1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_ult_x1: +** cblo w0, w1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_ule_x1: +** cbls w0, w1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_ugt_x1: +** cbhi w0, w1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_uge_x1: +** cbhs w0, w1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i32_x0_slt_x1: +** cblt w0, w1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i32_x0_sle_x1: +** cble w0, w1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i32_x0_sgt_x1: +** cbgt w0, w1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i32_x0_sge_x1: +** cbge w0, w1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_eq_x1: +** cbeq x0, x1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_ne_x1: +** cbne x0, x1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_ult_x1: +** cblo x0, x1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_ule_x1: +** cbls x0, x1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_ugt_x1: +** cbhi x0, x1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_uge_x1: +** cbhs x0, x1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i64_x0_slt_x1: +** cblt x0, x1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i64_x0_sle_x1: +** cble x0, x1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i64_x0_sgt_x1: +** cbgt x0, x1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i64_x0_sge_x1: +** cbge x0, x1, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_eq_42: +** cbeq w0, 42, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_ne_42: +** cbne w0, 42, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_ult_42: +** cbls w0, 41, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_ule_42: +** cbls w0, 42, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_ugt_42: +** cbhi w0, 42, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_uge_42: +** cbhi w0, 41, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i32_x0_slt_42: +** cble w0, 41, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i32_x0_sle_42: +** cble w0, 42, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i32_x0_sgt_42: +** cbgt w0, 42, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i32_x0_sge_42: +** cbgt w0, 41, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_eq_42: +** cbeq x0, 42, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_ne_42: +** cbne x0, 42, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_ult_42: +** cbls x0, 41, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_ule_42: +** cbls x0, 42, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_ugt_42: +** cbhi x0, 42, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_uge_42: +** cbhi x0, 41, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i64_x0_slt_42: +** cble x0, 41, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i64_x0_sle_42: +** cble x0, 42, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i64_x0_sgt_42: +** cbgt x0, 42, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i64_x0_sge_42: +** cbgt x0, 41, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u8_x0_eq_0: +** cbbeq w0, wzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u8_x0_ne_0: +** cbbne w0, wzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u8_x0_ult_0: +** b not_taken +*/ + +/* +** u8_x0_ule_0: +** cbbeq w0, wzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u8_x0_ugt_0: +** cbbne w0, wzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u8_x0_uge_0: +** b taken +*/ + +/* +** i8_x0_slt_0: +** tbnz w0, #7, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i8_x0_sle_0: +** cbble w0, wzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i8_x0_sgt_0: +** cbbgt w0, wzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i8_x0_sge_0: +** tbz w0, #7, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u16_x0_eq_0: +** cbheq w0, wzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u16_x0_ne_0: +** cbhne w0, wzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u16_x0_ult_0: +** b not_taken +*/ + +/* +** u16_x0_ule_0: +** cbheq w0, wzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u16_x0_ugt_0: +** cbhne w0, wzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u16_x0_uge_0: +** b taken +*/ + +/* +** i16_x0_slt_0: +** tbnz w0, #15, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i16_x0_sle_0: +** cbhle w0, wzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i16_x0_sgt_0: +** cbhgt w0, wzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i16_x0_sge_0: +** tbz w0, #15, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_eq_0: +** cbz w0, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_ne_0: +** cbnz w0, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_ult_0: +** b not_taken +*/ + +/* +** u32_x0_ule_0: +** cbz w0, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_ugt_0: +** cbnz w0, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_uge_0: +** b taken +*/ + +/* +** i32_x0_slt_0: +** tbnz w0, #31, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i32_x0_sle_0: +** cble w0, wzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i32_x0_sgt_0: +** cbgt w0, wzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i32_x0_sge_0: +** tbz w0, #31, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_eq_0: +** cbz x0, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_ne_0: +** cbnz x0, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_ult_0: +** b not_taken +*/ + +/* +** u64_x0_ule_0: +** cbz x0, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_ugt_0: +** cbnz x0, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_uge_0: +** b taken +*/ + +/* +** i64_x0_slt_0: +** tbnz x0, #63, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i64_x0_sle_0: +** cble x0, xzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i64_x0_sgt_0: +** cbgt x0, xzr, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i64_x0_sge_0: +** tbz x0, #63, .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u8_x0_eq_42: +** mov w([0-9]+), 42 +** cbbeq w0, w\1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u8_x0_ne_42: +** mov (w[0-9]+), 42 +** cbbne w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u8_x0_ult_42: +** mov (w[0-9]+), 41 +** cbbls w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u8_x0_ule_42: +** mov (w[0-9]+), 42 +** cbbls w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u8_x0_ugt_42: +** mov (w[0-9]+), 42 +** cbbhi w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u8_x0_uge_42: +** mov (w[0-9]+), 41 +** cbbhi w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i8_x0_slt_42: +** mov (w[0-9]+), 41 +** cbble w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i8_x0_sle_42: +** mov (w[0-9]+), 42 +** cbble w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i8_x0_sgt_42: +** mov (w[0-9]+), 42 +** cbbgt w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i8_x0_sge_42: +** mov (w[0-9]+), 41 +** cbbgt w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_eq_42: +** mov w([0-9]+), 42 +** cbheq w0, w\1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_ne_42: +** mov (w[0-9]+), 42 +** cbhne w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_ult_42: +** mov (w[0-9]+), 41 +** cbhls w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_ule_42: +** mov (w[0-9]+), 42 +** cbhls w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_ugt_42: +** mov (w[0-9]+), 42 +** cbhhi w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_uge_42: +** mov (w[0-9]+), 41 +** cbhhi w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i16_x0_slt_42: +** mov (w[0-9]+), 41 +** cbhle w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i16_x0_sle_42: +** mov (w[0-9]+), 42 +** cbhle w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i16_x0_sgt_42: +** mov (w[0-9]+), 42 +** cbhgt w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i16_x0_sge_42: +** mov (w[0-9]+), 41 +** cbhgt w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u8_x0_eq_64: +** mov w([0-9]+), 64 +** cbbeq w0, w\1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u8_x0_ne_64: +** mov (w[0-9]+), 64 +** cbbne w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u8_x0_ult_64: +** mov (w[0-9]+), 63 +** cbbls w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u8_x0_ule_64: +** mov (w[0-9]+), 64 +** cbbls w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u8_x0_ugt_64: +** mov (w[0-9]+), 64 +** cbbhi w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u8_x0_uge_64: +** mov (w[0-9]+), 63 +** cbbhi w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i8_x0_slt_64: +** mov (w[0-9]+), 63 +** cbble w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i8_x0_sle_64: +** mov (w[0-9]+), 64 +** cbble w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i8_x0_sgt_64: +** mov (w[0-9]+), 64 +** cbbgt w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i8_x0_sge_64: +** mov (w[0-9]+), 63 +** cbbgt w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_eq_64: +** mov w([0-9]+), 64 +** cbheq w0, w\1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_ne_64: +** mov (w[0-9]+), 64 +** cbhne w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_ult_64: +** mov (w[0-9]+), 63 +** cbhls w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_ule_64: +** mov (w[0-9]+), 64 +** cbhls w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_ugt_64: +** mov (w[0-9]+), 64 +** cbhhi w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_uge_64: +** mov (w[0-9]+), 63 +** cbhhi w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i16_x0_slt_64: +** mov (w[0-9]+), 63 +** cbhle w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i16_x0_sle_64: +** mov (w[0-9]+), 64 +** cbhle w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i16_x0_sgt_64: +** mov (w[0-9]+), 64 +** cbhgt w0, w1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i16_x0_sge_64: +** mov (w[0-9]+), 63 +** cbhgt w0, w1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u32_x0_eq_64: +** cmp w0, 64 +** beq .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_ne_64: +** cmp w0, 64 +** bne .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_ult_64: +** cbhi w0, 63, .L([0-9]+) +** b taken +** .L\1: +** b not_taken +*/ + +/* +** u32_x0_ule_64: +** cmp w0, 64 +** bls .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_ugt_64: +** cmp w0, 64 +** bhi .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u32_x0_uge_64: +** cmp w0, 63 +** bhi .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i32_x0_slt_64: +** cbgt w0, 63, .L([0-9]+) +** b taken +** .L\1: +** b not_taken +*/ + +/* +** i32_x0_sle_64: +** cmp w0, 64 +** ble .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i32_x0_sgt_64: +** cmp w0, 64 +** bgt .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i32_x0_sge_64: +** cmp w0, 63 +** bgt .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_eq_64: +** cmp x0, 64 +** beq .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_ne_64: +** cmp x0, 64 +** bne .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_ult_64: +** cbhi x0, 63, .L([0-9]+) +** b taken +** .L\1: +** b not_taken +*/ + +/* +** u64_x0_ule_64: +** cmp x0, 64 +** bls .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_ugt_64: +** cmp x0, 64 +** bhi .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u64_x0_uge_64: +** cmp x0, 63 +** bhi .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i64_x0_slt_64: +** cbgt x0, 63, .L([0-9]+) +** b taken +** .L\1: +** b not_taken +*/ + +/* +** i64_x0_sle_64: +** cmp x0, 64 +** ble .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i64_x0_sgt_64: +** cmp x0, 64 +** bgt .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** i64_x0_sge_64: +** cmp x0, 63 +** bgt .L([0-9]+) +** b not_taken +** .L\1: +** b taken +*/ + +/* +** u16_x0_eq_4098: +** mov w([0-9]+), 4098 +** cbheq w0, w\1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_ne_4098: +** mov (w[0-9]+), 4098 +** cbhne w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_ult_4098: +** mov (w[0-9]+), 4097 +** cbhls w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_ule_4098: +** mov (w[0-9]+), 4098 +** cbhls w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_ugt_4098: +** mov (w[0-9]+), 4098 +** cbhhi w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u16_x0_uge_4098: +** mov (w[0-9]+), 4097 +** cbhhi w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i16_x0_slt_4098: +** mov (w[0-9]+), 4097 +** cbhle w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i16_x0_sle_4098: +** mov (w[0-9]+), 4098 +** cbhle w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i16_x0_sgt_4098: +** mov (w[0-9]+), 4098 +** cbhgt w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i16_x0_sge_4098: +** mov (w[0-9]+), 4097 +** cbhgt w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u32_x0_eq_4098: +** mov w([0-9]+), 4098 +** cbeq w0, w\1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u32_x0_ne_4098: +** mov (w[0-9]+), 4098 +** cbne w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u32_x0_ult_4098: +** mov (w[0-9]+), 4097 +** cbls w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u32_x0_ule_4098: +** mov (w[0-9]+), 4098 +** cbls w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u32_x0_ugt_4098: +** mov (w[0-9]+), 4098 +** cbhi w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u32_x0_uge_4098: +** mov (w[0-9]+), 4097 +** cbhi w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i32_x0_slt_4098: +** mov (w[0-9]+), 4097 +** cble w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i32_x0_sle_4098: +** mov (w[0-9]+), 4098 +** cble w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i32_x0_sgt_4098: +** mov (w[0-9]+), 4098 +** cbgt w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i32_x0_sge_4098: +** mov (w[0-9]+), 4097 +** cbgt w0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u64_x0_eq_4098: +** mov x([0-9]+), 4098 +** cbeq x0, x\1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u64_x0_ne_4098: +** mov (x[0-9]+), 4098 +** cbne x0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u64_x0_ult_4098: +** mov (x[0-9]+), 4097 +** cbls x0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u64_x0_ule_4098: +** mov (x[0-9]+), 4098 +** cbls x0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u64_x0_ugt_4098: +** mov (x[0-9]+), 4098 +** cbhi x0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** u64_x0_uge_4098: +** mov (x[0-9]+), 4097 +** cbhi x0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i64_x0_slt_4098: +** mov (x[0-9]+), 4097 +** cble x0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i64_x0_sle_4098: +** mov (x[0-9]+), 4098 +** cble x0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i64_x0_sgt_4098: +** mov (x[0-9]+), 4098 +** cbgt x0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** i64_x0_sge_4098: +** mov (x[0-9]+), 4097 +** cbgt x0, \1, .L([0-9]+) +** b not_taken +** .L\2: +** b taken +*/ + +/* +** far_branch_u8_x0_eq_x1: +** sub sp, sp, #16 +** str wzr, \[sp, 12\] +** cbbeq w0|w1, w1|w0, .L([0-9]+) +** b .L([0-9]+) +** .L\1: +** str wzr, \[sp, 12\] +** ... +** str wzr, \[sp, 12\] +** .L\2: +** add sp, sp, 16 +** b taken +*/ + +/* +** far_branch_u16_x0_eq_x1: +** sub sp, sp, #16 +** str wzr, \[sp, 12\] +** cbheq w0|w1, w1|w0, .L([0-9]+) +** b .L([0-9]+) +** .L\1: +** str wzr, \[sp, 12\] +** ... +** str wzr, \[sp, 12\] +** .L\2: +** add sp, sp, 16 +** b taken +*/ + +/* +** far_branch_u32_x0_eq_x1: +** sub sp, sp, #16 +** str wzr, \[sp, 12\] +** cbeq w0, w1, .L([0-9]+) +** b .L([0-9]+) +** .L\1: +** str wzr, \[sp, 12\] +** ... +** str wzr, \[sp, 12\] +** .L\2: +** add sp, sp, 16 +** b taken +*/ + +/* +** far_branch_u64_x0_eq_x1: +** sub sp, sp, #16 +** str wzr, \[sp, 12\] +** cbeq x0, x1, .L([0-9]+) +** b .L([0-9]+) +** .L\1: +** str wzr, \[sp, 12\] +** ... +** str wzr, \[sp, 12\] +** .L\2: +** add sp, sp, 16 +** b taken +*/ + +/* +** far_branch_u8_x0_eq_42: +** sub sp, sp, #16 +** mov w([0-9]+), 42 +** str wzr, \[sp, 12\] +** cbbeq w0, w\1, .L([0-9]+) +** b .L([0-9]+) +** .L\2: +** str wzr, \[sp, 12\] +** ... +** str wzr, \[sp, 12\] +** .L\3: +** add sp, sp, 16 +** b taken +*/ + +/* +** far_branch_u16_x0_eq_42: +** sub sp, sp, #16 +** mov w([0-9]+), 42 +** str wzr, \[sp, 12\] +** cbheq w0, w\1, .L([0-9]+) +** b .L([0-9]+) +** .L\2: +** str wzr, \[sp, 12\] +** ... +** str wzr, \[sp, 12\] +** .L\3: +** add sp, sp, 16 +** b taken +*/ + +/* +** far_branch_u32_x0_eq_42: +** sub sp, sp, #16 +** str wzr, \[sp, 12\] +** cbeq w0, 42, .L([0-9]+) +** b .L([0-9]+) +** .L\1: +** str wzr, \[sp, 12\] +** ... +** str wzr, \[sp, 12\] +** .L\2: +** add sp, sp, 16 +** b taken +*/ + +/* +** far_branch_u64_x0_eq_42: +** sub sp, sp, #16 +** str wzr, \[sp, 12\] +** cbeq x0, 42, .L([0-9]+) +** b .L([0-9]+) +** .L\1: +** str wzr, \[sp, 12\] +** ... +** str wzr, \[sp, 12\] +** .L\2: +** add sp, sp, 16 +** b taken +*/ diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-1-be.c b/gcc/testsuite/gcc.target/aarch64/fmov-1-be.c new file mode 100644 index 0000000..4227c67 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-1-be.c @@ -0,0 +1,151 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbig-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8-a") + +typedef int v2si __attribute__ ((vector_size (8))); +typedef float v2sf __attribute__ ((vector_size (8))); +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef long v2di __attribute__ ((vector_size (16))); +typedef double v2df __attribute__ ((vector_size (16))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef float v4sf __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + +/* +** f_v4hi: +** fmov s0, s0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return x & (v4hi){ 0, 0, 0xffff, 0xffff }; +} + +/* +** g_v4hi: +** movi d([0-9]+), 0xffff00000000ffff +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v4hi +g_v4hi (v4hi x) +{ + return x & (v4hi){ 0xffff, 0, 0, 0xffff }; +} + +/* +** f_v8hi: +** fmov s0, s0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return x & (v8hi){ 0, 0, 0, 0, 0, 0, 0xffff, 0xffff }; +} + +/* +** g_v8hi: +** fmov d0, d0 +** ret +*/ +v8hi +g_v8hi (v8hi x) +{ + return x & (v8hi){ 0, 0, 0, 0, 0xffff, 0xffff, 0xffff, 0xffff }; +} + +/* +** f_v2si: +** fmov s0, s0 +** ret +*/ +v2si +f_v2si (v2si x) +{ + return x & (v2si){ 0, 0xffffffff }; +} + +/* +** f_v2di: +** fmov d0, d0 +** ret +*/ +v2di +f_v2di (v2di x) +{ + return x & (v2di){ 0, 0xffffffffffffffff }; +} + +/* +** g_v2di: +** fmov s0, s0 +** ret +*/ +v2di +g_v2di (v2di x) +{ + return x & (v2di){ 0, 0xffffffff }; +} + +/* +** f_v4si: +** fmov s0, s0 +** ret +*/ +v4si +f_v4si (v4si x) +{ + return x & (v4si){ 0, 0, 0, 0xffffffff }; +} + +/* +** h_v4si: +** fmov d0, d0 +** ret +*/ +v4si +h_v4si (v4si x) +{ + return x & (v4si){ 0, 0, 0xffffffff, 0xffffffff }; +} + +/* +** f_v8qi: +** fmov s0, s0 +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return x & (v8qi){ 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff }; +} + +/* +** f_v16qi: +** fmov d0, d0 +** ret +*/ +v16qi +f_v16qi (v16qi x) +{ + return x & (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; +} + +/* +** g_v16qi: +** fmov s0, s0 +** ret +*/ +v16qi +g_v16qi (v16qi x) +{ + return x & (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff }; +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-1-le.c b/gcc/testsuite/gcc.target/aarch64/fmov-1-le.c new file mode 100644 index 0000000..618702a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-1-le.c @@ -0,0 +1,151 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlittle-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8-a") + +typedef int v2si __attribute__ ((vector_size (8))); +typedef float v2sf __attribute__ ((vector_size (8))); +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef long v2di __attribute__ ((vector_size (16))); +typedef double v2df __attribute__ ((vector_size (16))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef float v4sf __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + +/* +** f_v4hi: +** fmov s0, s0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return x & (v4hi){ 0xffff, 0xffff, 0, 0 }; +} + +/* +** g_v4hi: +** movi d([0-9]+), 0xffff00000000ffff +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v4hi +g_v4hi (v4hi x) +{ + return x & (v4hi){ 0xffff, 0, 0, 0xffff }; +} + +/* +** f_v8hi: +** fmov s0, s0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return x & (v8hi){ 0xffff, 0xffff, 0, 0, 0, 0, 0, 0 }; +} + +/* +** g_v8hi: +** fmov d0, d0 +** ret +*/ +v8hi +g_v8hi (v8hi x) +{ + return x & (v8hi){ 0xffff, 0xffff, 0xffff, 0xffff, 0, 0, 0, 0 }; +} + +/* +** f_v2si: +** fmov s0, s0 +** ret +*/ +v2si +f_v2si (v2si x) +{ + return x & (v2si){ 0xffffffff, 0 }; +} + +/* +** f_v2di: +** fmov d0, d0 +** ret +*/ +v2di +f_v2di (v2di x) +{ + return x & (v2di){ 0xffffffffffffffff, 0 }; +} + +/* +** g_v2di: +** fmov s0, s0 +** ret +*/ +v2di +g_v2di (v2di x) +{ + return x & (v2di){ 0xffffffff, 0 }; +} + +/* +** f_v4si: +** fmov s0, s0 +** ret +*/ +v4si +f_v4si (v4si x) +{ + return x & (v4si){ 0xffffffff, 0, 0, 0 }; +} + +/* +** h_v4si: +** fmov d0, d0 +** ret +*/ +v4si +h_v4si (v4si x) +{ + return x & (v4si){ 0xffffffff, 0xffffffff, 0, 0 }; +} + +/* +** f_v8qi: +** fmov s0, s0 +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return x & (v8qi){ 0xff, 0xff, 0xff, 0xff, 0, 0, 0, 0 }; +} + +/* +** f_v16qi: +** fmov d0, d0 +** ret +*/ +v16qi +f_v16qi (v16qi x) +{ + return x & (v16qi){ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0, 0, 0, 0, 0, 0, 0, 0 }; +} + +/* +** g_v16qi: +** fmov s0, s0 +** ret +*/ +v16qi +g_v16qi (v16qi x) +{ + return x & (v16qi){ 0xff, 0xff, 0xff, 0xff, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }; +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-2-be.c b/gcc/testsuite/gcc.target/aarch64/fmov-2-be.c new file mode 100644 index 0000000..1e38066 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-2-be.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbig-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8.2-a+fp16") + +typedef int v2si __attribute__ ((vector_size (8))); +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef long v2di __attribute__ ((vector_size (16))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + +/* +** f_v2di: +** fmov h0, h0 +** ret +*/ +v2di +f_v2di (v2di x) +{ + return x & (v2di){ 0, 0xffff }; +} + +/* +** f_v4si: +** fmov h0, h0 +** ret +*/ +v4si +f_v4si (v4si x) +{ + return x & (v4si){ 0, 0, 0, 0xffff }; +} + +/* +** f_v2si: +** fmov h0, h0 +** ret +*/ +v2si +f_v2si (v2si x) +{ + return x & (v2si){ 0, 0xffff }; +} + +/* +** f_v8hi: +** fmov h0, h0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return x & (v8hi){ 0, 0, 0, 0, 0, 0, 0, 0xffff }; +} + +/* +** f_v4hi: +** fmov h0, h0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return x & (v4hi){ 0, 0, 0, 0xffff }; +} + +/* +** f_v16qi: +** fmov h0, h0 +** ret +*/ +v16qi +f_v16qi (v16qi x) +{ + return x & (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xff, 0xff }; +} + +/* +** f_v8qi: +** fmov h0, h0 +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return x & (v8qi){ 0, 0, 0, 0, 0, 0, 0xff, 0xff }; +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-2-le.c b/gcc/testsuite/gcc.target/aarch64/fmov-2-le.c new file mode 100644 index 0000000..7627680 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-2-le.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlittle-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8.2-a+fp16") + +typedef int v2si __attribute__ ((vector_size (8))); +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef long v2di __attribute__ ((vector_size (16))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + +/* +** f_v2di: +** fmov h0, h0 +** ret +*/ +v2di +f_v2di (v2di x) +{ + return x & (v2di){ 0xffff, 0 }; +} + +/* +** f_v4si: +** fmov h0, h0 +** ret +*/ +v4si +f_v4si (v4si x) +{ + return x & (v4si){ 0xffff, 0, 0, 0 }; +} + +/* +** f_v2si: +** fmov h0, h0 +** ret +*/ +v2si +f_v2si (v2si x) +{ + return x & (v2si){ 0xffff, 0 }; +} + +/* +** f_v8hi: +** fmov h0, h0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return x & (v8hi){ 0xffff, 0, 0, 0, 0, 0, 0, 0 }; +} + +/* +** f_v4hi: +** fmov h0, h0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return x & (v4hi){ 0xffff, 0, 0, 0 }; +} + +/* +** f_v16qi: +** fmov h0, h0 +** ret +*/ +v16qi +f_v16qi (v16qi x) +{ + return x & (v16qi){ 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +} + +/* +** f_v8qi: +** fmov h0, h0 +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return x & (v8qi){ 0xff, 0xff, 0, 0, 0, 0, 0, 0 }; +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-3-be.c b/gcc/testsuite/gcc.target/aarch64/fmov-3-be.c new file mode 100644 index 0000000..0bddd96 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-3-be.c @@ -0,0 +1,77 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbig-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8-a") + +typedef short v4hi __attribute__ ((vector_size (8))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef float v4sf __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); + +/* +** f_v4hi: +** fmov s0, s0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 4, 5, 2, 3 }); +} + +/* +** f_v8hi: +** fmov s0, s0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return __builtin_shuffle (x, (v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 8, 9, 10, 11, 12, 13, 6, 7 }); +} + +/* +** f_v4si: +** fmov d0, d0 +** ret +*/ +v4si +f_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 6, 7, 2, 3 }); +} + +/* +** g_v4si: +** fmov d0, d0 +** ret +*/ +v4si +g_v4si (v4si x) +{ + return __builtin_shuffle ((v4si){ 0, 0, 0, 0 }, x, (v4si){ 2, 3, 6, 7 }); +} + +/* +** h_v4si: +** fmov s0, s0 +** ret +*/ +v4si +h_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 4, 5, 6, 3 }); +} + +/* +** f_v4sf: +** fmov d0, d0 +** ret +*/ +v4sf +f_v4sf (v4sf x) +{ + return __builtin_shuffle (x, (v4sf){ 0, 0, 0, 0 }, (v4si){ 6, 7, 2, 3 }); +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-3-le.c b/gcc/testsuite/gcc.target/aarch64/fmov-3-le.c new file mode 100644 index 0000000..4545841 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-3-le.c @@ -0,0 +1,129 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlittle-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8-a") + +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef float v4sf __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + +/* +** f_v4hi: +** fmov s0, s0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 0, 1, 4, 5 }); +} + +/* +** g_v4hi: +** (?:(?!fmov).)* +** ret +*/ +v4hi +g_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 3, 1, 4, 2 }); +} + +/* +** f_v8hi: +** fmov s0, s0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return __builtin_shuffle (x, (v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 1, 8, 9, 10, 11, 12, 13 }); +} + +/* +** f_v4si: +** fmov d0, d0 +** ret +*/ +v4si +f_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 0, 1, 4, 5 }); +} + +/* +** g_v4si: +** fmov d0, d0 +** ret +*/ +v4si +g_v4si (v4si x) +{ + return __builtin_shuffle ((v4si){ 0, 0, 0, 0 }, x, (v4si){ 4, 5, 2, 3 }); +} + +/* +** h_v4si: +** fmov s0, s0 +** ret +*/ +v4si +h_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 0, 4, 5, 6 }); +} + +/* +** f_v4sf: +** fmov d0, d0 +** ret +*/ +v4sf +f_v4sf (v4sf x) +{ + return __builtin_shuffle (x, (v4sf){ 0, 0, 0, 0 }, (v4si){ 0, 1, 6, 7 }); +} + +/* +** f_v8qi: +** fmov s0, s0 +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return __builtin_shuffle (x, (v8qi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8qi){ 0, 1, 2, 3, 10, 11, 12, 13 }); +} + +/* +** f_v16qi: +** fmov d0, d0 +** ret +*/ +v16qi +f_v16qi (v16qi x) +{ + return __builtin_shuffle ( + x, (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + (v16qi){ 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 }); +} + +/* +** g_v16qi: +** fmov s0, s0 +** ret +*/ +v16qi +g_v16qi (v16qi x) +{ + return __builtin_shuffle ( + x, (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + (v16qi){ 0, 1, 2, 3, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 }); +} + diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-4-be.c b/gcc/testsuite/gcc.target/aarch64/fmov-4-be.c new file mode 100644 index 0000000..58212ef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-4-be.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbig-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8.2-a+fp16") + +typedef short v4hi __attribute__ ((vector_size (8))); +typedef short v8hi __attribute__ ((vector_size (16))); + +/* +** f_v4hi: +** fmov h0, h0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 4, 5, 6, 3 }); +} + +/* +** g_v4hi: +** fmov h0, h0 +** ret +*/ +v4hi +g_v4hi (v4hi x) +{ + return __builtin_shuffle ((v4hi){ 0, 0, 0, 0 }, x, (v4hi){ 0, 1, 2, 7 }); +} + +/* +** f_v8hi: +** fmov h0, h0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return __builtin_shuffle (x, (v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 8, 9, 10, 11, 12, 13, 14, 7 }); +} + +/* +** g_v8hi: +** fmov h0, h0 +** ret +*/ +v8hi +g_v8hi (v8hi x) +{ + return __builtin_shuffle ((v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, x, + (v8hi){ 0, 1, 2, 3, 4, 5, 6, 15 }); +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-4-le.c b/gcc/testsuite/gcc.target/aarch64/fmov-4-le.c new file mode 100644 index 0000000..3449a51 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-4-le.c @@ -0,0 +1,94 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlittle-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8.2-a+fp16") + +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + +/* +** f_v4hi: +** fmov h0, h0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 0, 4, 5, 6 }); +} + +/* +** g_v4hi: +** fmov h0, h0 +** ret +*/ +v4hi +g_v4hi (v4hi x) +{ + return __builtin_shuffle ((v4hi){ 0, 0, 0, 0 }, x, (v4hi){ 4, 0, 1, 2 }); +} + +/* +** f_v8hi: +** fmov h0, h0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return __builtin_shuffle (x, (v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 8, 9, 10, 11, 12, 13, 14 }); +} + +/* +** g_v8hi: +** fmov h0, h0 +** ret +*/ +v8hi +g_v8hi (v8hi x) +{ + return __builtin_shuffle ((v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, x, + (v8hi){ 8, 0, 1, 2, 3, 4, 5, 6 }); +} + +/* +** f_v8qi: +** fmov h0, h0 +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return __builtin_shuffle (x, (v8qi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8qi){ 0, 1, 8, 9, 10, 11, 12, 13 }); +} + + +/* +** g_v8qi: +** fmov h0, h0 +** ret +*/ +v8qi +g_v8qi (v8qi x) +{ + return __builtin_shuffle ((v8qi){ 0, 0, 0, 0, 0, 0, 0, 0 }, x, + (v8qi){ 8, 9, 0, 1, 2, 3, 4, 5 }); +} + +/* +** h_v16qi: +** fmov h0, h0 +** ret +*/ +v16qi +h_v16qi (v16qi x) +{ + return __builtin_shuffle ( + x, (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + (v16qi){ 0, 1, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 }); +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-5-be.c b/gcc/testsuite/gcc.target/aarch64/fmov-5-be.c new file mode 100644 index 0000000..0fcefa7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-5-be.c @@ -0,0 +1,150 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbig-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8.2-a+fp16") + +typedef __fp16 v4hf __attribute__ ((vector_size (8))); +typedef __fp16 v8hf __attribute__ ((vector_size (16))); +typedef __bf16 v4bf __attribute__ ((vector_size (8))); +typedef __bf16 v8bf __attribute__ ((vector_size (16))); +typedef short v4hi __attribute__ ((vector_size (8))); +typedef short v8hi __attribute__ ((vector_size (16))); + +/* +** f_v4hf: +** fmov h0, h0 +** ret +*/ +v4hf +f_v4hf (v4hf x) +{ + return __builtin_shuffle (x, (v4hf){ 0, 0, 0, 0 }, (v4hi){ 4, 5, 6, 3 }); +} + +/* +** g_v4hf: +** fmov h0, h0 +** ret +*/ +v4hf +g_v4hf (v4hf x) +{ + return __builtin_shuffle ((v4hf){ 0, 0, 0, 0 }, x, (v4hi){ 0, 1, 2, 7 }); +} + +/* +** h_v4hf: +** fmov s0, s0 +** ret +*/ +v4hf +h_v4hf (v4hf x) +{ + return __builtin_shuffle (x, (v4hf){ 0, 0, 0, 0 }, (v4hi){ 4, 5, 2, 3 }); +} + +/* +** f_v8hf: +** fmov h0, h0 +** ret +*/ +v8hf +f_v8hf (v8hf x) +{ + return __builtin_shuffle (x, (v8hf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 8, 9, 10, 11, 12, 13, 14, 7 }); +} + +/* +** g_v8hf: +** fmov h0, h0 +** ret +*/ +v8hf +g_v8hf (v8hf x) +{ + return __builtin_shuffle ((v8hf){ 0, 0, 0, 0, 0, 0, 0, 0 }, x, + (v8hi){ 0, 1, 2, 3, 4, 5, 6, 15 }); +} + +/* +** h_v8hf: +** fmov s0, s0 +** ret +*/ +v8hf +h_v8hf (v8hf x) +{ + return __builtin_shuffle (x, (v8hf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 8, 9, 10, 11, 12, 13, 6, 7 }); +} + +/* +** f_v4bf: +** fmov h0, h0 +** ret +*/ +v4bf +f_v4bf (v4bf x) +{ + return __builtin_shuffle (x, (v4bf){ 0, 0, 0, 0 }, (v4hi){ 4, 5, 6, 3 }); +} + +/* +** g_v4bf: +** fmov h0, h0 +** ret +*/ +v4bf +g_v4bf (v4bf x) +{ + return __builtin_shuffle ((v4bf){ 0, 0, 0, 0 }, x, (v4hi){ 0, 1, 2, 7 }); +} + +/* +** h_v4bf: +** fmov s0, s0 +** ret +*/ +v4bf +h_v4bf (v4bf x) +{ + return __builtin_shuffle (x, (v4bf){ 0, 0, 0, 0 }, (v4hi){ 4, 5, 2, 3 }); +} + +/* +** f_v8bf: +** fmov h0, h0 +** ret +*/ +v8bf +f_v8bf (v8bf x) +{ + return __builtin_shuffle (x, (v8bf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 8, 9, 10, 11, 12, 13, 14, 7 }); +} + +/* +** g_v8bf: +** fmov h0, h0 +** ret +*/ +v8bf +g_v8bf (v8bf x) +{ + return __builtin_shuffle ((v8bf){ 0, 0, 0, 0, 0, 0, 0, 0 }, x, + (v8hi){ 0, 1, 2, 3, 4, 5, 6, 15 }); +} + +/* +** h_v8bf: +** fmov s0, s0 +** ret +*/ +v8bf +h_v8bf (v8bf x) +{ + return __builtin_shuffle (x, (v8bf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 8, 9, 10, 11, 12, 13, 6, 7 }); +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-5-le.c b/gcc/testsuite/gcc.target/aarch64/fmov-5-le.c new file mode 100644 index 0000000..e3ad420 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-5-le.c @@ -0,0 +1,150 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlittle-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8.2-a+fp16") + +typedef __fp16 v4hf __attribute__ ((vector_size (8))); +typedef __fp16 v8hf __attribute__ ((vector_size (16))); +typedef __bf16 v4bf __attribute__ ((vector_size (8))); +typedef __bf16 v8bf __attribute__ ((vector_size (16))); +typedef short v4hi __attribute__ ((vector_size (8))); +typedef short v8hi __attribute__ ((vector_size (16))); + +/* +** f_v4hf: +** fmov h0, h0 +** ret +*/ +v4hf +f_v4hf (v4hf x) +{ + return __builtin_shuffle (x, (v4hf){ 0, 0, 0, 0 }, (v4hi){ 0, 4, 5, 6 }); +} + +/* +** g_v4hf: +** fmov h0, h0 +** ret +*/ +v4hf +g_v4hf (v4hf x) +{ + return __builtin_shuffle ((v4hf){ 0, 0, 0, 0 }, x, (v4hi){ 4, 0, 1, 2 }); +} + +/* +** h_v4hf: +** fmov s0, s0 +** ret +*/ +v4hf +h_v4hf (v4hf x) +{ + return __builtin_shuffle (x, (v4hf){ 0, 0, 0, 0 }, (v4hi){ 0, 1, 4, 5 }); +} + +/* +** f_v8hf: +** fmov h0, h0 +** ret +*/ +v8hf +f_v8hf (v8hf x) +{ + return __builtin_shuffle (x, (v8hf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 8, 9, 10, 11, 12, 13, 14 }); +} + +/* +** g_v8hf: +** fmov h0, h0 +** ret +*/ +v8hf +g_v8hf (v8hf x) +{ + return __builtin_shuffle ((v8hf){ 0, 0, 0, 0, 0, 0, 0, 0 }, x, + (v8hi){ 8, 0, 1, 2, 3, 4, 5, 6 }); +} + +/* +** h_v8hf: +** fmov s0, s0 +** ret +*/ +v8hf +h_v8hf (v8hf x) +{ + return __builtin_shuffle (x, (v8hf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 1, 8, 9, 10, 11, 12, 13 }); +} + +/* +** f_v4bf: +** fmov h0, h0 +** ret +*/ +v4bf +f_v4bf (v4bf x) +{ + return __builtin_shuffle (x, (v4bf){ 0, 0, 0, 0 }, (v4hi){ 0, 4, 5, 6 }); +} + +/* +** g_v4bf: +** fmov h0, h0 +** ret +*/ +v4bf +g_v4bf (v4bf x) +{ + return __builtin_shuffle ((v4bf){ 0, 0, 0, 0 }, x, (v4hi){ 4, 0, 1, 2 }); +} + +/* +** h_v4bf: +** fmov s0, s0 +** ret +*/ +v4bf +h_v4bf (v4bf x) +{ + return __builtin_shuffle (x, (v4bf){ 0, 0, 0, 0 }, (v4hi){ 0, 1, 4, 5 }); +} + +/* +** f_v8bf: +** fmov h0, h0 +** ret +*/ +v8bf +f_v8bf (v8bf x) +{ + return __builtin_shuffle (x, (v8bf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 8, 9, 10, 11, 12, 13, 14 }); +} + +/* +** g_v8bf: +** fmov h0, h0 +** ret +*/ +v8bf +g_v8bf (v8bf x) +{ + return __builtin_shuffle ((v8bf){ 0, 0, 0, 0, 0, 0, 0, 0 }, x, + (v8hi){ 8, 0, 1, 2, 3, 4, 5, 6 }); +} + +/* +** h_v8bf: +** fmov s0, s0 +** ret +*/ +v8bf +h_v8bf (v8bf x) +{ + return __builtin_shuffle (x, (v8bf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 1, 8, 9, 10, 11, 12, 13 }); +} diff --git a/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-0.c b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-0.c new file mode 100644 index 0000000..e544b04f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-0.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target mmap } */ +/* { dg-options "-Wno-experimental-fmv-target" } */ + +#include <stdint.h> + +typedef struct { + uint64_t size; +} ifunc_arg_t; + +#include "ifunc-resolver.in" diff --git a/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-1.c b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-1.c new file mode 100644 index 0000000..be70687 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target mmap } */ +/* { dg-options "-Wno-experimental-fmv-target" } */ + +#include <stdint.h> + +typedef struct { + uint64_t size; + uint64_t hwcap; +} ifunc_arg_t; + +#include "ifunc-resolver.in" diff --git a/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-2.c b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-2.c new file mode 100644 index 0000000..bf594d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-2.c @@ -0,0 +1,14 @@ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target mmap } */ +/* { dg-options "-Wno-experimental-fmv-target" } */ + +#include <stdint.h> + +typedef struct { + uint64_t size; + uint64_t hwcap; + uint64_t hwcap2; +} ifunc_arg_t; + +#include "ifunc-resolver.in" diff --git a/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-3.c b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-3.c new file mode 100644 index 0000000..f16d01b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-3.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target mmap } */ +/* { dg-options "-Wno-experimental-fmv-target" } */ + +#include <stdint.h> + +typedef struct { + uint64_t size; + uint64_t hwcap; + uint64_t hwcap2; + uint64_t hwcap3; +} ifunc_arg_t; + +#include "ifunc-resolver.in" diff --git a/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-4.c b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-4.c new file mode 100644 index 0000000..1b4ccbd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-4.c @@ -0,0 +1,16 @@ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target mmap } */ +/* { dg-options "-Wno-experimental-fmv-target" } */ + +#include <stdint.h> + +typedef struct { + uint64_t size; + uint64_t hwcap; + uint64_t hwcap2; + uint64_t hwcap3; + uint64_t hwcap4; +} ifunc_arg_t; + +#include "ifunc-resolver.in" diff --git a/gcc/testsuite/gcc.target/aarch64/ifunc-resolver.in b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver.in new file mode 100644 index 0000000..ada0b33 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver.in @@ -0,0 +1,48 @@ +#include <unistd.h> +#include <string.h> +#include <sys/mman.h> + +/* Allocate memory buffer of size LEN with a protected page + following right after the buffer end so that any memory + accesses past the end of the buffer would trigger SEGFAUL. */ +void *allocate_mem (size_t len) +{ + size_t pagesize = sysconf (_SC_PAGESIZE); + char *m = mmap (NULL, pagesize * 2, + PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, + -1, 0); + mprotect (m + pagesize, pagesize, PROT_NONE); + m = m + pagesize - len; + memset(m, 0, len); + return m; +} + +int impl () +{ + return 0; +} + +#ifndef _IFUNC_ARG_HWCAP +#define _IFUNC_ARG_HWCAP (1ULL << 62) +#endif + +void +__init_cpu_features_resolver (unsigned long hwcap, const void *arg); + +static void * +fun_resolver (uint64_t a0, const uint64_t *a1) +{ + ifunc_arg_t *arg = allocate_mem (sizeof (ifunc_arg_t)); + arg->size = sizeof (ifunc_arg_t); + /* Call this function with synthetic ifunc_arg_t arg. */ + __init_cpu_features_resolver (_IFUNC_ARG_HWCAP, arg); + return (void *)(uintptr_t)impl; +} + +int fun (void) __attribute__ ((ifunc ("fun_resolver"))); + +int main (int argc, char *argv[]) +{ + return fun (); +} diff --git a/gcc/testsuite/gcc.target/aarch64/imm_choice_comparison-2.c b/gcc/testsuite/gcc.target/aarch64/imm_choice_comparison-2.c new file mode 100644 index 0000000..379fc50 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/imm_choice_comparison-2.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* PR target/120372 */ + +/* Go from 2 moves to none. */ + +/* +** GT: +** ... +** cmp w0, 11182080 +** ... +*/ + +int +GT (unsigned int x) +{ + return x > 0xaa9fff; +} + +/* +** LE: +** ... +** cmp w0, 11182080 +** ... +*/ + +int +LE (unsigned int x) +{ + return x <= 0xaa9fff; +} + +/* +** GE: +** ... +** cmp x0, 11182080 +** ... +*/ + +int +GE (long long x) +{ + return x >= 0xaaa000; +} + +/* +** LT: +** ... +** cmp w0, 11182080 +** ... +*/ + +int +LT (int x) +{ + return x < 0xaaa000; +} + +/* Optimize the immediate in conditionals. */ + +/* +** check: +** ... +** cmp w0, 11182080 +** ... +*/ + +int +check (int x, int y) +{ + if (x > y && GT (x)) + return 100; + + return x; +} + +/* +** tern: +** ... +** cmp w0, 11182080 +** ... +*/ + +int +tern (int x) +{ + return x >= 0xaaa000 ? 5 : -3; +} diff --git a/gcc/testsuite/gcc.target/aarch64/inszero_split_1.c b/gcc/testsuite/gcc.target/aarch64/inszero_split_1.c new file mode 100644 index 0000000..5c739bd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/inszero_split_1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* Avoid INS from WZR register when optimizing for speed. */ + +#include <arm_neon.h> + +/* +** foo: +** movi? [vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0 +** ins v0.h\[2\], v(\1).h\[0\] +** ret +*/ +uint16x8_t foo(uint16x8_t a) { + a[2] = 0; + return a; +} diff --git a/gcc/testsuite/gcc.target/aarch64/ldapr-sext.c b/gcc/testsuite/gcc.target/aarch64/ldapr-sext.c index f57c09d..e8a545a 100644 --- a/gcc/testsuite/gcc.target/aarch64/ldapr-sext.c +++ b/gcc/testsuite/gcc.target/aarch64/ldapr-sext.c @@ -33,7 +33,7 @@ TEST(s8_s64, s8, long long) /* **test_s16_s64: **... -** ldapursh x0, \[x[0-9]+\] +** ldapursh x0, \[x[0-9]+, [0-9]+\] ** ret */ @@ -42,7 +42,7 @@ TEST(s16_s64, s16, long long) /* **test_s32_s64: **... -** ldapursw x0, \[x[0-9]+\] +** ldapursw x0, \[x[0-9]+, [0-9]+\] ** ret */ @@ -60,7 +60,7 @@ TEST(s8_s32, s8, int) /* **test_s16_s32: **... -** ldapursh w0, \[x[0-9]+\] +** ldapursh w0, \[x[0-9]+, [0-9]+\] ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/ldapur.c b/gcc/testsuite/gcc.target/aarch64/ldapur.c new file mode 100644 index 0000000..5c68bdd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ldapur.c @@ -0,0 +1,77 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -std=c99" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include <stdatomic.h> +#include <stdint.h> + +#pragma GCC target "arch=armv8.8-a" + +atomic_ullong u64; +atomic_uint u32; +atomic_ushort u16; +atomic_uchar u8[2]; /* Force an offset for u8 */ + +#define TEST(name, ldsize, rettype) \ +rettype \ +test_##name (void) \ +{ \ + return atomic_load_explicit (&ldsize, memory_order_acquire); \ +} \ + + +/* +** test_u8_u64: +** ... +** ldapurb w[0-9]+, \[x[0-9]+, [0-9]+\] +** ret +*/ +TEST(u8_u64, u8[1], uint64_t) + +/* +** test_u16_u64: +** ... +** ldapurh w[0-9]+, \[x[0-9]+, [0-9]+\] +** ret +*/ +TEST(u16_u64, u16, uint64_t) + +/* +**test_u32_u64: +** ... +** ldapur w[0-9]+, \[x[0-9]+, [0-9]+\] +** ret +*/ +TEST(u32_u64, u32, uint64_t) + +/* +**test_u64_u64: +** ... +** ldapur x[0-9]+, \[x[0-9]+, [0-9]+\] +** ret +*/ +TEST(u64_u64, u64, uint64_t) + +/* +**test_u8_u32: +** ... +** ldapurb w[0-9]+, \[x[0-9]+, [0-9]+\] +** ret +*/ +TEST(u8_u32, u8[1], uint32_t) + +/* +**test_u16_u32: +** ... +** ldapurh w[0-9]+, \[x[0-9]+, [0-9]+\] +** ret +*/ +TEST(u16_u32, u16, uint32_t) + +/* +**test_u32_u32: +** ... +** ldapur w[0-9]+, \[x[0-9]+, [0-9]+\] +** ret +*/ +TEST(u32_u32, u32, uint32_t)
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/aarch64/ldapur_avoid.c b/gcc/testsuite/gcc.target/aarch64/ldapur_avoid.c new file mode 100644 index 0000000..ad87a30 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ldapur_avoid.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -std=c99 -moverride=tune=avoid_ldapur" } */ + +#include <stdatomic.h> +#include <stdint.h> + +#pragma GCC target "arch=armv8.8-a" +/* LDAPUR is only avoided for armv8.4 to armv8.7. This checks for the working +of avoid_ldapur flag. */ + +/* { dg-final { scan-assembler-not "ldapur\t" } } */ + +atomic_ullong u64; +atomic_uint u32; +atomic_ushort u16; +atomic_uchar u8[2]; /* Force an offset for u8 */ + +#define TEST(name, ldsize, rettype) \ +rettype \ +test_##name (void) \ +{ \ + return atomic_load_explicit (&ldsize, memory_order_acquire); \ +} \ + +TEST(u8_u64, u8[1], uint64_t) +TEST(u16_u64, u16, uint64_t) +TEST(u32_u64, u32, uint64_t) +TEST(u64_u64, u64, uint64_t) +TEST(u8_u32, u8[1], uint32_t) +TEST(u16_u32, u16, uint32_t) +TEST(u32_u32, u32, uint32_t) + +/* { dg-final { scan-assembler-times "ldapr\t" 3 } } */ +/* { dg-final { scan-assembler-times "ldaprh\t" 2 } } */ +/* { dg-final { scan-assembler-times "ldaprb\t" 2 } } */ + + diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt13.c b/gcc/testsuite/gcc.target/aarch64/popcnt13.c new file mode 100644 index 0000000..2a30e98 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/popcnt13.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#pragma GCC target "+nocssc+sve" + +/* +** h128: +** ldr q([0-9]+), \[x0\] +** ptrue p([0-9]+).b, vl16 +** cnt z([0-9]+).d, p\2/m, z\1.d +** addp d([0-9]+), v\3.2d +** fmov x0, d\4 +** ret +*/ + +unsigned h128 (const unsigned __int128 *a) { + return __builtin_popcountg (a[0]); +} + +/* There should be only one POPCOUNT. */ +/* { dg-final { scan-tree-dump-times "POPCOUNT " 1 "optimized" } } */ +/* { dg-final { scan-tree-dump-not " __builtin_popcount" "optimized" } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt9.c b/gcc/testsuite/gcc.target/aarch64/popcnt9.c index c778fc7..cfed8c5 100644 --- a/gcc/testsuite/gcc.target/aarch64/popcnt9.c +++ b/gcc/testsuite/gcc.target/aarch64/popcnt9.c @@ -3,7 +3,7 @@ /* { dg-final { check-function-bodies "**" "" } } */ /* PR target/113042 */ -#pragma GCC target "+nocssc" +#pragma GCC target "+nocssc+nosve" /* ** h128: diff --git a/gcc/testsuite/gcc.target/aarch64/pr113027-1.c b/gcc/testsuite/gcc.target/aarch64/pr113027-1.c new file mode 100644 index 0000000..6d9a51f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr113027-1.c @@ -0,0 +1,27 @@ +/* { dg-options "-O2" } */ + +#include <arm_neon.h> + +float64x2x2_t +f1 (float64x2x2_t x) +{ + x.val[0][1] += 1.0; + return x; +} + +float64x2x3_t +f2 (float64x2x3_t x) +{ + x.val[0][0] = x.val[1][1] + x.val[2][0]; + return x; +} + +float64x2x4_t +f3 (float64x2x4_t x) +{ + x.val[0][0] = x.val[1][1] + x.val[2][0] - x.val[3][1]; + return x; +} + +/* { dg-final { scan-assembler-not {\tmov\t} } } */ +/* { dg-final { scan-assembler-not {\[sp,} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr113027-2.c b/gcc/testsuite/gcc.target/aarch64/pr113027-2.c new file mode 100644 index 0000000..ec756ec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr113027-2.c @@ -0,0 +1,268 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" { target aarch64_little_endian } } } */ + +#include <arm_neon.h> + +#define TEST(TYPE, A, B, C, D) \ + TYPE \ + test_##TYPE (TYPE a) \ + { \ + a.val[A][B] = a.val[C][D]; \ + return a; \ + } + +/* +** test_bfloat16x4x2_t: +** ins v1\.h\[3\], v0\.h\[2\] +** ret +*/ +TEST (bfloat16x4x2_t, 1, 3, 0, 2) + +/* +** test_float16x4x2_t: +** ins v1\.h\[1\], v0\.h\[3\] +** ret +*/ +TEST (float16x4x2_t, 1, 1, 0, 3) + +/* +** test_float32x2x2_t: +** ins v1\.s\[0\], v0\.s\[1\] +** ret +*/ +TEST (float32x2x2_t, 1, 0, 0, 1) + +/* +** test_float64x1x2_t: +** fmov d1, d0 +** ret +*/ +TEST (float64x1x2_t, 1, 0, 0, 0) + +/* +** test_int8x8x2_t: +** ins v0\.b\[5\], v1\.b\[7\] +** ret +*/ +TEST (int8x8x2_t, 0, 5, 1, 7) + +/* +** test_int16x4x2_t: +** ins v0\.h\[2\], v1\.h\[2\] +** ret +*/ +TEST (int16x4x2_t, 0, 2, 1, 2) + +/* +** test_int32x2x2_t: +** ins v0\.s\[0\], v1\.s\[1\] +** ret +*/ +TEST (int32x2x2_t, 0, 0, 1, 1) + +/* +** test_int64x1x2_t: +** fmov d0, d1 +** ret +*/ +TEST (int64x1x2_t, 0, 0, 1, 0) + +/* +** test_uint8x8x2_t: +** ins v1\.b\[6\], v0\.b\[3\] +** ret +*/ +TEST (uint8x8x2_t, 1, 6, 0, 3) + +/* +** test_uint16x4x2_t: +** ins v1\.h\[2\], v1\.h\[0\] +** ret +*/ +TEST (uint16x4x2_t, 1, 2, 1, 0) + +/* +** test_uint32x2x2_t: +** ins v1\.s\[0\], v1\.s\[1\] +** ret +*/ +TEST (uint32x2x2_t, 1, 0, 1, 1) + +/* +** test_uint64x1x2_t: +** fmov d1, d0 +** ret +*/ +TEST (uint64x1x2_t, 1, 0, 0, 0) + +//-------------------------------------------------------------- + +/* +** test_bfloat16x4x3_t: +** ins v2\.h\[3\], v0\.h\[2\] +** ret +*/ +TEST (bfloat16x4x3_t, 2, 3, 0, 2) + +/* +** test_float16x4x3_t: +** ins v0\.h\[1\], v1\.h\[3\] +** ret +*/ +TEST (float16x4x3_t, 0, 1, 1, 3) + +/* +** test_float32x2x3_t: +** ins v1\.s\[0\], v2\.s\[1\] +** ret +*/ +TEST (float32x2x3_t, 1, 0, 2, 1) + +/* +** test_float64x1x3_t: +** fmov d1, d2 +** ret +*/ +TEST (float64x1x3_t, 1, 0, 2, 0) + +/* +** test_int8x8x3_t: +** ins v0\.b\[5\], v2\.b\[6\] +** ret +*/ +TEST (int8x8x3_t, 0, 5, 2, 6) + +/* +** test_int16x4x3_t: +** ins v2\.h\[2\], v1\.h\[1\] +** ret +*/ +TEST (int16x4x3_t, 2, 2, 1, 1) + +/* +** test_int32x2x3_t: +** ins v1\.s\[0\], v1\.s\[1\] +** ret +*/ +TEST (int32x2x3_t, 1, 0, 1, 1) + +/* +** test_int64x1x3_t: +** fmov d2, d1 +** ret +*/ +TEST (int64x1x3_t, 2, 0, 1, 0) + +/* +** test_uint8x8x3_t: +** ins v1\.b\[6\], v2\.b\[7\] +** ret +*/ +TEST (uint8x8x3_t, 1, 6, 2, 7) + +/* +** test_uint16x4x3_t: +** ins v2\.h\[2\], v1\.h\[3\] +** ret +*/ +TEST (uint16x4x3_t, 2, 2, 1, 3) + +/* +** test_uint32x2x3_t: +** ins v2\.s\[0\], v0\.s\[1\] +** ret +*/ +TEST (uint32x2x3_t, 2, 0, 0, 1) + +/* +** test_uint64x1x3_t: +** fmov d1, d2 +** ret +*/ +TEST (uint64x1x3_t, 1, 0, 2, 0) + +//-------------------------------------------------------------- + +/* +** test_bfloat16x4x4_t: +** ins v2\.h\[3\], v3\.h\[2\] +** ret +*/ +TEST (bfloat16x4x4_t, 2, 3, 3, 2) + +/* +** test_float16x4x4_t: +** ins v0\.h\[2\], v3\.h\[1\] +** ret +*/ +TEST (float16x4x4_t, 0, 2, 3, 1) + +/* +** test_float32x2x4_t: +** ins v3\.s\[0\], v2\.s\[1\] +** ret +*/ +TEST (float32x2x4_t, 3, 0, 2, 1) + +/* +** test_float64x1x4_t: +** fmov d1, d3 +** ret +*/ +TEST (float64x1x4_t, 1, 0, 3, 0) + +/* +** test_int8x8x4_t: +** ins v0\.b\[4\], v3\.b\[7\] +** ret +*/ +TEST (int8x8x4_t, 0, 4, 3, 7) + +/* +** test_int16x4x4_t: +** ins v3\.h\[3\], v1\.h\[1\] +** ret +*/ +TEST (int16x4x4_t, 3, 3, 1, 1) + +/* +** test_int32x2x4_t: +** ins v1\.s\[0\], v3\.s\[1\] +** ret +*/ +TEST (int32x2x4_t, 1, 0, 3, 1) + +/* +** test_int64x1x4_t: +** fmov d3, d1 +** ret +*/ +TEST (int64x1x4_t, 3, 0, 1, 0) + +/* +** test_uint8x8x4_t: +** ins v3\.b\[6\], v2\.b\[4\] +** ret +*/ +TEST (uint8x8x4_t, 3, 6, 2, 4) + +/* +** test_uint16x4x4_t: +** ins v3\.h\[1\], v1\.h\[3\] +** ret +*/ +TEST (uint16x4x4_t, 3, 1, 1, 3) + +/* +** test_uint32x2x4_t: +** ins v0\.s\[0\], v3\.s\[1\] +** ret +*/ +TEST (uint32x2x4_t, 0, 0, 3, 1) + +/* +** test_uint64x1x4_t: +** fmov d1, d3 +** ret +*/ +TEST (uint64x1x4_t, 1, 0, 3, 0) diff --git a/gcc/testsuite/gcc.target/aarch64/pr113027-3.c b/gcc/testsuite/gcc.target/aarch64/pr113027-3.c new file mode 100644 index 0000000..561e672 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr113027-3.c @@ -0,0 +1,268 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" { target aarch64_little_endian } } } */ + +#include <arm_neon.h> + +#define TEST(TYPE, A, B, C, D) \ + TYPE \ + test_##TYPE (TYPE a) \ + { \ + a.val[A][B] = a.val[C][D]; \ + return a; \ + } + +/* +** test_bfloat16x8x2_t: +** ins v1\.h\[6\], v0\.h\[5\] +** ret +*/ +TEST (bfloat16x8x2_t, 1, 6, 0, 5) + +/* +** test_float16x8x2_t: +** ins v1\.h\[2\], v0\.h\[7\] +** ret +*/ +TEST (float16x8x2_t, 1, 2, 0, 7) + +/* +** test_float32x4x2_t: +** ins v1\.s\[3\], v0\.s\[1\] +** ret +*/ +TEST (float32x4x2_t, 1, 3, 0, 1) + +/* +** test_float64x2x2_t: +** ins v1\.d\[0\], v0\.d\[0\] +** ret +*/ +TEST (float64x2x2_t, 1, 0, 0, 0) + +/* +** test_int8x16x2_t: +** ins v0\.b\[15\], v1\.b\[13\] +** ret +*/ +TEST (int8x16x2_t, 0, 15, 1, 13) + +/* +** test_int16x8x2_t: +** ins v0\.h\[2\], v1\.h\[7\] +** ret +*/ +TEST (int16x8x2_t, 0, 2, 1, 7) + +/* +** test_int32x4x2_t: +** ins v0\.s\[3\], v1\.s\[1\] +** ret +*/ +TEST (int32x4x2_t, 0, 3, 1, 1) + +/* +** test_int64x2x2_t: +** ins v0\.d\[0\], v1\.d\[1\] +** ret +*/ +TEST (int64x2x2_t, 0, 0, 1, 1) + +/* +** test_uint8x16x2_t: +** ins v1\.b\[13\], v0\.b\[11\] +** ret +*/ +TEST (uint8x16x2_t, 1, 13, 0, 11) + +/* +** test_uint16x8x2_t: +** ins v1\.h\[6\], v1\.h\[3\] +** ret +*/ +TEST (uint16x8x2_t, 1, 6, 1, 3) + +/* +** test_uint32x4x2_t: +** ins v1\.s\[3\], v1\.s\[1\] +** ret +*/ +TEST (uint32x4x2_t, 1, 3, 1, 1) + +/* +** test_uint64x2x2_t: +** ins v1\.d\[0\], v1\.d\[1\] +** ret +*/ +TEST (uint64x2x2_t, 1, 0, 1, 1) + +//-------------------------------------------------------------- + +/* +** test_bfloat16x8x3_t: +** ins v2\.h\[3\], v0\.h\[7\] +** ret +*/ +TEST (bfloat16x8x3_t, 2, 3, 0, 7) + +/* +** test_float16x8x3_t: +** ins v0\.h\[4\], v1\.h\[6\] +** ret +*/ +TEST (float16x8x3_t, 0, 4, 1, 6) + +/* +** test_float32x4x3_t: +** ins v1\.s\[2\], v2\.s\[1\] +** ret +*/ +TEST (float32x4x3_t, 1, 2, 2, 1) + +/* +** test_float64x2x3_t: +** ins v1\.d\[0\], v2\.d\[1\] +** ret +*/ +TEST (float64x2x3_t, 1, 0, 2, 1) + +/* +** test_int8x16x3_t: +** ins v0\.b\[9\], v2\.b\[14\] +** ret +*/ +TEST (int8x16x3_t, 0, 9, 2, 14) + +/* +** test_int16x8x3_t: +** ins v2\.h\[6\], v1\.h\[3\] +** ret +*/ +TEST (int16x8x3_t, 2, 6, 1, 3) + +/* +** test_int32x4x3_t: +** ins v1\.s\[3\], v1\.s\[1\] +** ret +*/ +TEST (int32x4x3_t, 1, 3, 1, 1) + +/* +** test_int64x2x3_t: +** ins v2\.d\[1\], v1\.d\[0\] +** ret +*/ +TEST (int64x2x3_t, 2, 1, 1, 0) + +/* +** test_uint8x16x3_t: +** ins v1\.b\[10\], v2\.b\[8\] +** ret +*/ +TEST (uint8x16x3_t, 1, 10, 2, 8) + +/* +** test_uint16x8x3_t: +** ins v2\.h\[5\], v1\.h\[2\] +** ret +*/ +TEST (uint16x8x3_t, 2, 5, 1, 2) + +/* +** test_uint32x4x3_t: +** ins v2\.s\[3\], v0\.s\[1\] +** ret +*/ +TEST (uint32x4x3_t, 2, 3, 0, 1) + +/* +** test_uint64x2x3_t: +** ins v1\.d\[0\], v2\.d\[1\] +** ret +*/ +TEST (uint64x2x3_t, 1, 0, 2, 1) + +//-------------------------------------------------------------- + +/* +** test_bfloat16x8x4_t: +** ins v2\.h\[5\], v3\.h\[6\] +** ret +*/ +TEST (bfloat16x8x4_t, 2, 5, 3, 6) + +/* +** test_float16x8x4_t: +** ins v0\.h\[3\], v3\.h\[5\] +** ret +*/ +TEST (float16x8x4_t, 0, 3, 3, 5) + +/* +** test_float32x4x4_t: +** ins v3\.s\[2\], v2\.s\[1\] +** ret +*/ +TEST (float32x4x4_t, 3, 2, 2, 1) + +/* +** test_float64x2x4_t: +** ins v1\.d\[1\], v3\.d\[0\] +** ret +*/ +TEST (float64x2x4_t, 1, 1, 3, 0) + +/* +** test_int8x16x4_t: +** ins v0\.b\[14\], v3\.b\[10\] +** ret +*/ +TEST (int8x16x4_t, 0, 14, 3, 10) + +/* +** test_int16x8x4_t: +** ins v3\.h\[4\], v1\.h\[6\] +** ret +*/ +TEST (int16x8x4_t, 3, 4, 1, 6) + +/* +** test_int32x4x4_t: +** ins v1\.s\[3\], v3\.s\[1\] +** ret +*/ +TEST (int32x4x4_t, 1, 3, 3, 1) + +/* +** test_int64x2x4_t: +** ins v3\.d\[0\], v2\.d\[0\] +** ret +*/ +TEST (int64x2x4_t, 3, 0, 2, 0) + +/* +** test_uint8x16x4_t: +** ins v3\.b\[13\], v2\.b\[6\] +** ret +*/ +TEST (uint8x16x4_t, 3, 13, 2, 6) + +/* +** test_uint16x8x4_t: +** ins v3\.h\[2\], v1\.h\[7\] +** ret +*/ +TEST (uint16x8x4_t, 3, 2, 1, 7) + +/* +** test_uint32x4x4_t: +** ins v0\.s\[3\], v3\.s\[2\] +** ret +*/ +TEST (uint32x4x4_t, 0, 3, 3, 2) + +/* +** test_uint64x2x4_t: +** ins v1\.d\[0\], v3\.d\[1\] +** ret +*/ +TEST (uint64x2x4_t, 1, 0, 3, 1) diff --git a/gcc/testsuite/gcc.target/aarch64/pr113027-4.c b/gcc/testsuite/gcc.target/aarch64/pr113027-4.c new file mode 100644 index 0000000..67f45df --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr113027-4.c @@ -0,0 +1,268 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" { target aarch64_little_endian } } } */ + +#include <arm_neon.h> + +#define TEST(TYPE, A, B) \ + TYPE \ + test_##TYPE (TYPE a, TYPE *ptr) \ + { \ + a.val[A][B] = ptr->val[0][0]; \ + return a; \ + } + +/* +** test_bfloat16x4x2_t: +** ld1 \{v1\.h\}\[3\], \[x0\] +** ret +*/ +TEST (bfloat16x4x2_t, 1, 3) + +/* +** test_float16x4x2_t: +** ld1 \{v1\.h\}\[1\], \[x0\] +** ret +*/ +TEST (float16x4x2_t, 1, 1) + +/* +** test_float32x2x2_t: +** ld1 \{v1\.s\}\[0\], \[x0\] +** ret +*/ +TEST (float32x2x2_t, 1, 0) + +/* +** test_float64x1x2_t: +** ldr d1, \[x0\] +** ret +*/ +TEST (float64x1x2_t, 1, 0) + +/* +** test_int8x8x2_t: +** ld1 \{v0\.b\}\[5\], \[x0\] +** ret +*/ +TEST (int8x8x2_t, 0, 5) + +/* +** test_int16x4x2_t: +** ld1 \{v0\.h\}\[2\], \[x0\] +** ret +*/ +TEST (int16x4x2_t, 0, 2) + +/* +** test_int32x2x2_t: +** ld1 \{v0\.s\}\[0\], \[x0\] +** ret +*/ +TEST (int32x2x2_t, 0, 0) + +/* +** test_int64x1x2_t: +** ldr d0, \[x0\] +** ret +*/ +TEST (int64x1x2_t, 0, 0) + +/* +** test_uint8x8x2_t: +** ld1 \{v1\.b\}\[6\], \[x0\] +** ret +*/ +TEST (uint8x8x2_t, 1, 6) + +/* +** test_uint16x4x2_t: +** ld1 \{v1\.h\}\[2\], \[x0\] +** ret +*/ +TEST (uint16x4x2_t, 1, 2) + +/* +** test_uint32x2x2_t: +** ld1 \{v1\.s\}\[0\], \[x0\] +** ret +*/ +TEST (uint32x2x2_t, 1, 0) + +/* +** test_uint64x1x2_t: +** ldr d1, \[x0\] +** ret +*/ +TEST (uint64x1x2_t, 1, 0) + +//-------------------------------------------------------------- + +/* +** test_bfloat16x4x3_t: +** ld1 \{v2\.h\}\[3\], \[x0\] +** ret +*/ +TEST (bfloat16x4x3_t, 2, 3) + +/* +** test_float16x4x3_t: +** ld1 \{v0\.h\}\[1\], \[x0\] +** ret +*/ +TEST (float16x4x3_t, 0, 1) + +/* +** test_float32x2x3_t: +** ld1 \{v1\.s\}\[0\], \[x0\] +** ret +*/ +TEST (float32x2x3_t, 1, 0) + +/* +** test_float64x1x3_t: +** ldr d1, \[x0\] +** ret +*/ +TEST (float64x1x3_t, 1, 0) + +/* +** test_int8x8x3_t: +** ld1 \{v0\.b\}\[5\], \[x0\] +** ret +*/ +TEST (int8x8x3_t, 0, 5) + +/* +** test_int16x4x3_t: +** ld1 \{v2\.h\}\[2\], \[x0\] +** ret +*/ +TEST (int16x4x3_t, 2, 2) + +/* +** test_int32x2x3_t: +** ld1 \{v1\.s\}\[0\], \[x0\] +** ret +*/ +TEST (int32x2x3_t, 1, 0) + +/* +** test_int64x1x3_t: +** ldr d2, \[x0\] +** ret +*/ +TEST (int64x1x3_t, 2, 0) + +/* +** test_uint8x8x3_t: +** ld1 \{v1\.b\}\[6\], \[x0\] +** ret +*/ +TEST (uint8x8x3_t, 1, 6) + +/* +** test_uint16x4x3_t: +** ld1 \{v2\.h\}\[2\], \[x0\] +** ret +*/ +TEST (uint16x4x3_t, 2, 2) + +/* +** test_uint32x2x3_t: +** ld1 \{v2\.s\}\[0\], \[x0\] +** ret +*/ +TEST (uint32x2x3_t, 2, 0) + +/* +** test_uint64x1x3_t: +** ldr d1, \[x0\] +** ret +*/ +TEST (uint64x1x3_t, 1, 0) + +//-------------------------------------------------------------- + +/* +** test_bfloat16x4x4_t: +** ld1 \{v2\.h\}\[3\], \[x0\] +** ret +*/ +TEST (bfloat16x4x4_t, 2, 3) + +/* +** test_float16x4x4_t: +** ld1 \{v0\.h\}\[2\], \[x0\] +** ret +*/ +TEST (float16x4x4_t, 0, 2) + +/* +** test_float32x2x4_t: +** ld1 \{v3\.s\}\[0\], \[x0\] +** ret +*/ +TEST (float32x2x4_t, 3, 0) + +/* +** test_float64x1x4_t: +** ldr d1, \[x0\] +** ret +*/ +TEST (float64x1x4_t, 1, 0) + +/* +** test_int8x8x4_t: +** ld1 \{v0\.b\}\[4\], \[x0\] +** ret +*/ +TEST (int8x8x4_t, 0, 4) + +/* +** test_int16x4x4_t: +** ld1 \{v3\.h\}\[3\], \[x0\] +** ret +*/ +TEST (int16x4x4_t, 3, 3) + +/* +** test_int32x2x4_t: +** ld1 \{v1\.s\}\[0\], \[x0\] +** ret +*/ +TEST (int32x2x4_t, 1, 0) + +/* +** test_int64x1x4_t: +** ldr d3, \[x0\] +** ret +*/ +TEST (int64x1x4_t, 3, 0) + +/* +** test_uint8x8x4_t: +** ld1 \{v3\.b\}\[6\], \[x0\] +** ret +*/ +TEST (uint8x8x4_t, 3, 6) + +/* +** test_uint16x4x4_t: +** ld1 \{v3\.h\}\[1\], \[x0\] +** ret +*/ +TEST (uint16x4x4_t, 3, 1) + +/* +** test_uint32x2x4_t: +** ld1 \{v0\.s\}\[0\], \[x0\] +** ret +*/ +TEST (uint32x2x4_t, 0, 0) + +/* +** test_uint64x1x4_t: +** ldr d1, \[x0\] +** ret +*/ +TEST (uint64x1x4_t, 1, 0) diff --git a/gcc/testsuite/gcc.target/aarch64/pr113027-5.c b/gcc/testsuite/gcc.target/aarch64/pr113027-5.c new file mode 100644 index 0000000..5695eca --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr113027-5.c @@ -0,0 +1,268 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" { target aarch64_little_endian } } } */ + +#include <arm_neon.h> + +#define TEST(TYPE, A, B) \ + TYPE \ + test_##TYPE (TYPE a, TYPE *ptr) \ + { \ + a.val[A][B] = ptr->val[0][0]; \ + return a; \ + } + +/* +** test_bfloat16x8x2_t: +** ld1 \{v1\.h\}\[6\], \[x0\] +** ret +*/ +TEST (bfloat16x8x2_t, 1, 6) + +/* +** test_float16x8x2_t: +** ld1 \{v1\.h\}\[2\], \[x0\] +** ret +*/ +TEST (float16x8x2_t, 1, 2) + +/* +** test_float32x4x2_t: +** ld1 \{v1\.s\}\[3\], \[x0\] +** ret +*/ +TEST (float32x4x2_t, 1, 3) + +/* +** test_float64x2x2_t: +** ld1 \{v1\.d\}\[0\], \[x0\] +** ret +*/ +TEST (float64x2x2_t, 1, 0) + +/* +** test_int8x16x2_t: +** ld1 \{v0\.b\}\[15\], \[x0\] +** ret +*/ +TEST (int8x16x2_t, 0, 15) + +/* +** test_int16x8x2_t: +** ld1 \{v0\.h\}\[2\], \[x0\] +** ret +*/ +TEST (int16x8x2_t, 0, 2) + +/* +** test_int32x4x2_t: +** ld1 \{v0\.s\}\[3\], \[x0\] +** ret +*/ +TEST (int32x4x2_t, 0, 3) + +/* +** test_int64x2x2_t: +** ld1 \{v0\.d\}\[0\], \[x0\] +** ret +*/ +TEST (int64x2x2_t, 0, 0) + +/* +** test_uint8x16x2_t: +** ld1 \{v1\.b\}\[13\], \[x0\] +** ret +*/ +TEST (uint8x16x2_t, 1, 13) + +/* +** test_uint16x8x2_t: +** ld1 \{v1\.h\}\[6\], \[x0\] +** ret +*/ +TEST (uint16x8x2_t, 1, 6) + +/* +** test_uint32x4x2_t: +** ld1 \{v1\.s\}\[3\], \[x0\] +** ret +*/ +TEST (uint32x4x2_t, 1, 3) + +/* +** test_uint64x2x2_t: +** ld1 \{v1\.d\}\[0\], \[x0\] +** ret +*/ +TEST (uint64x2x2_t, 1, 0) + +//-------------------------------------------------------------- + +/* +** test_bfloat16x8x3_t: +** ld1 \{v2\.h\}\[3\], \[x0\] +** ret +*/ +TEST (bfloat16x8x3_t, 2, 3) + +/* +** test_float16x8x3_t: +** ld1 \{v0\.h\}\[4\], \[x0\] +** ret +*/ +TEST (float16x8x3_t, 0, 4) + +/* +** test_float32x4x3_t: +** ld1 \{v1\.s\}\[2\], \[x0\] +** ret +*/ +TEST (float32x4x3_t, 1, 2) + +/* +** test_float64x2x3_t: +** ld1 \{v1\.d\}\[0\], \[x0\] +** ret +*/ +TEST (float64x2x3_t, 1, 0) + +/* +** test_int8x16x3_t: +** ld1 \{v0\.b\}\[9\], \[x0\] +** ret +*/ +TEST (int8x16x3_t, 0, 9) + +/* +** test_int16x8x3_t: +** ld1 \{v2\.h\}\[6\], \[x0\] +** ret +*/ +TEST (int16x8x3_t, 2, 6) + +/* +** test_int32x4x3_t: +** ld1 \{v1\.s\}\[3\], \[x0\] +** ret +*/ +TEST (int32x4x3_t, 1, 3) + +/* +** test_int64x2x3_t: +** ld1 \{v2\.d\}\[1\], \[x0\] +** ret +*/ +TEST (int64x2x3_t, 2, 1) + +/* +** test_uint8x16x3_t: +** ld1 \{v1\.b\}\[10\], \[x0\] +** ret +*/ +TEST (uint8x16x3_t, 1, 10) + +/* +** test_uint16x8x3_t: +** ld1 \{v2\.h\}\[5\], \[x0\] +** ret +*/ +TEST (uint16x8x3_t, 2, 5) + +/* +** test_uint32x4x3_t: +** ld1 \{v2\.s\}\[3\], \[x0\] +** ret +*/ +TEST (uint32x4x3_t, 2, 3) + +/* +** test_uint64x2x3_t: +** ld1 \{v1\.d\}\[0\], \[x0\] +** ret +*/ +TEST (uint64x2x3_t, 1, 0) + +//-------------------------------------------------------------- + +/* +** test_bfloat16x8x4_t: +** ld1 \{v2\.h\}\[5\], \[x0\] +** ret +*/ +TEST (bfloat16x8x4_t, 2, 5) + +/* +** test_float16x8x4_t: +** ld1 \{v0\.h\}\[3\], \[x0\] +** ret +*/ +TEST (float16x8x4_t, 0, 3) + +/* +** test_float32x4x4_t: +** ld1 \{v3\.s\}\[2\], \[x0\] +** ret +*/ +TEST (float32x4x4_t, 3, 2) + +/* +** test_float64x2x4_t: +** ld1 \{v1\.d\}\[1\], \[x0\] +** ret +*/ +TEST (float64x2x4_t, 1, 1) + +/* +** test_int8x16x4_t: +** ld1 \{v0\.b\}\[14\], \[x0\] +** ret +*/ +TEST (int8x16x4_t, 0, 14) + +/* +** test_int16x8x4_t: +** ld1 \{v3\.h\}\[4\], \[x0\] +** ret +*/ +TEST (int16x8x4_t, 3, 4) + +/* +** test_int32x4x4_t: +** ld1 \{v1\.s\}\[3\], \[x0\] +** ret +*/ +TEST (int32x4x4_t, 1, 3) + +/* +** test_int64x2x4_t: +** ld1 \{v3\.d\}\[0\], \[x0\] +** ret +*/ +TEST (int64x2x4_t, 3, 0) + +/* +** test_uint8x16x4_t: +** ld1 \{v3\.b\}\[13\], \[x0\] +** ret +*/ +TEST (uint8x16x4_t, 3, 13) + +/* +** test_uint16x8x4_t: +** ld1 \{v3\.h\}\[2\], \[x0\] +** ret +*/ +TEST (uint16x8x4_t, 3, 2) + +/* +** test_uint32x4x4_t: +** ld1 \{v0\.s\}\[3\], \[x0\] +** ret +*/ +TEST (uint32x4x4_t, 0, 3) + +/* +** test_uint64x2x4_t: +** ld1 \{v1\.d\}\[0\], \[x0\] +** ret +*/ +TEST (uint64x2x4_t, 1, 0) diff --git a/gcc/testsuite/gcc.target/aarch64/pr113027-6.c b/gcc/testsuite/gcc.target/aarch64/pr113027-6.c new file mode 100644 index 0000000..12d3a38 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr113027-6.c @@ -0,0 +1,267 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" { target aarch64_little_endian } } } */ + +#include <arm_neon.h> + +#define TEST(TYPE, A, B) \ + void \ + test_##TYPE (TYPE a, TYPE *ptr) \ + { \ + ptr->val[0][0] = a.val[A][B]; \ + } + +/* +** test_bfloat16x4x2_t: +** st1 \{v1\.h\}\[3\], \[x0\] +** ret +*/ +TEST (bfloat16x4x2_t, 1, 3) + +/* +** test_float16x4x2_t: +** st1 \{v1\.h\}\[1\], \[x0\] +** ret +*/ +TEST (float16x4x2_t, 1, 1) + +/* +** test_float32x2x2_t: +** str s1, \[x0\] +** ret +*/ +TEST (float32x2x2_t, 1, 0) + +/* +** test_float64x1x2_t: +** str d1, \[x0\] +** ret +*/ +TEST (float64x1x2_t, 1, 0) + +/* +** test_int8x8x2_t: +** st1 \{v0\.b\}\[5\], \[x0\] +** ret +*/ +TEST (int8x8x2_t, 0, 5) + +/* +** test_int16x4x2_t: +** st1 \{v0\.h\}\[2\], \[x0\] +** ret +*/ +TEST (int16x4x2_t, 0, 2) + +/* +** test_int32x2x2_t: +** str s0, \[x0\] +** ret +*/ +TEST (int32x2x2_t, 0, 0) + +/* +** test_int64x1x2_t: +** str d0, \[x0\] +** ret +*/ +TEST (int64x1x2_t, 0, 0) + +/* +** test_uint8x8x2_t: +** st1 \{v1\.b\}\[6\], \[x0\] +** ret +*/ +TEST (uint8x8x2_t, 1, 6) + +/* +** test_uint16x4x2_t: +** st1 \{v1\.h\}\[2\], \[x0\] +** ret +*/ +TEST (uint16x4x2_t, 1, 2) + +/* +** test_uint32x2x2_t: +** str s1, \[x0\] +** ret +*/ +TEST (uint32x2x2_t, 1, 0) + +/* +** test_uint64x1x2_t: +** str d1, \[x0\] +** ret +*/ +TEST (uint64x1x2_t, 1, 0) + +//-------------------------------------------------------------- + +/* +** test_bfloat16x4x3_t: +** st1 \{v2\.h\}\[3\], \[x0\] +** ret +*/ +TEST (bfloat16x4x3_t, 2, 3) + +/* +** test_float16x4x3_t: +** st1 \{v0\.h\}\[1\], \[x0\] +** ret +*/ +TEST (float16x4x3_t, 0, 1) + +/* +** test_float32x2x3_t: +** str s1, \[x0\] +** ret +*/ +TEST (float32x2x3_t, 1, 0) + +/* +** test_float64x1x3_t: +** str d1, \[x0\] +** ret +*/ +TEST (float64x1x3_t, 1, 0) + +/* +** test_int8x8x3_t: +** st1 \{v0\.b\}\[5\], \[x0\] +** ret +*/ +TEST (int8x8x3_t, 0, 5) + +/* +** test_int16x4x3_t: +** st1 \{v2\.h\}\[2\], \[x0\] +** ret +*/ +TEST (int16x4x3_t, 2, 2) + +/* +** test_int32x2x3_t: +** str s1, \[x0\] +** ret +*/ +TEST (int32x2x3_t, 1, 0) + +/* +** test_int64x1x3_t: +** str d2, \[x0\] +** ret +*/ +TEST (int64x1x3_t, 2, 0) + +/* +** test_uint8x8x3_t: +** st1 \{v1\.b\}\[6\], \[x0\] +** ret +*/ +TEST (uint8x8x3_t, 1, 6) + +/* +** test_uint16x4x3_t: +** st1 \{v2\.h\}\[2\], \[x0\] +** ret +*/ +TEST (uint16x4x3_t, 2, 2) + +/* +** test_uint32x2x3_t: +** str s2, \[x0\] +** ret +*/ +TEST (uint32x2x3_t, 2, 0) + +/* +** test_uint64x1x3_t: +** str d1, \[x0\] +** ret +*/ +TEST (uint64x1x3_t, 1, 0) + +//-------------------------------------------------------------- + +/* +** test_bfloat16x4x4_t: +** st1 \{v2\.h\}\[3\], \[x0\] +** ret +*/ +TEST (bfloat16x4x4_t, 2, 3) + +/* +** test_float16x4x4_t: +** st1 \{v0\.h\}\[2\], \[x0\] +** ret +*/ +TEST (float16x4x4_t, 0, 2) + +/* +** test_float32x2x4_t: +** str s3, \[x0\] +** ret +*/ +TEST (float32x2x4_t, 3, 0) + +/* +** test_float64x1x4_t: +** str d1, \[x0\] +** ret +*/ +TEST (float64x1x4_t, 1, 0) + +/* +** test_int8x8x4_t: +** st1 \{v0\.b\}\[4\], \[x0\] +** ret +*/ +TEST (int8x8x4_t, 0, 4) + +/* +** test_int16x4x4_t: +** st1 \{v3\.h\}\[3\], \[x0\] +** ret +*/ +TEST (int16x4x4_t, 3, 3) + +/* +** test_int32x2x4_t: +** str s1, \[x0\] +** ret +*/ +TEST (int32x2x4_t, 1, 0) + +/* +** test_int64x1x4_t: +** str d3, \[x0\] +** ret +*/ +TEST (int64x1x4_t, 3, 0) + +/* +** test_uint8x8x4_t: +** st1 \{v3\.b\}\[6\], \[x0\] +** ret +*/ +TEST (uint8x8x4_t, 3, 6) + +/* +** test_uint16x4x4_t: +** st1 \{v3\.h\}\[1\], \[x0\] +** ret +*/ +TEST (uint16x4x4_t, 3, 1) + +/* +** test_uint32x2x4_t: +** str s0, \[x0\] +** ret +*/ +TEST (uint32x2x4_t, 0, 0) + +/* +** test_uint64x1x4_t: +** str d1, \[x0\] +** ret +*/ +TEST (uint64x1x4_t, 1, 0) diff --git a/gcc/testsuite/gcc.target/aarch64/pr113027-7.c b/gcc/testsuite/gcc.target/aarch64/pr113027-7.c new file mode 100644 index 0000000..b3ae1a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr113027-7.c @@ -0,0 +1,267 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" { target aarch64_little_endian } } } */ + +#include <arm_neon.h> + +#define TEST(TYPE, A, B) \ + void \ + test_##TYPE (TYPE a, TYPE *ptr) \ + { \ + ptr->val[0][0] = a.val[A][B]; \ + } + +/* +** test_bfloat16x8x2_t: +** st1 \{v1\.h\}\[6\], \[x0\] +** ret +*/ +TEST (bfloat16x8x2_t, 1, 6) + +/* +** test_float16x8x2_t: +** st1 \{v1\.h\}\[2\], \[x0\] +** ret +*/ +TEST (float16x8x2_t, 1, 2) + +/* +** test_float32x4x2_t: +** st1 \{v1\.s\}\[3\], \[x0\] +** ret +*/ +TEST (float32x4x2_t, 1, 3) + +/* +** test_float64x2x2_t: +** str d1, \[x0\] +** ret +*/ +TEST (float64x2x2_t, 1, 0) + +/* +** test_int8x16x2_t: +** st1 \{v0\.b\}\[15\], \[x0\] +** ret +*/ +TEST (int8x16x2_t, 0, 15) + +/* +** test_int16x8x2_t: +** st1 \{v0\.h\}\[2\], \[x0\] +** ret +*/ +TEST (int16x8x2_t, 0, 2) + +/* +** test_int32x4x2_t: +** st1 \{v0\.s\}\[3\], \[x0\] +** ret +*/ +TEST (int32x4x2_t, 0, 3) + +/* +** test_int64x2x2_t: +** str d0, \[x0\] +** ret +*/ +TEST (int64x2x2_t, 0, 0) + +/* +** test_uint8x16x2_t: +** st1 \{v1\.b\}\[13\], \[x0\] +** ret +*/ +TEST (uint8x16x2_t, 1, 13) + +/* +** test_uint16x8x2_t: +** st1 \{v1\.h\}\[6\], \[x0\] +** ret +*/ +TEST (uint16x8x2_t, 1, 6) + +/* +** test_uint32x4x2_t: +** st1 \{v1\.s\}\[3\], \[x0\] +** ret +*/ +TEST (uint32x4x2_t, 1, 3) + +/* +** test_uint64x2x2_t: +** str d1, \[x0\] +** ret +*/ +TEST (uint64x2x2_t, 1, 0) + +//-------------------------------------------------------------- + +/* +** test_bfloat16x8x3_t: +** st1 \{v2\.h\}\[3\], \[x0\] +** ret +*/ +TEST (bfloat16x8x3_t, 2, 3) + +/* +** test_float16x8x3_t: +** st1 \{v0\.h\}\[4\], \[x0\] +** ret +*/ +TEST (float16x8x3_t, 0, 4) + +/* +** test_float32x4x3_t: +** st1 \{v1\.s\}\[2\], \[x0\] +** ret +*/ +TEST (float32x4x3_t, 1, 2) + +/* +** test_float64x2x3_t: +** str d1, \[x0\] +** ret +*/ +TEST (float64x2x3_t, 1, 0) + +/* +** test_int8x16x3_t: +** st1 \{v0\.b\}\[9\], \[x0\] +** ret +*/ +TEST (int8x16x3_t, 0, 9) + +/* +** test_int16x8x3_t: +** st1 \{v2\.h\}\[6\], \[x0\] +** ret +*/ +TEST (int16x8x3_t, 2, 6) + +/* +** test_int32x4x3_t: +** st1 \{v1\.s\}\[3\], \[x0\] +** ret +*/ +TEST (int32x4x3_t, 1, 3) + +/* +** test_int64x2x3_t: +** st1 \{v2\.d\}\[1\], \[x0\] +** ret +*/ +TEST (int64x2x3_t, 2, 1) + +/* +** test_uint8x16x3_t: +** st1 \{v1\.b\}\[10\], \[x0\] +** ret +*/ +TEST (uint8x16x3_t, 1, 10) + +/* +** test_uint16x8x3_t: +** st1 \{v2\.h\}\[5\], \[x0\] +** ret +*/ +TEST (uint16x8x3_t, 2, 5) + +/* +** test_uint32x4x3_t: +** st1 \{v2\.s\}\[3\], \[x0\] +** ret +*/ +TEST (uint32x4x3_t, 2, 3) + +/* +** test_uint64x2x3_t: +** str d1, \[x0\] +** ret +*/ +TEST (uint64x2x3_t, 1, 0) + +//-------------------------------------------------------------- + +/* +** test_bfloat16x8x4_t: +** st1 \{v2\.h\}\[5\], \[x0\] +** ret +*/ +TEST (bfloat16x8x4_t, 2, 5) + +/* +** test_float16x8x4_t: +** st1 \{v0\.h\}\[3\], \[x0\] +** ret +*/ +TEST (float16x8x4_t, 0, 3) + +/* +** test_float32x4x4_t: +** st1 \{v3\.s\}\[2\], \[x0\] +** ret +*/ +TEST (float32x4x4_t, 3, 2) + +/* +** test_float64x2x4_t: +** st1 \{v1\.d\}\[1\], \[x0\] +** ret +*/ +TEST (float64x2x4_t, 1, 1) + +/* +** test_int8x16x4_t: +** st1 \{v0\.b\}\[14\], \[x0\] +** ret +*/ +TEST (int8x16x4_t, 0, 14) + +/* +** test_int16x8x4_t: +** st1 \{v3\.h\}\[4\], \[x0\] +** ret +*/ +TEST (int16x8x4_t, 3, 4) + +/* +** test_int32x4x4_t: +** st1 \{v1\.s\}\[3\], \[x0\] +** ret +*/ +TEST (int32x4x4_t, 1, 3) + +/* +** test_int64x2x4_t: +** str d3, \[x0\] +** ret +*/ +TEST (int64x2x4_t, 3, 0) + +/* +** test_uint8x16x4_t: +** st1 \{v3\.b\}\[13\], \[x0\] +** ret +*/ +TEST (uint8x16x4_t, 3, 13) + +/* +** test_uint16x8x4_t: +** st1 \{v3\.h\}\[2\], \[x0\] +** ret +*/ +TEST (uint16x8x4_t, 3, 2) + +/* +** test_uint32x4x4_t: +** st1 \{v0\.s\}\[3\], \[x0\] +** ret +*/ +TEST (uint32x4x4_t, 0, 3) + +/* +** test_uint64x2x4_t: +** str d1, \[x0\] +** ret +*/ +TEST (uint64x2x4_t, 1, 0) diff --git a/gcc/testsuite/gcc.target/aarch64/pr118348_1.c b/gcc/testsuite/gcc.target/aarch64/pr118348_1.c index 75f6dad..2715dcb 100644 --- a/gcc/testsuite/gcc.target/aarch64/pr118348_1.c +++ b/gcc/testsuite/gcc.target/aarch64/pr118348_1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target aarch64_sve128_hw } } */ +/* { dg-do run { target { aarch64_sve128_hw && fstack_protector } } } */ /* { dg-options "-O2 -fopenmp-simd -fno-trapping-math -msve-vector-bits=128 --param aarch64-autovec-preference=sve-only -fstack-protector-strong" } */ #pragma GCC target "+sve" diff --git a/gcc/testsuite/gcc.target/aarch64/pr118348_2.c b/gcc/testsuite/gcc.target/aarch64/pr118348_2.c index 2e20004..4ce8d20 100644 --- a/gcc/testsuite/gcc.target/aarch64/pr118348_2.c +++ b/gcc/testsuite/gcc.target/aarch64/pr118348_2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target aarch64_sve256_hw } } */ +/* { dg-do run { target { aarch64_sve256_hw && fstack_protector } } } */ /* { dg-options "-O2 -fopenmp-simd -fno-trapping-math -msve-vector-bits=256 --param aarch64-autovec-preference=sve-only -fstack-protector-strong" } */ #include "pr118348_1.c" diff --git a/gcc/testsuite/gcc.target/aarch64/pr121300.c b/gcc/testsuite/gcc.target/aarch64/pr121300.c new file mode 100644 index 0000000..5f2cd9a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr121300.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-S -O3 -march=armv9-a+sme2" } */ + +#include <arm_sme.h> + +svfloat16x2_t test (svfloat16x2_t zd, svfloat16x2_t zm) __arm_streaming +{ + return svamin_f16_x2 (zd, zm); // { dg-error "ACLE function .svamin_f16_x2. requires ISA extension .faminmax." } +} diff --git a/gcc/testsuite/gcc.target/aarch64/reg-alloc-4.c b/gcc/testsuite/gcc.target/aarch64/reg-alloc-4.c index ceb6f50..0576dc2 100644 --- a/gcc/testsuite/gcc.target/aarch64/reg-alloc-4.c +++ b/gcc/testsuite/gcc.target/aarch64/reg-alloc-4.c @@ -61,7 +61,9 @@ foo (volatile struct L *head, int inc) "r" (inner->next), /* x15 */ "r" (inner->next), /* x16 */ "r" (inner->next), /* x17 */ +#ifndef __vxworks /* x18 is a fixed register on VxWorks, used for the TCB. */ "r" (inner->next), /* x18 */ +#endif "r" (inner->next) : /* x30 */ "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"); diff --git a/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_1.c b/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_1.c index acd2e11..8fc1569 100644 --- a/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_1.c +++ b/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_1.c @@ -4,24 +4,24 @@ /* ** uadd: -** dup v([0-9]+).8b, w1 -** dup v([0-9]+).8b, w0 +** dup v([0-9]+).8b, w[01] +** dup v([0-9]+).8b, w[01] ** uqadd b([0-9]+), (?:b\2, b\1|b\1, b\2) ** umov w0, v\3.b\[0\] ** ret */ /* ** uadd2: -** dup v([0-9]+).8b, w1 -** dup v([0-9]+).8b, w0 +** dup v([0-9]+).8b, w[01] +** dup v([0-9]+).8b, w[01] ** uqadd b([0-9]+), (?:b\2, b\1|b\1, b\2) ** umov w0, v\3.b\[0\] ** ret */ /* ** usub: { xfail *-*-* } -** dup v([0-9]+).8b, w1 -** dup v([0-9]+).8b, w0 +** dup v([0-9]+).8b, w[01] +** dup v([0-9]+).8b, w[01] ** uqsub b([0-9]+), b\1, b\2 ** umov w0, v\3.b\[0\] ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_2.c b/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_2.c index 86c88f8..dd0fefa 100644 --- a/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_2.c +++ b/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_2.c @@ -4,16 +4,16 @@ /* ** uadd: -** dup v([0-9]+).4h, w1 -** dup v([0-9]+).4h, w0 +** dup v([0-9]+).4h, w[01] +** dup v([0-9]+).4h, w[01] ** uqadd h([0-9]+), (?:h\2, h\1|h\1, h\2) ** umov w0, v\3.h\[0\] ** ret */ /* ** uadd2: -** dup v([0-9]+).4h, w1 -** dup v([0-9]+).4h, w0 +** dup v([0-9]+).4h, w[01] +** dup v([0-9]+).4h, w[01] ** uqadd h([0-9]+), (?:h\2, h\1|h\1, h\2) ** umov w0, v\3.h\[0\] ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_1.c b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_1.c index ab68d6e..fb19bd4 100644 --- a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_1.c +++ b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_1.c @@ -3,4 +3,6 @@ int i; -/* { dg-error "'-fsanitize=shadow-call-stack' requires '-ffixed-x18'" "" {target "aarch64*-*-*" } 0 } */ +/* aarch64-*-vxworks has x18 as a fixed register. */ +/* { dg-error "'-fsanitize=shadow-call-stack' requires '-ffixed-x18'" "" { target { aarch64*-*-* && { ! aarch64-*-vxworks* } } } 0 } */ +/* { dg-message "sorry, unimplemented: '-fsanitize=shadow-call-stack' conflicts with the use of register x18" "" { target { aarch64-*-vxworks* } } 0 } */ diff --git a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_2.c b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_2.c index b5139a2..2c381cd 100644 --- a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_2.c +++ b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_2.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-fsanitize=shadow-call-stack -ffixed-x18 -fexceptions" } */ +/* { dg-skip-if "conflicts with x18" { aarch64-*-vxworks* } } */ int i; diff --git a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_3.c b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_3.c index b88e490..95d41e7 100644 --- a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_3.c +++ b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_3.c @@ -3,6 +3,7 @@ /* scs_pop: ldr x30, [x18, #-8]! */ /* { dg-do compile } */ /* { dg-options "-O2 -fsanitize=shadow-call-stack -ffixed-x18 -fno-exceptions" } */ +/* { dg-skip-if "conflicts with x18" { aarch64-*-vxworks* } } */ int foo (int); diff --git a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_4.c b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_4.c index f631693..1e84ab6 100644 --- a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_4.c +++ b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_4.c @@ -3,6 +3,7 @@ /* scs_pop: ldr x30, [x18, #-8]! */ /* { dg-do compile } */ /* { dg-options "-O2 -fno-omit-frame-pointer -fsanitize=shadow-call-stack -ffixed-x18 -fno-exceptions" } */ +/* { dg-skip-if "conflicts with x18" { aarch64-*-vxworks* } } */ int foo (int); diff --git a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_5.c b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_5.c index d7f8298..e76de47 100644 --- a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_5.c +++ b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_5.c @@ -8,6 +8,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fno-omit-frame-pointer -fsanitize=shadow-call-stack -fno-exceptions -ffixed-x18 --save-temps -fno-stack-protector" } */ +/* { dg-skip-if "conflicts with x18" { aarch64-*-vxworks* } } */ #include "test_frame_common.h" diff --git a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_6.c b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_6.c index 8d088ae..3509375 100644 --- a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_6.c +++ b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_6.c @@ -8,6 +8,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fomit-frame-pointer -fsanitize=shadow-call-stack -fno-exceptions -ffixed-x18 --save-temps -fno-stack-protector" } */ +/* { dg-skip-if "conflicts with x18" { aarch64-*-vxworks* } } */ #include "test_frame_common.h" diff --git a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_7.c b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_7.c index a2f376e..9ddd71a 100644 --- a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_7.c +++ b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_7.c @@ -8,6 +8,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fomit-frame-pointer -fsanitize=shadow-call-stack -fno-exceptions -ffixed-x18 --save-temps -fno-stack-protector" } */ +/* { dg-skip-if "conflicts with x18" { aarch64-*-vxworks* } } */ #include "test_frame_common.h" diff --git a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_8.c b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_8.c index 5162cbb..be8d816 100644 --- a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_8.c +++ b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_8.c @@ -10,6 +10,7 @@ /* { dg-do compile } */ /* { dg-options "-O0 -fomit-frame-pointer -fsanitize=shadow-call-stack -fno-exceptions -ffixed-x18 --save-temps -fno-stack-protector" } */ +/* { dg-skip-if "conflicts with x18" { aarch64-*-vxworks* } } */ int func1 (void) { diff --git a/gcc/testsuite/gcc.target/aarch64/simd/bcax_d.c b/gcc/testsuite/gcc.target/aarch64/simd/bcax_d.c new file mode 100644 index 0000000..a7640c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/bcax_d.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_neon.h> + +#pragma GCC target "+sha3" + +#define BCAX(x,y,z) ((x) ^ ((y) & ~(z))) + +/* When the inputs come from GP regs don't form a BCAX. */ +uint64_t bcax_d_gp (uint64_t a, uint64_t b, uint64_t c) { return BCAX (a, b, c); } + +uint64x1_t bcax_d (uint64x1_t a, uint64x1_t b, uint64x1_t c) { return BCAX (a, b, c); } +uint32x2_t bcax_s (uint32x2_t a, uint32x2_t b, uint32x2_t c) { return BCAX (a, b, c); } +uint16x4_t bcax_h (uint16x4_t a, uint16x4_t b, uint16x4_t c) { return BCAX (a, b, c); } +uint8x8_t bcax_b (uint8x8_t a, uint8x8_t b, uint8x8_t c) { return BCAX (a, b, c); } + +/* { dg-final { scan-assembler-times {bcax\tv0.16b, v0.16b, v1.16b, v2.16b} 4 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/simd/eor3_d.c b/gcc/testsuite/gcc.target/aarch64/simd/eor3_d.c new file mode 100644 index 0000000..7f2b2b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/eor3_d.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_neon.h> + +#pragma GCC target "+sha3" + +#define EOR3(x,y,z) ((x) ^ (y) ^ (z)) + +uint32x2_t bcax_s (uint32x2_t a, uint32x2_t b, uint32x2_t c) { return EOR3 (a, b, c); } +uint16x4_t bcax_h (uint16x4_t a, uint16x4_t b, uint16x4_t c) { return EOR3 (a, b, c); } +uint8x8_t bcax_b (uint8x8_t a, uint8x8_t b, uint8x8_t c) { return EOR3 (a, b, c); } + +/* { dg-final { scan-assembler-times {eor3\tv0.16b, v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b} 3 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_1.c b/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_1.c new file mode 100644 index 0000000..f082198 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_1.c @@ -0,0 +1,716 @@ +/* { dg-do compile } */ +/* { dg-options "-O -march=armv9-a+bf16" } */ + +#include <arm_neon.h> + +/* We should use the highpart instruction where doing so would avoid data + movement instructions. This case, where all the arguments are non-constant + vector highparts, can be handled by either gimple_fold_builtin or combine. */ + +#ifndef TEST_UN_HIGHPARTS +#define TEST_UN_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (INTYPE a) \ + { \ + return FN##_##SUFF (vget_high_##SUFF (a)); \ + } +#endif + +#ifndef TEST_BIN_W_HIGHPARTS +#define TEST_BIN_W_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (RETTYPE a, INTYPE b) \ + { \ + return FN##_##SUFF (a, vget_high_##SUFF (b)); \ + } +#endif + +#ifndef TEST_BIN_N_HIGHPARTS +#define TEST_BIN_N_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (INTYPE a) \ + { \ + return FN##_##SUFF (vget_high_##SUFF (a), a[1]); \ + } +#endif + +#ifndef TEST_TERN_N_HIGHPARTS +#define TEST_TERN_N_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (RETTYPE a, INTYPE b) \ + { \ + return FN##_##SUFF (a, vget_high_##SUFF (b), b[1]); \ + } +#endif + +#ifndef TEST_BIN_HIGHPARTS +#define TEST_BIN_HIGHPARTS(FN, RETTYPE, INTYPE, H_INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (INTYPE a, INTYPE b) \ + { \ + return FN##_##SUFF (vget_high_##SUFF (a), \ + vget_high_##SUFF (b)); \ + } +#endif + +#ifndef TEST_TERN_HIGHPARTS +#define TEST_TERN_HIGHPARTS(FN, RETTYPE, INTYPE, H_INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (RETTYPE a, INTYPE b, INTYPE c) \ + { \ + return FN##_##SUFF(a, vget_high_##SUFF (b), \ + vget_high_##SUFF (c)); \ + } +#endif + +#define TEST_UNOP(FN) \ + TEST_UN_HIGHPARTS (FN, int16x8_t, int8x16_t, s8) \ + TEST_UN_HIGHPARTS (FN, uint16x8_t, uint8x16_t, u8) \ + TEST_UN_HIGHPARTS (FN, int32x4_t, int16x8_t, s16) \ + TEST_UN_HIGHPARTS (FN, uint32x4_t, uint16x8_t, u16) \ + TEST_UN_HIGHPARTS (FN, int64x2_t, int32x4_t, s32) \ + TEST_UN_HIGHPARTS (FN, uint64x2_t, uint32x4_t, u32) + +#define TEST_BINOP(FN) \ + TEST_BIN_HIGHPARTS (FN, int16x8_t, int8x16_t, int8x8_t, s8) \ + TEST_BIN_HIGHPARTS (FN, uint16x8_t, uint8x16_t, uint8x8_t, u8) \ + TEST_BIN_HIGHPARTS (FN, int32x4_t, int16x8_t, int16x4_t, s16) \ + TEST_BIN_HIGHPARTS (FN, uint32x4_t, uint16x8_t, uint16x4_t, u16) \ + TEST_BIN_HIGHPARTS (FN, int64x2_t, int32x4_t, int32x2_t, s32) \ + TEST_BIN_HIGHPARTS (FN, uint64x2_t, uint32x4_t, uint32x2_t, u32) + +#define TEST_BINOP_N(FN) \ + TEST_BIN_N_HIGHPARTS (FN, int32x4_t, int16x8_t, s16) \ + TEST_BIN_N_HIGHPARTS (FN, uint32x4_t, uint16x8_t, u16) \ + TEST_BIN_N_HIGHPARTS (FN, int64x2_t, int32x4_t, s32) \ + TEST_BIN_N_HIGHPARTS (FN, uint64x2_t, uint32x4_t, u32) + +#define TEST_BINOP_W(FN) \ + TEST_BIN_W_HIGHPARTS (FN, int16x8_t, int8x16_t, s8) \ + TEST_BIN_W_HIGHPARTS (FN, uint16x8_t, uint8x16_t, u8) \ + TEST_BIN_W_HIGHPARTS (FN, int32x4_t, int16x8_t, s16) \ + TEST_BIN_W_HIGHPARTS (FN, uint32x4_t, uint16x8_t, u16) \ + TEST_BIN_W_HIGHPARTS (FN, int64x2_t, int32x4_t, s32) \ + TEST_BIN_W_HIGHPARTS (FN, uint64x2_t, uint32x4_t, u32) + +#define TEST_TERNOP_N(FN) \ + TEST_TERN_N_HIGHPARTS (FN, int32x4_t, int16x8_t, s16) \ + TEST_TERN_N_HIGHPARTS (FN, uint32x4_t, uint16x8_t, u16) \ + TEST_TERN_N_HIGHPARTS (FN, int64x2_t, int32x4_t, s32) \ + TEST_TERN_N_HIGHPARTS (FN, uint64x2_t, uint32x4_t, u32) + +#define TEST_TERNOP(FN) \ + TEST_TERN_HIGHPARTS (FN, int16x8_t, int8x16_t, int8x8_t, s8) \ + TEST_TERN_HIGHPARTS (FN, uint16x8_t, uint8x16_t, uint8x8_t, u8) \ + TEST_TERN_HIGHPARTS (FN, int32x4_t, int16x8_t, int16x4_t, s16) \ + TEST_TERN_HIGHPARTS (FN, uint32x4_t, uint16x8_t, uint16x4_t, u16) \ + TEST_TERN_HIGHPARTS (FN, int64x2_t, int32x4_t, int32x2_t, s32) \ + TEST_TERN_HIGHPARTS (FN, uint64x2_t, uint32x4_t, uint32x2_t, u32) + +#define TEST_VQDMULL \ + TEST_BIN_HIGHPARTS (vqdmull, int32x4_t, int16x8_t, int16x4_t, s16) \ + TEST_BIN_HIGHPARTS (vqdmull, int64x2_t, int32x4_t, int32x2_t, s32) + +#define TEST_VQDMULL_N \ + TEST_BIN_N_HIGHPARTS (vqdmull_n, int32x4_t, int16x8_t, s16) \ + TEST_BIN_N_HIGHPARTS (vqdmull_n, int64x2_t, int32x4_t, s32) + +#define TEST_VQMLAL \ + TEST_TERN_HIGHPARTS (vqdmlal, int32x4_t, int16x8_t, int16x4_t, s16) \ + TEST_TERN_HIGHPARTS (vqdmlal, int64x2_t, int32x4_t, int32x2_t, s32) + +#define TEST_VQMLAL_N \ + TEST_TERN_N_HIGHPARTS (vqdmlal_n, int32x4_t, int16x8_t, s16) \ + TEST_TERN_N_HIGHPARTS (vqdmlal_n, int64x2_t, int32x4_t, s32) + +#define TEST_VQMLSL \ + TEST_TERN_HIGHPARTS (vqdmlsl, int32x4_t, int16x8_t, int16x4_t, s16) \ + TEST_TERN_HIGHPARTS (vqdmlsl, int64x2_t, int32x4_t, int32x2_t, s32) + +#define TEST_VQMLSL_N \ + TEST_TERN_N_HIGHPARTS (vqdmlsl_n, int32x4_t, int16x8_t, s16) \ + TEST_TERN_N_HIGHPARTS (vqdmlsl_n, int64x2_t, int32x4_t, s32) + +#define TEST_VMOVL \ + TEST_UNOP (vmovl) + +#define TEST_VMULL \ + TEST_BINOP (vmull) \ + TEST_BIN_HIGHPARTS (vmull, poly16x8_t, poly8x16_t, poly8x8_t, p8) + +#define TEST_VMULL_N \ + TEST_BINOP_N (vmull_n) + +#define TEST_VADDL \ + TEST_BINOP (vaddl) + +#define TEST_VSUBL \ + TEST_BINOP (vsubl) + +#define TEST_VMLAL \ + TEST_TERNOP (vmlal) + +#define TEST_VMLAL_N \ + TEST_TERNOP_N (vmlal_n) + +#define TEST_VMLSL \ + TEST_TERNOP (vmlsl) + +#define TEST_VMLSL_N \ + TEST_TERNOP_N (vmlsl_n) + +#define TEST_VABDL \ + TEST_BINOP (vabdl) + +#define TEST_VABAL \ + TEST_TERNOP (vabal) + +#define TEST_VSUBW \ + TEST_BINOP_W (vsubw) + +#define TEST_VADDW \ + TEST_BINOP_W (vaddw) + +/* +** test_vmovl_s8: +** sxtl2 v0\.8h, v0\.16b +** ret +*/ + +/* +** test_vmovl_u8: +** uxtl2 v0\.8h, v0\.16b +** ret +*/ + +/* +** test_vmovl_s16: +** sxtl2 v0\.4s, v0\.8h +** ret +*/ + +/* +** test_vmovl_u16: +** uxtl2 v0\.4s, v0\.8h +** ret +*/ + +/* +** test_vmovl_s32: +** sxtl2 v0\.2d, v0\.4s +** ret +*/ + +/* +** test_vmovl_u32: +** uxtl2 v0\.2d, v0\.4s +** ret +*/ + +TEST_VMOVL + +/* +** test_vmull_s8: +** smull2 v0\.8h, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ + +/* +** test_vmull_u8: +** umull2 v0\.8h, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ + +/* +** test_vmull_s16: +** smull2 v0\.4s, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ + +/* +** test_vmull_u16: +** umull2 v0\.4s, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ + +/* +** test_vmull_s32: +** smull2 v0\.2d, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ + +/* +** test_vmull_u32: +** umull2 v0\.2d, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ + +/* +** test_vmull_p8: +** pmull2 v0\.8h, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ + +TEST_VMULL + +/* +** test_vmull_n_s16: +** smull2 v0\.4s, v0\.8h, v0\.h\[[0-7]\] +** ret +*/ + +/* +** test_vmull_n_u16: +** umull2 v0\.4s, v0\.8h, v0\.h\[[0-7]\] +** ret +*/ + +/* +** test_vmull_n_s32: +** smull2 v0\.2d, v0\.4s, v0\.s\[[0-3]\] +** ret +*/ + +/* +** test_vmull_n_u32: +** umull2 v0\.2d, v0\.4s, v0\.s\[[0-3]\] +** ret +*/ + +TEST_VMULL_N + +/* +** test_vaddl_s8: +** saddl2 v0\.8h, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ + +/* +** test_vaddl_u8: +** uaddl2 v0\.8h, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ + +/* +** test_vaddl_s16: +** saddl2 v0\.4s, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ + +/* +** test_vaddl_u16: +** uaddl2 v0\.4s, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ + +/* +** test_vaddl_s32: +** saddl2 v0\.2d, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ + +/* +** test_vaddl_u32: +** uaddl2 v0\.2d, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ + +TEST_VADDL + +/* +** test_vsubl_s8: +** ssubl2 v0\.8h, v0\.16b, v1\.16b +** ret +*/ + +/* +** test_vsubl_u8: +** usubl2 v0\.8h, v0\.16b, v1\.16b +** ret +*/ + +/* +** test_vsubl_s16: +** ssubl2 v0\.4s, v0\.8h, v1\.8h +** ret +*/ + +/* +** test_vsubl_u16: +** usubl2 v0\.4s, v0\.8h, v1\.8h +** ret +*/ + +/* +** test_vsubl_s32: +** ssubl2 v0\.2d, v0\.4s, v1\.4s +** ret +*/ + +/* +** test_vsubl_u32: +** usubl2 v0\.2d, v0\.4s, v1\.4s +** ret +*/ + +TEST_VSUBL + +/* +** test_vabal_s8: +** sabal2 v0\.8h, (v1\.16b, v2\.16b|v2\.16b, v1\.16b) +** ret +*/ + +/* +** test_vabal_u8: +** uabal2 v0\.8h, (v1\.16b, v2\.16b|v2\.16b, v1\.16b) +** ret +*/ + +/* +** test_vabal_s16: +** sabal2 v0\.4s, (v1\.8h, v2\.8h|v2\.8h, v1\.8h) +** ret +*/ + +/* +** test_vabal_u16: +** uabal2 v0\.4s, (v1\.8h, v2\.8h|v2\.8h, v1\.8h) +** ret +*/ + +/* +** test_vabal_s32: +** sabal2 v0\.2d, (v1\.4s, v2\.4s|v2\.4s, v1\.4s) +** ret +*/ + +/* +** test_vabal_u32: +** uabal2 v0\.2d, (v1\.4s, v2\.4s|v2\.4s, v1\.4s) +** ret +*/ + +TEST_VABAL + +/* +** test_vsubw_s8: +** ssubw2 v0\.8h, v0\.8h, v1\.16b +** ret +*/ + +/* +** test_vsubw_u8: +** usubw2 v0\.8h, v0\.8h, v1\.16b +** ret +*/ + +/* +** test_vsubw_s16: +** ssubw2 v0\.4s, v0\.4s, v1\.8h +** ret +*/ + +/* +** test_vsubw_u16: +** usubw2 v0\.4s, v0\.4s, v1\.8h +** ret +*/ + +/* +** test_vsubw_s32: +** ssubw2 v0\.2d, v0\.2d, v1\.4s +** ret +*/ + +/* +** test_vsubw_u32: +** usubw2 v0\.2d, v0\.2d, v1\.4s +** ret +*/ + +TEST_VSUBW + +/* +** test_vaddw_s8: +** saddw2 v0\.8h, v0\.8h, v1\.16b +** ret +*/ + +/* +** test_vaddw_u8: +** uaddw2 v0\.8h, v0\.8h, v1\.16b +** ret +*/ + +/* +** test_vaddw_s16: +** saddw2 v0\.4s, v0\.4s, v1\.8h +** ret +*/ + +/* +** test_vaddw_u16: +** uaddw2 v0\.4s, v0\.4s, v1\.8h +** ret +*/ + +/* +** test_vaddw_s32: +** saddw2 v0\.2d, v0\.2d, v1\.4s +** ret +*/ + +/* +** test_vaddw_u32: +** uaddw2 v0\.2d, v0\.2d, v1\.4s +** ret +*/ + +TEST_VADDW + +/* +** test_vabdl_s8: +** sabdl2 v0\.8h, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ + +/* +** test_vabdl_u8: +** uabdl2 v0\.8h, (v0\.16b, v1\.16b|v1\.16b, v0\.16b) +** ret +*/ + +/* +** test_vabdl_s16: +** sabdl2 v0\.4s, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ + +/* +** test_vabdl_u16: +** uabdl2 v0\.4s, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ + +/* +** test_vabdl_s32: +** sabdl2 v0\.2d, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ + +/* +** test_vabdl_u32: +** uabdl2 v0\.2d, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ + +TEST_VABDL + +/* +** test_vmlal_s8: +** smlal2 v0\.8h, (v1\.16b, v2\.16b|v2\.16b, v1\.16b) +** ret +*/ + +/* +** test_vmlal_u8: +** umlal2 v0\.8h, (v1\.16b, v2\.16b|v2\.16b, v1\.16b) +** ret +*/ + +/* +** test_vmlal_s16: +** smlal2 v0\.4s, (v1\.8h, v2\.8h|v2\.8h, v1\.8h) +** ret +*/ + +/* +** test_vmlal_u16: +** umlal2 v0\.4s, (v1\.8h, v2\.8h|v2\.8h, v1\.8h) +** ret +*/ + +/* +** test_vmlal_s32: +** smlal2 v0\.2d, (v1\.4s, v2\.4s|v2\.4s, v1\.4s) +** ret +*/ + +/* +** test_vmlal_u32: +** umlal2 v0\.2d, (v1\.4s, v2\.4s|v2\.4s, v1\.4s) +** ret +*/ + +TEST_VMLAL + +/* +** test_vmlal_n_s16: +** smlal2 v0\.4s, v1\.8h, v1\.h\[[0-7]\] +** ret +*/ + +/* +** test_vmlal_n_u16: +** umlal2 v0\.4s, v1\.8h, v1\.h\[[0-7]\] +** ret +*/ + +/* +** test_vmlal_n_s32: +** smlal2 v0\.2d, v1\.4s, v1\.s\[[0-3]\] +** ret +*/ + +/* +** test_vmlal_n_u32: +** umlal2 v0\.2d, v1\.4s, v1\.s\[[0-3]\] +** ret +*/ + +TEST_VMLAL_N + +/* +** test_vmlsl_s8: +** smlsl2 v0\.8h, v1\.16b, v2\.16b +** ret +*/ + +/* +** test_vmlsl_u8: +** umlsl2 v0\.8h, v1\.16b, v2\.16b +** ret +*/ + +/* +** test_vmlsl_s16: +** smlsl2 v0\.4s, v1\.8h, v2\.8h +** ret +*/ + +/* +** test_vmlsl_u16: +** umlsl2 v0\.4s, v1\.8h, v2\.8h +** ret +*/ + +/* +** test_vmlsl_s32: +** smlsl2 v0\.2d, v1\.4s, v2\.4s +** ret +*/ + +/* +** test_vmlsl_u32: +** umlsl2 v0\.2d, v1\.4s, v2\.4s +** ret +*/ + +TEST_VMLSL + +/* +** test_vmlsl_n_s16: +** smlsl2 v0\.4s, v1\.8h, v1\.h\[[0-7]\] +** ret +*/ + +/* +** test_vmlsl_n_u16: +** umlsl2 v0\.4s, v1\.8h, v1\.h\[[0-7]\] +** ret +*/ + +/* +** test_vmlsl_n_s32: +** smlsl2 v0\.2d, v1\.4s, v1\.s\[[0-3]\] +** ret +*/ + +/* +** test_vmlsl_n_u32: +** umlsl2 v0\.2d, v1\.4s, v1\.s\[[0-3]\] +** ret +*/ + +TEST_VMLSL_N + +/* +** test_vqdmull_s16: +** sqdmull2 v0\.4s, (v0\.8h, v1\.8h|v1\.8h, v0\.8h) +** ret +*/ + +/* +** test_vqdmull_s32: +** sqdmull2 v0\.2d, (v0\.4s, v1\.4s|v1\.4s, v0\.4s) +** ret +*/ + +TEST_VQDMULL + +/* +** test_vqdmull_n_s16: +** sqdmull2 v0\.4s, v0\.8h, v0\.h\[[0-7]\] +** ret +*/ + +/* +** test_vqdmull_n_s32: +** sqdmull2 v0\.2d, v0\.4s, v0\.s\[[0-3]\] +** ret +*/ + +TEST_VQDMULL_N + +/* +** test_vqdmlal_s16: +** sqdmlal2 v0\.4s, (v1\.8h, v2\.8h|v2\.8h, v1\.8h) +** ret +*/ + +/* +** test_vqdmlal_s32: +** sqdmlal2 v0\.2d, (v1\.4s, v2\.4s|v2\.4s, v1\.4s) +** ret +*/ + +TEST_VQMLAL + +/* +** test_vqdmlal_n_s16: +** sqdmlal2 v0\.4s, v1\.8h, v1\.h\[[0-7]\] +** ret +*/ + +/* +** test_vqdmlal_n_s32: +** sqdmlal2 v0\.2d, v1\.4s, v1\.s\[[0-3]\] +** ret +*/ + +TEST_VQMLAL_N + +/* +** test_vqdmlsl_s16: +** sqdmlsl2 v0\.4s, v1\.8h, v2\.8h +** ret +*/ + +/* +** test_vqdmlsl_s32: +** sqdmlsl2 v0\.2d, v1\.4s, v2\.4s +** ret +*/ + +TEST_VQMLSL + +/* +** test_vqdmlsl_n_s16: +** sqdmlsl2 v0\.4s, v1\.8h, v1\.h\[[0-7]\] +** ret +*/ + +/* +** test_vqdmlsl_n_s32: +** sqdmlsl2 v0\.2d, v1\.4s, v1\.s\[[0-3]\] +** ret +*/ + +TEST_VQMLSL_N + +/* { dg-final { check-function-bodies "**" ""} } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_2.c b/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_2.c new file mode 100644 index 0000000..5885b28 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_2.c @@ -0,0 +1,88 @@ +/* { dg-do compile } */ +/* { dg-options "-O -march=armv9-a+bf16" } */ + +/* We should not use the highpart instruction unless doing so would avoid + data movement instructions. That is, unless at least one argument is a + reference to the highpart of a non-constant vector. */ + +#define TEST_UN_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_##FN##_## SUFF () \ + { \ + INTYPE a = vdupq_n_##SUFF (0x1A); \ + return FN##_##SUFF (vget_high_##SUFF (a)); \ + } + +#define TEST_BIN_W_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (RETTYPE a) \ + { \ + INTYPE b = vdupq_n_##SUFF (0x1A); \ + return FN##_##SUFF (a, vget_high_##SUFF (b)); \ + } + +#define TEST_BIN_N_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (INTYPE c) \ + { \ + INTYPE a = vdupq_n_##SUFF (0x1A); \ + return FN##_##SUFF (vget_high_##SUFF (a), c[1]); \ + } + +#define TEST_TERN_N_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (RETTYPE a) \ + { \ + INTYPE b = vdupq_n_##SUFF (0x1A); \ + return FN##_##SUFF (a, vget_high_##SUFF (b), b[1]); \ + } + +#define TEST_BIN_HIGHPARTS(FN, RETTYPE, INTYPE, H_INTYPE, SUFF) \ + RETTYPE test_##FN##_## SUFF (H_INTYPE b) \ + { \ + INTYPE a = vdupq_n_##SUFF (0x1A); \ + return FN##_##SUFF (vget_high_##SUFF (a), b); \ + } + +#define TEST_TERN_HIGHPARTS(FN, RETTYPE, INTYPE, H_INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (RETTYPE a, H_INTYPE b) \ + { \ + INTYPE c = vdupq_n_##SUFF (0x1A); \ + return FN##_##SUFF (a, vget_high_##SUFF (c), b); \ + } + +#include "fold_to_highpart_1.c" + + +/* { dg-final { scan-assembler-not {uxtl2\t} } } */ +/* { dg-final { scan-assembler-not {sxtl2\t} } } */ + +/* { dg-final { scan-assembler-not {umull2\t} } } */ +/* { dg-final { scan-assembler-not {smull2\t} } } */ +/* { dg-final { scan-assembler-not {pmull2\t} } } */ + +/* { dg-final { scan-assembler-not {uaddl2\t} } } */ +/* { dg-final { scan-assembler-not {saddl2\t} } } */ + +/* { dg-final { scan-assembler-not {usubl2\t} } } */ +/* { dg-final { scan-assembler-not {ssubl2\t} } } */ + +/* { dg-final { scan-assembler-not {uabal2\t} } } */ +/* { dg-final { scan-assembler-not {sabal2\t} } } */ + +/* { dg-final { scan-assembler-not {uabdl2\t} } } */ +/* { dg-final { scan-assembler-not {sabdl2\t} } } */ + +/* { dg-final { scan-assembler-not {usubw2\t} } } */ +/* { dg-final { scan-assembler-not {ssubw2\t} } } */ + +/* { dg-final { scan-assembler-not {uaddw2\t} } } */ +/* { dg-final { scan-assembler-not {saddw2\t} } } */ + +/* { dg-final { scan-assembler-not {umlal2\t} } } */ +/* { dg-final { scan-assembler-not {smlal2\t} } } */ + +/* { dg-final { scan-assembler-not {umlsl2\t} } } */ +/* { dg-final { scan-assembler-not {smlsl2\t} } } */ + +/* { dg-final { scan-assembler-not {sqdmull2\t} } } */ + +/* { dg-final { scan-assembler-not {sqdmlal2\t} } } */ + +/* { dg-final { scan-assembler-not {sqdmlsl2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_3.c b/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_3.c new file mode 100644 index 0000000..3baf826 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_3.c @@ -0,0 +1,83 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +/* PR117850 */ + +/* We should use the highpart instruction where doing so would avoid data + movement instructions. We avoid a DUP here after extending the + VECTOR_CSTs to 128-bits. */ + +#define TEST_UN_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) +#define TEST_BIN_W_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) +#define TEST_BIN_N_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) +#define TEST_TERN_N_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) + +#define TEST_BIN_HIGHPART_A1(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_a1_##FN##_##SUFF (INTYPE a) \ + { \ + INTYPE b = vdupq_n_##SUFF (0x1A); \ + return FN##_##SUFF (vget_high_##SUFF (a), \ + vget_high_##SUFF (b)); \ + } + +#define TEST_BIN_HIGHPART_A2(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_a2_##FN##_##SUFF (INTYPE a) \ + { \ + INTYPE b = vdupq_n_##SUFF (0x1A); \ + return FN##_##SUFF (vget_high_##SUFF (b), \ + vget_high_##SUFF (a)); \ + } + +#define TEST_TERN_HIGHPART_A1(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_a1_##FN##_##SUFF (RETTYPE a, INTYPE b) \ + { \ + INTYPE c = vdupq_n_##SUFF (0x1A); \ + return FN##_##SUFF (a, vget_high_##SUFF (b), \ + vget_high_##SUFF (c)); \ + } + +#define TEST_TERN_HIGHPART_A2(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_a2_##FN##_##SUFF (RETTYPE a, INTYPE b) \ + { \ + INTYPE c = vdupq_n_##SUFF (0x1A); \ + return FN##_##SUFF (a, vget_high_##SUFF (c), \ + vget_high_##SUFF (b)); \ + } + +#define TEST_BIN_HIGHPARTS(FN, RETTYPE, INTYPE, H_INTYPE, SUFF) \ + TEST_BIN_HIGHPART_A1 (FN, RETTYPE, INTYPE, SUFF) \ + TEST_BIN_HIGHPART_A2 (FN, RETTYPE, INTYPE, SUFF) + +#define TEST_TERN_HIGHPARTS(FN, RETTYPE, INTYPE, H_INTYPE, SUFF) \ + TEST_TERN_HIGHPART_A1 (FN, RETTYPE, INTYPE, SUFF) \ + TEST_TERN_HIGHPART_A2 (FN, RETTYPE, INTYPE, SUFF) + + +#include "fold_to_highpart_1.c" + +/* { dg-final { scan-assembler-not {dup\t} } } */ + +/* { dg-final { scan-assembler-times {smull2\t} 6} } */ +/* { dg-final { scan-assembler-times {umull2\t} 6} } */ +/* { dg-final { scan-assembler-times {pmull2\t} 2} } */ + +/* { dg-final { scan-assembler-times {saddl2\t} 6} } */ +/* { dg-final { scan-assembler-times {uaddl2\t} 6} } */ + +/* { dg-final { scan-assembler-times {ssubl2\t} 6} } */ +/* { dg-final { scan-assembler-times {usubl2\t} 6} } */ + +/* { dg-final { scan-assembler-times {sabdl2\t} 6} } */ +/* { dg-final { scan-assembler-times {uabdl2\t} 6} } */ + +/* { dg-final { scan-assembler-times {smlal2\t} 6} } */ +/* { dg-final { scan-assembler-times {umlal2\t} 6} } */ + +/* { dg-final { scan-assembler-times {smlsl2\t} 6} } */ +/* { dg-final { scan-assembler-times {umlsl2\t} 6} } */ + +/* { dg-final { scan-assembler-times {sqdmull2\t} 4} } */ + +/* { dg-final { scan-assembler-times {sqdmlal2\t} 4} } */ + +/* { dg-final { scan-assembler-times {sqdmlsl2\t} 4} } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_4.c b/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_4.c new file mode 100644 index 0000000..046c7a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_4.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target aarch64_little_endian } */ +/* { dg-options "-O -fdump-tree-optimized" } */ + +#include "arm_neon.h" + +#define VEC_CST_u8 0x0102030405060708 +#define VEC_CST_u16 0x0001000200030004 +#define VEC_CST_u32 0x0000000100000002 + +/* Extend the 64b VECTOR_CST to the type required by the hi builtin. */ + +uint16x8_t +test_u8 (uint8x16_t a) +{ + const uint8x8_t b = vcreate_u8 (VEC_CST_u8); + return vmull_u8 (vget_high_u8 (a), b); +} + +/* { dg-final { scan-tree-dump-times "\{ 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1 \}" 1 "optimized" } } */ + +uint32x4_t +test_u16 (uint16x8_t a) +{ + const uint16x4_t b = vcreate_u16 (VEC_CST_u16); + return vmull_u16 (vget_high_u16 (a), b); +} + +/* { dg-final { scan-tree-dump-times "\{ 4, 3, 2, 1, 4, 3, 2, 1 \}" 1 "optimized" } } */ + +uint64x2_t +test_u32 (uint32x4_t a) +{ + const uint32x2_t b = vcreate_u32 (VEC_CST_u32); + return vmull_u32 (vget_high_u32 (a), b); +} + +/* { dg-final { scan-tree-dump-times "\{ 2, 1, 2, 1 \}" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_5.c b/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_5.c new file mode 100644 index 0000000..4f39b67 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_5.c @@ -0,0 +1,93 @@ +/* { dg-do compile } */ +/* { dg-options "-O -march=armv9-a+bf16" } */ + +/* Test that we can still fold when the base type of the vector who's + highpart we are referring to is incompatible with that of the hi + builtin. + + Use float64x2_t as it is never INTYPE. */ + +#define TEST_UN_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (float64x2_t a) \ + { \ + INTYPE x = vreinterpretq_##SUFF##_f64 (a); \ + return FN##_##SUFF(vget_high_##SUFF (x)); \ + } + +#define TEST_BIN_W_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (RETTYPE a, float64x2_t b) \ + { \ + INTYPE x = vreinterpretq_##SUFF##_f64 (b); \ + return FN##_##SUFF (a, vget_high_##SUFF (x)); \ + } + +#define TEST_BIN_N_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (float64x2_t a) \ + { \ + INTYPE x = vreinterpretq_##SUFF##_f64 (a); \ + return FN##_##SUFF (vget_high_##SUFF (x), x[1]); \ + } + +#define TEST_TERN_N_HIGHPARTS(FN, RETTYPE, INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (RETTYPE a, float64x2_t b) \ + { \ + INTYPE x = vreinterpretq_##SUFF##_f64 (b); \ + return FN##_##SUFF (a, vget_high_##SUFF (x), x[1]); \ + } + +#define TEST_BIN_HIGHPARTS(FN, RETTYPE, INTYPE, H_INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (float64x2_t a, float64x2_t b) \ + { \ + INTYPE x = vreinterpretq_##SUFF##_f64 (a); \ + INTYPE y = vreinterpretq_##SUFF##_f64 (b); \ + return FN##_##SUFF (vget_high_##SUFF (x), \ + vget_high_##SUFF (y)); \ + } + +#define TEST_TERN_HIGHPARTS(FN, RETTYPE, INTYPE, H_INTYPE, SUFF) \ + RETTYPE test_##FN##_##SUFF (RETTYPE a, float64x2_t b, float64x2_t c) \ + { \ + INTYPE x = vreinterpretq_##SUFF##_f64 (b); \ + INTYPE y = vreinterpretq_##SUFF##_f64 (c); \ + return FN##_##SUFF (a, vget_high_## SUFF (x), \ + vget_high_## SUFF (y)); \ + } + +#include "fold_to_highpart_1.c" + +/* { dg-final { scan-assembler-times {sxtl2\t} 3} } */ +/* { dg-final { scan-assembler-times {uxtl2\t} 3} } */ + +/* { dg-final { scan-assembler-times {smull2\t} 5} } */ +/* { dg-final { scan-assembler-times {umull2\t} 5} } */ +/* { dg-final { scan-assembler-times {pmull2\t} 1} } */ + +/* { dg-final { scan-assembler-times {saddl2\t} 3} } */ +/* { dg-final { scan-assembler-times {uaddl2\t} 3} } */ + +/* { dg-final { scan-assembler-times {ssubl2\t} 3} } */ +/* { dg-final { scan-assembler-times {usubl2\t} 3} } */ + +/* { dg-final { scan-assembler-times {sabdl2\t} 3} } */ +/* { dg-final { scan-assembler-times {uabdl2\t} 3} } */ + +/* { dg-final { scan-assembler-times {saddw2\t} 3} } */ +/* { dg-final { scan-assembler-times {uaddw2\t} 3} } */ + +/* { dg-final { scan-assembler-times {ssubw2\t} 3} } */ +/* { dg-final { scan-assembler-times {usubw2\t} 3} } */ + +/* { dg-final { scan-assembler-times {sabdl2\t} 3} } */ +/* { dg-final { scan-assembler-times {uabdl2\t} 3} } */ + +/* { dg-final { scan-assembler-times {smlal2\t} 5} } */ +/* { dg-final { scan-assembler-times {umlal2\t} 5} } */ + +/* { dg-final { scan-assembler-times {smlsl2\t} 5} } */ +/* { dg-final { scan-assembler-times {umlsl2\t} 5} } */ + +/* { dg-final { scan-assembler-times {sqdmull2\t} 4} } */ + +/* { dg-final { scan-assembler-times {sqdmlal2\t} 4} } */ + +/* { dg-final { scan-assembler-times {sqdmlsl2\t} 4} } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_6.c b/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_6.c new file mode 100644 index 0000000..3570d4d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_6.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target aarch64_little_endian } */ +/* { dg-options "-O2 -march=armv8-a+sve" } */ + +#include <arm_neon_sve_bridge.h> + +typedef int16_t int16x16_t __attribute__ ((vector_size (32))); + +/* Edge cases where we don't/can't fold, reject these gracefully. */ + +int8x16_t z; + +int16x8_t +test_addressable () +{ + return vmovl_s8 (vget_high_s8 (z)); +} + +int16x8_t +test_scalable_type (svint8_t scalable) +{ + return vmovl_s8 (vget_high_s8 (svget_neonq_s8 (scalable))); +} + +int16x8_t +test_scalar_type (__int128_t foo) +{ + return vmovl_s8 (vget_high_s8 (vreinterpretq_s8_p128 (foo))); +} + +int32x4_t +test_256b_type (int16x16_t foo) +{ + return vmovl_s16 ((int16x4_t) { foo[4], foo[5], foo[6], foo[7] }); +} + +/* { dg-final { scan-assembler-not {sxtl2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/mf8_data_1.c b/gcc/testsuite/gcc.target/aarch64/simd/mf8_data_1.c index a3fd9b8..79d1ccf 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/mf8_data_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/mf8_data_1.c @@ -1016,7 +1016,12 @@ mfloat8x8_t test_set_lane3(mfloat8x8_t a, const mfloat8_t *ptr) /* ** test_set_lane4: +** ( ** ins v0.b\[6\], wzr +** | +** movi? [vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0 +** ins v0.b\[6\], v(\1).b\[0\] +** ) ** ret */ mfloat8x8_t test_set_lane4(mfloat8x8_t a) @@ -1056,7 +1061,12 @@ mfloat8x16_t test_setq_lane3(mfloat8x16_t a, const mfloat8_t *ptr) /* ** test_setq_lane4: +** ( ** ins v0.b\[14\], wzr +** | +** movi? [vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0 +** ins v0.b\[14\], v(\1).b\[0\] +** ) ** ret */ mfloat8x16_t test_setq_lane4(mfloat8x16_t a) diff --git a/gcc/testsuite/gcc.target/aarch64/simd/shrn2subhn.c b/gcc/testsuite/gcc.target/aarch64/simd/shrn2subhn.c new file mode 100644 index 0000000..f90ea13 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/shrn2subhn.c @@ -0,0 +1,36 @@ +/* This test case checks that replacing a not+shift by a sub -1 works. */ +/* { dg-do compile } */ +/* { dg-additional-options "-O1" } */ +/* { dg-final { scan-assembler-times "\\tsubhn\\t" 6 } } */ + +#include<arm_neon.h> + +uint8x8_t neg_narrow_v8hi(uint16x8_t a) { + uint16x8_t b = vmvnq_u16(a); + return vshrn_n_u16(b, 8); +} + +uint8x8_t neg_narrow_vsubhn_v8hi(uint16x8_t a) { + uint16x8_t ones = vdupq_n_u16(0xffff); + return vsubhn_u16(ones, a); +} + +uint16x4_t neg_narrow_v4si(uint32x4_t a) { + uint32x4_t b = vmvnq_u32(a); + return vshrn_n_u32(b, 16); +} + +uint16x4_t neg_narrow_vsubhn_v4si(uint32x4_t a) { + uint32x4_t ones = vdupq_n_u32(0xffffffff); + return vsubhn_u32(ones, a); +} + +uint32x2_t neg_narrow_v2di(uint64x2_t a) { + uint64x2_t b = ~a; + return vshrn_n_u64(b, 32); +} + +uint32x2_t neg_narrow_vsubhn_v2di(uint64x2_t a) { + uint64x2_t ones = vdupq_n_u64(0xffffffffffffffff); + return vsubhn_u64(ones, a); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vabal_combine.c b/gcc/testsuite/gcc.target/aarch64/simd/vabal_combine.c deleted file mode 100644 index c51878a..0000000 --- a/gcc/testsuite/gcc.target/aarch64/simd/vabal_combine.c +++ /dev/null @@ -1,72 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O" } */ -/* { dg-final { check-function-bodies "**" "" "" } } */ - -#include <arm_neon.h> - -/* -** test_vabal_s8: -** sabal2 v0.8h, v2.16b, v1.16b -** ret -*/ -int16x8_t -test_vabal_s8 (int16x8_t sadv, int8x16_t pv, int8x16_t sv) -{ - return vabal_s8 (sadv, vget_high_s8 (pv), vget_high_s8 (sv)); -} - -/* -** test_vabal_u8: -** uabal2 v0.8h, v2.16b, v1.16b -** ret -*/ -uint16x8_t -test_vabal_u8 (uint16x8_t sadv, uint8x16_t pv, uint8x16_t sv) -{ - return vabal_u8 (sadv, vget_high_u8 (pv), vget_high_u8 (sv)); -} - -/* -** test_vabal_s16: -** sabal2 v0.4s, v2.8h, v1.8h -** ret -*/ -int32x4_t -test_vabal_s16 (int32x4_t sadv, int16x8_t pv, int16x8_t sv) -{ - return vabal_s16 (sadv, vget_high_s16 (pv), vget_high_s16 (sv)); -} - -/* -** test_vabal_u16: -** uabal2 v0.4s, v2.8h, v1.8h -** ret -*/ -uint32x4_t -test_vabal_u16 (uint32x4_t sadv, uint16x8_t pv, uint16x8_t sv) -{ - return vabal_u16 (sadv, vget_high_u16 (pv), vget_high_u16 (sv)); -} - -/* -** test_vabal_s32: -** sabal2 v0.2d, v2.4s, v1.4s -** ret -*/ -int64x2_t -test_vabal_s32 (int64x2_t sadv, int32x4_t pv, int32x4_t sv) -{ - return vabal_s32 (sadv, vget_high_s32 (pv), vget_high_s32 (sv)); -} - -/* -** test_vabal_u32: -** uabal2 v0.2d, v2.4s, v1.4s -** ret -*/ -uint64x2_t -test_vabal_u32 (uint64x2_t sadv, uint32x4_t pv, uint32x4_t sv) -{ - return vabal_u32 (sadv, vget_high_u32 (pv), vget_high_u32 (sv)); -} - diff --git a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c index 98922aa..3a63da7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c @@ -1,5 +1,5 @@ // { dg-options "-O -fomit-frame-pointer -fno-optimize-sibling-calls -funwind-tables" } -// { dg-final { check-function-bodies "**" "" } } +// { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {\t\.inst} } } void ns_callee (); void s_callee () [[arm::streaming]]; @@ -218,7 +218,7 @@ sc_caller_x1 (int *ptr, int a) [[arm::streaming_compatible]] ** bl ns_callee_stack ** ldr x16, \[x29, #?16\] ** tbz x16, 0, .* -** smstart sm +** .inst 0xd503437f // smstart sm ** ... */ void diff --git a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c index ee6f987..c72d03f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c @@ -1,5 +1,6 @@ // { dg-options "-O -fomit-frame-pointer -fno-optimize-sibling-calls -funwind-tables -mtrack-speculation" } -// { dg-final { check-function-bodies "**" "" } } +// { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {\t\.inst} } } + void ns_callee (); void s_callee () [[arm::streaming]]; @@ -196,7 +197,7 @@ sc_caller_x1 (int *ptr, int a) [[arm::streaming_compatible]] ** tst x16, #?1 ** beq [^\n]* ** csel x15, x15, xzr, ne -** smstart sm +** .inst 0xd503437f // smstart sm ** ... */ void diff --git a/gcc/testsuite/gcc.target/aarch64/sme/nonlocal_goto_1.c b/gcc/testsuite/gcc.target/aarch64/sme/nonlocal_goto_1.c index 4e3869f..572c17a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/nonlocal_goto_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/nonlocal_goto_1.c @@ -13,7 +13,7 @@ void run(void (*)()); ** ldr x16, \1 ** tbz x16, 0, .* ** smstop sm -** bl __clear_cache +** bl [^\n]*[cC]ache[^\n]* ** ldr x16, \1 ** tbz x16, 0, .* ** smstart sm diff --git a/gcc/testsuite/gcc.target/aarch64/sme/nonlocal_goto_2.c b/gcc/testsuite/gcc.target/aarch64/sme/nonlocal_goto_2.c index 2a2db72..721a2b7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/nonlocal_goto_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/nonlocal_goto_2.c @@ -7,7 +7,7 @@ void run(void (*)()); ** foo: ** ... ** smstop sm -** bl __clear_cache +** bl [^\n]*[cC]ache[^\n]* ** smstart sm ** add x0, .* ** smstop sm diff --git a/gcc/testsuite/gcc.target/aarch64/sme/nonlocal_goto_3.c b/gcc/testsuite/gcc.target/aarch64/sme/nonlocal_goto_3.c index 022b040..25db928 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/nonlocal_goto_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/nonlocal_goto_3.c @@ -9,7 +9,7 @@ void run(void (*)()); ** smstart sm ** ... ** smstop sm -** bl __clear_cache +** bl [^\n]*[cC]ache[^\n]* ** smstart sm ** add x0, .* ** smstop sm diff --git a/gcc/testsuite/gcc.target/aarch64/sme/pr121028.c b/gcc/testsuite/gcc.target/aarch64/sme/pr121028.c new file mode 100644 index 0000000..a6aa119 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme/pr121028.c @@ -0,0 +1,46 @@ +// PR121028 +// { dg-do assemble { target aarch64_asm_sme_ok } } +// { dg-options "-O --save-temps" } +// { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {\t\.inst} } } + +void ns_callee (); + +/* +** sc_caller_sme: +** ... +** mrs x16, svcr +** str x16, \[x29, #?16\] +** ldr x16, \[x29, #?16\] +** tbz x16, 0, .* +** smstop sm +** bl ns_callee +** ldr x16, \[x29, #?16\] +** tbz x16, 0, .* +** smstart sm +** ... +*/ +void sc_caller_sme() __arm_streaming_compatible +{ + ns_callee (); +} + +#pragma GCC target "+nosme" + +/* +** sc_caller_nosme: +** ... +** bl __arm_sme_state +** str x0, \[x29, #?16\] +** ldr x16, \[x29, #?16\] +** tbz x16, 0, .* +** .inst 0xd503427f // smstop sm +** bl ns_callee +** ldr x16, \[x29, #?16\] +** tbz x16, 0, .* +** .inst 0xd503437f // smstart sm +** ... +*/ +void sc_caller_nosme() __arm_streaming_compatible +{ + ns_callee (); +} diff --git a/gcc/testsuite/gcc.target/aarch64/sme/za_state_7.c b/gcc/testsuite/gcc.target/aarch64/sme/za_state_7.c new file mode 100644 index 0000000..38bc134 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme/za_state_7.c @@ -0,0 +1,21 @@ +// { dg-options "-O -fno-optimize-sibling-calls -fomit-frame-pointer" } + +#include <arm_sme.h> + +void callee(); + +__arm_new("za") __arm_locally_streaming int test() +{ + svbool_t all = svptrue_b8(); + svint8_t expected = svindex_s8(1, 1); + svwrite_hor_za8_m(0, 0, all, expected); + + callee(); + + svint8_t actual = svread_hor_za8_m(svdup_s8(0), all, 0, 0); + return svptest_any(all, svcmpne(all, expected, actual)); +} + +// { dg-final { scan-assembler {\tbl\t__arm_tpidr2_save\n} } } +// { dg-final { scan-assembler {\tbl\t__arm_tpidr2_restore\n} } } +// { dg-final { scan-assembler-times {\tsmstart\tza\n} 2 } } diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c new file mode 100644 index 0000000..b9fd96a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c @@ -0,0 +1,99 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat16x2_t, z0, + svamax_f16_x2 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat16x2_t, z0, + svamax_f16_x2 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.h - z29\.h} +** | +** famax [^\n]+, {z28\.h - z29\.h} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat16x2_t, z0, + svamax_f16_x2 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** famax {z18\.h - z19\.h}, {z18\.h - z19\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat16x2_t, z18, + svamax_f16_x2 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z18\.h - z19\.h} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z18, svfloat16x2_t, z23, + svamax_f16_x2 (z23, z18), + svamax (z23, z18)) + +/* +** amax_z28_z28_z0: +** famax {z28\.h - z29\.h}, {z28\.h - z29\.h}, {z0\.h - z1\.h} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat16x2_t, z28, + svamax_f16_x2 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** famax {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z18\.h - z19\.h} +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat16x2_t, z0, + svamax_f16_x2 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.h - z5\.h}, {z4\.h - z5\.h}, [^\n]+ +** | +** famax {z4\.h - z5\.h}, {z4\.h - z5\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat16x2_t, z4, + svamax_f16_x2 (z4, z23), + svamax (z4, z23)) + diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c new file mode 100644 index 0000000..70e2697 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c @@ -0,0 +1,130 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.h - z3\.h}, {z0\.h - z3\.h}, {z4\.h - z7\.h} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat16x4_t, z0, + svamax_f16_x4 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.h - z3\.h}, {z0\.h - z3\.h}, {z4\.h - z7\.h} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat16x4_t, z0, + svamax_f16_x4 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.h - z31\.h} +** | +** famax [^\n]+, {z28\.h - z31\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat16x4_t, z0, + svamax_f16_x4 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z4\.h - z7\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat16x4_t, z18, + svamax_f16_x4 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.h - z31\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z28, svfloat16x4_t, z23, + svamax_f16_x4 (z23, z28), + svamax (z23, z28)) + +/* +** amax_z28_z28_z0: +** famax {z28\.h - z31\.h}, {z28\.h - z31\.h}, {z0\.h - z3\.h} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat16x4_t, z28, + svamax_f16_x4 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z0\.h - z3\.h}, {z0\.h - z3\.h}, [^\n]+ +** | +** famax {z0\.h - z3\.h}, {z0\.h - z3\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat16x4_t, z0, + svamax_f16_x4 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.h - z7\.h}, {z4\.h - z7\.h}, [^\n]+ +** | +** famax {z4\.h - z7\.h}, {z4\.h - z7\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat16x4_t, z4, + svamax_f16_x4 (z4, z23), + svamax (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c new file mode 100644 index 0000000..cf57d1b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c @@ -0,0 +1,98 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat32x2_t, z0, + svamax_f32_x2 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat32x2_t, z0, + svamax_f32_x2 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.s - z29\.s} +** | +** famax [^\n]+, {z28\.s - z29\.s} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat32x2_t, z0, + svamax_f32_x2 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** famax {z18\.s - z19\.s}, {z18\.s - z19\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat32x2_t, z18, + svamax_f32_x2 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z18\.s - z19\.s} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z18, svfloat32x2_t, z23, + svamax_f32_x2 (z23, z18), + svamax (z23, z18)) + +/* +** amax_z28_z28_z0: +** famax {z28\.s - z29\.s}, {z28\.s - z29\.s}, {z0\.s - z1\.s} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat32x2_t, z28, + svamax_f32_x2 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** famax {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z18\.s - z19\.s} +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat32x2_t, z0, + svamax_f32_x2 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.s - z5\.s}, {z4\.s - z5\.s}, [^\n]+ +** | +** famax {z4\.s - z5\.s}, {z4\.s - z5\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat32x2_t, z4, + svamax_f32_x2 (z4, z23), + svamax (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c new file mode 100644 index 0000000..10d9175 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c @@ -0,0 +1,131 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.s - z3\.s}, {z0\.s - z3\.s}, {z4\.s - z7\.s} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat32x4_t, z0, + svamax_f32_x4 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.s - z3\.s}, {z0\.s - z3\.s}, {z4\.s - z7\.s} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat32x4_t, z0, + svamax_f32_x4 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.s - z31\.s} +** | +** famax [^\n]+, {z28\.s - z31\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat32x4_t, z0, + svamax_f32_x4 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z4\.s - z7\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat32x4_t, z18, + svamax_f32_x4 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.s - z31\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z28, svfloat32x4_t, z23, + svamax_f32_x4 (z23, z28), + svamax (z23, z28)) + +/* +** amax_z28_z28_z0: +** famax {z28\.s - z31\.s}, {z28\.s - z31\.s}, {z0\.s - z3\.s} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat32x4_t, z28, + svamax_f32_x4 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z0\.s - z3\.s}, {z0\.s - z3\.s}, [^\n]+ +** | +** famax {z0\.s - z3\.s}, {z0\.s - z3\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat32x4_t, z0, + svamax_f32_x4 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.s - z7\.s}, {z4\.s - z7\.s}, [^\n]+ +** | +** famax {z4\.s - z7\.s}, {z4\.s - z7\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat32x4_t, z4, + svamax_f32_x4 (z4, z23), + svamax (z4, z23)) + diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c new file mode 100644 index 0000000..b7918ab --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c @@ -0,0 +1,98 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat64x2_t, z0, + svamax_f64_x2 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat64x2_t, z0, + svamax_f64_x2 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.d - z29\.d} +** | +** famax [^\n]+, {z28\.d - z29\.d} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat64x2_t, z0, + svamax_f64_x2 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** famax {z18\.d - z19\.d}, {z18\.d - z19\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat64x2_t, z18, + svamax_f64_x2 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z18\.d - z19\.d} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z18, svfloat64x2_t, z23, + svamax_f64_x2 (z23, z18), + svamax (z23, z18)) + +/* +** amax_z28_z28_z0: +** famax {z28\.d - z29\.d}, {z28\.d - z29\.d}, {z0\.d - z1\.d} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat64x2_t, z28, + svamax_f64_x2 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** famax {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z18\.d - z19\.d} +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat64x2_t, z0, + svamax_f64_x2 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.d - z5\.d}, {z4\.d - z5\.d}, [^\n]+ +** | +** famax {z4\.d - z5\.d}, {z4\.d - z5\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat64x2_t, z4, + svamax_f64_x2 (z4, z23), + svamax (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c new file mode 100644 index 0000000..153a37a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c @@ -0,0 +1,130 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.d - z3\.d}, {z0\.d - z3\.d}, {z4\.d - z7\.d} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat64x4_t, z0, + svamax_f64_x4 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.d - z3\.d}, {z0\.d - z3\.d}, {z4\.d - z7\.d} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat64x4_t, z0, + svamax_f64_x4 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.d - z31\.d} +** | +** famax [^\n]+, {z28\.d - z31\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat64x4_t, z0, + svamax_f64_x4 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z4\.d - z7\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat64x4_t, z18, + svamax_f64_x4 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.d - z31\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z28, svfloat64x4_t, z23, + svamax_f64_x4 (z23, z28), + svamax (z23, z28)) + +/* +** amax_z28_z28_z0: +** famax {z28\.d - z31\.d}, {z28\.d - z31\.d}, {z0\.d - z3\.d} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat64x4_t, z28, + svamax_f64_x4 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z0\.d - z3\.d}, {z0\.d - z3\.d}, [^\n]+ +** | +** famax {z0\.d - z3\.d}, {z0\.d - z3\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat64x4_t, z0, + svamax_f64_x4 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.d - z7\.d}, {z4\.d - z7\.d}, [^\n]+ +** | +** famax {z4\.d - z7\.d}, {z4\.d - z7\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat64x4_t, z4, + svamax_f64_x4 (z4, z23), + svamax (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c new file mode 100644 index 0000000..bd6e13b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c @@ -0,0 +1,98 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat16x2_t, z0, + svamin_f16_x2 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat16x2_t, z0, + svamin_f16_x2 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.h - z29\.h} +** | +** famin [^\n]+, {z28\.h - z29\.h} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat16x2_t, z0, + svamin_f16_x2 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** famin {z18\.h - z19\.h}, {z18\.h - z19\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat16x2_t, z18, + svamin_f16_x2 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z18\.h - z19\.h} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z18, svfloat16x2_t, z23, + svamin_f16_x2 (z23, z18), + svamin (z23, z18)) + +/* +** amin_z28_z28_z0: +** famin {z28\.h - z29\.h}, {z28\.h - z29\.h}, {z0\.h - z1\.h} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat16x2_t, z28, + svamin_f16_x2 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** famin {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z18\.h - z19\.h} +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat16x2_t, z0, + svamin_f16_x2 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.h - z5\.h}, {z4\.h - z5\.h}, [^\n]+ +** | +** famin {z4\.h - z5\.h}, {z4\.h - z5\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat16x2_t, z4, + svamin_f16_x2 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c new file mode 100644 index 0000000..9f71b1f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c @@ -0,0 +1,130 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.h - z3\.h}, {z0\.h - z3\.h}, {z4\.h - z7\.h} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat16x4_t, z0, + svamin_f16_x4 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.h - z3\.h}, {z0\.h - z3\.h}, {z4\.h - z7\.h} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat16x4_t, z0, + svamin_f16_x4 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.h - z31\.h} +** | +** famin [^\n]+, {z28\.h - z31\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat16x4_t, z0, + svamin_f16_x4 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z4\.h - z7\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat16x4_t, z18, + svamin_f16_x4 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.h - z31\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z28, svfloat16x4_t, z23, + svamin_f16_x4 (z23, z28), + svamin (z23, z28)) + +/* +** amin_z28_z28_z0: +** famin {z28\.h - z31\.h}, {z28\.h - z31\.h}, {z0\.h - z3\.h} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat16x4_t, z28, + svamin_f16_x4 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z0\.h - z3\.h}, {z0\.h - z3\.h}, [^\n]+ +** | +** famin {z0\.h - z3\.h}, {z0\.h - z3\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat16x4_t, z0, + svamin_f16_x4 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.h - z7\.h}, {z4\.h - z7\.h}, [^\n]+ +** | +** famin {z4\.h - z7\.h}, {z4\.h - z7\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat16x4_t, z4, + svamin_f16_x4 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c new file mode 100644 index 0000000..aaa6a2e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c @@ -0,0 +1,98 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat32x2_t, z0, + svamin_f32_x2 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat32x2_t, z0, + svamin_f32_x2 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.s - z29\.s} +** | +** famin [^\n]+, {z28\.s - z29\.s} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat32x2_t, z0, + svamin_f32_x2 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** famin {z18\.s - z19\.s}, {z18\.s - z19\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat32x2_t, z18, + svamin_f32_x2 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z18\.s - z19\.s} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z18, svfloat32x2_t, z23, + svamin_f32_x2 (z23, z18), + svamin (z23, z18)) + +/* +** amin_z28_z28_z0: +** famin {z28\.s - z29\.s}, {z28\.s - z29\.s}, {z0\.s - z1\.s} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat32x2_t, z28, + svamin_f32_x2 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** famin {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z18\.s - z19\.s} +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat32x2_t, z0, + svamin_f32_x2 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.s - z5\.s}, {z4\.s - z5\.s}, [^\n]+ +** | +** famin {z4\.s - z5\.s}, {z4\.s - z5\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat32x2_t, z4, + svamin_f32_x2 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c new file mode 100644 index 0000000..34c1098 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c @@ -0,0 +1,130 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.s - z3\.s}, {z0\.s - z3\.s}, {z4\.s - z7\.s} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat32x4_t, z0, + svamin_f32_x4 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.s - z3\.s}, {z0\.s - z3\.s}, {z4\.s - z7\.s} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat32x4_t, z0, + svamin_f32_x4 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.s - z31\.s} +** | +** famin [^\n]+, {z28\.s - z31\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat32x4_t, z0, + svamin_f32_x4 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z4\.s - z7\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat32x4_t, z18, + svamin_f32_x4 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.s - z31\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z28, svfloat32x4_t, z23, + svamin_f32_x4 (z23, z28), + svamin (z23, z28)) + +/* +** amin_z28_z28_z0: +** famin {z28\.s - z31\.s}, {z28\.s - z31\.s}, {z0\.s - z3\.s} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat32x4_t, z28, + svamin_f32_x4 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z0\.s - z3\.s}, {z0\.s - z3\.s}, [^\n]+ +** | +** famin {z0\.s - z3\.s}, {z0\.s - z3\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat32x4_t, z0, + svamin_f32_x4 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.s - z7\.s}, {z4\.s - z7\.s}, [^\n]+ +** | +** famin {z4\.s - z7\.s}, {z4\.s - z7\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat32x4_t, z4, + svamin_f32_x4 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c new file mode 100644 index 0000000..e4138e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c @@ -0,0 +1,98 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat64x2_t, z0, + svamin_f64_x2 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat64x2_t, z0, + svamin_f64_x2 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.d - z29\.d} +** | +** famin [^\n]+, {z28\.d - z29\.d} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat64x2_t, z0, + svamin_f64_x2 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** famin {z18\.d - z19\.d}, {z18\.d - z19\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat64x2_t, z18, + svamin_f64_x2 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z18\.d - z19\.d} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z18, svfloat64x2_t, z23, + svamin_f64_x2 (z23, z18), + svamin (z23, z18)) + +/* +** amin_z28_z28_z0: +** famin {z28\.d - z29\.d}, {z28\.d - z29\.d}, {z0\.d - z1\.d} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat64x2_t, z28, + svamin_f64_x2 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** famin {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z18\.d - z19\.d} +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat64x2_t, z0, + svamin_f64_x2 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.d - z5\.d}, {z4\.d - z5\.d}, [^\n]+ +** | +** famin {z4\.d - z5\.d}, {z4\.d - z5\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat64x2_t, z4, + svamin_f64_x2 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c new file mode 100644 index 0000000..8fbabe7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c @@ -0,0 +1,130 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.d - z3\.d}, {z0\.d - z3\.d}, {z4\.d - z7\.d} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat64x4_t, z0, + svamin_f64_x4 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.d - z3\.d}, {z0\.d - z3\.d}, {z4\.d - z7\.d} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat64x4_t, z0, + svamin_f64_x4 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.d - z31\.d} +** | +** famin [^\n]+, {z28\.d - z31\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat64x4_t, z0, + svamin_f64_x4 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z4\.d - z7\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat64x4_t, z18, + svamin_f64_x4 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.d - z31\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z28, svfloat64x4_t, z23, + svamin_f64_x4 (z23, z28), + svamin (z23, z28)) + +/* +** amin_z28_z28_z0: +** famin {z28\.d - z31\.d}, {z28\.d - z31\.d}, {z0\.d - z3\.d} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat64x4_t, z28, + svamin_f64_x4 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z0\.d - z3\.d}, {z0\.d - z3\.d}, [^\n]+ +** | +** famin {z0\.d - z3\.d}, {z0\.d - z3\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat64x4_t, z0, + svamin_f64_x4 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.d - z7\.d}, {z4\.d - z7\.d}, [^\n]+ +** | +** famin {z4\.d - z7\.d}, {z4\.d - z7\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat64x4_t, z4, + svamin_f64_x4 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-19.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-19.c index 38eab4d..49dc511 100644 --- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-19.c +++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-19.c @@ -1,4 +1,5 @@ /* { dg-options "-O2 -fstack-clash-protection -fomit-frame-pointer --param stack-clash-protection-guard-size=12 -fsanitize=shadow-call-stack -ffixed-x18 -fno-stack-protector" } */ +/* { dg-skip-if "conflicts with x18" { aarch64-*-vxworks* } } */ /* { dg-final { check-function-bodies "**" "" } } */ void f(int, ...); diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-20.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-20.c index 690aae8..35b8ccc 100644 --- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-20.c +++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-20.c @@ -1,3 +1,4 @@ /* { dg-options "-O2 -fstack-protector-all -fstack-clash-protection -fomit-frame-pointer --param stack-clash-protection-guard-size=12 -fsanitize=shadow-call-stack -ffixed-x18" } */ +/* { dg-skip-if "conflicts with x18" { aarch64-*-vxworks* } } */ #include "stack-check-prologue-19.c" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_2.c index 218a660..13ebb9f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_2.c @@ -10,6 +10,6 @@ dupq (int x) return svdupq_s32 (x, 1, 2, 3); } -/* { dg-final { scan-assembler {\tindex\tz[0-9]+\.s, #3, #-1} } } */ +/* { dg-final { scan-assembler {\tindex\tz[0-9]+\.s, #0, #1\n} } } */ /* { dg-final { scan-assembler {\tins\tv[0-9]+\.s\[0\], w0\n} } } */ /* { dg-final { scan-assembler {\tdup\tz[0-9]+\.q, z[0-9]+\.q\[0\]\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_4.c index cbee6f2..13d27e2 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_4.c @@ -10,6 +10,6 @@ dupq (int x) return svdupq_s32 (0, 1, x, 3); } -/* { dg-final { scan-assembler {\tindex\tz[0-9]+\.s, #3, #-1} } } */ +/* { dg-final { scan-assembler {\tindex\tz[0-9]+\.s, #0, #1\n} } } */ /* { dg-final { scan-assembler {\tins\tv[0-9]+\.s\[2\], w0\n} } } */ /* { dg-final { scan-assembler {\tdup\tz[0-9]+\.q, z[0-9]+\.q\[0\]\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/not_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/not_1.c new file mode 100644 index 0000000..875d788 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/not_1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svbool_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svnot_z (pg, x); + *any = svptest_last (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svbool_t x) +{ + svbool_t res = svnot_z (pg, x); + return svptest_first (pg, res); +} + +/* { dg-final { scan-assembler-times {\tnots\t} 2 } } */ +/* { dg-final { scan-assembler-not {\tnot\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_1.c new file mode 100644 index 0000000..6b920b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_1.c @@ -0,0 +1,14 @@ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include <arm_sve.h> +typedef svbfloat16_t vls_bfloat16_t __attribute__((arm_sve_vector_bits(32 * 8))); +svbfloat16_t foo(vls_bfloat16_t a, vls_bfloat16_t b) +{ + svbfloat16_t zero = svreinterpret_bf16_f32 (svdup_n_f32 (0.0f)); + return svzip2_bf16(zero, svuzp1_bf16(a,b)); +} + + +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ +/* { dg-final { scan-assembler-times {\tzip2\t} 1 } } */ +/* { dg-final { scan-assembler-not {\ttbl\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_7.c b/gcc/testsuite/gcc.target/aarch64/sve/adr_7.c new file mode 100644 index 0000000..b8a3bda --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/adr_7.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +#include <arm_sve.h> + +void f(int *p1, int *p2, unsigned long step, unsigned long end, svbool_t pg) { + for (unsigned long i = 0; i < end; i += step) { + svst1(pg, p1, svld1_s32(pg, p2)); + p1 += step; + p2 += step; + } +} + +// Checking that the induction variables are combined into a single variable, +// which is used for all addressing. +// (ie, theres only one scalar add, rather than 3, and the loads and stores use the +// more complex addressing modes) + +/* { dg-final { scan-assembler-not {\tld1w\tz[0-9]+\.s, p[0-9]+/z, \[x[0-9]+\]} } } */ +/* { dg-final { scan-assembler-not {\tst1w\tz[0-9]+\.s, p[0-9]+, \[x[0-9]+\]} } } */ + +/* { dg-final { scan-assembler-times {\tadd\tx[0-9]+, x[0-9]+, x[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-9]+/z, \[x[0-9]+, x[0-9]+, lsl 2\]} 1 } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s, p[0-9]+, \[x[0-9]+, x[0-9]+, lsl 2\]} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_16.c b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_16.c new file mode 100644 index 0000000..bfe49ef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -march=armv8-a+sve --param vect-scalar-cost-multiplier=1000 -fdump-tree-vect-details" } */ + +void +foo (char *restrict a, int *restrict b, int *restrict c, + int *restrict d, int stride) +{ + if (stride <= 1) + return; + + for (int i = 0; i < 3; i++) + { + int res = c[i]; + int t = b[i * stride]; + if (a[i] != 0) + res = t * d[i]; + c[i] = res; + } +} + +/* { dg-final { scan-tree-dump "vectorized 1 loops in function" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_17.c b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_17.c new file mode 100644 index 0000000..c405591 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_17.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -march=armv8-a+sve -mmax-vectorization -fdump-tree-vect-details" } */ + +void +foo (char *restrict a, int *restrict b, int *restrict c, + int *restrict d, int stride) +{ + if (stride <= 1) + return; + + for (int i = 0; i < 3; i++) + { + int res = c[i]; + int t = b[i * stride]; + if (a[i] != 0) + res = t * d[i]; + c[i] = res; + } +} + +/* { dg-final { scan-tree-dump "vectorized 1 loops in function" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_18.c b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_18.c new file mode 100644 index 0000000..8e91f9e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_18.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -march=armv8-a+sve -fdump-tree-vect-details" } */ + +void __attribute__ (( target ("max-vectorization"))) +foo (char *restrict a, int *restrict b, int *restrict c, + int *restrict d, int stride) +{ + if (stride <= 1) + return; + + for (int i = 0; i < 3; i++) + { + int res = c[i]; + int t = b[i * stride]; + if (a[i] != 0) + res = t * d[i]; + c[i] = res; + } +} + +/* { dg-final { scan-tree-dump "vectorized 1 loops in function" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/mask_load_2.c b/gcc/testsuite/gcc.target/aarch64/sve/mask_load_2.c new file mode 100644 index 0000000..66d9510 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/mask_load_2.c @@ -0,0 +1,23 @@ +// { dg-do compile } +// { dg-options "-march=armv8-a+sve -msve-vector-bits=128 -O3" } + +typedef struct Array { + int elems[3]; +} Array; + +int loop(Array **pp, int len, int idx) { + int nRet = 0; + + #pragma GCC unroll 0 + for (int i = 0; i < len; i++) { + Array *p = pp[i]; + if (p) { + nRet += p->elems[idx]; + } + } + + return nRet; +} + +// { dg-final { scan-assembler-times {ld1w\tz[0-9]+\.d, p[0-7]/z} 1 } } +// { dg-final { scan-assembler-times {add\tz[0-9]+\.s, p[0-7]/m} 1 } } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pack_fcvt_signed_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pack_fcvt_signed_1.c index 367fbd9..5c76cbd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pack_fcvt_signed_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pack_fcvt_signed_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize --param aarch64-vect-compare-costs=0" } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pack_fcvt_unsigned_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pack_fcvt_unsigned_1.c index c5da480..5e3881a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pack_fcvt_unsigned_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pack_fcvt_unsigned_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize --param aarch64-vect-compare-costs=0" } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pack_float_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pack_float_1.c index 2683a87..4810df8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pack_float_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pack_float_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize --param aarch64-vect-compare-costs=0" } */ void __attribute__ ((noinline, noclone)) pack_float_plus_1point1 (float *d, double *s, int size) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary.c index a8fd4c8..4708d57 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_int_opt_n.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_int_opt_n.c index 08cd6a0..4530b18 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_int_opt_n.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_int_opt_n.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_opt_n.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_opt_n.c index f5c9cbf..3097459 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_opt_n.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_opt_n.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_opt_single_n.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_opt_single_n.c index 91ae3c8..5e9d21c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_opt_single_n.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_opt_single_n.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_rotate.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_rotate.c index 12368ce..768a740 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_rotate.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_rotate.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_uint64_opt_n.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_uint64_opt_n.c index dd52a58..ce14abb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_uint64_opt_n.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_uint64_opt_n.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_uint_opt_n.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_uint_opt_n.c index e55ddfb..ceeb5ae 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_uint_opt_n.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binary_uint_opt_n.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binaryxn.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binaryxn.c index 6796229..f8b6b82 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binaryxn.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-binaryxn.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-clast.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-clast.c index 7f2ec4a..45f74ed 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-clast.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-clast.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-compare_opt_n.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-compare_opt_n.c index d18427b..fc601a1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-compare_opt_n.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-compare_opt_n.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-compare_wide_opt_n.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-compare_wide_opt_n.c index 983ab5c..4959f1d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-compare_wide_opt_n.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-compare_wide_opt_n.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-count_pred.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-count_pred.c index de36b66..d8a8a81 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-count_pred.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-count_pred.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-unary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-fold_left.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-fold_left.c index 333140d..6cf2683 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-fold_left.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-fold_left.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load.c index 93d6693..a32b636 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_ext.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_ext.c index c88686a..72e743b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_ext.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_ext.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_ext_gather_index.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_ext_gather_index.c index 5f4b562fc..1178104 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_ext_gather_index.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_ext_gather_index.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_ext_gather_offset.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_ext_gather_offset.c index 0fe8ab3..ebd313a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_ext_gather_offset.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_ext_gather_offset.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_gather_sv.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_gather_sv.c index 758f00f..d531987 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_gather_sv.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_gather_sv.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_gather_vs.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_gather_vs.c index f82471f..55c9cef 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_gather_vs.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_gather_vs.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_replicate.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_replicate.c index ba500b6..5532232 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_replicate.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-load_replicate.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2 -march=armv8.2-a+sve+f64mm" } */ +/* { dg-options "-O2 -march=armv8.2-a+sve+f64mm -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-prefetch.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-prefetch.c index 71894c4..78bdb0b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-prefetch.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-prefetch.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-prefetch_gather_index.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-prefetch_gather_index.c index 1b7cc42..e219007 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-prefetch_gather_index.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-prefetch_gather_index.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-prefetch_gather_offset.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-prefetch_gather_offset.c index 7f4ff2d..98897e9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-prefetch_gather_offset.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-prefetch_gather_offset.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-ptest.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-ptest.c index 0a587fc..c6fe6b9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-ptest.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-ptest.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-unary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-rdffr.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-rdffr.c index d795f8e..7e2c1b9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-rdffr.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-rdffr.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-reduction.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-reduction.c index 42b37ae..f7f75f6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-reduction.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-reduction.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* { dg-options "-O2 -fdump-tree-optimized -funwind-tables" } */ #include "../pfalse-unary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-reduction_wide.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-reduction_wide.c index bd9a980..54b6197 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-reduction_wide.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-reduction_wide.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-unary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-shift_right_imm.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-shift_right_imm.c index 62a0755..e8b8a55 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-shift_right_imm.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-shift_right_imm.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store.c index 751e60e..1539f58 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store_scatter_index.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store_scatter_index.c index 44792d3..21c8f6b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store_scatter_index.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store_scatter_index.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store_scatter_offset.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store_scatter_offset.c index f3820e0..a908289 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store_scatter_offset.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-store_scatter_offset.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-storexn.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-storexn.c index e49266d..12b5e14 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-storexn.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-storexn.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-ternary_opt_n.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-ternary_opt_n.c index acdd141..89873fc 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-ternary_opt_n.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-ternary_opt_n.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-ternary_rotate.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-ternary_rotate.c index 7698045..c6d2cfb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-ternary_rotate.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-ternary_rotate.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary.c index 037376b..8a3b3e0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-unary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_convert_narrowt.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_convert_narrowt.c index 1287a70..04bc049 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_convert_narrowt.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_convert_narrowt.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2 -march=armv8.2-a+sve+bf16" } */ +/* { dg-options "-O2 -march=armv8.2-a+sve+bf16 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_convertxn.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_convertxn.c index f519266..f39d2c5 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_convertxn.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_convertxn.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2 -march=armv8.2-a+sve+bf16" } */ +/* { dg-options "-O2 -march=armv8.2-a+sve+bf16 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_n.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_n.c index fabde3e..4403e50 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_n.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_n.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_pred.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_pred.c index 46c9592..f06b067 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_pred.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_pred.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-unary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_to_uint.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_to_uint.c index b820bde..a851c4a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_to_uint.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unary_to_uint.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-unary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unaryxn.c b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unaryxn.c index 1e99b7f..dde812b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unaryxn.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pfalse-unaryxn.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-unary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr96357.c b/gcc/testsuite/gcc.target/aarch64/sve/pr96357.c index 9a7f912..6dd0409 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pr96357.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr96357.c @@ -5,10 +5,10 @@ int d; void f1(char f, char *g, char *h, char *l, char *n) { - double i = d, j = 1.0 - f, k = j ? d : j; - if (k == 1.0) - i = 0.0; - *l = *n = *g = *h = i * 0.5; + double j = 1.0 - f, k = j ? d : j; + + char i = (k == 1.0) ? 10 : 50; + *l = *n = *g = *h = i; } void diff --git a/gcc/testsuite/gcc.target/aarch64/sve/shift_rev_1.c b/gcc/testsuite/gcc.target/aarch64/sve/shift_rev_1.c new file mode 100644 index 0000000..29ed378 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/shift_rev_1.c @@ -0,0 +1,83 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=armv8.2-a+sve" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include <arm_sve.h> + +/* +** ror32_sve_lsl_imm: +** ptrue (p[0-3]).b, all +** revw z0.d, \1/m, z0.d +** ret +*/ +svuint64_t +ror32_sve_lsl_imm (svuint64_t r) +{ + return svorr_u64_z (svptrue_b64 (), svlsl_n_u64_z (svptrue_b64 (), r, 32), + svlsr_n_u64_z (svptrue_b64 (), r, 32)); +} + +/* +** ror32_sve_lsl_operand: +** ptrue (p[0-3]).b, all +** revw z0.d, \1/m, z0.d +** ret +*/ +svuint64_t +ror32_sve_lsl_operand (svuint64_t r) +{ + svbool_t pt = svptrue_b64 (); + return svorr_u64_z (pt, svlsl_n_u64_z (pt, r, 32), svlsr_n_u64_z (pt, r, 32)); +} + +/* +** ror16_sve_lsl_imm: +** ptrue (p[0-3]).b, all +** revh z0.s, \1/m, z0.s +** ret +*/ +svuint32_t +ror16_sve_lsl_imm (svuint32_t r) +{ + return svorr_u32_z (svptrue_b32 (), svlsl_n_u32_z (svptrue_b32 (), r, 16), + svlsr_n_u32_z (svptrue_b32 (), r, 16)); +} + +/* +** ror16_sve_lsl_operand: +** ptrue (p[0-3]).b, all +** revh z0.s, \1/m, z0.s +** ret +*/ +svuint32_t +ror16_sve_lsl_operand (svuint32_t r) +{ + svbool_t pt = svptrue_b32 (); + return svorr_u32_z (pt, svlsl_n_u32_z (pt, r, 16), svlsr_n_u32_z (pt, r, 16)); +} + +/* +** ror8_sve_lsl_imm: +** ptrue (p[0-3]).b, all +** revb z0.h, \1/m, z0.h +** ret +*/ +svuint16_t +ror8_sve_lsl_imm (svuint16_t r) +{ + return svorr_u16_z (svptrue_b16 (), svlsl_n_u16_z (svptrue_b16 (), r, 8), + svlsr_n_u16_z (svptrue_b16 (), r, 8)); +} + +/* +** ror8_sve_lsl_operand: +** ptrue (p[0-3]).b, all +** revb z0.h, \1/m, z0.h +** ret +*/ +svuint16_t +ror8_sve_lsl_operand (svuint16_t r) +{ + svbool_t pt = svptrue_b16 (); + return svorr_u16_z (pt, svlsl_n_u16_z (pt, r, 8), svlsr_n_u16_z (pt, r, 8)); +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/shift_rev_2.c b/gcc/testsuite/gcc.target/aarch64/sve/shift_rev_2.c new file mode 100644 index 0000000..2d380b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/shift_rev_2.c @@ -0,0 +1,63 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=armv8.2-a+sve" } */ + +#include <arm_sve.h> + +#define PTRUE_B(BITWIDTH) svptrue_b##BITWIDTH () + +#define ROR_SVE_LSL(NAME, INPUT_TYPE, SHIFT_AMOUNT, BITWIDTH) \ + INPUT_TYPE \ + NAME##_imm (INPUT_TYPE r) \ + { \ + return svorr_u##BITWIDTH##_z (PTRUE_B (BITWIDTH), \ + svlsl_n_u##BITWIDTH##_z (PTRUE_B (BITWIDTH), \ + r, SHIFT_AMOUNT), \ + svlsr_n_u##BITWIDTH##_z (PTRUE_B (BITWIDTH), \ + r, SHIFT_AMOUNT)); \ + } \ + \ + INPUT_TYPE \ + NAME##_operand (INPUT_TYPE r) \ + { \ + svbool_t pt = PTRUE_B (BITWIDTH); \ + return svorr_u##BITWIDTH##_z ( \ + pt, svlsl_n_u##BITWIDTH##_z (pt, r, SHIFT_AMOUNT), \ + svlsr_n_u##BITWIDTH##_z (pt, r, SHIFT_AMOUNT)); \ + } + +/* Make sure that the pattern doesn't match incorrect bit-widths, eg. a shift of + 8 matching the 32-bit mode. */ + +ROR_SVE_LSL (higher_ror32, svuint64_t, 64, 64); +ROR_SVE_LSL (higher_ror16, svuint32_t, 32, 32); +ROR_SVE_LSL (higher_ror8, svuint16_t, 16, 16); + +ROR_SVE_LSL (lower_ror32, svuint64_t, 16, 64); +ROR_SVE_LSL (lower_ror16, svuint32_t, 8, 32); +ROR_SVE_LSL (lower_ror8, svuint16_t, 4, 16); + +/* Check off-by-one cases. */ + +ROR_SVE_LSL (off_1_high_ror32, svuint64_t, 33, 64); +ROR_SVE_LSL (off_1_high_ror16, svuint32_t, 17, 32); +ROR_SVE_LSL (off_1_high_ror8, svuint16_t, 9, 16); + +ROR_SVE_LSL (off_1_low_ror32, svuint64_t, 31, 64); +ROR_SVE_LSL (off_1_low_ror16, svuint32_t, 15, 32); +ROR_SVE_LSL (off_1_low_ror8, svuint16_t, 7, 16); + +/* Check out of bounds cases. */ + +ROR_SVE_LSL (oob_ror32, svuint64_t, 65, 64); +ROR_SVE_LSL (oob_ror16, svuint32_t, 33, 32); +ROR_SVE_LSL (oob_ror8, svuint16_t, 17, 16); + +/* Check zero case. */ + +ROR_SVE_LSL (zero_ror32, svuint64_t, 0, 64); +ROR_SVE_LSL (zero_ror16, svuint32_t, 0, 32); +ROR_SVE_LSL (zero_ror8, svuint16_t, 0, 16); + +/* { dg-final { scan-assembler-times "\trevb\t" 0 } } */ +/* { dg-final { scan-assembler-times "\trevh\t" 0 } } */ +/* { dg-final { scan-assembler-times "\trevw\t" 0 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/shift_rev_3.c b/gcc/testsuite/gcc.target/aarch64/sve/shift_rev_3.c new file mode 100644 index 0000000..126766d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/shift_rev_3.c @@ -0,0 +1,83 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=armv8.2-a+sve+sve2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include <arm_sve.h> + +/* +** lsl_usra_32_sve_lsl_imm: +** lsl z0.d, z1.d, #34 +** usra z0.d, z1.d, #30 +** ret +*/ +svuint64_t +lsl_usra_32_sve_lsl_imm (svuint64_t __attribute__ ((unused)) dummy, svuint64_t r) +{ + return svorr_u64_z (svptrue_b64 (), svlsl_n_u64_z (svptrue_b64 (), r, 34), + svlsr_n_u64_z (svptrue_b64 (), r, 30)); +} + +/* +** lsl_usra_32_sve_lsl_operand: +** lsl z0.d, z1.d, #34 +** usra z0.d, z1.d, #30 +** ret +*/ +svuint64_t +lsl_usra_32_sve_lsl_operand (svuint64_t __attribute__ ((unused)) dummy, svuint64_t r) +{ + svbool_t pt = svptrue_b64 (); + return svorr_u64_z (pt, svlsl_n_u64_z (pt, r, 34), svlsr_n_u64_z (pt, r, 30)); +} + +/* +** lsl_usra_16_sve_lsl_imm: +** lsl z0.s, z1.s, #14 +** usra z0.s, z1.s, #18 +** ret +*/ +svuint32_t +lsl_usra_16_sve_lsl_imm (svuint32_t __attribute__ ((unused)) dummy, svuint32_t r) +{ + return svorr_u32_z (svptrue_b32 (), svlsl_n_u32_z (svptrue_b32 (), r, 14), + svlsr_n_u32_z (svptrue_b32 (), r, 18)); +} + +/* +** lsl_usra_16_sve_lsl_operand: +** lsl z0.s, z1.s, #14 +** usra z0.s, z1.s, #18 +** ret +*/ +svuint32_t +lsl_usra_16_sve_lsl_operand (svuint32_t __attribute__ ((unused)) dummy, svuint32_t r) +{ + svbool_t pt = svptrue_b32 (); + return svorr_u32_z (pt, svlsl_n_u32_z (pt, r, 14), svlsr_n_u32_z (pt, r, 18)); +} + +/* +** lsl_usra_8_sve_lsl_imm: +** lsl z0.h, z1.h, #6 +** usra z0.h, z1.h, #10 +** ret +*/ +svuint16_t +lsl_usra_8_sve_lsl_imm (svuint16_t __attribute__ ((unused)) dummy, svuint16_t r) +{ + return svorr_u16_z (svptrue_b16 (), svlsl_n_u16_z (svptrue_b16 (), r, 6), + svlsr_n_u16_z (svptrue_b16 (), r, 10)); +} + +/* +** lsl_usra_8_sve_lsl_operand: +** lsl z0.h, z1.h, #6 +** usra z0.h, z1.h, #10 +** ret +*/ +svuint16_t +lsl_usra_8_sve_lsl_operand (svuint16_t __attribute__ ((unused)) dummy, svuint16_t r) +{ + svbool_t pt = svptrue_b16 (); + return svorr_u16_z (pt, svlsl_n_u16_z (pt, r, 6), svlsr_n_u16_z (pt, r, 10)); +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpack_float_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpack_float_1.c index deb4cf5..d1e74634 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/unpack_float_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpack_float_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize --param aarch64-vect-compare-costs=0" } */ void __attribute__ ((noinline, noclone)) unpack_float_plus_7point9 (double *d, float *s, int size) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmax_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmax_1.c new file mode 100644 index 0000000..e6aa047 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmax_1.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##RHS (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i], RHS) > c[i]) \ + out[i] = 3; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1) + +TEST_ALL (__builtin_fmaxf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_fmaxf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_fmaxf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 6 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmax_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmax_2.c new file mode 100644 index 0000000..87125a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmax_2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_builtin_fmax_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 9 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmin_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmin_1.c new file mode 100644 index 0000000..b9fded0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmin_1.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##RHS (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i], RHS) > c[i]) \ + out[i] = 3; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1) + +TEST_ALL (__builtin_fminf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_fminf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_fminf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 6 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmin_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmin_2.c new file mode 100644 index 0000000..5923b67 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmin_2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_builtin_fmin_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 9 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmax_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmax_1.c new file mode 100644 index 0000000..d328b37 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmax_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##RHS##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, b_i) + +TEST_ALL (__builtin_fmaxf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_fmaxf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_fmaxf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmax_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmax_2.c new file mode 100644 index 0000000..f84ded5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmax_2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_builtin_fmax_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 14 } } */ +/* { dg-final { scan-assembler-times {\tand} 21 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmin_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmin_1.c new file mode 100644 index 0000000..1821f03 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmin_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##RHS##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, b_i) + +TEST_ALL (__builtin_fminf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_fminf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_fminf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmin_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmin_2.c new file mode 100644 index 0000000..bceddf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmin_2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_builtin_fmin_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 14 } } */ +/* { dg-final { scan-assembler-times {\tand} 21 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_cvtf_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_cvtf_1.c new file mode 100644 index 0000000..fa4dd15 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_cvtf_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define COND_CVT(TYPE0, TYPE1, TYPE2, COUNT) \ + void \ + test_##TYPE0##_##TYPE1##_##TYPE2 (TYPE0 *__restrict out, \ + TYPE1 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE2 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? (TYPE0)a[i] : b[i]; \ + } + +#define TEST_CVTF(PFX, T) \ + T (_Float16, PFX##int16_t, uint64_t, 32) \ + T (_Float16, PFX##int16_t, uint32_t, 64) \ + T (_Float16, PFX##int32_t, uint64_t, 32) \ + T (_Float16, PFX##int32_t, uint32_t, 64) \ + T (_Float16, PFX##int64_t, uint64_t, 32) \ + T (float, PFX##int32_t, uint64_t, 32) \ + T (float, PFX##int64_t, uint64_t, 32) + +#define TEST_ALL(T) \ + TEST_CVTF (, T) \ + TEST_CVTF (u, T) + +TEST_ALL (COND_CVT) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 8 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 6 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 8 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fabs_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fabs_1.c new file mode 100644 index 0000000..d959aa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fabs_1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (__builtin_fabsf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_fabsf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_fabsf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fadd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fadd_1.c new file mode 100644 index 0000000..666cf89 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fadd_1.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] +#define imm_p5 0.5 + +#define ADD(A, B) A + B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, NAME, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##NAME##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b[i], a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b[i], b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b[i], c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, one, 1, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, one, 1, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, none, -1, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, none, -1, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, p5, 0.5, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, p5, 0.5, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, np5, -0.5, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, np5, -0.5, b_i) + +TEST_ALL (ADD, _Float16, uint64_t, 32) + +TEST_ALL (ADD, _Float16, uint32_t, 64) + +TEST_ALL (ADD, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 19 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 19 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 19 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 5 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 10 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fadd_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fadd_2.c new file mode 100644 index 0000000..e59864b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fadd_2.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fadd_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 11 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 22 } } */ +/* { dg-final { scan-assembler-times {\tand} 33 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 19 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 19 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 19 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 5 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 10 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fcvt_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fcvt_1.c new file mode 100644 index 0000000..3caae19 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fcvt_1.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define COND_CVT(TYPE0, TYPE1, TYPE2, COUNT) \ + void \ + test_##TYPE0##_##TYPE1##_##TYPE2 (TYPE0 *__restrict out, \ + TYPE1 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE2 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? (TYPE0)a[i] : b[i]; \ + } + +#define TEST_FCVT(T) \ + T (_Float16, float, uint64_t, 32) \ + T (_Float16, float, uint32_t, 64) \ + T (_Float16, double, uint64_t, 32) \ + T (float, double, uint64_t, 32) \ + T (float, _Float16, uint64_t, 32) \ + T (float, _Float16, uint32_t, 64) \ + T (double, _Float16, uint64_t,32) \ + T (double, float, uint64_t, 32) + +TEST_FCVT (COND_CVT) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.h\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fcvtz_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fcvtz_1.c new file mode 100644 index 0000000..426d3af --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fcvtz_1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define COND_CVT(TYPE0, TYPE1, TYPE2, COUNT) \ + void \ + test_##TYPE0##_##TYPE1##_##TYPE2 (TYPE0 *__restrict out, \ + TYPE1 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE2 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? (TYPE0)a[i] : b[i]; \ + } + +#define TEST_FCVTZ(PFX, T) \ + T (PFX##int16_t, _Float16, uint64_t, 32) \ + T (PFX##int16_t, _Float16, uint32_t, 64) \ + T (PFX##int32_t, _Float16, uint64_t, 32) \ + T (PFX##int32_t, _Float16, uint32_t, 64) \ + T (PFX##int64_t, _Float16, uint64_t, 32) \ + T (PFX##int32_t, float, uint64_t, 32) \ + T (PFX##int64_t, float, uint64_t, 32) \ + T (PFX##int32_t, double, uint64_t, 32) + +#define TEST_ALL(T) \ + TEST_FCVTZ (, T) \ + TEST_FCVTZ (u, T) + +TEST_ALL (COND_CVT) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 10 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 6 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 8 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.h\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.h\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fdiv_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fdiv_1.c new file mode 100644 index 0000000..ec5653e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fdiv_1.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define DIV(A, B) A / B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##RHS##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, c_i) + +TEST_ALL (DIV, _Float16, uint64_t, 32) + +TEST_ALL (DIV, _Float16, uint32_t, 64) + +TEST_ALL (DIV, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfdivr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfdiv\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfdivr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfdiv\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fdiv_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fdiv_2.c new file mode 100644 index 0000000..1ca3dbf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fdiv_2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fdiv_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 6 } } */ +/* { dg-final { scan-assembler-times {\tand} 9 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfdivr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfdiv\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfdivr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfdiv\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmaxnm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmaxnm_1.c new file mode 100644 index 0000000..d34872f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmaxnm_1.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-signed-zeros -ffinite-math-only -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define MAX(A, B) (A > B) ? A : B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##RHS##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, b_i) + +TEST_ALL (MAX, _Float16, uint64_t, 32) + +TEST_ALL (MAX, _Float16, uint32_t, 64) + +TEST_ALL (MAX, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmaxnm_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmaxnm_2.c new file mode 100644 index 0000000..282f3ed --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmaxnm_2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-signed-zeros -ffinite-math-only" } */ + +#include "unpacked_cond_fmaxnm_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 14 } } */ +/* { dg-final { scan-assembler-times {\tand} 21 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fminnm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fminnm_1.c new file mode 100644 index 0000000..d6c3c38 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fminnm_1.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-signed-zeros -ffinite-math-only -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define MIN(A, B) (A < B) ? A : B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##RHS##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, b_i) + +TEST_ALL (MIN, _Float16, uint64_t, 32) + +TEST_ALL (MIN, _Float16, uint32_t, 64) + +TEST_ALL (MIN, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fminnm_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fminnm_2.c new file mode 100644 index 0000000..8226a6f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fminnm_2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-signed-zeros -ffinite-math-only" } */ + +#include "unpacked_cond_fminnm_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 14 } } */ +/* { dg-final { scan-assembler-times {\tand} 21 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmla_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmla_1.c new file mode 100644 index 0000000..cae9242 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmla_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) + +TEST_ALL (FMLA (f16), _Float16, uint64_t, 32) + +TEST_ALL (FMLA (f16), _Float16, uint32_t, 64) + +TEST_ALL (FMLA (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmad\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmad\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmla_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmla_2.c new file mode 100644 index 0000000..72e04a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmla_2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fmla_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 8 } } */ +/* { dg-final { scan-assembler-times {\tand} 12 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmad\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmad\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmls_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmls_1.c new file mode 100644 index 0000000..db0f818 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmls_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) + +TEST_ALL (FMLS (f16), _Float16, uint64_t, 32) + +TEST_ALL (FMLS (f16), _Float16, uint32_t, 64) + +TEST_ALL (FMLS (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmsb\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmsb\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmls_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmls_2.c new file mode 100644 index 0000000..3012052 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmls_2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fmls_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 8 } } */ +/* { dg-final { scan-assembler-times {\tand} 12 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmsb\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmsb\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmul_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmul_1.c new file mode 100644 index 0000000..1ae7678 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmul_1.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] +#define imm_p5 0.5 + +#define MUL(A, B) A * B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##RHS##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, imm_p5, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, imm_p5, b_i) + +TEST_ALL (MUL, _Float16, uint64_t, 32) + +TEST_ALL (MUL, _Float16, uint32_t, 64) + +TEST_ALL (MUL, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 10 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 10 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 10 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmul_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmul_2.c new file mode 100644 index 0000000..21713f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmul_2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fmul_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 5 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 10 } } */ +/* { dg-final { scan-assembler-times {\tand} 15 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 10 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 10 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 10 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fneg_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fneg_1.c new file mode 100644 index 0000000..7280f4e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fneg_1.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define NEG(X) -X + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (NEG, _Float16, uint64_t, 32) + +TEST_ALL (NEG, _Float16, uint32_t, 64) + +TEST_ALL (NEG, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmla_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmla_1.c new file mode 100644 index 0000000..07bab63 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmla_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) + +TEST_ALL (FNMLA (f16), _Float16, uint64_t, 32) + +TEST_ALL (FNMLA (f16), _Float16, uint32_t, 64) + +TEST_ALL (FNMLA (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfnmla\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmad\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmad\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfnmla\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmla_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmla_2.c new file mode 100644 index 0000000..daef4e49 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmla_2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fnmla_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 8 } } */ +/* { dg-final { scan-assembler-times {\tand} 12 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfnmad\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmla\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmad\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfnmla\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmls_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmls_1.c new file mode 100644 index 0000000..5526378 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmls_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) + +TEST_ALL (FNMLS (f16), _Float16, uint64_t, 32) + +TEST_ALL (FNMLS (f16), _Float16, uint32_t, 64) + +TEST_ALL (FNMLS (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfnmsb\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmls\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmsb\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfnmls\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmls_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmls_2.c new file mode 100644 index 0000000..8a8f348 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmls_2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fnmls_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 8 } } */ +/* { dg-final { scan-assembler-times {\tand} 12 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfnmsb\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmls\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmsb\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfnmls\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_1.c new file mode 100644 index 0000000..ed4efb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (__builtin_roundf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_roundf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_roundf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c new file mode 100644 index 0000000..f20e2e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -mtune=generic -ftree-vectorize" } */ + +#include "unpacked_cond_frinta_1.c" + +/* Test that we don't drop SELs without -fno-trapping-math. */ + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tsel\t} 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinti_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinti_1.c new file mode 100644 index 0000000..d682d15 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinti_1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (__builtin_nearbyintf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_nearbyintf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_nearbyintf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfrinti\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrinti\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintm_1.c new file mode 100644 index 0000000..7d429b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintm_1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (__builtin_floorf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_floorf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_floorf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfrintm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrintm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintp_1.c new file mode 100644 index 0000000..c6d0c8c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintp_1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (__builtin_ceilf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_ceilf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_ceilf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfrintp\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrintp\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintx_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintx_1.c new file mode 100644 index 0000000..b8afef1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintx_1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (__builtin_rintf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_rintf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_rintf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfrintx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrintx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintz_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintz_1.c new file mode 100644 index 0000000..d55279b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintz_1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (__builtin_truncf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_truncf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_truncf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfrintz\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrintz\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fsubr_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fsubr_1.c new file mode 100644 index 0000000..eafd169 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fsubr_1.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] +#define imm_p5 0.5 + +#define SUBR(A, B) B - A + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##RHS##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, imm_p5, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, imm_p5, b_i) + +TEST_ALL (SUBR, _Float16, uint64_t, 32) + +TEST_ALL (SUBR, _Float16, uint32_t, 64) + +TEST_ALL (SUBR, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fsubr_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fsubr_2.c new file mode 100644 index 0000000..cd7a0e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fsubr_2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fsubr_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 14 } } */ +/* { dg-final { scan-assembler-times {\tand} 21 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cvtf_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cvtf_1.c new file mode 100644 index 0000000..76baffa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cvtf_1.c @@ -0,0 +1,217 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=2048 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include <stdint.h> + +typedef _Float16 v32hf __attribute__((vector_size(64))); +typedef _Float16 v64hf __attribute__((vector_size(128))); + +typedef float v32sf __attribute__((vector_size(128))); +typedef float v64sf __attribute__((vector_size(256))); + +typedef double v32df __attribute__((vector_size(256))); + +typedef int16_t v32hi __attribute__((vector_size(64))); +typedef int16_t v64hi __attribute__((vector_size(128))); +typedef uint16_t v32uhi __attribute__((vector_size(64))); +typedef uint16_t v64uhi __attribute__((vector_size(128))); + +typedef int32_t v32si __attribute__((vector_size(128))); +typedef int32_t v64si __attribute__((vector_size(256))); +typedef uint32_t v32usi __attribute__((vector_size(128))); +typedef uint32_t v64usi __attribute__((vector_size(256))); + +typedef int64_t v32di __attribute__((vector_size(256))); +typedef uint64_t v32udi __attribute__((vector_size(256))); + +/* +** float_2hf2hi: +** ... +** ld1h (z[0-9]+)\.d, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.d, vl32 +** scvtf (z[0-9]+)\.h, \2/m, \1\.h +** ... +*/ +v32hf +float_2hf2hi (v32hi x) +{ + return __builtin_convertvector (x, v32hf); +} + +/* +** float_2hf2uhi: +** ... +** ld1h (z[0-9]+)\.d, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.d, vl32 +** ucvtf (z[0-9]+)\.h, \2/m, \1\.h +** ... +*/ +v32hf +float_2hf2uhi (v32uhi x) +{ + return __builtin_convertvector (x, v32hf); +} + +/* +** float_2hf2si: +** ... +** ld1w (z[0-9]+)\.d, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.d, vl32 +** scvtf (z[0-9]+)\.h, \2/m, \1\.s +** ... +*/ +v32hf +float_2hf2si (v32si x) +{ + return __builtin_convertvector (x, v32hf); +} + +/* +** float_2hf2usi: +** ... +** ld1w (z[0-9]+)\.d, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.d, vl32 +** ucvtf (z[0-9]+)\.h, \2/m, \1\.s +** ... +*/ +v32hf +float_2hf2usi (v32usi x) +{ + return __builtin_convertvector (x, v32hf); +} + +/* +** float_2hf2di: +** ptrue (p[0-7])\.b, vl256 +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** scvtf (z[0-9]+)\.h, \1/m, \2\.d +** ... +*/ +v32hf +float_2hf2di (v32di x) +{ + return __builtin_convertvector (x, v32hf); +} + +/* +** float_2hf2udi: +** ptrue (p[0-7])\.b, vl256 +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** ucvtf (z[0-9]+)\.h, \1/m, \2\.d +** ... +*/ +v32hf +float_2hf2udi (v32udi x) +{ + return __builtin_convertvector (x, v32hf); +} + +/* +** float_4hf4hi: +** ... +** ld1h (z[0-9]+)\.s, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.s, vl64 +** scvtf (z[0-9]+)\.h, \2/m, \1\.h +** ... +*/ +v64hf +float_4hf4hi (v64hi x) +{ + return __builtin_convertvector (x, v64hf); +} + +/* +** float_4hf4uhi: +** ... +** ld1h (z[0-9]+)\.s, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.s, vl64 +** ucvtf (z[0-9]+)\.h, \2/m, \1\.h +** ... +*/ +v64hf +float_4hf4uhi (v64uhi x) +{ + return __builtin_convertvector (x, v64hf); +} + +/* +** float_4hf4si: +** ptrue (p[0-7])\.b, vl256 +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** scvtf (z[0-9]+)\.h, \1/m, \2\.s +** ... +*/ +v64hf +float_4hf4si (v64si x) +{ + return __builtin_convertvector (x, v64hf); +} + +/* +** float_4hf4usi: +** ptrue (p[0-7])\.b, vl256 +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** ucvtf (z[0-9]+)\.h, \1/m, \2\.s +** ... +*/ +v64hf +float_4hf4usi (v64usi x) +{ + return __builtin_convertvector (x, v64hf); +} + +/* +** float_2sf2si: +** ... +** ld1w (z[0-9]+)\.d, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.d, vl32 +** scvtf (z[0-9]+)\.s, \2/m, \1\.s +** ... +*/ +v32sf +float_2sf2si (v32si x) +{ + return __builtin_convertvector (x, v32sf); +} + +/* +** float_2sf2usi: +** ... +** ld1w (z[0-9]+)\.d, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.d, vl32 +** ucvtf (z[0-9]+)\.s, \2/m, \1\.s +** ... +*/ +v32sf +float_2sf2usi (v32usi x) +{ + return __builtin_convertvector (x, v32sf); +} + +/* +** float_2sf2di: +** ptrue (p[0-7])\.b, vl256 +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** scvtf (z[0-9]+)\.s, \1/m, \2\.d +** ... +*/ +v32sf +float_2sf2di (v32di x) +{ + return __builtin_convertvector (x, v32sf); +} + +/* +** float_2sf2udi: +** ptrue (p[0-7])\.b, vl256 +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** ucvtf (z[0-9]+)\.s, \1/m, \2\.d +** ... +*/ +v32sf +float_2sf2udi (v32udi x) +{ + return __builtin_convertvector (x, v32sf); +} + +/* { dg-final { check-function-bodies "**" "" ""} } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cvtf_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cvtf_2.c new file mode 100644 index 0000000..f578bcf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cvtf_2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=2048 -fno-trapping-math" } */ + +#include "unpacked_cvtf_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 14 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cvtf_3.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cvtf_3.c new file mode 100644 index 0000000..6324bdd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cvtf_3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include <stdint.h> + +void f64_i32 (double *restrict x, int32_t *restrict y, int n) +{ + for (int i = 0; i < n; i++) + x[i] = (double)y[i]; +} + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.[sd], p[0-7]/m, z[0-9]+\.d\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fabs_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fabs_1.c new file mode 100644 index 0000000..f09cfe8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fabs_1.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (__builtin_fabsf16, _Float16, uint64_t, 32) + +TEST_FN (__builtin_fabsf16, _Float16, uint32_t, 64) + +TEST_FN (__builtin_fabsf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fadd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fadd_1.c new file mode 100644 index 0000000..9675f56 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fadd_1.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define ADD(A, B) A + B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, NAME, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##NAME (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i], (TYPE0)RHS) > c[i]) \ + out[i] = 3; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b[i]) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, p5, 0.5) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, np5, -0.5) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, one, 1) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, none, -1) + +TEST_ALL (ADD, _Float16, uint64_t, 32) + +TEST_ALL (ADD, _Float16, uint32_t, 64) + +TEST_ALL (ADD, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 5 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 10 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 11 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 11 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 11 } } */ + +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fadd_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fadd_2.c new file mode 100644 index 0000000..7a74efd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fadd_2.c @@ -0,0 +1,26 @@ +/* { dg-do compile }*/ +/* { dg-options "-O2 -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fadd_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 12 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 11 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 11 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 11 } } */ + +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_1.c new file mode 100644 index 0000000..bf9c127 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_1.c @@ -0,0 +1,602 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 --param=aarch64-autovec-preference=sve-only -fno-schedule-insns -fno-schedule-insns2" } */ + +#include <stdint.h> + +#define UNLT(A, B) (!__builtin_isgreaterequal (A, B)) +#define UNLE(A, B) (!__builtin_isgreater (A, B)) +#define UNGT(A, B) (!__builtin_islessequal (A, B)) +#define UNGE(A, B) (!__builtin_isless (A, B)) +#define UNEQ(A, B) (!__builtin_islessgreater (A, B)) + +#define EQ(A, B) ((A) == (B)) +#define NE(A, B) ((A) != (B)) +#define LE(A, B) ((A) <= (B)) +#define LT(A, B) ((A) < (B)) +#define GE(A, B) ((A) >= (B)) +#define GT(A, B) ((A) > (B)) +#define ORDERED(A, B) (!__builtin_isunordered (A, B)) +#define UNORDERED(A, B) (__builtin_isunordered (A, B)) + +#define b_i b[i] + +#define TEST_FCM(TYPE0, TYPE1, CMP, RHS, COUNT) \ + void \ + f_##TYPE0##_##TYPE1##_##CMP##_##RHS (TYPE0 *__restrict out, \ + TYPE1 *__restrict a, \ + TYPE1 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = CMP (a[i], RHS) ? 3 : out[i]; \ + } + +#define TEST_CC_REG(CMP) \ + TEST_FCM (uint64_t, float, CMP, b_i, 32) \ + TEST_FCM (uint32_t, _Float16, CMP, b_i, 64) \ + TEST_FCM (uint64_t, _Float16, CMP, b_i, 32) + +#define TEST_CC_ALL(CMP) \ + TEST_CC_REG (CMP) \ + TEST_FCM (uint64_t, float, CMP, 0, 32) \ + TEST_FCM (uint32_t, _Float16, CMP, 0, 64) \ + TEST_FCM (uint64_t, _Float16, CMP, 0, 32) + + +/* +** f_uint64_t_float_UNLT_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmuo (p[0-9]+)\.s, \1/z, z[0-9]+\.s, z[0-9]+\.s +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmge p[0-9]+\.s, \3/z, z[0-9]+\.s, z[0-9]+\.s +** ... +*/ + +/* +** f_uint32_t__Float16_UNLT_b_i: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmuo (p[0-9]+)\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmge p[0-9]+\.h, \3/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t__Float16_UNLT_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmuo (p[0-9]+)\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmge p[0-9]+\.h, \3/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ +TEST_CC_REG (UNLT) + +/* +** f_uint64_t_float_UNLE_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmuo (p[0-9]+)\.s, \1/z, z[0-9]+\.s, z[0-9]+\.s +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmgt p[0-9]+\.s, \3/z, z[0-9]+\.s, z[0-9]+\.s +** ... +*/ + +/* +** f_uint32_t__Float16_UNLE_b_i: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmuo (p[0-9]+)\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmgt p[0-9]+\.h, \3/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t__Float16_UNLE_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmuo (p[0-9]+)\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmgt p[0-9]+\.h, \3/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ +TEST_CC_REG (UNLE) + +/* +** f_uint64_t_float_UNGT_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmuo (p[0-9]+)\.s, \1/z, z[0-9]+\.s, z[0-9]+\.s +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmle p[0-9]+\.s, \3/z, z[0-9]+\.s, z[0-9]+\.s +** ... +*/ + +/* +** f_uint32_t__Float16_UNGT_b_i: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmuo (p[0-9]+)\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmle p[0-9]+\.h, \3/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t__Float16_UNGT_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmuo (p[0-9]+)\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmle p[0-9]+\.h, \3/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ +TEST_CC_REG (UNGT) + +/* +** f_uint64_t_float_UNGE_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmuo (p[0-9]+)\.s, \1/z, z[0-9]+\.s, z[0-9]+\.s +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmlt p[0-9]+\.s, \3/z, z[0-9]+\.s, z[0-9]+\.s +** ... +*/ + +/* +** f_uint32_t__Float16_UNGE_b_i: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmuo (p[0-9]+)\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmlt p[0-9]+\.h, \3/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t__Float16_UNGE_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmuo (p[0-9]+)\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmlt p[0-9]+\.h, \3/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ +TEST_CC_REG (UNGE) + +/* +** f_uint64_t_float_UNEQ_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmuo (p[0-9]+)\.s, \1/z, z[0-9]+\.s, z[0-9]+\.s +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmne p[0-9]+\.s, \3/z, z[0-9]+\.s, z[0-9]+\.s +** ... +*/ + +/* +** f_uint32_t__Float16_UNEQ_b_i: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmuo (p[0-9]+)\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmne p[0-9]+\.h, \3/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t__Float16_UNEQ_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmuo (p[0-9]+)\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** not (p[0-9]+)\.b, \1/z, \2\.b +** fcmne p[0-9]+\.h, \3/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ +TEST_CC_REG (UNEQ) + +/* +** f_uint64_t_float_EQ_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmeq p[0-9]+\.s, \1/z, z[0-9]+\.s, z[0-9]+\.s +** ... +*/ + +/* +** f_uint32_t__Float16_EQ_b_i: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmeq p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t__Float16_EQ_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmeq p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t_float_EQ_0: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmeq p[0-9]+\.s, \1/z, z[0-9]+\.s, #0.0 +** ... +*/ + +/* +** f_uint32_t__Float16_EQ_0: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmeq p[0-9]+\.h, \1/z, z[0-9]+\.h, #0.0 +** ... +*/ + +/* +** f_uint64_t__Float16_EQ_0: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmeq p[0-9]+\.h, \1/z, z[0-9]+\.h, #0.0 +** ... +*/ +TEST_CC_ALL (EQ) + +/* +** f_uint64_t_float_NE_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmne p[0-9]+\.s, \1/z, z[0-9]+\.s, z[0-9]+\.s +** ... +*/ + +/* +** f_uint32_t__Float16_NE_b_i: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmne p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t__Float16_NE_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmne p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t_float_NE_0: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmne p[0-9]+\.s, \1/z, z[0-9]+\.s, #0.0 +** ... +*/ + +/* +** f_uint32_t__Float16_NE_0: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmne p[0-9]+\.h, \1/z, z[0-9]+\.h, #0.0 +** ... +*/ + +/* +** f_uint64_t__Float16_NE_0: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmne p[0-9]+\.h, \1/z, z[0-9]+\.h, #0.0 +** ... +*/ +TEST_CC_ALL (NE) + +/* +** f_uint64_t_float_LE_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmle p[0-9]+\.s, \1/z, z[0-9]+\.s, z[0-9]+\.s +** ... +*/ + +/* +** f_uint32_t__Float16_LE_b_i: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmle p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t__Float16_LE_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmle p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t_float_LE_0: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmle p[0-9]+\.s, \1/z, z[0-9]+\.s, #0.0 +** ... +*/ + +/* +** f_uint32_t__Float16_LE_0: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmle p[0-9]+\.h, \1/z, z[0-9]+\.h, #0.0 +** ... +*/ + +/* +** f_uint64_t__Float16_LE_0: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmle p[0-9]+\.h, \1/z, z[0-9]+\.h, #0.0 +** ... +*/ +TEST_CC_ALL (LE) + +/* +** f_uint64_t_float_LT_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmlt p[0-9]+\.s, \1/z, z[0-9]+\.s, z[0-9]+\.s +** ... +*/ + +/* +** f_uint32_t__Float16_LT_b_i: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmlt p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t__Float16_LT_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmlt p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t_float_LT_0: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmlt p[0-9]+\.s, \1/z, z[0-9]+\.s, #0.0 +** ... +*/ + +/* +** f_uint32_t__Float16_LT_0: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmlt p[0-9]+\.h, \1/z, z[0-9]+\.h, #0.0 +** ... +*/ + +/* +** f_uint64_t__Float16_LT_0: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmlt p[0-9]+\.h, \1/z, z[0-9]+\.h, #0.0 +** ... +*/ +TEST_CC_ALL (LT) + +/* +** f_uint64_t_float_GE_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmge p[0-9]+\.s, \1/z, z[0-9]+\.s, z[0-9]+\.s +** ... +*/ + +/* +** f_uint32_t__Float16_GE_b_i: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmge p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t__Float16_GE_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmge p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t_float_GE_0: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmge p[0-9]+\.s, \1/z, z[0-9]+\.s, #0.0 +** ... +*/ + +/* +** f_uint32_t__Float16_GE_0: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmge p[0-9]+\.h, \1/z, z[0-9]+\.h, #0.0 +** ... +*/ + +/* +** f_uint64_t__Float16_GE_0: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmge p[0-9]+\.h, \1/z, z[0-9]+\.h, #0.0 +** ... +*/ +TEST_CC_ALL (GE) + +/* +** f_uint64_t_float_GT_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmgt p[0-9]+\.s, \1/z, z[0-9]+\.s, z[0-9]+\.s +** ... +*/ + +/* +** f_uint32_t__Float16_GT_b_i: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmgt p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t__Float16_GT_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmgt p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t_float_GT_0: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmgt p[0-9]+\.s, \1/z, z[0-9]+\.s, #0.0 +** ... +*/ + +/* +** f_uint32_t__Float16_GT_0: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmgt p[0-9]+\.h, \1/z, z[0-9]+\.h, #0.0 +** ... +*/ + +/* +** f_uint64_t__Float16_GT_0: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmgt p[0-9]+\.h, \1/z, z[0-9]+\.h, #0.0 +** ... +*/ +TEST_CC_ALL (GT) + +/* +** f_uint64_t_float_ORDERED_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmuo p[0-9]+\.s, \1/z, z[0-9]+\.s, z[0-9]+\.s +** ... +*/ + +/* +** f_uint32_t__Float16_ORDERED_b_i: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmuo p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t__Float16_ORDERED_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmuo p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ +TEST_CC_REG (ORDERED) + +/* +** f_uint64_t_float_UNORDERED_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmuo p[0-9]+\.s, \1/z, z[0-9]+\.s, z[0-9]+\.s +** ... +*/ + +/* +** f_uint32_t__Float16_UNORDERED_b_i: +** ... +** ptrue (p[0-9]+)\.s, all +** ... +** fcmuo p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ + +/* +** f_uint64_t__Float16_UNORDERED_b_i: +** ... +** ptrue (p[0-9]+)\.d, all +** ... +** fcmuo p[0-9]+\.h, \1/z, z[0-9]+\.h, z[0-9]+\.h +** ... +*/ +TEST_CC_REG (UNORDERED) + + +/* { dg-final { check-function-bodies "**" "" ""} } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_2.c new file mode 100644 index 0000000..ab210da --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 --param=aarch64-autovec-preference=sve-only -fno-trapping-math" } */ + +#include "unpacked_fcm_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 32 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 32 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 32 } } */ + +/* { dg-final { scan-assembler-times {\tfcmeq\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfcmeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfcmeq\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcmeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcmne\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcmne\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcmne\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcmne\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcmle\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfcmle\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfcmle\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcmle\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcmlt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfcmlt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfcmlt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcmlt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcmge\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfcmge\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfcmge\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcmge\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcmgt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfcmgt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfcmgt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcmgt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcmuo\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfcmuo\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_combines_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_combines_1.c new file mode 100644 index 0000000..d793a6c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_combines_1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 --param=aarch64-autovec-preference=sve-only -fno-trapping-math" } */ + +#include "unpacked_fcm_1.c" + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 32 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 32 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 32 } } */ + +/* Drop a PTRUE predicated AND with the loop mask and comparison result in + favour of predicating the comparison with the loop mask. */ +/* { dg-final { scan-assembler-not {\tand\t} } } */ + +/* Similarly, for codes that are implemented via an inversion, prefer + NOT (predicated with the loop mask) over BIC+PTRUE. */ +/* { dg-final { scan-assembler-not {\tbic\t} } } */ +/* { dg-final { scan-assembler-times {\tnot\t} 15 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_combines_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_combines_2.c new file mode 100644 index 0000000..b85391b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_combines_2.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 --param=aarch64-autovec-preference=sve-only -fno-trapping-math" } */ + +#include <stdint.h> + +/* Ensure that we still emit NOR here, rather than two NOTs. */ + +#define TEST_FCM_NOR(TYPE0, TYPE1, CMP, COUNT) \ + void \ + f_##TYPE0##_##TYPE1##_##CMP (TYPE0 *__restrict out, \ + TYPE1 *__restrict a, \ + TYPE1 *__restrict b, \ + TYPE1 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = !(CMP (a[i], c[i]) | CMP (b[i], c[i])) ? 3 : out[i]; \ + } + +#define GT(A, B) ((A) > (B)) + +TEST_FCM_NOR (uint64_t, float, GT, 32) +TEST_FCM_NOR (uint64_t, _Float16, GT, 32) +TEST_FCM_NOR (uint32_t, _Float16, GT, 64) + +TEST_FCM_NOR (uint64_t, float, __builtin_isunordered, 32) +TEST_FCM_NOR (uint64_t, _Float16, __builtin_isunordered, 32) +TEST_FCM_NOR (uint32_t, _Float16, __builtin_isunordered, 64) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 6 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 6 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 6 } } */ + +/* { dg-final { scan-assembler-not {\tbic\t} } } */ +/* { dg-final { scan-assembler-not {\tnot\t} } } */ +/* { dg-final { scan-assembler-times {\tnor\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b\n} 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcvt_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcvt_1.c new file mode 100644 index 0000000..0babf15 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcvt_1.c @@ -0,0 +1,118 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=2048 -fno-schedule-insns -fno-schedule-insns2" } */ + +typedef _Float16 v32hf __attribute__((vector_size(64))); +typedef _Float16 v64hf __attribute__((vector_size(128))); + +typedef float v32sf __attribute__((vector_size(128))); +typedef float v64sf __attribute__((vector_size(256))); + +typedef double v32df __attribute__((vector_size(256))); + +/* +** trunc_2sf2df: +** ptrue (p[0-7])\.b, vl256 +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** fcvt (z[0-9]+)\.s, \1/m, \2\.d +** ... +*/ +v32sf +trunc_2sf2df (v32df x) +{ + return __builtin_convertvector (x, v32sf); +} + +/* +** trunc_2hf2df: +** ptrue (p[0-7])\.b, vl256 +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** fcvt (z[0-9]+)\.h, \1/m, \2\.d +** ... +*/ +v32hf +trunc_2hf2df (v32df x) +{ + return __builtin_convertvector (x, v32hf); +} + +/* +** trunc_4hf4sf: +** ptrue (p[0-7])\.b, vl256 +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** fcvt (z[0-9]+)\.h, \1/m, \2\.s +** ... +*/ +v64hf +trunc_4hf4sf (v64sf x) +{ + return __builtin_convertvector (x, v64hf); +} + +/* +** trunc_2hf2sf: +** ... +** ld1w (z[0-9]+)\.d, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.d, vl32 +** fcvt (z[0-9]+)\.h, \2/m, \1\.s +** ... +*/ +v32hf +trunc_2hf2sf (v32sf x) +{ + return __builtin_convertvector (x, v32hf); +} + +/* +** extend_2df2hf: +** ptrue (p[0-7])\.b, vl256 +** ld1h (z[0-9]+)\.d, \1/z, \[x0\] +** fcvt (z[0-9]+)\.d, \1/m, \2\.h +** ... +*/ +v32df +extend_2df2hf (v32hf x) +{ + return __builtin_convertvector (x, v32df); +} + +/* +** extend_2df2sf: +** ptrue (p[0-7])\.b, vl256 +** ld1w (z[0-9]+)\.d, \1/z, \[x0\] +** fcvt (z[0-9]+)\.d, \1/m, \2\.s +** ... +*/ +v32df +extend_2df2sf (v32sf x) +{ + return __builtin_convertvector (x, v32df); +} + +/* +** extend_4sf4hf: +** ptrue (p[0-7])\.b, vl256 +** ld1h (z[0-9]+)\.s, \1/z, \[x0\] +** fcvt (z[0-9]+)\.s, \1/m, \2\.h +** ... +*/ +v64sf +extend_4sf4hf (v64hf x) +{ + return __builtin_convertvector (x, v64sf); +} + +/* +** extend_2sf2hf: +** ... +** ld1h (z[0-9]+)\.d, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.d, vl32 +** fcvt (z[0-9]+)\.s, \2/m, \1\.h +** ... +*/ +v32sf +extend_2sf2hf (v32hf x) +{ + return __builtin_convertvector (x, v32sf); +} + +/* { dg-final { check-function-bodies "**" "" ""} } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcvt_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcvt_2.c new file mode 100644 index 0000000..8c369ee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcvt_2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=2048 -fno-trapping-math" } */ + +#include "unpacked_fcvt_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 8 } } */ + +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.h\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcvtz_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcvtz_1.c new file mode 100644 index 0000000..773a3dc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcvtz_1.c @@ -0,0 +1,244 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=2048 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include <stdint.h> + +typedef _Float16 v32hf __attribute__((vector_size(64))); +typedef _Float16 v64hf __attribute__((vector_size(128))); + +typedef float v32sf __attribute__((vector_size(128))); +typedef float v64sf __attribute__((vector_size(256))); + +typedef double v32df __attribute__((vector_size(256))); + +typedef int16_t v32hi __attribute__((vector_size(64))); +typedef int16_t v64hi __attribute__((vector_size(128))); +typedef uint16_t v32uhi __attribute__((vector_size(64))); +typedef uint16_t v64uhi __attribute__((vector_size(128))); + +typedef int32_t v32si __attribute__((vector_size(128))); +typedef int32_t v64si __attribute__((vector_size(256))); +typedef uint32_t v32usi __attribute__((vector_size(128))); +typedef uint32_t v64usi __attribute__((vector_size(256))); + +typedef int64_t v32di __attribute__((vector_size(256))); +typedef uint64_t v32udi __attribute__((vector_size(256))); + + +/* +** fix_trunc_2hi2hf: +** ... +** ld1h (z[0-9]+)\.d, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.d, vl32 +** fcvtzs (z[0-9]+)\.h, \2/m, \1\.h +** ... +*/ +v32hi +fix_trunc_2hi2hf (v32hf x) +{ + return __builtin_convertvector (x, v32hi); +} + +/* +** fix_trunc_2uhi2hf: +** ... +** ld1h (z[0-9]+)\.d, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.d, vl32 +** fcvtzu (z[0-9]+)\.h, \2/m, \1\.h +** ... +*/ +v32uhi +fix_trunc_2uhi2hf (v32hf x) +{ + return __builtin_convertvector (x, v32uhi); +} + +/* +** fix_trunc_2si2hf: +** ... +** ld1h (z[0-9]+)\.d, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.d, vl32 +** fcvtzs (z[0-9]+)\.s, \2/m, \1\.h +** ... +*/ +v32si +fix_trunc_2si2hf (v32hf x) +{ + return __builtin_convertvector (x, v32si); +} + +/* +** fix_trunc_2usi2hf: +** ... +** ld1h (z[0-9]+)\.d, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.d, vl32 +** fcvtzu (z[0-9]+)\.s, \2/m, \1\.h +** ... +*/ +v32usi +fix_trunc_2usi2hf (v32hf x) +{ + return __builtin_convertvector (x, v32usi); +} + +/* +** fix_trunc_2di2hf: +** ptrue (p[0-7])\.b, vl256 +** ld1h (z[0-9]+)\.d, \1/z, \[x0\] +** fcvtzs (z[0-9]+)\.d, \1/m, \2\.h +** ... +*/ +v32di +fix_trunc_2di2hf (v32hf x) +{ + return __builtin_convertvector (x, v32di); +} + +/* +** fix_trunc_2udi2hf: +** ptrue (p[0-7])\.b, vl256 +** ld1h (z[0-9]+)\.d, \1/z, \[x0\] +** fcvtzu (z[0-9]+)\.d, \1/m, \2\.h +** ... +*/ +v32udi +fix_trunc_2udi2hf (v32hf x) +{ + return __builtin_convertvector (x, v32udi); +} + +/* +** fix_trunc_4hi4hf: +** ... +** ld1h (z[0-9]+)\.s, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.s, vl64 +** fcvtzs (z[0-9]+)\.h, \2/m, \1\.h +** ... +*/ +v64hi +fix_trunc_4hi4hf (v64hf x) +{ + return __builtin_convertvector (x, v64hi); +} + +/* +** fix_trunc_4uhi4hf: +** ... +** ld1h (z[0-9]+)\.s, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.s, vl64 +** fcvtzu (z[0-9]+)\.h, \2/m, \1\.h +** ... +*/ +v64uhi +fix_trunc_4uhi4hf (v64hf x) +{ + return __builtin_convertvector (x, v64uhi); +} + +/* +** fix_trunc_4si4hf: +** ptrue (p[0-7])\.b, vl256 +** ld1h (z[0-9]+)\.s, \1/z, \[x0\] +** fcvtzs (z[0-9]+)\.s, \1/m, \2\.h +** ... +*/ +v64si +fix_trunc_4si4hf (v64hf x) +{ + return __builtin_convertvector (x, v64si); +} + +/* +** fix_trunc_4usi4hf: +** ptrue (p[0-7])\.b, vl256 +** ld1h (z[0-9]+)\.s, \1/z, \[x0\] +** fcvtzu (z[0-9]+)\.s, \1/m, \2\.h +** ... +*/ +v64usi +fix_trunc_4usi4hf (v64hf x) +{ + return __builtin_convertvector (x, v64usi); +} + +/* +** fix_trunc_2si2sf: +** ... +** ld1w (z[0-9]+)\.d, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.d, vl32 +** fcvtzs (z[0-9]+)\.s, \2/m, \1\.s +** ... +*/ +v32si +fix_trunc_2si2sf (v32sf x) +{ + return __builtin_convertvector (x, v32si); +} + +/* +** fix_trunc_2usi2sf: +** ... +** ld1w (z[0-9]+)\.d, p[0-7]/z, \[x0\] +** ptrue (p[0-7])\.d, vl32 +** fcvtzu (z[0-9]+)\.s, \2/m, \1\.s +** ... +*/ +v32usi +fix_trunc_2usi2sf (v32sf x) +{ + return __builtin_convertvector (x, v32usi); +} + +/* +** fix_trunc_2di2sf: +** ptrue (p[0-7])\.b, vl256 +** ld1w (z[0-9]+)\.d, \1/z, \[x0\] +** fcvtzs (z[0-9]+)\.d, \1/m, \2\.s +** ... +*/ +v32di +fix_trunc_2di2sf (v32sf x) +{ + return __builtin_convertvector (x, v32di); +} + +/* +** fix_trunc_2udi2sf: +** ptrue (p[0-7])\.b, vl256 +** ld1w (z[0-9]+)\.d, \1/z, \[x0\] +** fcvtzu (z[0-9]+)\.d, \1/m, \2\.s +** ... +*/ +v32udi +fix_trunc_2udi2sf (v32sf x) +{ + return __builtin_convertvector (x, v32udi); +} + +/* +** fix_trunc_2si2df: +** ptrue (p[0-7])\.b, vl256 +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** fcvtzs (z[0-9]+)\.s, \1/m, \2\.d +** ... +*/ +v32si +fix_trunc_2si2df (v32df x) +{ + return __builtin_convertvector (x, v32si); +} + +/* +** fix_trunc_2usi2df: +** ptrue (p[0-7])\.b, vl256 +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** fcvtzu (z[0-9]+)\.s, \1/m, \2\.d +** ... +*/ +v32usi +fix_trunc_2usi2df (v32df x) +{ + return __builtin_convertvector (x, v32usi); +} + +/* { dg-final { check-function-bodies "**" "" ""} } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcvtz_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcvtz_2.c new file mode 100644 index 0000000..0587753 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcvtz_2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=2048 -fno-trapping-math" } */ + +#include "unpacked_fcvtz_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 16 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.h\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.h\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_1.c new file mode 100644 index 0000000..78d0d9c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define b_i b[i] +#define DIV(A, B) A / B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##RHS (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i], (TYPE0)RHS) > c[i]) \ + out[i] = 3; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (DIV, _Float16, uint64_t, 32) + +TEST_ALL (DIV, _Float16, uint32_t, 64) + +TEST_ALL (DIV, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfdivr?\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfdivr?\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_2.c new file mode 100644 index 0000000..a8f70e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fdiv_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfdivr?\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfdivr?\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_3.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_3.c new file mode 100644 index 0000000..ecd088f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_3.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -moverride=sve_width=2048 -mlow-precision-div" } */ + +#include "unpacked_fdiv_1.c" + +/* { dg-final { scan-assembler-not {\tfrecpe\tz[0-9]+\.h} } } */ +/* { dg-final { scan-assembler-not {\tfrecps\tz[0-9]+\.h} } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrecpe\tz[0-9]+\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrecps\tz[0-9]+\.s} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmaxnm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmaxnm_1.c new file mode 100644 index 0000000..5239e4b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmaxnm_1.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-signed-zeros -ffinite-math-only -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define b_i b[i] +#define MAX(A, B) (A > B) ? A : B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##RHS (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (c[i] = FN (a[i], RHS)) \ + out[i] = 3; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1) + +TEST_ALL (MAX, _Float16, uint64_t, 32) + +TEST_ALL (MAX, _Float16, uint32_t, 64) + +TEST_ALL (MAX, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 6 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmaxnm_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmaxnm_2.c new file mode 100644 index 0000000..11aa7c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmaxnm_2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-signed-zeros -ffinite-math-only -fno-trapping-math -moverride=sve_width=2048" } */ + +#include "unpacked_fmaxnm_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 9 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fminnm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fminnm_1.c new file mode 100644 index 0000000..02a5f46 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fminnm_1.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-signed-zeros -ffinite-math-only -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define b_i b[i] +#define MIN(A, B) (A < B) ? A : B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##RHS (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (c[i] = FN (a[i], RHS) ) \ + out[i] = 3; \ + } + + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1) + +TEST_ALL (MIN, _Float16, uint64_t, 32) + +TEST_ALL (MIN, _Float16, uint32_t, 64) + +TEST_ALL (MIN, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 6 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fminnm_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fminnm_2.c new file mode 100644 index 0000000..81f583b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fminnm_2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-signed-zeros -ffinite-math-only -fno-trapping-math -moverride=sve_width=2048" } */ + +#include "unpacked_fminnm_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 9 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmla_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmla_1.c new file mode 100644 index 0000000..312bccc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmla_1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE0 *__restrict d) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN > d[i]) \ + out[i] = 3; \ + } + +TEST_FN (FMLA (f16), _Float16, uint64_t, 32) + +TEST_FN (FMLA (f16), _Float16, uint32_t, 64) + +TEST_FN (FMLA (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fmla|fmad)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fmla|fmad)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmla_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmla_2.c new file mode 100644 index 0000000..ca3f94d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmla_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fmla_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fmla|fmad)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fmla|fmad)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmls_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmls_1.c new file mode 100644 index 0000000..f7cbfb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmls_1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE0 *__restrict d) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN > d[i]) \ + out[i] = 3; \ + } + +TEST_FN (FMLS (f16), _Float16, uint64_t, 32) + +TEST_FN (FMLS (f16), _Float16, uint32_t, 64) + +TEST_FN (FMLS (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fmls|fmsb)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fmls|fmsb)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmls_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmls_2.c new file mode 100644 index 0000000..387dbec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmls_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fmls_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fmls|fmsb)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fmls|fmsb)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmul_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmul_1.c new file mode 100644 index 0000000..a180a07 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmul_1.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define b_i b[i] +#define immp5 0.5 +#define MUL(A, B) A * B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##RHS (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i], (TYPE0)RHS) > c[i]) \ + out[i] = 3; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, immp5) + +TEST_ALL (MUL, _Float16, uint64_t, 32) + +TEST_ALL (MUL, _Float16, uint32_t, 64) + +TEST_ALL (MUL, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 5 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 5 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 5 } } */ + +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmul_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmul_2.c new file mode 100644 index 0000000..eb05600 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmul_2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fmul_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 5 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 5 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 5 } } */ + +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fneg_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fneg_1.c new file mode 100644 index 0000000..d489ecb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fneg_1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define NEG(X) -X + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (NEG, _Float16, uint64_t, 32) + +TEST_FN (NEG, _Float16, uint32_t, 64) + +TEST_FN (NEG, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmla_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmla_1.c new file mode 100644 index 0000000..bf13ff5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmla_1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE0 *__restrict d) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN > d[i]) \ + out[i] = 3; \ + } + +TEST_FN (FNMLA (f16), _Float16, uint64_t, 32) + +TEST_FN (FNMLA (f16), _Float16, uint32_t, 64) + +TEST_FN (FNMLA (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fnmla|fnmad)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fnmla|fnmad)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmla_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmla_2.c new file mode 100644 index 0000000..64130ba --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmla_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fnmla_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fnmla|fnmad)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fnmla|fnmad)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmls_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmls_1.c new file mode 100644 index 0000000..399920a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmls_1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE0 *__restrict d) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN > d[i]) \ + out[i] = 3; \ + } + +TEST_FN (FNMLS (f16), _Float16, uint64_t, 32) + +TEST_FN (FNMLS (f16), _Float16, uint32_t, 64) + +TEST_FN (FNMLS (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fnmls|fnmsb)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fnmls|fnmsb)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmls_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmls_2.c new file mode 100644 index 0000000..59fb7f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmls_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fnmls_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fnmls|fnmsb)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fnmls|fnmsb)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c new file mode 100644 index 0000000..3cbdef3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (__builtin_roundf16, _Float16, uint64_t, 32) + +TEST_FN (__builtin_roundf16, _Float16, uint32_t, 64) + +TEST_FN (__builtin_roundf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_2.c new file mode 100644 index 0000000..4564686 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include "unpacked_frinta_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c new file mode 100644 index 0000000..7645fed --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (__builtin_nearbyintf16, _Float16, uint64_t, 32) + +TEST_FN (__builtin_nearbyintf16, _Float16, uint32_t, 64) + +TEST_FN (__builtin_nearbyintf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrinti\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrinti\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_2.c new file mode 100644 index 0000000..eadce07 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include "unpacked_frinti_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrinti\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrinti\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c new file mode 100644 index 0000000..98f85fb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (__builtin_floorf16, _Float16, uint64_t, 32) + +TEST_FN (__builtin_floorf16, _Float16, uint32_t, 64) + +TEST_FN (__builtin_floorf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_2.c new file mode 100644 index 0000000..56988be --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include "unpacked_frintm_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c new file mode 100644 index 0000000..f233697 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (__builtin_ceilf16, _Float16, uint64_t, 32) + +TEST_FN (__builtin_ceilf16, _Float16, uint32_t, 64) + +TEST_FN (__builtin_ceilf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintp\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintp\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_2.c new file mode 100644 index 0000000..c24c632 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include "unpacked_frintp_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintp\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintp\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c new file mode 100644 index 0000000..73403a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (__builtin_rintf16, _Float16, uint64_t, 32) + +TEST_FN (__builtin_rintf16, _Float16, uint32_t, 64) + +TEST_FN (__builtin_rintf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_2.c new file mode 100644 index 0000000..e8b8924 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include "unpacked_frintx_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c new file mode 100644 index 0000000..7377843 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (__builtin_truncf16, _Float16, uint64_t, 32) + +TEST_FN (__builtin_truncf16, _Float16, uint32_t, 64) + +TEST_FN (__builtin_truncf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintz\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintz\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_2.c new file mode 100644 index 0000000..1779122 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include "unpacked_frintz_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintz\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintz\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fsubr_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fsubr_1.c new file mode 100644 index 0000000..2cc8ec2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fsubr_1.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define b_i b[i] +#define immp5 0.5 +#define SUBR(A, B) B - A + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##RHS (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i], (TYPE0)RHS) > c[i]) \ + out[i] = 3; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, immp5) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1) + +TEST_ALL (SUBR, _Float16, uint64_t, 32) + +TEST_ALL (SUBR, _Float16, uint32_t, 64) + +TEST_ALL (SUBR, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 6 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tfsubr?\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfsubr?\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fsubr_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fsubr_2.c new file mode 100644 index 0000000..de9325c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fsubr_2.c @@ -0,0 +1,20 @@ +/* { dg-do compile }*/ +/* { dg-options "-O2 -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fsubr_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 6 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vec_init_3.c b/gcc/testsuite/gcc.target/aarch64/sve/vec_init_3.c index 25910db..5100a87 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vec_init_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/vec_init_3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -mlittle-endian" } */ /* { dg-final { check-function-bodies "**" "" "" } } */ typedef char v16qi __attribute__ ((vector_size (16))); @@ -8,7 +8,7 @@ typedef short v8hi __attribute__ ((vector_size (16))); typedef short v4hi __attribute__ ((vector_size (8))); typedef int v4si __attribute__ ((vector_size (16))); typedef int v2si __attribute__ ((vector_size (8))); -typedef long v2di __attribute__ ((vector_size (16))); +typedef long long v2di __attribute__ ((vector_size (16))); /* ** f_v16qi: @@ -97,3 +97,113 @@ g_v4si (void) { return (v4si){ 3, -1, -5, -9 }; } + +/* +** g_min_1: +** index z0\.s, #-16, #1 +** ret +*/ +v4si +g_min_1 (void) +{ + return (v4si){ -16, -15, -14, -13 }; +} + +/* +** g_min_min: +** index z0\.s, #-16, #-16 +** ret +*/ +v4si +g_min_min (void) +{ + return (v4si){ -16, -32, -48, -64 }; +} + +/* +** g_min_max: +** index z0\.s, #-16, #15 +** ret +*/ +v4si +g_min_max (void) +{ + return (v4si){ -16, -1, 14, 29 }; +} + +/* +** g_max_1: +** index z0\.s, #15, #1 +** ret +*/ +v4si +g_max_1 (void) +{ + return (v4si){ 15, 16, 17, 18 }; +} + +/* +** g_max_min: +** index z0\.s, #15, #-16 +** ret +*/ +v4si +g_max_min (void) +{ + return (v4si){ 15, -1, -17, -33 }; +} + +/* +** g_max_max: +** index z0\.s, #15, #15 +** ret +*/ +v4si +g_max_max (void) +{ + return (v4si){ 15, 30, 45, 60 }; +} + +/* +** g_ob_1: +** ((?!index).)* +** ret +*/ +v4si +g_ob_1 (void) +{ + return (v4si){ -17, -16, -15, -14 }; +} + +/* +** g_ob_2: +** ((?!index).)* +** ret +*/ +v4si +g_ob_2 (void) +{ + return (v4si){ 16, 17, 18, 19 }; +} + +/* +** g_ob_3: +** ((?!index).)* +** ret +*/ +v4si +g_ob_3 (void) +{ + return (v4si){ 0, -17, -34, -51 }; +} + +/* +** g_ob_4: +** ((?!index).)* +** ret +*/ +v4si +g_ob_4 (void) +{ + return (v4si){ 0, 16, 32, 48 }; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vec_init_4.c b/gcc/testsuite/gcc.target/aarch64/sve/vec_init_4.c new file mode 100644 index 0000000..0681d95 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/vec_init_4.c @@ -0,0 +1,209 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbig-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +typedef char v16qi __attribute__ ((vector_size (16))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef short v4hi __attribute__ ((vector_size (8))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef int v2si __attribute__ ((vector_size (8))); +typedef long long v2di __attribute__ ((vector_size (16))); + +/* +** f_v16qi: +** index z0\.b, #15, #-1 +** ret +*/ +v16qi +f_v16qi (void) +{ + return (v16qi){ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; +} + +/* +** f_v8qi: +** index z0\.b, #7, #-1 +** ret +*/ +v8qi +f_v8qi (void) +{ + return (v8qi){ 0, 1, 2, 3, 4, 5, 6, 7 }; +} + +/* +** f_v8hi: +** index z0\.h, #7, #-1 +** ret +*/ +v8hi +f_v8hi (void) +{ + return (v8hi){ 0, 1, 2, 3, 4, 5, 6, 7 }; +} + +/* +** f_v4hi: +** index z0\.h, #3, #-1 +** ret +*/ +v4hi +f_v4hi (void) +{ + return (v4hi){ 0, 1, 2, 3 }; +} + +/* +** f_v4si: +** index z0\.s, #3, #-1 +** ret +*/ +v4si +f_v4si (void) +{ + return (v4si){ 0, 1, 2, 3 }; +} + +/* +** f_v2si: +** index z0\.s, #1, #-1 +** ret +*/ +v2si +f_v2si (void) +{ + return (v2si){ 0, 1 }; +} + +/* +** f_v2di: +** index z0\.d, #1, #-1 +** ret +*/ +v2di +f_v2di (void) +{ + return (v2di){ 0, 1 }; +} + +/* +** g_v4si: +** index z0\.s, #-9, #4 +** ret +*/ +v4si +g_v4si (void) +{ + return (v4si){ 3, -1, -5, -9 }; +} + +/* +** g_min_1: +** index z0\.s, #-16, #1 +** ret +*/ +v4si +g_min_1 (void) +{ + return (v4si){ -13, -14, -15, -16 }; +} + +/* +** g_min_min: +** index z0\.s, #-16, #-16 +** ret +*/ +v4si +g_min_min (void) +{ + return (v4si){ -64, -48, -32, -16 }; +} + +/* +** g_min_max: +** index z0\.s, #-16, #15 +** ret +*/ +v4si +g_min_max (void) +{ + return (v4si){ 29, 14, -1, -16 }; +} + +/* +** g_max_1: +** index z0\.s, #15, #1 +** ret +*/ +v4si +g_max_1 (void) +{ + return (v4si){ 18, 17, 16, 15 }; +} + +/* +** g_max_min: +** index z0\.s, #15, #-16 +** ret +*/ +v4si +g_max_min (void) +{ + return (v4si){ -33, -17, -1, 15 }; +} + +/* +** g_max_max: +** index z0\.s, #15, #15 +** ret +*/ +v4si +g_max_max (void) +{ + return (v4si){ 60, 45, 30, 15 }; +} + +/* +** g_ob_1: +** ((?!index).)* +** ret +*/ +v4si +g_ob_1 (void) +{ + return (v4si){ -14, -15, -16, -17 }; +} + +/* +** g_ob_2: +** ((?!index).)* +** ret +*/ +v4si +g_ob_2 (void) +{ + return (v4si){ 19, 18, 17, 16 }; +} + +/* +** g_ob_3: +** ((?!index).)* +** ret +*/ +v4si +g_ob_3 (void) +{ + return (v4si){ -51, -34, -17, 0 }; +} + +/* +** g_ob_4: +** ((?!index).)* +** ret +*/ +v4si +g_ob_4 (void) +{ + return (v4si){ 48, 32, 16, 0 }; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/dupq_1.c b/gcc/testsuite/gcc.target/aarch64/sve2/dupq_1.c index 5472e30..9db60b1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/dupq_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/dupq_1.c @@ -1,5 +1,5 @@ /* { dg-options "-O2 -msve-vector-bits=256" } */ -/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include <arm_sve.h> @@ -15,7 +15,7 @@ typedef svuint64_t fixed_uint64_t __attribute__((arm_sve_vector_bits(256))); ** trn1 z0\.d, z0\.d, z0\.d ** ret */ -fixed_uint64_t +[[gnu::noipa]] fixed_uint64_t f1 (fixed_uint64_t z0) { return __builtin_shufflevector (z0, z0, 0, 0, 2, 2); @@ -26,7 +26,7 @@ f1 (fixed_uint64_t z0) ** trn2 z0\.d, z0\.d, z0\.d ** ret */ -fixed_uint64_t +[[gnu::noipa]] fixed_uint64_t f2 (fixed_uint64_t z0) { return __builtin_shufflevector (z0, z0, 1, 1, 3, 3); @@ -37,7 +37,7 @@ f2 (fixed_uint64_t z0) ** dupq z0\.s, z0\.s\[0\] ** ret */ -fixed_int32_t +[[gnu::noipa]] fixed_int32_t f3 (fixed_int32_t z0) { return __builtin_shufflevector (z0, z0, 0, 0, 0, 0, 4, 4, 4, 4); @@ -48,7 +48,7 @@ f3 (fixed_int32_t z0) ** dupq z0\.s, z0\.s\[1\] ** ret */ -fixed_int32_t +[[gnu::noipa]] fixed_int32_t f4 (fixed_int32_t z0) { return __builtin_shufflevector (z0, z0, 1, 1, 1, 1, 5, 5, 5, 5); @@ -59,7 +59,7 @@ f4 (fixed_int32_t z0) ** dupq z0\.s, z0\.s\[2\] ** ret */ -fixed_int32_t +[[gnu::noipa]] fixed_int32_t f5 (fixed_int32_t z0) { return __builtin_shufflevector (z0, z0, 2, 2, 2, 2, 6, 6, 6, 6); @@ -70,7 +70,7 @@ f5 (fixed_int32_t z0) ** dupq z0\.s, z0\.s\[3\] ** ret */ -fixed_int32_t +[[gnu::noipa]] fixed_int32_t f6 (fixed_int32_t z0) { return __builtin_shufflevector (z0, z0, 3, 3, 3, 3, 7, 7, 7, 7); @@ -81,7 +81,7 @@ f6 (fixed_int32_t z0) ** dupq z0\.h, z0\.h\[0\] ** ret */ -fixed_uint16_t +[[gnu::noipa]] fixed_uint16_t f7 (fixed_uint16_t z0) { return __builtin_shufflevector (z0, z0, @@ -95,7 +95,7 @@ f7 (fixed_uint16_t z0) ** dupq z0\.h, z0\.h\[5\] ** ret */ -fixed_uint16_t +[[gnu::noipa]] fixed_uint16_t f8 (fixed_uint16_t z0) { return __builtin_shufflevector (z0, z0, @@ -108,7 +108,7 @@ f8 (fixed_uint16_t z0) ** dupq z0\.h, z0\.h\[7\] ** ret */ -fixed_uint16_t +[[gnu::noipa]] fixed_uint16_t f9 (fixed_uint16_t z0) { return __builtin_shufflevector (z0, z0, @@ -121,7 +121,7 @@ f9 (fixed_uint16_t z0) ** dupq z0\.b, z0\.b\[0\] ** ret */ -fixed_uint8_t +[[gnu::noipa]] fixed_uint8_t f10 (fixed_uint8_t z0) { return __builtin_shufflevector (z0, z0, @@ -136,7 +136,7 @@ f10 (fixed_uint8_t z0) ** dupq z0\.b, z0\.b\[13\] ** ret */ -fixed_uint8_t +[[gnu::noipa]] fixed_uint8_t f11 (fixed_uint8_t z0) { return __builtin_shufflevector (z0, z0, @@ -151,7 +151,7 @@ f11 (fixed_uint8_t z0) ** dupq z0\.b, z0\.b\[15\] ** ret */ -fixed_uint8_t +[[gnu::noipa]] fixed_uint8_t f12 (fixed_uint8_t z0) { return __builtin_shufflevector (z0, z0, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/dupq_1_run.c b/gcc/testsuite/gcc.target/aarch64/sve2/dupq_1_run.c new file mode 100644 index 0000000..fd25034 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/dupq_1_run.c @@ -0,0 +1,87 @@ +/* { dg-do run { target { aarch64_sve256_hw && aarch64_sve2p1_hw } } } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include "dupq_1.c" + +#define TEST(A, B) \ + do { \ + typeof(B) actual_ = (A); \ + if (__builtin_memcmp (&actual_, &(B), sizeof (actual_)) != 0) \ + __builtin_abort (); \ + } while (0) + +int +main () +{ + fixed_uint64_t a64 = { 0x1122, -1, 0x5566, -2 }; + fixed_int32_t a32 = { 0x1122, -0x3344, 0x5566, -0x7788, + 0x99aa, -0xbbcc, 0xddee, -0xff00 }; + fixed_uint16_t a16 = { 0x9a12, 0xbc34, 0xde56, 0xf078, + 0x00ff, 0x11ee, 0x22dd, 0x33cc, + 0x44bb, 0x55aa, 0x6699, 0x7788, + 0xfe01, 0xdc23, 0xba45, 0x9867 }; + fixed_uint8_t a8 = { 0x01, 0x12, 0x23, 0x34, 0x45, 0x56, 0x67, 0x70, + 0x89, 0x9a, 0xab, 0xbc, 0xcd, 0xde, 0xef, 0xf8, + 0xfe, 0xed, 0xdc, 0xcb, 0xba, 0xa9, 0x98, 0x8f, + 0x76, 0x65, 0x54, 0x43, 0x32, 0x21, 0x10, 0x07 }; + + fixed_uint64_t expected1 = { 0x1122, 0x1122, 0x5566, 0x5566 }; + TEST (f1 (a64), expected1); + + fixed_uint64_t expected2 = { -1, -1, -2, -2 }; + TEST (f2 (a64), expected2); + + fixed_int32_t expected3 = { 0x1122, 0x1122, 0x1122, 0x1122, + 0x99aa, 0x99aa, 0x99aa, 0x99aa }; + TEST (f3 (a32), expected3); + + fixed_int32_t expected4 = { -0x3344, -0x3344, -0x3344, -0x3344, + -0xbbcc, -0xbbcc, -0xbbcc, -0xbbcc }; + TEST (f4 (a32), expected4); + + fixed_int32_t expected5 = { 0x5566, 0x5566, 0x5566, 0x5566, + 0xddee, 0xddee, 0xddee, 0xddee }; + TEST (f5 (a32), expected5); + + fixed_int32_t expected6 = { -0x7788, -0x7788, -0x7788, -0x7788, + -0xff00, -0xff00, -0xff00, -0xff00 }; + TEST (f6 (a32), expected6); + + fixed_uint16_t expected7 = { 0x9a12, 0x9a12, 0x9a12, 0x9a12, + 0x9a12, 0x9a12, 0x9a12, 0x9a12, + 0x44bb, 0x44bb, 0x44bb, 0x44bb, + 0x44bb, 0x44bb, 0x44bb, 0x44bb }; + TEST (f7 (a16), expected7); + + fixed_uint16_t expected8 = { 0x11ee, 0x11ee, 0x11ee, 0x11ee, + 0x11ee, 0x11ee, 0x11ee, 0x11ee, + 0xdc23, 0xdc23, 0xdc23, 0xdc23, + 0xdc23, 0xdc23, 0xdc23, 0xdc23 }; + TEST (f8 (a16), expected8); + + fixed_uint16_t expected9 = { 0x33cc, 0x33cc, 0x33cc, 0x33cc, + 0x33cc, 0x33cc, 0x33cc, 0x33cc, + 0x9867, 0x9867, 0x9867, 0x9867, + 0x9867, 0x9867, 0x9867, 0x9867 }; + TEST (f9 (a16), expected9); + + fixed_uint8_t expected10 = { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, + 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe }; + TEST (f10 (a8), expected10); + + fixed_uint8_t expected11 = { 0xde, 0xde, 0xde, 0xde, 0xde, 0xde, 0xde, 0xde, + 0xde, 0xde, 0xde, 0xde, 0xde, 0xde, 0xde, 0xde, + 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, + 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21 }; + TEST (f11 (a8), expected11); + + fixed_uint8_t expected12 = { 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, + 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, + 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, + 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 }; + TEST (f12 (a8), expected12); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/eon_bsl2n.c b/gcc/testsuite/gcc.target/aarch64/sve2/eon_bsl2n.c new file mode 100644 index 0000000..74b4637 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/eon_bsl2n.c @@ -0,0 +1,52 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include <arm_neon.h> +#include <arm_sve.h> + +#define EON(x, y) (~((x) ^ (y))) + +/* +** eon_d: +** bsl2n z0.d, z0.d, z0.d, z1.d +** ret +*/ +uint32x2_t eon_d(uint32x2_t a, uint32x2_t b) { return EON(a, b); } + +/* +** eon_d_mp: +** movprfx z0, z1 +** bsl2n z0.d, z0.d, z1.d, z2.d +** ret +*/ +uint32x2_t eon_d_mp(uint32x2_t c, uint32x2_t a, uint32x2_t b) { return EON(a, b); } + +/* +** eon_q: +** bsl2n z0.d, z0.d, z0.d, z1.d +** ret +*/ +uint64x2_t eon_q(uint64x2_t a, uint64x2_t b) { return EON(a, b); } + +/* +** eon_q_mp: +** movprfx z0, z1 +** bsl2n z0.d, z0.d, z1.d, z2.d +** ret +*/ +uint64x2_t eon_q_mp(uint64x2_t c, uint64x2_t a, uint64x2_t b) { return EON(a, b); } + +/* +** eon_z: +** bsl2n z0.d, z0.d, z0.d, z1.d +** ret +*/ +svuint64_t eon_z(svuint64_t a, svuint64_t b) { return EON(a, b); } + +/* +** eon_z_mp: +** movprfx z0, z1 +** bsl2n z0.d, z0.d, z1.d, z2.d +** ret +*/ +svuint64_t eon_z_mp(svuint64_t c, svuint64_t a, svuint64_t b) { return EON(a, b); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/extq_1.c b/gcc/testsuite/gcc.target/aarch64/sve2/extq_1.c index 03c5fb1..be5ae71 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/extq_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/extq_1.c @@ -1,5 +1,5 @@ /* { dg-options "-O2 -msve-vector-bits=256" } */ -/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include <arm_sve.h> @@ -15,7 +15,7 @@ typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(256))); ** extq z0\.b, z0\.b, z1\.b, #8 ** ret */ -fixed_float64_t +[[gnu::noipa]] fixed_float64_t f1 (fixed_float64_t z0, fixed_float64_t z1) { return __builtin_shufflevector (z0, z1, 1, 4, 3, 6); @@ -26,7 +26,7 @@ f1 (fixed_float64_t z0, fixed_float64_t z1) ** extq z0\.b, z0\.b, z1\.b, #4 ** ret */ -fixed_uint32_t +[[gnu::noipa]] fixed_uint32_t f2 (fixed_uint32_t z0, fixed_uint32_t z1) { return __builtin_shufflevector (z0, z1, 1, 2, 3, 8, 5, 6, 7, 12); @@ -37,7 +37,7 @@ f2 (fixed_uint32_t z0, fixed_uint32_t z1) ** extq z0\.b, z0\.b, z1\.b, #12 ** ret */ -fixed_uint32_t +[[gnu::noipa]] fixed_uint32_t f3 (fixed_uint32_t z0, fixed_uint32_t z1) { return __builtin_shufflevector (z0, z1, 3, 8, 9, 10, 7, 12, 13, 14); @@ -48,7 +48,7 @@ f3 (fixed_uint32_t z0, fixed_uint32_t z1) ** extq z0\.b, z0\.b, z1\.b, #2 ** ret */ -fixed_float16_t +[[gnu::noipa]] fixed_float16_t f4 (fixed_float16_t z0, fixed_float16_t z1) { return __builtin_shufflevector (z0, z1, @@ -61,7 +61,7 @@ f4 (fixed_float16_t z0, fixed_float16_t z1) ** extq z0\.b, z0\.b, z1\.b, #10 ** ret */ -fixed_float16_t +[[gnu::noipa]] fixed_float16_t f5 (fixed_float16_t z0, fixed_float16_t z1) { return __builtin_shufflevector (z0, z1, @@ -74,7 +74,7 @@ f5 (fixed_float16_t z0, fixed_float16_t z1) ** extq z0\.b, z0\.b, z1\.b, #14 ** ret */ -fixed_float16_t +[[gnu::noipa]] fixed_float16_t f6 (fixed_float16_t z0, fixed_float16_t z1) { return __builtin_shufflevector (z0, z1, @@ -87,7 +87,7 @@ f6 (fixed_float16_t z0, fixed_float16_t z1) ** extq z0\.b, z0\.b, z1\.b, #1 ** ret */ -fixed_int8_t +[[gnu::noipa]] fixed_int8_t f7 (fixed_int8_t z0, fixed_int8_t z1) { return __builtin_shufflevector (z0, z1, @@ -102,7 +102,7 @@ f7 (fixed_int8_t z0, fixed_int8_t z1) ** extq z0\.b, z0\.b, z1\.b, #11 ** ret */ -fixed_int8_t +[[gnu::noipa]] fixed_int8_t f8 (fixed_int8_t z0, fixed_int8_t z1) { return __builtin_shufflevector (z0, z1, @@ -117,7 +117,7 @@ f8 (fixed_int8_t z0, fixed_int8_t z1) ** extq z0\.b, z0\.b, z1\.b, #15 ** ret */ -fixed_int8_t +[[gnu::noipa]] fixed_int8_t f9 (fixed_int8_t z0, fixed_int8_t z1) { return __builtin_shufflevector (z0, z1, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/extq_1_run.c b/gcc/testsuite/gcc.target/aarch64/sve2/extq_1_run.c new file mode 100644 index 0000000..6b72c98 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/extq_1_run.c @@ -0,0 +1,73 @@ +/* { dg-do run { target { aarch64_sve256_hw && aarch64_sve2p1_hw } } } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include "extq_1.c" + +#define TEST(A, B) \ + do { \ + typeof(B) actual_ = (A); \ + if (__builtin_memcmp (&actual_, &(B), sizeof (actual_)) != 0) \ + __builtin_abort (); \ + } while (0) + +int +main () +{ + fixed_float64_t a64 = { 1.5, 3.75, -5.25, 9 }; + fixed_float64_t b64 = { -2, 4.125, -6.375, 11.5 }; + fixed_float64_t expected1 = { 3.75, -2, 9, -6.375 }; + TEST (f1 (a64, b64), expected1); + + fixed_uint32_t a32 = { 0x1122, -0x3344, 0x5566, -0x7788, + 0x99aa, -0xbbcc, 0xddee, -0xff00 }; + fixed_uint32_t b32 = { 1 << 20, 1 << 21, 1 << 22, 1 << 23, + 5 << 6, 5 << 7, 5 << 8, 5 << 9 }; + fixed_uint32_t expected2 = { -0x3344, 0x5566, -0x7788, 1 << 20, + -0xbbcc, 0xddee, -0xff00, 5 << 6 }; + fixed_uint32_t expected3 = { -0x7788, 1 << 20, 1 << 21, 1 << 22, + -0xff00, 5 << 6, 5 << 7, 5 << 8 }; + TEST (f2 (a32, b32), expected2); + TEST (f3 (a32, b32), expected3); + + fixed_float16_t a16 = { 0.5, 0.75, 1, 1.25, 1.5, 1.75, 2, 2.25, + 2.5, 2.75, 3, 3.25, 3.5, 3.75, 4, 4.25 }; + fixed_float16_t b16 = { -0.5, -0.75, -1, -1.25, -1.5, -1.75, -2, -2.25, + -2.5, -2.75, -3, -3.25, -3.5, -3.75, -4, -4.25 }; + fixed_float16_t expected4 = { 0.75, 1, 1.25, 1.5, 1.75, 2, 2.25, -0.5, + 2.75, 3, 3.25, 3.5, 3.75, 4, 4.25, -2.5 }; + fixed_float16_t expected5 = { 1.75, 2, 2.25, -0.5, -0.75, -1, -1.25, -1.5, + 3.75, 4, 4.25, -2.5, -2.75, -3, -3.25, -3.5 }; + fixed_float16_t expected6 = { 2.25, -0.5, -0.75, -1, + -1.25, -1.5, -1.75, -2, + 4.25, -2.5, -2.75, -3, + -3.25, -3.5, -3.75, -4 }; + TEST (f4 (a16, b16), expected4); + TEST (f5 (a16, b16), expected5); + TEST (f6 (a16, b16), expected6); + + fixed_int8_t a8 = { 0x01, 0x12, 0x23, 0x34, 0x45, 0x56, 0x67, 0x70, + 0x89, 0x9a, 0xab, 0xbc, 0xcd, 0xde, 0xef, 0xf8, + 0xfe, 0xed, 0xdc, 0xcb, 0xba, 0xa9, 0x98, 0x8f, + 0x76, 0x65, 0x54, 0x43, 0x32, 0x21, 0x10, 0x07 }; + fixed_int8_t b8 = { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, + 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff, 0x00, + 0x13, 0x24, 0x35, 0x46, 0x57, 0x68, 0x79, 0x8a, + 0x9b, 0xac, 0xbd, 0xce, 0xdf, 0xe0, 0xf1, 0x02 }; + fixed_int8_t expected7 = { 0x12, 0x23, 0x34, 0x45, 0x56, 0x67, 0x70, 0x89, + 0x9a, 0xab, 0xbc, 0xcd, 0xde, 0xef, 0xf8, 0x11, + 0xed, 0xdc, 0xcb, 0xba, 0xa9, 0x98, 0x8f, 0x76, + 0x65, 0x54, 0x43, 0x32, 0x21, 0x10, 0x07, 0x13 }; + fixed_int8_t expected8 = { 0xbc, 0xcd, 0xde, 0xef, 0xf8, 0x11, 0x22, 0x33, + 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xaa, 0xbb, + 0x43, 0x32, 0x21, 0x10, 0x07, 0x13, 0x24, 0x35, + 0x46, 0x57, 0x68, 0x79, 0x8a, 0x9b, 0xac, 0xbd }; + fixed_int8_t expected9 = { 0xf8, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff, + 0x07, 0x13, 0x24, 0x35, 0x46, 0x57, 0x68, 0x79, + 0x8a, 0x9b, 0xac, 0xbd, 0xce, 0xdf, 0xe0, 0xf1 }; + TEST (f7 (a8, b8), expected7); + TEST (f8 (a8, b8), expected8); + TEST (f9 (a8, b8), expected9); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/nbsl_nor_nand_neon.c b/gcc/testsuite/gcc.target/aarch64/sve2/nbsl_nor_nand_neon.c new file mode 100644 index 0000000..09bfc19 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/nbsl_nor_nand_neon.c @@ -0,0 +1,68 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include <arm_neon.h> + +#define NAND(x, y) (~((x) & (y))) +#define NOR(x, y) (~((x) | (y))) + +/* +** nand_d: +** nbsl z0.d, z0.d, z1.d, z1.d +** ret +*/ +uint32x2_t nand_d(uint32x2_t a, uint32x2_t b) { return NAND(a, b); } + +/* +** nand_d_mp: +** movprfx z0, z1 +** nbsl z0.d, z0.d, z2.d, z2.d +** ret +*/ +uint32x2_t nand_d_mp(uint32x2_t c, uint32x2_t a, uint32x2_t b) { return NAND(a, b); } + +/* +** nor_d: +** nbsl z0.d, z0.d, z1.d, z0.d +** ret +*/ +uint32x2_t nor_d(uint32x2_t a, uint32x2_t b) { return NOR(a, b); } + +/* +** nor_d_mp: +** movprfx z0, z1 +** nbsl z0.d, z0.d, z2.d, z1.d +** ret +*/ +uint32x2_t nor_d_mp(uint32x2_t c, uint32x2_t a, uint32x2_t b) { return NOR(a, b); } + +/* +** nand_q: +** nbsl z0.d, z0.d, z1.d, z1.d +** ret +*/ +uint64x2_t nand_q(uint64x2_t a, uint64x2_t b) { return NAND(a, b); } + +/* +** nand_q_mp: +** movprfx z0, z1 +** nbsl z0.d, z0.d, z2.d, z2.d +** ret +*/ +uint32x4_t nand_q_mp(uint32x4_t c, uint32x4_t a, uint32x4_t b) { return NAND(a, b); } + +/* +** nor_q: +** nbsl z0.d, z0.d, z1.d, z0.d +** ret +*/ +uint64x2_t nor_q(uint64x2_t a, uint64x2_t b) { return NOR(a, b); } + +/* +** nor_q_mp: +** movprfx z0, z1 +** nbsl z0.d, z0.d, z2.d, z1.d +** ret +*/ +uint32x4_t nor_q_mp(uint32x4_t c, uint32x4_t a, uint32x4_t b) { return NOR(a, b); } + diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary.c index 94470a5..977fa39 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_int_opt_n.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_int_opt_n.c index b8747b8..b816fa1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_int_opt_n.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_int_opt_n.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_int_opt_single_n.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_int_opt_single_n.c index 7cb7ee5..0e4427a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_int_opt_single_n.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_int_opt_single_n.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_opt_n.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_opt_n.c index 787126f..81d0c82 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_opt_n.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_opt_n.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_opt_single_n.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_opt_single_n.c index 6b2b0a42..3920bdb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_opt_single_n.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_opt_single_n.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2 -march=armv8.2-a+sve2+faminmax" } */ +/* { dg-options "-O2 -march=armv8.2-a+sve2+faminmax -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_to_uint.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_to_uint.c index a0a7f80..c7d10b3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_to_uint.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_to_uint.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_uint_opt_n.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_uint_opt_n.c index c13db48..122fba7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_uint_opt_n.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_uint_opt_n.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_wide.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_wide.c index 145b077..7f35859 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_wide.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-binary_wide.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-compare.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-compare.c index da175db..b079a56 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-compare.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-compare.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-binary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_ext_gather_index_restricted.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_ext_gather_index_restricted.c index c0476ce..14e77c00 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_ext_gather_index_restricted.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_ext_gather_index_restricted.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_ext_gather_offset_restricted.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_ext_gather_offset_restricted.c index f644024..b680548 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_ext_gather_offset_restricted.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_ext_gather_offset_restricted.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_gather_sv_restricted.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_gather_sv_restricted.c index a48a8a9..6d1a356 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_gather_sv_restricted.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_gather_sv_restricted.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_gather_vs.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_gather_vs.c index 1fc08a3..9cb4471 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_gather_vs.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-load_gather_vs.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-shift_left_imm_to_uint.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-shift_left_imm_to_uint.c index bd2c937..e57a650 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-shift_left_imm_to_uint.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-shift_left_imm_to_uint.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-shift_right_imm.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-shift_right_imm.c index f4994de..710ca73 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-shift_right_imm.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-shift_right_imm.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-store_scatter_index_restricted.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-store_scatter_index_restricted.c index 6bec3b3..dc9cf46 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-store_scatter_index_restricted.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-store_scatter_index_restricted.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-store_scatter_offset_restricted.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-store_scatter_offset_restricted.c index bcb4a14..2728c9b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-store_scatter_offset_restricted.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-store_scatter_offset_restricted.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary.c index ba7e931..9f33295 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2 -march=armv9.2-a+sve+sme" } */ +/* { dg-options "-O2 -march=armv9.2-a+sve+sme -funwind-tables" } */ #include "../pfalse-unary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary_convert.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary_convert.c index 7aa59ff..68769fe 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary_convert.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary_convert.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary_convert_narrowt.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary_convert_narrowt.c index 1a4525c..692891f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary_convert_narrowt.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary_convert_narrowt.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary_to_int.c b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary_to_int.c index b64bfc3..7dffa1c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary_to_int.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pfalse-unary_to_int.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target elf } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -funwind-tables" } */ #include "../pfalse-unary_0.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pr120999.c b/gcc/testsuite/gcc.target/aarch64/sve2/pr120999.c new file mode 100644 index 0000000..2dca36a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pr120999.c @@ -0,0 +1,17 @@ +/* PR target/120999. */ +/* { dg-do assemble } */ +/* { dg-options "-O2 --save-temps" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include <arm_sve.h> + +#define NOR(x, y) (~((x) | (y))) + +/* +** nor_z: +** movprfx z0, z1 +** nbsl z0.d, z0.d, z2.d, z1.d +** ret +*/ +svuint64_t nor_z(svuint64_t c, svuint64_t a, svuint64_t b) { return NOR(a, b); } + diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/uzpq_1.c b/gcc/testsuite/gcc.target/aarch64/sve2/uzpq_1.c index f923e94..587f670 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/uzpq_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/uzpq_1.c @@ -1,5 +1,5 @@ /* { dg-options "-O2 -msve-vector-bits=256" } */ -/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include <arm_sve.h> @@ -15,7 +15,7 @@ typedef svint64_t fixed_int64_t __attribute__((arm_sve_vector_bits(256))); ** trn1 z0\.d, z0\.d, z1\.d ** ret */ -fixed_int64_t +[[gnu::noipa]] fixed_int64_t f1 (fixed_int64_t z0, fixed_int64_t z1) { return __builtin_shufflevector (z0, z1, 0, 4, 2, 6); @@ -26,7 +26,7 @@ f1 (fixed_int64_t z0, fixed_int64_t z1) ** trn2 z0\.d, z0\.d, z1\.d ** ret */ -fixed_int64_t +[[gnu::noipa]] fixed_int64_t f2 (fixed_int64_t z0, fixed_int64_t z1) { return __builtin_shufflevector (z0, z1, 1, 5, 3, 7); @@ -37,7 +37,7 @@ f2 (fixed_int64_t z0, fixed_int64_t z1) ** uzpq1 z0\.s, z0\.s, z1\.s ** ret */ -fixed_float32_t +[[gnu::noipa]] fixed_float32_t f3 (fixed_float32_t z0, fixed_float32_t z1) { return __builtin_shufflevector (z0, z1, 0, 2, 8, 10, 4, 6, 12, 14); @@ -48,7 +48,7 @@ f3 (fixed_float32_t z0, fixed_float32_t z1) ** uzpq2 z0\.s, z0\.s, z1\.s ** ret */ -fixed_float32_t +[[gnu::noipa]] fixed_float32_t f4 (fixed_float32_t z0, fixed_float32_t z1) { return __builtin_shufflevector (z0, z1, 1, 3, 9, 11, 5, 7, 13, 15); @@ -59,7 +59,7 @@ f4 (fixed_float32_t z0, fixed_float32_t z1) ** uzpq1 z0\.h, z0\.h, z1\.h ** ret */ -fixed_bfloat16_t +[[gnu::noipa]] fixed_bfloat16_t f5 (fixed_bfloat16_t z0, fixed_bfloat16_t z1) { return __builtin_shufflevector (z0, z1, @@ -72,7 +72,7 @@ f5 (fixed_bfloat16_t z0, fixed_bfloat16_t z1) ** uzpq2 z0\.h, z0\.h, z1\.h ** ret */ -fixed_bfloat16_t +[[gnu::noipa]] fixed_bfloat16_t f6 (fixed_bfloat16_t z0, fixed_bfloat16_t z1) { return __builtin_shufflevector (z0, z1, @@ -85,7 +85,7 @@ f6 (fixed_bfloat16_t z0, fixed_bfloat16_t z1) ** uzpq1 z0\.b, z0\.b, z1\.b ** ret */ -fixed_uint8_t +[[gnu::noipa]] fixed_uint8_t f7 (fixed_uint8_t z0, fixed_uint8_t z1) { return __builtin_shufflevector (z0, z1, @@ -100,7 +100,7 @@ f7 (fixed_uint8_t z0, fixed_uint8_t z1) ** uzpq2 z0\.b, z0\.b, z1\.b ** ret */ -fixed_uint8_t +[[gnu::noipa]] fixed_uint8_t f8 (fixed_uint8_t z0, fixed_uint8_t z1) { return __builtin_shufflevector (z0, z1, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/uzpq_1_run.c b/gcc/testsuite/gcc.target/aarch64/sve2/uzpq_1_run.c new file mode 100644 index 0000000..9044cae --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/uzpq_1_run.c @@ -0,0 +1,78 @@ +/* { dg-do run { target { aarch64_sve256_hw && aarch64_sve2p1_hw } } } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include "uzpq_1.c" + +typedef svuint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(256))); + +#define TEST(A, B) \ + do { \ + typeof(A) actual_ = (A); \ + if (__builtin_memcmp (&actual_, &(B), sizeof (actual_)) != 0) \ + __builtin_abort (); \ + } while (0) + +int +main () +{ + fixed_int64_t a64 = { 0x1122LL << 31, -1LL << 47, 0x5566 << 15, -2 }; + fixed_int64_t b64 = { 42, -0x3344LL << 19, 303, -0x7788LL << 27 }; + fixed_int64_t expected1 = { 0x1122LL << 31, 42, + 0x5566 << 15, 303 }; + fixed_int64_t expected2 = { -1LL << 47, -0x3344LL << 19, + -2, -0x7788LL << 27 }; + TEST (f1 (a64, b64), expected1); + TEST (f2 (a64, b64), expected2); + + fixed_float32_t a32 = { 0.5, 0.75, 1, 1.25, 2.5, 2.75, 3, 3.25 }; + fixed_float32_t b32 = { -0.5, -0.75, -1, -1.25, -2.5, -2.75, -3, -3.25 }; + fixed_float32_t expected3 = { 0.5, 1, -0.5, -1, + 2.5, 3, -2.5, -3 }; + fixed_float32_t expected4 = { 0.75, 1.25, -0.75, -1.25, + 2.75, 3.25, -2.75, -3.25 }; + TEST (f3 (a32, b32), expected3); + TEST (f4 (a32, b32), expected4); + + fixed_uint16_t a16_i = { 0x9a12, 0xbc34, 0xde56, 0xf078, + 0x00ff, 0x11ee, 0x22dd, 0x33cc, + 0x44bb, 0x55aa, 0x6699, 0x7788, + 0xfe01, 0xdc23, 0xba45, 0x9867 }; + fixed_uint16_t b16_i = { 0x1010, 0x2020, 0x3030, 0x4040, + 0x5050, 0x6060, 0x7070, 0x8080, + 0x9090, 0xa0a0, 0xb0b0, 0xc0c0, + 0xd0d0, 0xe0e0, 0xf0f0, 0x0f0f }; + fixed_uint16_t expected5 = { 0x9a12, 0xde56, 0x00ff, 0x22dd, + 0x1010, 0x3030, 0x5050, 0x7070, + 0x44bb, 0x6699, 0xfe01, 0xba45, + 0x9090, 0xb0b0, 0xd0d0, 0xf0f0 }; + fixed_uint16_t expected6 = { 0xbc34, 0xf078, 0x11ee, 0x33cc, + 0x2020, 0x4040, 0x6060, 0x8080, + 0x55aa, 0x7788, 0xdc23, 0x9867, + 0xa0a0, 0xc0c0, 0xe0e0, 0x0f0f }; + fixed_bfloat16_t a16, b16; + __builtin_memcpy (&a16, &a16_i, sizeof (a16)); + __builtin_memcpy (&b16, &b16_i, sizeof (b16)); + TEST (f5 (a16, b16), expected5); + TEST (f6 (a16, b16), expected6); + + fixed_uint8_t a8 = { 0x01, 0x12, 0x23, 0x34, 0x45, 0x56, 0x67, 0x70, + 0x89, 0x9a, 0xab, 0xbc, 0xcd, 0xde, 0xef, 0xf8, + 0xfe, 0xed, 0xdc, 0xcb, 0xba, 0xa9, 0x98, 0x8f, + 0x76, 0x65, 0x54, 0x43, 0x32, 0x21, 0x10, 0x07 }; + fixed_uint8_t b8 = { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, + 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff, 0x00, + 0x13, 0x24, 0x35, 0x46, 0x57, 0x68, 0x79, 0x8a, + 0x9b, 0xac, 0xbd, 0xce, 0xdf, 0xe0, 0xf1, 0x02 }; + fixed_uint8_t expected7 = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, + 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd, 0xff, + 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10, + 0x13, 0x35, 0x57, 0x79, 0x9b, 0xbd, 0xdf, 0xf1 }; + fixed_uint8_t expected8 = { 0x12, 0x34, 0x56, 0x70, 0x9a, 0xbc, 0xde, 0xf8, + 0x22, 0x44, 0x66, 0x88, 0xaa, 0xcc, 0xee, 0x00, + 0xed, 0xcb, 0xa9, 0x8f, 0x65, 0x43, 0x21, 0x07, + 0x24, 0x46, 0x68, 0x8a, 0xac, 0xce, 0xe0, 0x02 }; + TEST (f7 (a8, b8), expected7); + TEST (f8 (a8, b8), expected8); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/zipq_1.c b/gcc/testsuite/gcc.target/aarch64/sve2/zipq_1.c index fa420a9..76fb4b4 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/zipq_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/zipq_1.c @@ -1,5 +1,5 @@ /* { dg-options "-O2 -msve-vector-bits=256" } */ -/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include <arm_sve.h> @@ -15,7 +15,7 @@ typedef svint64_t fixed_int64_t __attribute__((arm_sve_vector_bits(256))); ** trn1 z0\.d, z0\.d, z1\.d ** ret */ -fixed_int64_t +[[gnu::noipa]] fixed_int64_t f1 (fixed_int64_t z0, fixed_int64_t z1) { return __builtin_shufflevector (z0, z1, 0, 4, 2, 6); @@ -26,7 +26,7 @@ f1 (fixed_int64_t z0, fixed_int64_t z1) ** trn2 z0\.d, z0\.d, z1\.d ** ret */ -fixed_int64_t +[[gnu::noipa]] fixed_int64_t f2 (fixed_int64_t z0, fixed_int64_t z1) { return __builtin_shufflevector (z0, z1, 1, 5, 3, 7); @@ -37,7 +37,7 @@ f2 (fixed_int64_t z0, fixed_int64_t z1) ** zipq1 z0\.s, z0\.s, z1\.s ** ret */ -fixed_float32_t +[[gnu::noipa]] fixed_float32_t f3 (fixed_float32_t z0, fixed_float32_t z1) { return __builtin_shufflevector (z0, z1, 0, 8, 1, 9, 4, 12, 5, 13); @@ -48,7 +48,7 @@ f3 (fixed_float32_t z0, fixed_float32_t z1) ** zipq2 z0\.s, z0\.s, z1\.s ** ret */ -fixed_float32_t +[[gnu::noipa]] fixed_float32_t f4 (fixed_float32_t z0, fixed_float32_t z1) { return __builtin_shufflevector (z0, z1, 2, 10, 3, 11, 6, 14, 7, 15); @@ -59,7 +59,7 @@ f4 (fixed_float32_t z0, fixed_float32_t z1) ** zipq1 z0\.h, z0\.h, z1\.h ** ret */ -fixed_bfloat16_t +[[gnu::noipa]] fixed_bfloat16_t f5 (fixed_bfloat16_t z0, fixed_bfloat16_t z1) { return __builtin_shufflevector (z0, z1, @@ -72,7 +72,7 @@ f5 (fixed_bfloat16_t z0, fixed_bfloat16_t z1) ** zipq2 z0\.h, z0\.h, z1\.h ** ret */ -fixed_bfloat16_t +[[gnu::noipa]] fixed_bfloat16_t f6 (fixed_bfloat16_t z0, fixed_bfloat16_t z1) { return __builtin_shufflevector (z0, z1, @@ -85,7 +85,7 @@ f6 (fixed_bfloat16_t z0, fixed_bfloat16_t z1) ** zipq1 z0\.b, z0\.b, z1\.b ** ret */ -fixed_uint8_t +[[gnu::noipa]] fixed_uint8_t f7 (fixed_uint8_t z0, fixed_uint8_t z1) { return __builtin_shufflevector (z0, z1, @@ -100,7 +100,7 @@ f7 (fixed_uint8_t z0, fixed_uint8_t z1) ** zipq2 z0\.b, z0\.b, z1\.b ** ret */ -fixed_uint8_t +[[gnu::noipa]] fixed_uint8_t f8 (fixed_uint8_t z0, fixed_uint8_t z1) { return __builtin_shufflevector (z0, z1, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/zipq_1_run.c b/gcc/testsuite/gcc.target/aarch64/sve2/zipq_1_run.c new file mode 100644 index 0000000..211f9d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/zipq_1_run.c @@ -0,0 +1,78 @@ +/* { dg-do run { target { aarch64_sve256_hw && aarch64_sve2p1_hw } } } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include "zipq_1.c" + +typedef svuint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(256))); + +#define TEST(A, B) \ + do { \ + typeof(A) actual_ = (A); \ + if (__builtin_memcmp (&actual_, &(B), sizeof (actual_)) != 0) \ + __builtin_abort (); \ + } while (0) + +int +main () +{ + fixed_int64_t a64 = { 0x1122LL << 31, -1LL << 47, 0x5566 << 15, -2 }; + fixed_int64_t b64 = { 42, -0x3344LL << 19, 303, -0x7788LL << 27 }; + fixed_int64_t expected1 = { 0x1122LL << 31, 42, + 0x5566 << 15, 303 }; + fixed_int64_t expected2 = { -1LL << 47, -0x3344LL << 19, + -2, -0x7788LL << 27 }; + TEST (f1 (a64, b64), expected1); + TEST (f2 (a64, b64), expected2); + + fixed_float32_t a32 = { 0.5, 0.75, 1, 1.25, 2.5, 2.75, 3, 3.25 }; + fixed_float32_t b32 = { -0.5, -0.75, -1, -1.25, -2.5, -2.75, -3, -3.25 }; + fixed_float32_t expected3 = { 0.5, -0.5, 0.75, -0.75, + 2.5, -2.5, 2.75, -2.75 }; + fixed_float32_t expected4 = { 1, -1, 1.25, -1.25, + 3, -3, 3.25, -3.25 }; + TEST (f3 (a32, b32), expected3); + TEST (f4 (a32, b32), expected4); + + fixed_uint16_t a16_i = { 0x9a12, 0xbc34, 0xde56, 0xf078, + 0x00ff, 0x11ee, 0x22dd, 0x33cc, + 0x44bb, 0x55aa, 0x6699, 0x7788, + 0xfe01, 0xdc23, 0xba45, 0x9867 }; + fixed_uint16_t b16_i = { 0x1010, 0x2020, 0x3030, 0x4040, + 0x5050, 0x6060, 0x7070, 0x8080, + 0x9090, 0xa0a0, 0xb0b0, 0xc0c0, + 0xd0d0, 0xe0e0, 0xf0f0, 0x0f0f }; + fixed_uint16_t expected5 = { 0x9a12, 0x1010, 0xbc34, 0x2020, + 0xde56, 0x3030, 0xf078, 0x4040, + 0x44bb, 0x9090, 0x55aa, 0xa0a0, + 0x6699, 0xb0b0, 0x7788, 0xc0c0 }; + fixed_uint16_t expected6 = { 0x00ff, 0x5050, 0x11ee, 0x6060, + 0x22dd, 0x7070, 0x33cc, 0x8080, + 0xfe01, 0xd0d0, 0xdc23, 0xe0e0, + 0xba45, 0xf0f0, 0x9867, 0x0f0f }; + fixed_bfloat16_t a16, b16; + __builtin_memcpy (&a16, &a16_i, sizeof (a16)); + __builtin_memcpy (&b16, &b16_i, sizeof (b16)); + TEST (f5 (a16, b16), expected5); + TEST (f6 (a16, b16), expected6); + + fixed_uint8_t a8 = { 0x01, 0x12, 0x23, 0x34, 0x45, 0x56, 0x67, 0x70, + 0x89, 0x9a, 0xab, 0xbc, 0xcd, 0xde, 0xef, 0xf8, + 0xfe, 0xed, 0xdc, 0xcb, 0xba, 0xa9, 0x98, 0x8f, + 0x76, 0x65, 0x54, 0x43, 0x32, 0x21, 0x10, 0x07 }; + fixed_uint8_t b8 = { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, + 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff, 0x00, + 0x13, 0x24, 0x35, 0x46, 0x57, 0x68, 0x79, 0x8a, + 0x9b, 0xac, 0xbd, 0xce, 0xdf, 0xe0, 0xf1, 0x02 }; + fixed_uint8_t expected7 = { 0x01, 0x11, 0x12, 0x22, 0x23, 0x33, 0x34, 0x44, + 0x45, 0x55, 0x56, 0x66, 0x67, 0x77, 0x70, 0x88, + 0xfe, 0x13, 0xed, 0x24, 0xdc, 0x35, 0xcb, 0x46, + 0xba, 0x57, 0xa9, 0x68, 0x98, 0x79, 0x8f, 0x8a }; + fixed_uint8_t expected8 = { 0x89, 0x99, 0x9a, 0xaa, 0xab, 0xbb, 0xbc, 0xcc, + 0xcd, 0xdd, 0xde, 0xee, 0xef, 0xff, 0xf8, 0x00, + 0x76, 0x9b, 0x65, 0xac, 0x54, 0xbd, 0x43, 0xce, + 0x32, 0xdf, 0x21, 0xe0, 0x10, 0xf1, 0x07, 0x02 }; + TEST (f7 (a8, b8), expected7); + TEST (f8 (a8, b8), expected8); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/unroll-vect.c b/gcc/testsuite/gcc.target/aarch64/unroll-vect.c new file mode 100644 index 0000000..3cb774b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/unroll-vect.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O3 -march=armv8-a --param aarch64-autovec-preference=asimd-only -std=gnu99" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* +** f1: +** ... +** add v[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s +** add v[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s +** add v[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s +** add v[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s +** ... +*/ +void f1 (int *restrict a, int n) +{ +#pragma GCC unroll 16 + for (int i = 0; i < n; i++) + a[i] *= 2; +} + diff --git a/gcc/testsuite/gcc.target/aarch64/vec-set-zero.c b/gcc/testsuite/gcc.target/aarch64/vec-set-zero.c index b34b902c..ba4696e 100644 --- a/gcc/testsuite/gcc.target/aarch64/vec-set-zero.c +++ b/gcc/testsuite/gcc.target/aarch64/vec-set-zero.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2" } */ +/* { dg-options "-Os" } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/aarch64/vector-compare-5.c b/gcc/testsuite/gcc.target/aarch64/vector-compare-5.c new file mode 100644 index 0000000..a1a601d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vector-compare-5.c @@ -0,0 +1,67 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-additional-options "-fdump-tree-original-all" } */ + +typedef int v4i __attribute__((vector_size(4*sizeof(int)))); + +/* Ensure we can simplify `VEC_COND_EXPR(a OP1 b) OP2 VEC_COND_EXPR(a OP3 b)` + * into `VEC_COND_EXPR(a OP4 b)` + */ + +void use (v4i const *z); + +void +g (v4i *x, v4i const *y, v4i *z, v4i *t) +{ + *z = *x > *y | *x == *y; // expect >= + *t = *x > *y | *x <= *y; // expect true +} + +void +h (v4i *x, v4i const *y, v4i *z, v4i *t) +{ + *z = *x <= *y & *x >= *y; // expect x == y + *t = *x <= *y & *x != *y; // expect x<y +} + +void +i (v4i *x, v4i const *y, v4i *z, v4i *t) +{ + *z = *x == *y | *x != *y; // expect true + *t = *x == *y & *x != *y; // expect false +} + +void +k (v4i *x, v4i const *y, v4i *z, v4i *t) +{ + *z = *x < *y | *x == *y; // x <= y + *t = *x < *y & *x > *y; // expect false +} + +void +m (v4i *x, v4i const *y, v4i *z, v4i *t) +{ + *z = *x <= *y ^ *x >= *y; /* expect x != y */ + *t = *x <= *y ^ *x != *y; /* expect x <= y */ +} + +void +n (v4i *x, v4i const *y, v4i *z, v4i *t) +{ + *z = *x == *y ^ *x != *y; /* expect true */ + *t = *x == *y ^ *x == *y; /* expect false */ +} + + +/* { dg-final { scan-tree-dump ".*\\*zD\\.\\d+\\s*=\\s*VEC_COND_EXPR\\s*<\\s*\\*xD\\.\\d+\\s*>=\\s*VIEW_CONVERT_EXPR<v4iD\\.\\d+>\\(\\*yD\\.\\d+\\)\\s*,\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*,\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*>\\s*;" "original" } } */ +/* { dg-final { scan-tree-dump ".*\\*tD\\.\\d+\\s*=\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*;" "original" } } */ +/* { dg-final { scan-tree-dump ".*\\*zD\\.\\d+\\s*=\\s*VEC_COND_EXPR\\s*<\\s*\\*xD\\.\\d+\\s*==\\s*VIEW_CONVERT_EXPR<v4iD\\.\\d+>\\(\\*yD\\.\\d+\\)\\s*,\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*,\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*>\\s*;" "original" } } */ +/* { dg-final { scan-tree-dump ".*\\*tD\\.\\d+\\s*=\\s*VEC_COND_EXPR\\s*<\\s*\\*xD\\.\\d+\\s*<\\s*VIEW_CONVERT_EXPR<v4iD\\.\\d+>\\(\\*yD\\.\\d+\\)\\s*,\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*,\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*>\\s*;" "original" } } */ +/* { dg-final { scan-tree-dump ".*\\*zD\\.\\d+\\s*=\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*;" "original" } } */ +/* { dg-final { scan-tree-dump ".*\\*tD\\.\\d+\\s*=\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*;" "original" } } */ +/* { dg-final { scan-tree-dump ".*\\*zD\\.\\d+\\s*=\\s*VEC_COND_EXPR\\s*<\\s*\\*xD\\.\\d+\\s*<=\\s*VIEW_CONVERT_EXPR<v4iD\\.\\d+>\\(\\*yD\\.\\d+\\)\\s*,\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*,\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*>\\s*;" "original" } } */ +/* { dg-final { scan-tree-dump ".*\\*tD\\.\\d+\\s*=\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*;" "original" } } */ +/* { dg-final { scan-tree-dump ".*\\*zD\\.\\d+\\s*=\\s*VEC_COND_EXPR\\s*<\\s*\\*xD\\.\\d+\\s*!=\\s*VIEW_CONVERT_EXPR<v4iD\\.\\d+>\\(\\*yD\\.\\d+\\)\\s*,\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*,\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*>\\s*;" "original" } } */ +/* { dg-final { scan-tree-dump ".*\\*tD\\.\\d+\\s*=\\s*VEC_COND_EXPR\\s*<\\s*\\*xD\\.\\d+\\s*>=\\s*VIEW_CONVERT_EXPR<v4iD\\.\\d+>\\(\\*yD\\.\\d+\\)\\s*,\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*,\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*>\\s*;" "original" } } */ +/* { dg-final { scan-tree-dump ".*\\*zD\\.\\d+\\s*=\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*;" "original" } } */ +/* { dg-final { scan-tree-dump ".*\\*tD\\.\\d+\\s*=\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*;" "original" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vld2-1.c b/gcc/testsuite/gcc.target/aarch64/vld2-1.c new file mode 100644 index 0000000..8a26767 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vld2-1.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-forwprop1-details" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ +/* PR tree-optimization/89606 */ + +#include <arm_neon.h> + +/* +**func1: +** ld2 {v0.2d - v1.2d}, \[x0\] +** ld2 {v0.d - v1.d}\[1\], \[x1\] +** ret +*/ +float64x2x2_t func1(const double *p1, const double *p2) +{ + float64x2x2_t v = vld2q_f64(p1); + return vld2q_lane_f64(p2, v, 1); +} + +/* +**func2: +** ld2 {v0.2s - v1.2s}, \[x0\] +** ld2 {v0.s - v1.s}\[1\], \[x1\] +** ret +*/ +float32x2x2_t func2(const float *p1, const float *p2) +{ + float32x2x2_t v = vld2_f32(p1); + return vld2_lane_f32(p2, v, 1); +} + +/* +**func3: +** ld2 {v([0-9]+).2s - v([0-9]+).2s}, \[x1\] +** ld2 {v\1.s - v\2.s}\[1\], \[x2\] +** stp d\1, d\2, \[x0\] +** ret +*/ +void func3(float32x2x2_t *p, const float *p1, const float *p2) +{ + float32x2x2_t v = vld2_f32(p1); + *p = vld2_lane_f32(p2, v, 1); +} + +/* { dg-final { scan-tree-dump-times "after previous" 3 "forwprop1" } } */ diff --git a/gcc/testsuite/gcc.target/arc/fma-1.c b/gcc/testsuite/gcc.target/arc/fma-1.c index c195ad9..b32989f 100644 --- a/gcc/testsuite/gcc.target/arc/fma-1.c +++ b/gcc/testsuite/gcc.target/arc/fma-1.c @@ -2,7 +2,8 @@ /* { dg-skip-if "FPU not available" { arc700 || arc6xx } } */ /* { dg-options "-s -std=gnu11 -O2 -frounding-math -mfpu=fpus_all" } */ -const float a, b = 7.8539818525e01; +const float b = 7.8539818525e01; +extern const float a; /* Check if the fma operation is generated correctly. */ diff --git a/gcc/testsuite/gcc.target/arc/mult-cmp0.c b/gcc/testsuite/gcc.target/arc/mult-cmp0.c new file mode 100644 index 0000000..680c72e --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/mult-cmp0.c @@ -0,0 +1,66 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +/* mpy.f r1,r0,r1 + mov_s r0,5 ;3 + j_s.d [blink] + mov.ne r0,r1 */ +unsigned int +ubar (unsigned int a, unsigned int b) +{ + unsigned int c = a * b; + if (c == 0) + { + return 5; + } + return c; +} + +/* mpy.f r1,r0,r1 + mov_s r0,5 ;3 + j_s.d [blink] + mov.ne r0,r1 */ +signed int +bar (signed int a, signed int b) +{ + signed int c = a * b; + if (c == 0) + { + return 5; + } + return c; +} + +/* mpy.f 0,r0,r1 + mov_s r0,1 ;3 + j_s.d [blink] + mov.eq r0,5 */ +unsigned int +ufoo (unsigned int a, unsigned int b) +{ + if (a * b == 0) + { + return 5; + } + return 1; +} + +/* mpy.f 0,r0,r1 + mov_s r0,1 ;3 + j_s.d [blink] + mov.eq r0,5 */ +unsigned int +foo (signed int a, signed int b) +{ + if (a * b == 0) + { + return 5; + } + return 1; +} + +/* { dg-final { scan-assembler-times "mpy\\.f\\s+0" 2 } } */ +/* { dg-final { scan-assembler-times "mov\\.ne\\s+" 2 } } */ +/* { dg-final { scan-assembler-times "mpy\\.f\\s+r" 2 } } */ +/* { dg-final { scan-assembler-times "mov\\.eq\\s+" 2 } } */ + diff --git a/gcc/testsuite/gcc.target/arc/overflow-1.c b/gcc/testsuite/gcc.target/arc/overflow-1.c new file mode 100644 index 0000000..cf1d0d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/overflow-1.c @@ -0,0 +1,98 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +#include <stdbool.h> +#include <stdint.h> + +/* + * add.f r0,r0,r1 + * st_s r0,[r2] + * mov_s r0,1 + * j_s.d [blink] + * mov.nv r0,0 + */ +bool add_overflow (int32_t a, int32_t b, int32_t *res) +{ + return __builtin_add_overflow (a, b, res); +} + +/* + * add.f r0,r0,-1234 + * st_s r0,[r1] + * mov_s r0,1 + * j_s.d [blink] + * mov.nv r0,0 + */ +bool addi_overflow (int32_t a, int32_t *res) +{ + return __builtin_add_overflow (a, -1234, res); +} + +/* + * add.f r0,r0,r1 + * st_s r0,[r2] + * j_s.d [blink] + * rlc r0,0 + */ +bool uadd_overflow (uint32_t a, uint32_t b, uint32_t *res) +{ + return __builtin_add_overflow (a, b, res); +} + +/* + * add.f r2,r0, 4321 + * seths r0,r0,-4321 + * j_s.d [blink] + * st_s r2,[r1] + */ +bool uaddi_overflow (uint32_t a, uint32_t *res) +{ + return __builtin_add_overflow (a, 4321, res); +} + +/* + * add.f r0,r0,r1 + * mov_s r0,1 + * j_s.d [blink] + * mov.nv r0,0 + */ +bool add_overflow_p (int32_t a, int32_t b, int32_t res) +{ + return __builtin_add_overflow_p (a, b, res); +} + +/* + * add.f r0,r0,-1000 + * mov_s r0,1 + * j_s.d [blink] + * mov.nv r0,0 + */ +bool addi_overflow_p (int32_t a, int32_t res) +{ + return __builtin_add_overflow_p (a, -1000, res); +} + +/* + * add.f 0,r0,r1 + * j_s.d [blink] + * rlc r0,0
+ */ +bool uadd_overflow_p (uint32_t a, uint32_t b, uint32_t res) +{ + return __builtin_add_overflow_p (a, b, res); +} + +/* + * j_s.d [blink] + * seths r0,r0,-2000 + */ +bool uaddi_overflow_p (uint32_t a, uint32_t res) +{ + return __builtin_add_overflow_p (a, 2000, res); +} + +/* { dg-final { scan-assembler-times "add.f\\s\+" 7 } } */ +/* { dg-final { scan-assembler-times "mov\.nv\\s\+" 4 } } */ +/* { dg-final { scan-assembler-times "rlc\\s\+" 2 } } */
+/* { dg-final { scan-assembler-times "seths\\s\+" 2 } } */ +/* { dg-final { scan-assembler-not "cmp" } } */ diff --git a/gcc/testsuite/gcc.target/arc/overflow-2.c b/gcc/testsuite/gcc.target/arc/overflow-2.c new file mode 100644 index 0000000..b4de8c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/overflow-2.c @@ -0,0 +1,97 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +#include <stdbool.h> +#include <stdint.h> + +/* + * sub.f r0,r0,r1 + * st_s r0,[r2] + * mov_s r0,1 + * j_s.d [blink] + * mov.nv r0,0 + */ +bool sub_overflow (int32_t a, int32_t b, int32_t *res) +{ + return __builtin_sub_overflow (a, b, res); +} + +/* + * sub.f r0,r0,-1234 + * st_s r0,[r1] + * mov_s r0,1 + * j_s.d [blink] + * mov.nv r0,0 + */ +bool subi_overflow (int32_t a, int32_t *res) +{ + return __builtin_sub_overflow (a, -1234, res); +} + +/* + * sub.f r3,r0,r1 + * st_s r3,[r2] + * j_s.d [blink] + * setlo r0,r0,r1 + */ +bool usub_overflow (uint32_t a, uint32_t b, uint32_t *res) +{ + return __builtin_sub_overflow (a, b, res); +} + +/* + * sub.f r2,r0,4321 + * seths r0,4320,r0 + * j_s.d [blink] + * st_s r2,[r1] + */ +bool usubi_overflow (uint32_t a, uint32_t *res) +{ + return __builtin_sub_overflow (a, 4321, res); +} + +/* + * sub.f r0,r0,r1 + * mov_s r0,1 + * j_s.d [blink] + * mov.nv r0,0 + */ +bool sub_overflow_p (int32_t a, int32_t b, int32_t res) +{ + return __builtin_sub_overflow_p (a, b, res); +} + +/* + * sub.f r0,r0,-1000 + * mov_s r0,1 + * j_s.d [blink] + * mov.nv r0,0 + */ +bool subi_overflow_p (int32_t a, int32_t res) +{ + return __builtin_sub_overflow_p (a, -1000, res); +} + +/* + * j_s.d [blink] + * setlo r0,r0,r1 + */ +bool usub_overflow_p (uint32_t a, uint32_t b, uint32_t res) +{ + return __builtin_sub_overflow_p (a, b, res); +} + +/* + * seths r0,1999,r0 + * j_s.d [blink] + */ +bool usubi_overflow_p (uint32_t a, uint32_t res) +{ + return __builtin_sub_overflow_p (a, 2000, res); +} + +/* { dg-final { scan-assembler-times "sub.f\\s\+" 6 } } */ +/* { dg-final { scan-assembler-times "mov\.nv\\s\+" 4 } } */ +/* { dg-final { scan-assembler-times "setlo\\s\+" 2 } } */ +/* { dg-final { scan-assembler-times "seths\\s\+" 2 } } */ +/* { dg-final { scan-assembler-not "cmp" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr120351.c b/gcc/testsuite/gcc.target/arm/pr120351.c new file mode 100644 index 0000000..d8e9d73 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr120351.c @@ -0,0 +1,47 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-add-options arm_neon } */ +/* { dg-additional-options "-O2" } */ + + +typedef struct A +{ + int f1; +} A; + +__inline void ref (A* x) +{ + __atomic_fetch_add(&x->f1, 1, 0); +} + +typedef struct B +{ + A *d; + int *ptr; +} B; + +void insertOne (B*, B*); + +void init (B *); +__inline void copy (B *p, B *q) +{ + p->d = q->d; + p->ptr = q->ptr; + ref (p->d); +} + +__inline void emplace(B* x) +{ + B dummy; + B _tmp; + init (&dummy); + copy (&_tmp, &dummy); + insertOne(x, &_tmp); +} + +void testing () +{ + B test; + init (&test); + emplace(&test); +} diff --git a/gcc/testsuite/gcc.target/arm/pr121065.c b/gcc/testsuite/gcc.target/arm/pr121065.c new file mode 100644 index 0000000..dfc6059 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr121065.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=cortex-m55" } */ + +_Accum sa; +char c; + +void +div_csa () +{ + c /= sa; +} diff --git a/gcc/testsuite/gcc.target/avr/torture/pr120423-1.c b/gcc/testsuite/gcc.target/avr/torture/pr120423-1.c new file mode 100644 index 0000000..91b4bbc --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr120423-1.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ + +struct data +{ + int a; + int b; + long c; +}; + +unsigned char val; +unsigned val2; + +void func1 (struct data *d) +{ + d->a = 0; + d->b = 0x100 * val - 1; +} + +void func2 (struct data *d) +{ + d->a = 0; + d->c = 0x10000 * val2 - 1; +} + +void func3 (struct data *d) +{ + d->a = 0; + d->c = 0x1000000 * val - 1; +} diff --git a/gcc/testsuite/gcc.target/avr/torture/pr120423-116389.c b/gcc/testsuite/gcc.target/avr/torture/pr120423-116389.c new file mode 100644 index 0000000..928c135 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr120423-116389.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ + +struct T { int val; }; + +void f_int (int); +char* get_pos (void); +struct T* get_pT (void); + +void func (char i) +{ + struct T t = * get_pT (); + unsigned diff = get_pos () - &i; + + if (diff) + { + long val32 = t.val; + if (get_pos ()) + val32 = diff; + if (get_pos ()) + f_int (2 * val32); + } +} diff --git a/gcc/testsuite/gcc.target/avr/torture/pr120423-2.c b/gcc/testsuite/gcc.target/avr/torture/pr120423-2.c new file mode 100644 index 0000000..56e6141 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr120423-2.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-ffixed-18 -ffixed-20 -ffixed-22" } */ + +struct data +{ + int a; + int b; + long c; +}; + +unsigned char val; +unsigned val2; + +void func1 (struct data *d) +{ + d->a = 0; + d->b = 0x100 * val - 1; +} + +void func2 (struct data *d) +{ + d->a = 0; + d->c = 0x10000 * val2 - 1; +} + +void func3 (struct data *d) +{ + d->a = 0; + d->c = 0x1000000 * val - 1; +} diff --git a/gcc/testsuite/gcc.target/i386/20020224-1.c b/gcc/testsuite/gcc.target/i386/20020224-1.c index 2905719..769332b 100644 --- a/gcc/testsuite/gcc.target/i386/20020224-1.c +++ b/gcc/testsuite/gcc.target/i386/20020224-1.c @@ -4,6 +4,7 @@ while callee was actually not poping it up (as the hidden argument was passed in register). */ /* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -fomit-frame-pointer" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowd2ps-2.c b/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowd2ps-2.c index cfd5644..c9a2d19 100644 --- a/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowd2ps-2.c +++ b/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowd2ps-2.c @@ -1,6 +1,6 @@ /* { dg-do run { target { ! ia32 } } } */ /* { dg-require-effective-target amx_avx512 } */ -/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512" } */ +/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512 -mavx512fp16" } */ #define AMX_AVX512 #define DO_TEST test_amx_avx512_cvtrowd2ps void test_amx_avx512_cvtrowd2ps(); diff --git a/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2bf16-2.c b/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2bf16-2.c index acd5f76..2014ec6 100644 --- a/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2bf16-2.c +++ b/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2bf16-2.c @@ -1,6 +1,6 @@ /* { dg-do run { target { ! ia32 } } } */ /* { dg-require-effective-target amx_avx512 } */ -/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512" } */ +/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512 -mavx512fp16" } */ #define AMX_AVX512 #define DO_TEST test_amx_avx512_cvtrowps2bf16 void test_amx_avx512_cvtrowps2bf16(); diff --git a/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2ph-2.c b/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2ph-2.c index 1fd28de..ca53ed00 100644 --- a/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2ph-2.c +++ b/gcc/testsuite/gcc.target/i386/amxavx512-cvtrowps2ph-2.c @@ -1,6 +1,6 @@ /* { dg-do run { target { ! ia32 } } } */ /* { dg-require-effective-target amx_avx512 } */ -/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512" } */ +/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512 -mavx512fp16" } */ #define AMX_AVX512 #define DO_TEST test_amx_avx512_cvtrowps2ph void test_amx_avx512_cvtrowps2ph(); diff --git a/gcc/testsuite/gcc.target/i386/amxavx512-movrow-2.c b/gcc/testsuite/gcc.target/i386/amxavx512-movrow-2.c index ea28d82..b2dee14 100644 --- a/gcc/testsuite/gcc.target/i386/amxavx512-movrow-2.c +++ b/gcc/testsuite/gcc.target/i386/amxavx512-movrow-2.c @@ -1,6 +1,6 @@ /* { dg-do run { target { ! ia32 } } } */ /* { dg-require-effective-target amx_avx512 } */ -/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512" } */ +/* { dg-options "-O2 -march=x86-64-v3 -mamx-avx512 -mavx512fp16" } */ #define AMX_AVX512 #define DO_TEST test_amx_avx512_movrow void test_amx_avx512_movrow(); diff --git a/gcc/testsuite/gcc.target/i386/apx-1.c b/gcc/testsuite/gcc.target/i386/apx-1.c index 4e580ec..b118928 100644 --- a/gcc/testsuite/gcc.target/i386/apx-1.c +++ b/gcc/testsuite/gcc.target/i386/apx-1.c @@ -3,6 +3,6 @@ /* { dg-error "'-mapxf' is not supported for 32-bit code" "" { target ia32 } 0 } */ void -apx_hanlder () +apx_handler () { } diff --git a/gcc/testsuite/gcc.target/i386/asm-hard-reg-1.c b/gcc/testsuite/gcc.target/i386/asm-hard-reg-1.c new file mode 100644 index 0000000..8080f56 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/asm-hard-reg-1.c @@ -0,0 +1,80 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +test (void) +{ + int x, y; + + __asm__ __volatile__ ("" : "=a" (x), "={rbx}" (y)); + __asm__ __volatile__ ("" : "=a" (x), "={rax}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=a" (x) : "{rax}" (y)); + __asm__ __volatile__ ("" : "=&a" (x) : "{rax}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "a" (x), "{rax}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "={rbx}" (x), "=a" (y)); + __asm__ __volatile__ ("" : "={rax}" (x), "=a" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rax}" (x) : "a" (y)); + __asm__ __volatile__ ("" : "=&{rax}" (x) : "a" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rax}" (x), "a" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "=b" (x), "={rax}" (y)); + __asm__ __volatile__ ("" : "=b" (x), "={rbx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=b" (x) : "{rbx}" (y)); + __asm__ __volatile__ ("" : "=&b" (x) : "{rbx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "b" (x), "{rbx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "={rax}" (x), "=b" (y)); + __asm__ __volatile__ ("" : "={rbx}" (x), "=b" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rbx}" (x) : "b" (y)); + __asm__ __volatile__ ("" : "=&{rbx}" (x) : "b" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rbx}" (x), "b" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "=c" (x), "={rax}" (y)); + __asm__ __volatile__ ("" : "=c" (x), "={rcx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=c" (x) : "{rcx}" (y)); + __asm__ __volatile__ ("" : "=&c" (x) : "{rcx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "c" (x), "{rcx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "={rax}" (x), "=c" (y)); + __asm__ __volatile__ ("" : "={rcx}" (x), "=c" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rcx}" (x) : "c" (y)); + __asm__ __volatile__ ("" : "=&{rcx}" (x) : "c" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rcx}" (x), "c" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "=d" (x), "={rax}" (y)); + __asm__ __volatile__ ("" : "=d" (x), "={rdx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=d" (x) : "{rdx}" (y)); + __asm__ __volatile__ ("" : "=&d" (x) : "{rdx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "d" (x), "{rdx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "={rax}" (x), "=d" (y)); + __asm__ __volatile__ ("" : "={rdx}" (x), "=d" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rdx}" (x) : "d" (y)); + __asm__ __volatile__ ("" : "=&{rdx}" (x) : "d" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rdx}" (x), "d" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "=S" (x), "={rax}" (y)); + __asm__ __volatile__ ("" : "=S" (x), "={rsi}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=S" (x) : "{rsi}" (y)); + __asm__ __volatile__ ("" : "=&S" (x) : "{rsi}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "S" (x), "{rsi}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "={rax}" (x), "=S" (y)); + __asm__ __volatile__ ("" : "={rsi}" (x), "=S" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rsi}" (x) : "S" (y)); + __asm__ __volatile__ ("" : "=&{rsi}" (x) : "S" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rsi}" (x), "S" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "=D" (x), "={rax}" (y)); + __asm__ __volatile__ ("" : "=D" (x), "={rdi}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=D" (x) : "{rdi}" (y)); + __asm__ __volatile__ ("" : "=&D" (x) : "{rdi}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "D" (x), "{rdi}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "={rax}" (x), "=D" (y)); + __asm__ __volatile__ ("" : "={rdi}" (x), "=D" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rdi}" (x) : "D" (y)); + __asm__ __volatile__ ("" : "=&{rdi}" (x) : "D" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rdi}" (x), "D" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ +} diff --git a/gcc/testsuite/gcc.target/i386/asm-hard-reg-2.c b/gcc/testsuite/gcc.target/i386/asm-hard-reg-2.c new file mode 100644 index 0000000..b35cf53 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/asm-hard-reg-2.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +test (void) +{ + int x, y, yy; +#ifdef __x86_64__ + int z __attribute__ ((mode (TI))); +#else + long z; +#endif + + __asm__ __volatile__ ("" : "=A" (z), "={rbx}" (y)); + __asm__ __volatile__ ("" : "=A" (z), "={rax}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=A" (z), "={rdx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=A" (z) : "{rax}" (y)); + __asm__ __volatile__ ("" : "=A" (z) : "{rdx}" (y)); + __asm__ __volatile__ ("" : "=&A" (z) : "{rax}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=&A" (z) : "{rdx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "A" (z), "{rax}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "A" (z), "{rdx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "={rbx}" (y), "=A" (z)); + __asm__ __volatile__ ("" : "={rax}" (y), "=A" (z)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rdx}" (y), "=A" (z)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rax}" (y) : "A" (z)); + __asm__ __volatile__ ("" : "={rdx}" (y) : "A" (z)); + __asm__ __volatile__ ("" : "=&{rax}" (y) : "A" (z)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=&{rdx}" (y) : "A" (z)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rax}" (y), "A" (z)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rdx}" (y), "A" (z)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + /* Note, we do not error for */ + __asm__ __volatile__ ("" : "=A" (x), "={rax}" (y)); + __asm__ __volatile__ ("" : "=A" (x), "={rdx}" (y)); + /* This is due to how constraint A is implemented. RA has the freedom to + choose between rax or rdx for operand 0 since x fits into a single + register and does not require a register pair. Of course, we error out if + rax and rdx are taken by other operands as in the following: */ + __asm__ __volatile__ ("" : "=A" (x), "={rax}" (y), "={rdx}" (yy)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=A" (x), "={rdx}" (y), "={rax}" (yy)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ +} diff --git a/gcc/testsuite/gcc.target/i386/attributes-error.c b/gcc/testsuite/gcc.target/i386/attributes-error.c index 405eda5..5d1c77d 100644 --- a/gcc/testsuite/gcc.target/i386/attributes-error.c +++ b/gcc/testsuite/gcc.target/i386/attributes-error.c @@ -1,12 +1,40 @@ +/* { dg-options "-msse2" } */ /* { dg-do compile } */ /* { dg-require-effective-target ia32 } */ -void foo1(int i, int j) __attribute__((fastcall, cdecl)); /* { dg-error "not compatible" } */ -void foo2(int i, int j) __attribute__((fastcall, stdcall)); /* { dg-error "not compatible" } */ +void foo1(int i, int j) __attribute__((cdecl, regparm(2))); +void foo2(int i, int j) __attribute__((stdcall, regparm(2))); void foo3(int i, int j) __attribute__((fastcall, regparm(2))); /* { dg-error "not compatible" } */ -void foo4(int i, int j) __attribute__((stdcall, cdecl)); /* { dg-error "not compatible" } */ -void foo5(int i, int j) __attribute__((stdcall, fastcall)); /* { dg-error "not compatible" } */ -void foo6(int i, int j) __attribute__((cdecl, fastcall)); /* { dg-error "not compatible" } */ -void foo7(int i, int j) __attribute__((cdecl, stdcall)); /* { dg-error "not compatible" } */ -void foo8(int i, int j) __attribute__((regparm(2), fastcall)); /* { dg-error "not compatible" } */ +void foo4(int i, int j) __attribute__((thiscall, regparm(2))); /* { dg-error "not compatible" } */ +void foo5(int i, int j) __attribute__((sseregparm, regparm(2))); + +void foo6(int i, int j) __attribute__((stdcall, fastcall)); /* { dg-error "not compatible" } */ +void foo7(int i, int j) __attribute__((regparm(2), fastcall)); /* { dg-error "not compatible" } */ +void foo8(int i, int j) __attribute__((cdecl, fastcall)); /* { dg-error "not compatible" } */ +void foo9(int i, int j) __attribute__((thiscall, fastcall)); /* { dg-error "not compatible" } */ +void foo10(int i, int j) __attribute__((sseregparm, fastcall)); + +void foo11(int i, int j) __attribute__((cdecl, stdcall)); /* { dg-error "not compatible" } */ +void foo12(int i, int j) __attribute__((fastcall, stdcall)); /* { dg-error "not compatible" } */ +void foo13(int i, int j) __attribute__((thiscall, stdcall)); /* { dg-error "not compatible" } */ +void foo14(int i, int j) __attribute__((regparm(2), stdcall)); +void foo15(int i, int j) __attribute__((sseregparm, stdcall)); + +void foo16(int i, int j) __attribute__((stdcall, cdecl)); /* { dg-error "not compatible" } */ +void foo17(int i, int j) __attribute__((fastcall, cdecl)); /* { dg-error "not compatible" } */ +void foo18(int i, int j) __attribute__((thiscall, cdecl)); /* { dg-error "not compatible" } */ +void foo19(int i, int j) __attribute__((regparm(2), cdecl)); +void foo20(int i, int j) __attribute__((sseregparm, cdecl)); + +void foo21(int i, int j) __attribute__((stdcall, thiscall)); /* { dg-error "not compatible" } */ +void foo22(int i, int j) __attribute__((fastcall, thiscall)); /* { dg-error "not compatible" } */ +void foo23(int i, int j) __attribute__((cdecl, thiscall)); /* { dg-error "not compatible" } */ +void foo24(int i, int j) __attribute__((regparm(2), thiscall)); /* { dg-error "not compatible" } */ +void foo25(int i, int j) __attribute__((sseregparm, thiscall)); + +void foo26(int i, int j) __attribute__((cdecl, sseregparm)); +void foo27(int i, int j) __attribute__((fastcall, sseregparm)); +void foo28(int i, int j) __attribute__((stdcall, sseregparm)); +void foo29(int i, int j) __attribute__((thiscall, sseregparm)); +void foo30(int i, int j) __attribute__((regparm(2), sseregparm)); diff --git a/gcc/testsuite/gcc.target/i386/attributes-ignore.c b/gcc/testsuite/gcc.target/i386/attributes-ignore.c new file mode 100644 index 0000000..93a3770 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/attributes-ignore.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target { ! ia32 } } } */ + +void foo1(int i, int j) __attribute__((regparm(0))); /* { dg-warning "ignored" } */ +void foo2(int i, int j) __attribute__((stdcall)); /* { dg-warning "ignored" } */ +void foo3(int i, int j) __attribute__((fastcall)); /* { dg-warning "ignored" } */ +void foo4(int i, int j) __attribute__((cdecl)); /* { dg-warning "ignored" } */ +void foo5(int i, int j) __attribute__((thiscall)); /* { dg-warning "ignored" } */ +void foo6(int i, int j) __attribute__((sseregparm)); /* { dg-warning "ignored" } */ diff --git a/gcc/testsuite/gcc.target/i386/auto-init-padding-3.c b/gcc/testsuite/gcc.target/i386/auto-init-padding-3.c index 7c20a28..a12069a 100644 --- a/gcc/testsuite/gcc.target/i386/auto-init-padding-3.c +++ b/gcc/testsuite/gcc.target/i386/auto-init-padding-3.c @@ -23,8 +23,5 @@ int foo () return var.four.internal1; } -/* { dg-final { scan-assembler "movl\t\\\$0," } } */ -/* { dg-final { scan-assembler "movl\t\\\$16," { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "rep stosq" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\t\\\$32," { target ia32 } } } */ -/* { dg-final { scan-assembler "rep stosl" { target ia32 } } } */ +/* { dg-final { scan-assembler-times "pxor\t%xmm0, %xmm0" 1 } } */ +/* { dg-final { scan-assembler-times "movaps\t%xmm0, " 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/auto-init-padding-9.c b/gcc/testsuite/gcc.target/i386/auto-init-padding-9.c index a87b68b..4f26aa4 100644 --- a/gcc/testsuite/gcc.target/i386/auto-init-padding-9.c +++ b/gcc/testsuite/gcc.target/i386/auto-init-padding-9.c @@ -2,6 +2,36 @@ padding. */ /* { dg-do compile } */ /* { dg-options "-ftrivial-auto-var-init=zero -march=x86-64" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**... +** leaq -160\(%rbp\), %rax +** movq %rax, %rcx +** pxor %xmm0, %xmm0 +** movl \$160, %edx +** movl %edx, %edi +** andl \$-64, %edi +** movl \$0, %esi +**.L[0-9]+: +** movl %esi, %edx +** movaps %xmm0, \(%rax,%rdx\) +** movaps %xmm0, 16\(%rax,%rdx\) +** movaps %xmm0, 32\(%rax,%rdx\) +** movaps %xmm0, 48\(%rax,%rdx\) +** addl \$64, %esi +** cmpl %edi, %esi +** jb .L[0-9]+ +** movl %esi, %eax +** addq %rax, %rcx +** movaps %xmm0, \(%rcx\) +** movaps %xmm0, 16\(%rcx\) +** movzbl -116\(%rbp\), %eax +** movsbl %al, %eax +**... +*/ struct test_trailing_hole { int one; @@ -18,8 +48,4 @@ int foo () return var[2].four; } -/* { dg-final { scan-assembler "movl\t\\\$0," } } */ -/* { dg-final { scan-assembler "movl\t\\\$20," { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "rep stosq" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\t\\\$40," { target ia32} } } */ -/* { dg-final { scan-assembler "rep stosl" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c index 444a25e..5da06b5 100644 --- a/gcc/testsuite/gcc.target/i386/avx-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-1.c @@ -842,37 +842,33 @@ /* sm3intrin.h */ #define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A, B, C, 1) -/* avx10_2-512mediaintrin.h */ +/* avx10_2mediaintrin.h */ #define __builtin_ia32_mpsadbw512(A, B, C) __builtin_ia32_mpsadbw512 (A, B, 1) #define __builtin_ia32_mpsadbw512_mask(A, B, C, D, E) __builtin_ia32_mpsadbw512_mask (A, B, 1, D, E) - -/* avx10_2mediaintrin.h */ -#define __builtin_ia32_mpsadbw128_mask(A, B, C, D, E) __builtin_ia32_mpsadbw128_mask (A, B, 1, D, E) #define __builtin_ia32_mpsadbw256_mask(A, B, C, D, E) __builtin_ia32_mpsadbw256_mask (A, B, 1, D, E) +#define __builtin_ia32_mpsadbw128_mask(A, B, C, D, E) __builtin_ia32_mpsadbw128_mask (A, B, 1, D, E) -/* avx10_2-512convertintrin.h */ +/* avx10_2convertintrin.h */ #define __builtin_ia32_vcvt2ps2phx512_mask_round(A, B, C, D, E) __builtin_ia32_vcvt2ps2phx512_mask_round(A, B, C, D, 8) -/* avx10_2-512bf16intrin.h */ -#define __builtin_ia32_rndscalebf16512_mask(A, B, C, D) __builtin_ia32_rndscalebf16512_mask(A, 123, C, D) -#define __builtin_ia32_reducebf16512_mask(A, B, C, D) __builtin_ia32_reducebf16512_mask(A, 123, C, D) -#define __builtin_ia32_getmantbf16512_mask(A, B, C, D) __builtin_ia32_getmantbf16512_mask(A, 1, C, D) -#define __builtin_ia32_fpclassbf16512_mask(A, B, C) __builtin_ia32_fpclassbf16512_mask(A, 1, C) -#define __builtin_ia32_cmpbf16512_mask(A, B, C, D) __builtin_ia32_cmpbf16512_mask(A, B, 1, D) - /* avx10_2bf16intrin.h */ +#define __builtin_ia32_rndscalebf16512_mask(A, B, C, D) __builtin_ia32_rndscalebf16512_mask(A, 123, C, D) #define __builtin_ia32_rndscalebf16256_mask(A, B, C, D) __builtin_ia32_rndscalebf16256_mask(A, 123, C, D) #define __builtin_ia32_rndscalebf16128_mask(A, B, C, D) __builtin_ia32_rndscalebf16128_mask(A, 123, C, D) +#define __builtin_ia32_reducebf16512_mask(A, B, C, D) __builtin_ia32_reducebf16512_mask(A, 123, C, D) #define __builtin_ia32_reducebf16256_mask(A, B, C, D) __builtin_ia32_reducebf16256_mask(A, 123, C, D) #define __builtin_ia32_reducebf16128_mask(A, B, C, D) __builtin_ia32_reducebf16128_mask(A, 123, C, D) +#define __builtin_ia32_getmantbf16512_mask(A, B, C, D) __builtin_ia32_getmantbf16512_mask(A, 1, C, D) #define __builtin_ia32_getmantbf16256_mask(A, B, C, D) __builtin_ia32_getmantbf16256_mask(A, 1, C, D) #define __builtin_ia32_getmantbf16128_mask(A, B, C, D) __builtin_ia32_getmantbf16128_mask(A, 1, C, D) +#define __builtin_ia32_fpclassbf16512_mask(A, B, C) __builtin_ia32_fpclassbf16512_mask(A, 1, C) #define __builtin_ia32_fpclassbf16256_mask(A, B, C) __builtin_ia32_fpclassbf16256_mask(A, 1, C) #define __builtin_ia32_fpclassbf16128_mask(A, B, C) __builtin_ia32_fpclassbf16128_mask(A, 1, C) +#define __builtin_ia32_cmpbf16512_mask(A, B, C, D) __builtin_ia32_cmpbf16512_mask(A, B, 1, D) #define __builtin_ia32_cmpbf16256_mask(A, B, C, D) __builtin_ia32_cmpbf16256_mask(A, B, 1, D) #define __builtin_ia32_cmpbf16128_mask(A, B, C, D) __builtin_ia32_cmpbf16128_mask(A, B, 1, D) -/* avx10_2-512satcvtintrin.h */ +/* avx10_2satcvtintrin.h */ #define __builtin_ia32_cvtph2ibs512_mask_round(A, B, C, D) __builtin_ia32_cvtph2ibs512_mask_round(A, B, C, 8) #define __builtin_ia32_cvtph2iubs512_mask_round(A, B, C, D) __builtin_ia32_cvtph2iubs512_mask_round(A, B, C, 8) #define __builtin_ia32_cvtps2ibs512_mask_round(A, B, C, D) __builtin_ia32_cvtps2ibs512_mask_round(A, B, C, 8) @@ -889,8 +885,6 @@ #define __builtin_ia32_cvttps2qqs512_mask_round(A, B, C, D) __builtin_ia32_cvttps2qqs512_mask_round(A, B, C, 8) #define __builtin_ia32_cvttps2udqs512_mask_round(A, B, C, D) __builtin_ia32_cvttps2udqs512_mask_round(A, B, C, 8) #define __builtin_ia32_cvttps2uqqs512_mask_round(A, B, C, D) __builtin_ia32_cvttps2uqqs512_mask_round(A, B, C, 8) - -/* avx10_2satcvtintrin.h */ #define __builtin_ia32_cvttsd2sis32_round(A, B) __builtin_ia32_cvttsd2sis32_round(A, 8) #define __builtin_ia32_cvttsd2usis32_round(A, B) __builtin_ia32_cvttsd2usis32_round(A, 8) #define __builtin_ia32_cvttss2sis32_round(A, B) __builtin_ia32_cvttss2sis32_round(A, 8) @@ -902,24 +896,22 @@ #define __builtin_ia32_cvttss2usis64_round(A, B) __builtin_ia32_cvttss2usis64_round(A, 8) #endif -/* avx10_2-512minmaxintrin.h */ +/* avx10_2minmaxintrin.h */ +#define __builtin_ia32_minmaxbf16512_mask(A, B, C, W, U) __builtin_ia32_minmaxbf16512_mask (A, B, 4, W, U) +#define __builtin_ia32_minmaxbf16256_mask(A, B, C, D, E) __builtin_ia32_minmaxbf16256_mask (A, B, 4, D, E) +#define __builtin_ia32_minmaxbf16128_mask(A, B, C, D, E) __builtin_ia32_minmaxbf16128_mask (A, B, 4, D, E) #define __builtin_ia32_minmaxpd512_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxpd512_mask_round (A, B, 4, D, E, 4) +#define __builtin_ia32_minmaxpd256_mask(A, B, C, D, E) __builtin_ia32_minmaxpd256_mask (A, B, 4, D, E) +#define __builtin_ia32_minmaxpd128_mask(A, B, C, D, E) __builtin_ia32_minmaxpd128_mask (A, B, 4, D, E) #define __builtin_ia32_minmaxph512_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxph512_mask_round (A, B, 4, D, E, 4) +#define __builtin_ia32_minmaxph256_mask(A, B, C, D, E) __builtin_ia32_minmaxph256_mask (A, B, 4, D, E) +#define __builtin_ia32_minmaxph128_mask(A, B, C, D, E) __builtin_ia32_minmaxph128_mask (A, B, 4, D, E) #define __builtin_ia32_minmaxps512_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxps512_mask_round (A, B, 4, D, E, 4) -#define __builtin_ia32_minmaxbf16512_mask(A, B, C, W, U) __builtin_ia32_minmaxbf16512_mask (A, B, 4, W, U) - -/* avx10_2minmaxintrin.h */ +#define __builtin_ia32_minmaxps256_mask(A, B, C, D, E) __builtin_ia32_minmaxps256_mask (A, B, 4, D, E) +#define __builtin_ia32_minmaxps128_mask(A, B, C, D, E) __builtin_ia32_minmaxps128_mask (A, B, 4, D, E) #define __builtin_ia32_minmaxsd_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxsd_mask_round (A, B, 4, D, E, 4) #define __builtin_ia32_minmaxsh_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxsh_mask_round (A, B, 4, D, E, 4) #define __builtin_ia32_minmaxss_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxss_mask_round (A, B, 4, D, E, 4) -#define __builtin_ia32_minmaxbf16128_mask(A, B, C, D, E) __builtin_ia32_minmaxbf16128_mask (A, B, 4, D, E) -#define __builtin_ia32_minmaxbf16256_mask(A, B, C, D, E) __builtin_ia32_minmaxbf16256_mask (A, B, 4, D, E) -#define __builtin_ia32_minmaxpd128_mask(A, B, C, D, E) __builtin_ia32_minmaxpd128_mask (A, B, 4, D, E) -#define __builtin_ia32_minmaxpd256_mask(A, B, C, D, E) __builtin_ia32_minmaxpd256_mask (A, B, 4, D, E) -#define __builtin_ia32_minmaxph128_mask(A, B, C, D, E) __builtin_ia32_minmaxph128_mask (A, B, 4, D, E) -#define __builtin_ia32_minmaxph256_mask(A, B, C, D, E) __builtin_ia32_minmaxph256_mask (A, B, 4, D, E) -#define __builtin_ia32_minmaxps128_mask(A, B, C, D, E) __builtin_ia32_minmaxps128_mask (A, B, 4, D, E) -#define __builtin_ia32_minmaxps256_mask(A, B, C, D, E) __builtin_ia32_minmaxps256_mask (A, B, 4, D, E) #include <wmmintrin.h> #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10-check.h b/gcc/testsuite/gcc.target/i386/avx10-check.h index 7d4326d..6a1a151 100644 --- a/gcc/testsuite/gcc.target/i386/avx10-check.h +++ b/gcc/testsuite/gcc.target/i386/avx10-check.h @@ -5,9 +5,8 @@ #ifndef DO_TEST #define DO_TEST do_test -#if defined(AVX10_512BIT) || defined(AVX10_SCALAR) static void test_512 (void); -#else +#ifndef AVX10_SCALAR static void test_256 (void); static void test_128 (void); #endif @@ -16,9 +15,8 @@ __attribute__ ((noinline)) static void do_test (void) { -#if defined(AVX10_512BIT) || defined(AVX10_SCALAR) test_512 (); -#else +#ifndef AVX10_SCALAR test_256 (); test_128 (); #endif diff --git a/gcc/testsuite/gcc.target/i386/avx10-minmax-helper.h b/gcc/testsuite/gcc.target/i386/avx10-minmax-helper.h index e799975..6c9bffc 100644 --- a/gcc/testsuite/gcc.target/i386/avx10-minmax-helper.h +++ b/gcc/testsuite/gcc.target/i386/avx10-minmax-helper.h @@ -66,12 +66,10 @@ check_minmax_##UNION_TYPE (UNION_TYPE u, const VALUE_TYPE *v) \ return err; \ } -#if defined (AVX10_512BIT) CHECK_EXP_MINMAX (union512, float, int) CHECK_EXP_MINMAX (union512d, double, long int) CHECK_EXP_MINMAX (union512bf16_bf, __bf16, short int) CHECK_EXP_MINMAX (union512h, _Float16, short int) -#endif CHECK_EXP_MINMAX (union256, float, int) CHECK_EXP_MINMAX (union256d, double, long int) CHECK_EXP_MINMAX (union128, float, int) diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-1.c b/gcc/testsuite/gcc.target/i386/avx10_1-1.c index bd3249e..cfd9662 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-1.c @@ -1,6 +1,5 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-O2 -march=x86-64 -mavx10.1" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-10.c b/gcc/testsuite/gcc.target/i386/avx10_1-10.c deleted file mode 100644 index dba2a4e..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-10.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f -mno-evex512" } */ -/* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-11.c b/gcc/testsuite/gcc.target/i386/avx10_1-11.c deleted file mode 100644 index 608817a..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-11.c +++ /dev/null @@ -1,7 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1 -mno-avx512f" } */ -/* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-12.c b/gcc/testsuite/gcc.target/i386/avx10_1-12.c deleted file mode 100644 index 1650f26..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-12.c +++ /dev/null @@ -1,7 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mno-avx10.1-512 -mavx512f" } */ -/* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-13.c b/gcc/testsuite/gcc.target/i386/avx10_1-13.c deleted file mode 100644 index a864e96..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-13.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1-256" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("avx512f"))) __m512d -foo () -{ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-14.c b/gcc/testsuite/gcc.target/i386/avx10_1-14.c deleted file mode 100644 index 76573e6..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-14.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx512f" } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("avx10.1-256"))) __m512d -foo () -{ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-15.c b/gcc/testsuite/gcc.target/i386/avx10_1-15.c deleted file mode 100644 index b227cf3..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-15.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("avx512f,no-evex512"))) __m512d -foo () -{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-16.c b/gcc/testsuite/gcc.target/i386/avx10_1-16.c deleted file mode 100644 index b3fdb3f..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-16.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx512f -mno-evex512" } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("avx10.1"))) __m512d -foo () -{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-17.c b/gcc/testsuite/gcc.target/i386/avx10_1-17.c deleted file mode 100644 index 09f1252..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-17.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx512f" } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("no-avx10.1-512"))) __m512d -foo () -{ /* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-18.c b/gcc/testsuite/gcc.target/i386/avx10_1-18.c deleted file mode 100644 index c1edce8..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-18.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("no-avx512f"))) __m512d -foo () -{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-19.c b/gcc/testsuite/gcc.target/i386/avx10_1-19.c deleted file mode 100644 index 25b5887..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-19.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mno-avx10.1-512" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("avx512f"))) __m512d -foo () -{ /* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-2.c b/gcc/testsuite/gcc.target/i386/avx10_1-2.c index 19962bc..bf1de23 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-2.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64 -mavx10.1" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler "%zmm" } } */ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-20.c b/gcc/testsuite/gcc.target/i386/avx10_1-20.c deleted file mode 100644 index a223065..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-20.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mno-avx512f" } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("avx10.1"))) __m512d -foo () -{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-21.c b/gcc/testsuite/gcc.target/i386/avx10_1-21.c deleted file mode 100644 index 2ae437e..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-21.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1-256 -mevex512 -Wno-psabi" } */ -/* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler-not "%zmm" } } */ - -#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-22.c b/gcc/testsuite/gcc.target/i386/avx10_1-22.c deleted file mode 100644 index df7bffb..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-22.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1-256 -Wno-psabi" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler-not "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("evex512"))) __m512d -foo () -{ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-23.c b/gcc/testsuite/gcc.target/i386/avx10_1-23.c deleted file mode 100644 index 1f84584..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-23.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mevex512 -Wno-psabi" } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler-not "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("avx10.1-256"))) __m512d -foo () -{ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-26.c b/gcc/testsuite/gcc.target/i386/avx10_1-26.c deleted file mode 100644 index d887404..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-26.c +++ /dev/null @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx512f" } */ -/* { dg-require-ifunc "" } */ - -#include <immintrin.h> -__attribute__((target_clones ("default","avx10.1"))) -__m512d foo(__m512d a, __m512d b) -{ - return a + b; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-3.c b/gcc/testsuite/gcc.target/i386/avx10_1-3.c index 992364a..3be988a 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-3.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-3.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=x86-64 -mavx10.1" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-4.c b/gcc/testsuite/gcc.target/i386/avx10_1-4.c index b3d2603..fbc92d5 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-4.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-4.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=x86-64 -mavx10.1" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-5.c b/gcc/testsuite/gcc.target/i386/avx10_1-5.c new file mode 100644 index 0000000..bada568 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-5.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx10.1 -mno-avx512f -Wno-psabi" } */ +/* { dg-final { scan-assembler-not "%zmm" } } */ + +#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-6.c b/gcc/testsuite/gcc.target/i386/avx10_1-6.c new file mode 100644 index 0000000..192d1d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-6.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx512f -mno-avx10.1" } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-7.c b/gcc/testsuite/gcc.target/i386/avx10_1-7.c index fb74ffb..d887404 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-7.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-7.c @@ -1,6 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ +/* { dg-options "-O2 -march=x86-64-v3 -mavx512f" } */ +/* { dg-require-ifunc "" } */ -#include "avx10_1-2.c" +#include <immintrin.h> +__attribute__((target_clones ("default","avx10.1"))) +__m512d foo(__m512d a, __m512d b) +{ + return a + b; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-8.c b/gcc/testsuite/gcc.target/i386/avx10_1-8.c deleted file mode 100644 index dbb7d64..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-8.c +++ /dev/null @@ -1,6 +0,0 @@ -/* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f -mno-evex512" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ - -#include "avx10_1-1.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-9.c b/gcc/testsuite/gcc.target/i386/avx10_1-9.c deleted file mode 100644 index b951738..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-9.c +++ /dev/null @@ -1,7 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f" } */ -/* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-1.c deleted file mode 100644 index f28be2a..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-1.c +++ /dev/null @@ -1,145 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64-v3 -mavx10.2 -O2" } */ -/* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vmaxbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vmaxbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vmaxbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vminbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vminbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vminbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vscalefbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vscalefbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vscalefbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfmadd132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfmadd132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfmadd231bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfmadd132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfmsub132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfmsub132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfmsub231bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfmsub132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfnmadd132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfnmadd132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfnmadd231bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfnmadd132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfnmsub132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfnmsub132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfnmsub231bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfnmsub132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vrsqrtbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vrsqrtbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vrsqrtbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vsqrtbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vsqrtbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vsqrtbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vgetexpbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vgetexpbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vgetexpbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vrndscalebf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vrndscalebf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vrndscalebf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vreducebf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vreducebf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vreducebf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vgetmantbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vgetmantbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vgetmantbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfpclassbf16z\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfpclassbf16z\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcmpbf16\[ \\t\]+\\\$1\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%k\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcmpbf16\[ \\t\]+\\\$2\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%k\[0-9\]\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ - -#include <immintrin.h> - -#define IMM 123 - -volatile __m512bh res, x1, x2; -volatile __mmask32 m32; - -void extern -avx10_2_test (void) -{ - res = _mm512_add_pbh (x1, x2); - res = _mm512_mask_add_pbh (res, m32, x1, x2); - res = _mm512_maskz_add_pbh (m32, x1, x2); - res = _mm512_sub_pbh (x1, x2); - res = _mm512_mask_sub_pbh (res, m32, x1, x2); - res = _mm512_maskz_sub_pbh (m32, x1, x2); - res = _mm512_mul_pbh (x1, x2); - res = _mm512_mask_mul_pbh (res, m32, x1, x2); - res = _mm512_maskz_mul_pbh (m32, x1, x2); - res = _mm512_div_pbh (x1, x2); - res = _mm512_mask_div_pbh (res, m32, x1, x2); - res = _mm512_maskz_div_pbh (m32, x1, x2); - res = _mm512_max_pbh (x1, x2); - res = _mm512_mask_max_pbh (res, m32, x1, x2); - res = _mm512_maskz_max_pbh (m32, x1, x2); - res = _mm512_min_pbh (x1, x2); - res = _mm512_mask_min_pbh (res, m32, x1, x2); - res = _mm512_maskz_min_pbh (m32, x1, x2); - res = _mm512_scalef_pbh (x1, x2); - res = _mm512_mask_scalef_pbh (res, m32, x1, x2); - res = _mm512_maskz_scalef_pbh (m32, x1, x2); - - res = _mm512_fmadd_pbh (res, x1, x2); - res = _mm512_mask_fmadd_pbh (res, m32, x1, x2); - res = _mm512_mask3_fmadd_pbh (res, x1, x2, m32); - res = _mm512_maskz_fmadd_pbh (m32,res, x1, x2); - res = _mm512_fmsub_pbh (res, x1, x2); - res = _mm512_mask_fmsub_pbh (res, m32, x1, x2); - res = _mm512_mask3_fmsub_pbh (res, x1, x2, m32); - res = _mm512_maskz_fmsub_pbh (m32,res, x1, x2); - res = _mm512_fnmadd_pbh (res, x1, x2); - res = _mm512_mask_fnmadd_pbh (res, m32, x1, x2); - res = _mm512_mask3_fnmadd_pbh (res, x1, x2, m32); - res = _mm512_maskz_fnmadd_pbh (m32,res, x1, x2); - res = _mm512_fnmsub_pbh (res, x1, x2); - res = _mm512_mask_fnmsub_pbh (res, m32, x1, x2); - res = _mm512_mask3_fnmsub_pbh (res, x1, x2, m32); - res = _mm512_maskz_fnmsub_pbh (m32,res, x1, x2); - - res = _mm512_rsqrt_pbh (x1); - res = _mm512_mask_rsqrt_pbh (res, m32, x1); - res = _mm512_maskz_rsqrt_pbh (m32, x1); - res = _mm512_sqrt_pbh (x1); - res = _mm512_mask_sqrt_pbh (res, m32, x1); - res = _mm512_maskz_sqrt_pbh (m32, x1); - res = _mm512_rcp_pbh (x1); - res = _mm512_mask_rcp_pbh (res, m32, x1); - res = _mm512_maskz_rcp_pbh (m32, x1); - res = _mm512_getexp_pbh (x1); - res = _mm512_mask_getexp_pbh (res, m32, x1); - res = _mm512_maskz_getexp_pbh (m32, x1); - - res = _mm512_roundscale_pbh (x1, IMM); - res = _mm512_mask_roundscale_pbh (res, m32, x1, IMM); - res = _mm512_maskz_roundscale_pbh (m32, x1, IMM); - res = _mm512_reduce_pbh (x1, IMM); - res = _mm512_mask_reduce_pbh (res, m32, x1, IMM); - res = _mm512_maskz_reduce_pbh (m32, x1, IMM); - res = _mm512_getmant_pbh (x1, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); - res = _mm512_mask_getmant_pbh (res, m32, x1, _MM_MANT_NORM_p75_1p5, - _MM_MANT_SIGN_src); - res = _mm512_maskz_getmant_pbh (m32, x1, _MM_MANT_NORM_p75_1p5, - _MM_MANT_SIGN_src); - - m32 = _mm512_fpclass_pbh_mask (x1, 13); - m32 = _mm512_mask_fpclass_pbh_mask (2, x1, 13); - - m32 = _mm512_cmp_pbh_mask (x1, x2, 1); - m32 = _mm512_mask_cmp_pbh_mask (m32, x1, x2, 2); -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-vector-cmp-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-vector-cmp-1.c deleted file mode 100644 index ff72698..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-vector-cmp-1.c +++ /dev/null @@ -1,19 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64-v3 -mavx10.2 -O2 -mprefer-vector-width=512" } */ -/* { dg-final { scan-assembler-times "vcmpbf16" 5 } } */ - -typedef __bf16 v32bf __attribute__ ((__vector_size__ (64))); - -#define VCMPMN(type, op, name) \ -type \ -__attribute__ ((noinline, noclone)) \ -vec_cmp_##type##type##name (type a, type b) \ -{ \ - return a op b; \ -} - -VCMPMN (v32bf, <, lt) -VCMPMN (v32bf, <=, le) -VCMPMN (v32bf, >, gt) -VCMPMN (v32bf, >=, ge) -VCMPMN (v32bf, ==, eq) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-vector-fma-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-vector-fma-1.c deleted file mode 100644 index cc9497c..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-vector-fma-1.c +++ /dev/null @@ -1,34 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64-v3 -mavx10.2 -O2" } */ -/* { dg-final { scan-assembler-times "vfmadd132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfmsub132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfnmadd132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vfnmsub132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ - -#include <immintrin.h> - -typedef __bf16 v32bf __attribute__ ((__vector_size__ (64))); - -v32bf -foo_madd (v32bf a, v32bf b, v32bf c) -{ - return a * b + c; -} - -v32bf -foo_msub (v32bf a, v32bf b, v32bf c) -{ - return a * b - c; -} - -v32bf -foo_nmadd (v32bf a, v32bf b, v32bf c) -{ - return -a * b + c; -} - -v32bf -foo_nmsub (v32bf a, v32bf b, v32bf c) -{ - return -a * b - c; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-vector-operations-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-vector-operations-1.c deleted file mode 100644 index 9ca2b95..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-vector-operations-1.c +++ /dev/null @@ -1,42 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64-v3 -mavx10.2 -O2" } */ -/* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ - -#include <immintrin.h> - -typedef __bf16 v32bf __attribute__ ((__vector_size__ (64))); - -v32bf -foo_mul (v32bf a, v32bf b) -{ - return a * b; -} - -v32bf -foo_add (v32bf a, v32bf b) -{ - return a + b; -} - -v32bf -foo_div (v32bf a, v32bf b) -{ - return a / b; -} - -v32bf -foo_sub (v32bf a, v32bf b) -{ - return a - b; -} - -__attribute__((optimize("fast-math"))) -v32bf -foo_div_fast_math (v32bf a, v32bf b) -{ - return a / b; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-vector-smaxmin-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-vector-smaxmin-1.c deleted file mode 100644 index ee2ac85..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-bf16-vector-smaxmin-1.c +++ /dev/null @@ -1,20 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64-v3 -mavx10.2 -mprefer-vector-width=512 -Ofast" } */ -/* { dg-final { scan-assembler-times "vmaxbf16" 1 } } */ -/* { dg-final { scan-assembler-times "vminbf16" 1 } } */ - -void -maxbf16_512 (__bf16* dest, __bf16* src1, __bf16* src2) -{ - int i; - for (i = 0; i < 32; i++) - dest[i] = src1[i] > src2[i] ? src1[i] : src2[i]; -} - -void -minbf16_512 (__bf16* dest, __bf16* src1, __bf16* src2) -{ - int i; - for (i = 0; i < 32; i++) - dest[i] = src1[i] < src2[i] ? src1[i] : src2[i]; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c deleted file mode 100644 index ff103d0..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c +++ /dev/null @@ -1,188 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64-v3 -mavx10.2 -O2" } */ -/* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvthf82ph\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvthf82ph\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvthf82ph\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2bf8\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2bf8\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2bf8\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2bf8s\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2bf8s\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2bf8s\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2hf8\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2hf8\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2hf8\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2hf8s\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2hf8s\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2hf8s\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpsllw\[ \t]\+\\\$8, %zmm\[0-9]\+, %zmm\[0-9]\+(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vpsllw\[ \t]\+\\\$8, %zmm\[0-9]\+, %zmm\[0-9]\+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpmovsxbw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%zmm\[0-9\](?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vpmovsxbw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ - -#include <immintrin.h> - -volatile __m256i x256i, z1; -volatile __m512i x512i; -volatile __m512 x, a1, b1; -volatile __m512h y, x512h, z; -volatile __mmask16 m16; -volatile __mmask32 m32; -volatile __mmask64 m64; -const void *a; -__m512bh *c; -__m512h *d; - -void extern -avx10_2_test (void) -{ - y = _mm512_cvtx2ps_ph (a1, b1); - y = _mm512_mask_cvtx2ps_ph (y, m32, a1, b1); - y = _mm512_maskz_cvtx2ps_ph (m32, a1, b1); - - y = _mm512_cvtx_round2ps_ph (a1, b1, 8); - y = _mm512_mask_cvtx_round2ps_ph (y, m32, a1, b1, 8); - y = _mm512_maskz_cvtx_round2ps_ph (m32, a1, b1, 8); -} - -void extern -avx10_2_vcvtbiasph2bf8_test (void) -{ - x256i = _mm512_cvtbiasph_bf8 (x512i, x512h); - x256i = _mm512_mask_cvtbiasph_bf8 (x256i, m32, x512i, x512h); - x256i = _mm512_maskz_cvtbiasph_bf8 (m32, x512i, x512h); -} - -void extern -avx10_2_vcvtbiasph2bf8s_test (void) -{ - x256i = _mm512_cvts_biasph_bf8 (x512i, x512h); - x256i = _mm512_mask_cvts_biasph_bf8 (x256i, m32, x512i, x512h); - x256i = _mm512_maskz_cvts_biasph_bf8 (m32, x512i, x512h); -} - -void extern -avx10_2_vcvtbiasph2hf8_test (void) -{ - x256i = _mm512_cvtbiasph_hf8 (x512i, x512h); - x256i = _mm512_mask_cvtbiasph_hf8 (x256i, m32, x512i, x512h); - x256i = _mm512_maskz_cvtbiasph_hf8 (m32, x512i, x512h); -} - -void extern -avx10_2_vcvtbiasph2hf8s_test (void) -{ - x256i = _mm512_cvts_biasph_hf8 (x512i, x512h); - x256i = _mm512_mask_cvts_biasph_hf8 (x256i, m32, x512i, x512h); - x256i = _mm512_maskz_cvts_biasph_hf8 (m32, x512i, x512h); -} - -void extern -avx10_2_vcvt2ph2bf8_test (void) -{ - x512i = _mm512_cvt2ph_bf8 (x512h, x512h); - x512i = _mm512_mask_cvt2ph_bf8 (x512i, m64, x512h, x512h); - x512i = _mm512_maskz_cvt2ph_bf8 (m64, x512h, x512h); -} - -void extern -avx10_2_vcvt2ph2bf8s_test (void) -{ - x512i = _mm512_cvts_2ph_bf8 (x512h, x512h); - x512i = _mm512_mask_cvts_2ph_bf8 (x512i, m64, x512h, x512h); - x512i = _mm512_maskz_cvts_2ph_bf8 (m64, x512h, x512h); -} - -void extern -avx10_2_vcvt2ph2hf8_test (void) -{ - x512i = _mm512_cvt2ph_hf8 (x512h, x512h); - x512i = _mm512_mask_cvt2ph_hf8 (x512i, m64, x512h, x512h); - x512i = _mm512_maskz_cvt2ph_hf8 (m64, x512h, x512h); -} - -void extern -avx10_2_vcvt2ph2hf8s_test (void) -{ - x512i = _mm512_cvts_2ph_hf8 (x512h, x512h); - x512i = _mm512_mask_cvts_2ph_hf8 (x512i, m64, x512h, x512h); - x512i = _mm512_maskz_cvts_2ph_hf8 (m64, x512h, x512h); -} - -void extern -avx10_2_vcvthf82ph_test (void) -{ - x512h = _mm512_cvthf8_ph (x256i); - x512h = _mm512_mask_cvthf8_ph (x512h, m32, x256i); - x512h = _mm512_maskz_cvthf8_ph (m32, x256i); -} - -void extern -avx10_2_vcvtph2bf8_test (void) -{ - x256i = _mm512_cvtph_bf8 (x512h); - x256i = _mm512_mask_cvtph_bf8 (x256i, m32, x512h); - x256i = _mm512_maskz_cvtph_bf8 (m32, x512h); -} - -void extern -avx10_2_vcvtph2bf8s_test (void) -{ - x256i = _mm512_cvts_ph_bf8 (x512h); - x256i = _mm512_mask_cvts_ph_bf8 (x256i, m32, x512h); - x256i = _mm512_maskz_cvts_ph_bf8 (m32, x512h); -} - -void extern -avx10_2_vcvtph2hf8_test (void) -{ - x256i = _mm512_cvtph_hf8 (x512h); - x256i = _mm512_mask_cvtph_hf8 (x256i, m32, x512h); - x256i = _mm512_maskz_cvtph_hf8 (m32, x512h); -} - -void extern -avx10_2_vcvtph2hf8s_test (void) -{ - x256i = _mm512_cvts_ph_hf8 (x512h); - x256i = _mm512_mask_cvts_ph_hf8 (x256i, m32, x512h); - x256i = _mm512_maskz_cvts_ph_hf8 (m32, x512h); -} - -void extern -avx10_2_cvtbf8_fp16_test (void) -{ - y = _mm512_cvtbf8_ph (z1); - y = _mm512_mask_cvtbf8_ph (z, m32, z1); - y = _mm512_maskz_cvtbf8_ph (m32, z1); -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-media-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-media-1.c deleted file mode 100644 index a0675f6..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-media-1.c +++ /dev/null @@ -1,112 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64-v3 -mavx10.2 -O2" } */ -/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpbuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vdpphps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vdpphps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vdpphps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vmpsadbw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vmpsadbw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vmpsadbw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ - - -#include <immintrin.h> - -volatile __m512 a; -volatile __m512h b,c; -volatile __m512i x,y,z,z1; -volatile __mmask16 m16; -volatile __mmask32 m32; - -void avx10_2_test (void) -{ - x = _mm512_dpbssd_epi32 (x, y, z); - x = _mm512_mask_dpbssd_epi32 (x, m16, y, z); - x = _mm512_maskz_dpbssd_epi32 (m16, x, y, z); - - x = _mm512_dpbssds_epi32 (x, y, z); - x = _mm512_mask_dpbssds_epi32 (x, m16, y, z); - x = _mm512_maskz_dpbssds_epi32 (m16, x, y, z); - - x = _mm512_dpbsud_epi32 (x, y, z); - x = _mm512_mask_dpbsud_epi32 (x, m16, y, z); - x = _mm512_maskz_dpbsud_epi32 (m16, x, y, z); - - x = _mm512_dpbsuds_epi32 (x, y, z); - x = _mm512_mask_dpbsuds_epi32 (x, m16, y, z); - x = _mm512_maskz_dpbsuds_epi32 (m16, x, y, z); - - x = _mm512_dpbuud_epi32 (x, y, z); - x = _mm512_mask_dpbuud_epi32 (x, m16, y, z); - x = _mm512_maskz_dpbuud_epi32 (m16, x, y, z); - - x = _mm512_dpbuuds_epi32 (x, y, z); - x = _mm512_mask_dpbuuds_epi32 (x, m16, y, z); - x = _mm512_maskz_dpbuuds_epi32 (m16, x, y, z); - - x = _mm512_dpwsud_epi32 (x, y, z); - x = _mm512_mask_dpwsud_epi32 (x, m16, y, z); - x = _mm512_maskz_dpwsud_epi32 (m16, x, y, z); - - x = _mm512_dpwsuds_epi32 (x, y, z); - x = _mm512_mask_dpwsuds_epi32 (x, m16, y, z); - x = _mm512_maskz_dpwsuds_epi32 (m16, x, y, z); - - x = _mm512_dpwusd_epi32 (x, y, z); - x = _mm512_mask_dpwusd_epi32 (x, m16, y, z); - x = _mm512_maskz_dpwusd_epi32 (m16, x, y, z); - - x = _mm512_dpwusds_epi32 (x, y, z); - x = _mm512_mask_dpwusds_epi32 (x, m16, y, z); - x = _mm512_maskz_dpwusds_epi32 (m16, x, y, z); - - x = _mm512_dpwuud_epi32 (x, y, z); - x = _mm512_mask_dpwuud_epi32 (x, m16, y, z); - x = _mm512_maskz_dpwuud_epi32 (m16, x, y, z); - - x = _mm512_dpwuuds_epi32 (x, y, z); - x = _mm512_mask_dpwuuds_epi32 (x, m16, y, z); - x = _mm512_maskz_dpwuuds_epi32 (m16, x, y, z); - - a = _mm512_dpph_ps (a, b, c); - a = _mm512_mask_dpph_ps (a, m16, b, c); - a = _mm512_maskz_dpph_ps (m16, a, b, c); - - x = _mm512_mpsadbw_epu8 (x, y, 1); - x = _mm512_mask_mpsadbw_epu8 (x, m32, y, z, 1); - x = _mm512_maskz_mpsadbw_epu8 (m32, x, y, 1); -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-minmax-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-minmax-1.c deleted file mode 100644 index fb9a92a..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-minmax-1.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-final { scan-assembler-times "vminmaxbf16\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vminmaxbf16\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vminmaxbf16\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vminmaxph\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vminmaxph\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vminmaxph\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vminmaxps\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vminmaxps\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vminmaxps\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vminmaxpd\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vminmaxpd\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vminmaxpd\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 2 } } */ - - -#include <immintrin.h> - -volatile __m512bh x1; -volatile __m512h x2; -volatile __m512 x3; -volatile __m512d x4; -volatile __mmask32 m32; -volatile __mmask16 m16; -volatile __mmask8 m8; - -void extern -avx10_2_test (void) -{ - x1 = _mm512_minmax_pbh (x1, x1, 100); - x1 = _mm512_mask_minmax_pbh (x1, m32, x1, x1, 100); - x1 = _mm512_maskz_minmax_pbh (m32, x1, x1, 100); - x2 = _mm512_minmax_ph (x2, x2, 1); - x2 = _mm512_mask_minmax_ph (x2, m32, x2, x2, 1); - x2 = _mm512_maskz_minmax_ph (m32, x2, x2, 1); - x2 = _mm512_minmax_round_ph (x2, x2, 1, 4); - x2 = _mm512_mask_minmax_round_ph (x2, m32, x2, x2, 1, 4); - x2 = _mm512_maskz_minmax_round_ph (m32, x2, x2, 1, 4); - x3 = _mm512_minmax_ps (x3, x3, 1); - x3 = _mm512_mask_minmax_ps (x3, m16, x3, x3, 1); - x3 = _mm512_maskz_minmax_ps (m16, x3, x3, 1); - x3 = _mm512_minmax_round_ps (x3, x3, 1, 4); - x3 = _mm512_mask_minmax_round_ps (x3, m16, x3, x3, 1, 4); - x3 = _mm512_maskz_minmax_round_ps (m16, x3, x3, 1, 4); - x4 = _mm512_minmax_pd (x4, x4, 100); - x4 = _mm512_mask_minmax_pd (x4, m8, x4, x4, 100); - x4 = _mm512_maskz_minmax_pd (m8, x4, x4, 100); - x4 = _mm512_minmax_round_pd (x4, x4, 100, 4); - x4 = _mm512_mask_minmax_round_pd (x4, m8, x4, x4, 100, 4); - x4 = _mm512_maskz_minmax_round_pd (m8, x4, x4, 100, 4); -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-movrs-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-movrs-1.c deleted file mode 100644 index 2aaa1a9..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-movrs-1.c +++ /dev/null @@ -1,40 +0,0 @@ -/* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-march=x86-64-v3 -mavx10.2 -mmovrs -O2" } */ -/* { dg-final { scan-assembler-times "vmovrsb\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+" 3 } } */ -/* { dg-final { scan-assembler-times "vmovrsb\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}" 2 } } */ -/* { dg-final { scan-assembler-times "vmovrsb\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}{z}" 1 } } */ -/* { dg-final { scan-assembler-times "vmovrsd\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+" 3 } } */ -/* { dg-final { scan-assembler-times "vmovrsd\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}" 2 } } */ -/* { dg-final { scan-assembler-times "vmovrsd\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}{z}" 1 } } */ -/* { dg-final { scan-assembler-times "vmovrsq\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+" 3 } } */ -/* { dg-final { scan-assembler-times "vmovrsq\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}" 2 } } */ -/* { dg-final { scan-assembler-times "vmovrsq\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}{z}" 1 } } */ -/* { dg-final { scan-assembler-times "vmovrsw\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+" 3 } } */ -/* { dg-final { scan-assembler-times "vmovrsw\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}" 2 } } */ -/* { dg-final { scan-assembler-times "vmovrsw\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}{z}" 1 } } */ - -#include <immintrin.h> - -__m512i *px; -volatile __m512i x; -volatile __mmask64 m1; -volatile __mmask16 m2; -volatile __mmask8 m3; -volatile __mmask32 m4; - -void extern -avx10_movrs_test (void) -{ - x = _mm512_loadrs_epi8(px); - x = _mm512_mask_loadrs_epi8(x, m1, px); - x = _mm512_maskz_loadrs_epi8(m1, px); - x = _mm512_loadrs_epi32(px); - x = _mm512_mask_loadrs_epi32(x, m2, px); - x = _mm512_maskz_loadrs_epi32(m2, px); - x = _mm512_loadrs_epi64(px); - x = _mm512_mask_loadrs_epi64(x, m3, px); - x = _mm512_maskz_loadrs_epi64(m3, px); - x = _mm512_loadrs_epi16(px); - x = _mm512_mask_loadrs_epi16(x, m4, px); - x = _mm512_maskz_loadrs_epi16(m4, px); -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-satcvt-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-satcvt-1.c deleted file mode 100644 index 74a515b..0000000 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-satcvt-1.c +++ /dev/null @@ -1,247 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-final { scan-assembler-times "vcvtph2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vcvtph2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2ibs\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2ibs\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vcvtph2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2iubs\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtph2iubs\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttph2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vcvttph2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttph2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttph2ibs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttph2ibs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttph2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vcvttph2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttph2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttph2iubs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttph2iubs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtps2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vcvtps2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtps2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtps2ibs\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtps2ibs\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtps2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vcvtps2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtps2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtps2iubs\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtps2iubs\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vcvttps2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2ibs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2ibs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ -/* { dg-final { scan-assembler-times "vcvttps2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2iubs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2iubs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbf162ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbf162ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbf162ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbf162iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbf162iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtbf162iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttbf162ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttbf162ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttbf162ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttbf162iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttbf162iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttbf162iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2dqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2dqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2dqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2dqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2dqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2dqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2qqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2qqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2qqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2qqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2qqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2qqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2udqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2udqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2udqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2udqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2udqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2udqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2uqqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2uqqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2uqqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2uqqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2uqqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttpd2uqqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2dqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2dqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2dqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2dqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2dqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2dqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2qqs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2qqs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2qqs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2qqs\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2qqs\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2qqs\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2udqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2udqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2udqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2udqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2udqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2udqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2uqqs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2uqqs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2uqqs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2uqqs\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2uqqs\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttps2uqqs\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ - -#include <immintrin.h> - -volatile __m256 hx; -volatile __m256i hxi; -volatile __m512 x; -volatile __m512h xh; -volatile __m512i xi; -volatile __m512d xd; -volatile __m512bh xbh; -volatile __mmask8 m8; -volatile __mmask16 m16; -volatile __mmask32 m32; - -void extern -avx10_2_test (void) -{ - xi = _mm512_ipcvts_ph_epi8 (xh); - xi = _mm512_mask_ipcvts_ph_epi8 (xi, m32, xh); - xi = _mm512_maskz_ipcvts_ph_epi8 (m32, xh); - xi = _mm512_ipcvts_roundph_epi8 (xh, 4); - xi = _mm512_mask_ipcvts_roundph_epi8 (xi, m32, xh, 8); - xi = _mm512_maskz_ipcvts_roundph_epi8 (m32, xh, 11); - - xi = _mm512_ipcvts_ph_epu8 (xh); - xi = _mm512_mask_ipcvts_ph_epu8 (xi, m32, xh); - xi = _mm512_maskz_ipcvts_ph_epu8 (m32, xh); - xi = _mm512_ipcvts_roundph_epu8 (xh, 4); - xi = _mm512_mask_ipcvts_roundph_epu8 (xi, m32, xh, 8); - xi = _mm512_maskz_ipcvts_roundph_epu8 (m32, xh, 11); - - xi = _mm512_ipcvtts_ph_epi8 (xh); - xi = _mm512_mask_ipcvtts_ph_epi8 (xi, m32, xh); - xi = _mm512_maskz_ipcvtts_ph_epi8 (m32, xh); - xi = _mm512_ipcvtts_roundph_epi8 (xh, 4); - xi = _mm512_mask_ipcvtts_roundph_epi8 (xi, m32, xh, 8); - xi = _mm512_maskz_ipcvtts_roundph_epi8 (m32, xh, 8); - - xi = _mm512_ipcvtts_ph_epu8 (xh); - xi = _mm512_mask_ipcvtts_ph_epu8 (xi, m32, xh); - xi = _mm512_maskz_ipcvtts_ph_epu8 (m32, xh); - xi = _mm512_ipcvtts_roundph_epu8 (xh, 4); - xi = _mm512_mask_ipcvtts_roundph_epu8 (xi, m32, xh, 8); - xi = _mm512_maskz_ipcvtts_roundph_epu8 (m32, xh, 8); - - xi = _mm512_ipcvts_ps_epi8 (x); - xi = _mm512_mask_ipcvts_ps_epi8 (xi, m16, x); - xi = _mm512_maskz_ipcvts_ps_epi8 (m16, x); - xi = _mm512_ipcvts_roundps_epi8 (x, 4); - xi = _mm512_mask_ipcvts_roundps_epi8 (xi, m16, x, 8); - xi = _mm512_maskz_ipcvts_roundps_epi8 (m16, x, 11); - - xi = _mm512_ipcvts_ps_epu8 (x); - xi = _mm512_mask_ipcvts_ps_epu8 (xi, m16, x); - xi = _mm512_maskz_ipcvts_ps_epu8 (m16, x); - xi = _mm512_ipcvts_roundps_epu8 (x, 4); - xi = _mm512_mask_ipcvts_roundps_epu8 (xi, m16, x, 8); - xi = _mm512_maskz_ipcvts_roundps_epu8 (m16, x, 11); - - xi = _mm512_ipcvtts_ps_epi8 (x); - xi = _mm512_mask_ipcvtts_ps_epi8 (xi, m16, x); - xi = _mm512_maskz_ipcvtts_ps_epi8 (m16, x); - xi = _mm512_ipcvtts_roundps_epi8 (x, 4); - xi = _mm512_mask_ipcvtts_roundps_epi8 (xi, m16, x, 8); - xi = _mm512_maskz_ipcvtts_roundps_epi8 (m16, x, 8); - - xi = _mm512_ipcvtts_ps_epu8 (x); - xi = _mm512_mask_ipcvtts_ps_epu8 (xi, m16, x); - xi = _mm512_maskz_ipcvtts_ps_epu8 (m16, x); - xi = _mm512_ipcvtts_roundps_epu8 (x, 4); - xi = _mm512_mask_ipcvtts_roundps_epu8 (xi, m16, x, 8); - xi = _mm512_maskz_ipcvtts_roundps_epu8 (m16, x, 8); - - xi = _mm512_ipcvts_bf16_epi8 (xbh); - xi = _mm512_mask_ipcvts_bf16_epi8 (xi, m32, xbh); - xi = _mm512_maskz_ipcvts_bf16_epi8 (m32, xbh); - - xi = _mm512_ipcvts_bf16_epu8 (xbh); - xi = _mm512_mask_ipcvts_bf16_epu8 (xi, m32, xbh); - xi = _mm512_maskz_ipcvts_bf16_epu8 (m32, xbh); - - xi = _mm512_ipcvtts_bf16_epi8 (xbh); - xi = _mm512_mask_ipcvtts_bf16_epi8 (xi, m32, xbh); - xi = _mm512_maskz_ipcvtts_bf16_epi8 (m32, xbh); - - xi = _mm512_ipcvtts_bf16_epu8 (xbh); - xi = _mm512_mask_ipcvtts_bf16_epu8 (xi, m32, xbh); - xi = _mm512_maskz_ipcvtts_bf16_epu8 (m32, xbh); - - hxi = _mm512_cvtts_pd_epi32 (xd); - hxi = _mm512_mask_cvtts_pd_epi32 (hxi, m8, xd); - hxi = _mm512_maskz_cvtts_pd_epi32 (m8, xd); - hxi = _mm512_cvtts_roundpd_epi32 (xd, 8); - hxi = _mm512_mask_cvtts_roundpd_epi32 (hxi, m8, xd, 8); - hxi = _mm512_maskz_cvtts_roundpd_epi32 (m8, xd, 8); - - xi = _mm512_cvtts_pd_epi64 (xd); - xi = _mm512_mask_cvtts_pd_epi64 (xi, m8, xd); - xi = _mm512_maskz_cvtts_pd_epi64 (m8, xd); - xi = _mm512_cvtts_roundpd_epi64 (xd, 8); - xi = _mm512_mask_cvtts_roundpd_epi64 (xi, m8, xd, 8); - xi = _mm512_maskz_cvtts_roundpd_epi64 (m8, xd, 8); - - hxi = _mm512_cvtts_pd_epu32 (xd); - hxi = _mm512_mask_cvtts_pd_epu32 (hxi, m8, xd); - hxi = _mm512_maskz_cvtts_pd_epu32 (m8, xd); - hxi = _mm512_cvtts_roundpd_epu32 (xd, 8); - hxi = _mm512_mask_cvtts_roundpd_epu32 (hxi, m8, xd, 8); - hxi = _mm512_maskz_cvtts_roundpd_epu32 (m8, xd, 8); - - xi = _mm512_cvtts_pd_epu64 (xd); - xi = _mm512_mask_cvtts_pd_epu64 (xi, m8, xd); - xi = _mm512_maskz_cvtts_pd_epu64 (m8, xd); - xi = _mm512_cvtts_roundpd_epu64 (xd, 8); - xi = _mm512_mask_cvtts_roundpd_epu64 (xi, m8, xd, 8); - xi = _mm512_maskz_cvtts_roundpd_epu64 (m8, xd, 8); - - xi = _mm512_cvtts_ps_epi32 (x); - xi = _mm512_mask_cvtts_ps_epi32 (xi, m16, x); - xi = _mm512_maskz_cvtts_ps_epi32 (m16, x); - xi = _mm512_cvtts_roundps_epi32 (x, 8); - xi = _mm512_mask_cvtts_roundps_epi32 (xi, m16, x, 8); - xi = _mm512_maskz_cvtts_roundps_epi32 (m16, x, 8); - - xi = _mm512_cvtts_ps_epi64 (hx); - xi = _mm512_mask_cvtts_ps_epi64 (xi, m8, hx); - xi = _mm512_maskz_cvtts_ps_epi64 (m8, hx); - xi = _mm512_cvtts_roundps_epi64 (hx, 8); - xi = _mm512_mask_cvtts_roundps_epi64 (xi, m8, hx, 8); - xi = _mm512_maskz_cvtts_roundps_epi64 (m8, hx, 8); - - xi = _mm512_cvtts_ps_epu32 (x); - xi = _mm512_mask_cvtts_ps_epu32 (xi, m16, x); - xi = _mm512_maskz_cvtts_ps_epu32 (m16, x); - xi = _mm512_cvtts_roundps_epu32 (x, 8); - xi = _mm512_mask_cvtts_roundps_epu32 (xi, m16, x, 8); - xi = _mm512_maskz_cvtts_roundps_epu32 (m16, x, 8); - - xi = _mm512_cvtts_ps_epu64 (hx); - xi = _mm512_mask_cvtts_ps_epu64 (xi, m8, hx); - xi = _mm512_maskz_cvtts_ps_epu64 (m8, hx); - xi = _mm512_cvtts_roundps_epu64 (hx, 8); - xi = _mm512_mask_cvtts_roundps_epu64 (xi, m8, hx, 8); - xi = _mm512_maskz_cvtts_roundps_epu64 (m8, hx, 8); -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-bf16-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-bf16-1.c index 9b33b91..f5a29bf 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-bf16-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-bf16-1.c @@ -1,47 +1,72 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64-v3 -mavx10.2 -O2" } */ +/* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmaxbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmaxbf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmaxbf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmaxbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmaxbf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmaxbf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vminbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vminbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vminbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminbf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminbf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminbf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminbf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefbf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vscalefbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vscalefbf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vscalefbf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vscalefbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vscalefbf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vscalefbf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd231bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfmadd132bf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfmadd132bf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfmadd231bf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ @@ -50,6 +75,10 @@ /* { dg-final { scan-assembler-times "vfmadd132bf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfmadd231bf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfmadd132bf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsub132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsub132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsub231bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsub132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfmsub132bf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfmsub132bf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfmsub231bf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ @@ -58,6 +87,10 @@ /* { dg-final { scan-assembler-times "vfmsub132bf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfmsub231bf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfmsub132bf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfnmadd132bf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfnmadd132bf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfnmadd231bf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ @@ -66,6 +99,10 @@ /* { dg-final { scan-assembler-times "vfnmadd132bf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfnmadd231bf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfnmadd132bf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132bf16\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfnmsub132bf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfnmsub132bf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfnmsub231bf16\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ @@ -74,52 +111,77 @@ /* { dg-final { scan-assembler-times "vfnmsub132bf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfnmsub231bf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfnmsub132bf16\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrsqrtbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrsqrtbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrsqrtbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrsqrtbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrsqrtbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrsqrtbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrsqrtbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrsqrtbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrsqrtbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsqrtbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsqrtbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsqrtbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vsqrtbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vsqrtbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vsqrtbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vsqrtbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vsqrtbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vsqrtbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetexpbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetexpbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetexpbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetexpbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetexpbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetexpbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscalebf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscalebf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscalebf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrndscalebf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrndscalebf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrndscalebf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrndscalebf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrndscalebf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrndscalebf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreducebf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreducebf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreducebf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vreducebf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vreducebf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vreducebf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vreducebf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vreducebf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vreducebf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetmantbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetmantbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetmantbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetmantbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetmantbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetmantbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfpclassbf16z\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfpclassbf16z\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfpclassbf16y\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfpclassbf16y\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfpclassbf16x\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfpclassbf16x\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcmpbf16\[ \\t\]+\\\$1\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%k\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcmpbf16\[ \\t\]+\\\$2\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%k\[0-9\]\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcmpbf16\[ \\t\]+\\\$1\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%k\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcmpbf16\[ \\t\]+\\\$2\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%k\[0-9\]\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcmpbf16\[ \\t\]+\\\$1\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%k\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ @@ -128,14 +190,19 @@ #include <immintrin.h> #define IMM 123 +volatile __m512bh res2, x5, x6; volatile __m256bh res, x1, x2; volatile __m128bh res1, x3, x4; +volatile __mmask32 m32; volatile __mmask16 m16; volatile __mmask8 m8; void extern avx10_2_test (void) { + res2 = _mm512_add_pbh (x5, x6); + res2 = _mm512_mask_add_pbh (res2, m32, x5, x6); + res2 = _mm512_maskz_add_pbh (m32, x5, x6); res = _mm256_add_pbh (x1, x2); res = _mm256_mask_add_pbh (res, m16, x1, x2); res = _mm256_maskz_add_pbh (m16, x1, x2); @@ -143,6 +210,9 @@ avx10_2_test (void) res1 = _mm_mask_add_pbh (res1, m8, x3, x4); res1 = _mm_maskz_add_pbh (m8, x3, x4); + res2 = _mm512_sub_pbh (x5, x6); + res2 = _mm512_mask_sub_pbh (res2, m32, x5, x6); + res2 = _mm512_maskz_sub_pbh (m32, x5, x6); res = _mm256_sub_pbh (x1, x2); res = _mm256_mask_sub_pbh (res, m16, x1, x2); res = _mm256_maskz_sub_pbh (m16, x1, x2); @@ -150,6 +220,9 @@ avx10_2_test (void) res1 = _mm_mask_sub_pbh (res1, m8, x3, x4); res1 = _mm_maskz_sub_pbh (m8, x3, x4); + res2 = _mm512_mul_pbh (x5, x6); + res2 = _mm512_mask_mul_pbh (res2, m32, x5, x6); + res2 = _mm512_maskz_mul_pbh (m32, x5, x6); res = _mm256_mul_pbh (x1, x2); res = _mm256_mask_mul_pbh (res, m16, x1, x2); res = _mm256_maskz_mul_pbh (m16, x1, x2); @@ -157,6 +230,9 @@ avx10_2_test (void) res1 = _mm_mask_mul_pbh (res1, m8, x3, x4); res1 = _mm_maskz_mul_pbh (m8, x3, x4); + res2 = _mm512_div_pbh (x5, x6); + res2 = _mm512_mask_div_pbh (res2, m32, x5, x6); + res2 = _mm512_maskz_div_pbh (m32, x5, x6); res = _mm256_div_pbh (x1, x2); res = _mm256_mask_div_pbh (res, m16, x1, x2); res = _mm256_maskz_div_pbh (m16, x1, x2); @@ -164,6 +240,9 @@ avx10_2_test (void) res1 = _mm_mask_div_pbh (res1, m8, x3, x4); res1 = _mm_maskz_div_pbh (m8, x3, x4); + res2 = _mm512_max_pbh (x5, x6); + res2 = _mm512_mask_max_pbh (res2, m32, x5, x6); + res2 = _mm512_maskz_max_pbh (m32, x5, x6); res = _mm256_max_pbh (x1, x2); res = _mm256_mask_max_pbh (res, m16, x1, x2); res = _mm256_maskz_max_pbh (m16, x1, x2); @@ -171,6 +250,9 @@ avx10_2_test (void) res1 = _mm_mask_max_pbh (res1, m8, x3, x4); res1 = _mm_maskz_max_pbh (m8, x3, x4); + res2 = _mm512_min_pbh (x5, x6); + res2 = _mm512_mask_min_pbh (res2, m32, x5, x6); + res2 = _mm512_maskz_min_pbh (m32, x5, x6); res = _mm256_min_pbh (x1, x2); res = _mm256_mask_min_pbh (res, m16, x1, x2); res = _mm256_maskz_min_pbh (m16, x1, x2); @@ -178,6 +260,9 @@ avx10_2_test (void) res1 = _mm_mask_min_pbh (res1, m8, x3, x4); res1 = _mm_maskz_min_pbh (m8, x3, x4); + res2 = _mm512_scalef_pbh (x5, x6); + res2 = _mm512_mask_scalef_pbh (res2, m32, x5, x6); + res2 = _mm512_maskz_scalef_pbh (m32, x5, x6); res = _mm256_scalef_pbh (x1, x2); res = _mm256_mask_scalef_pbh (res, m16, x1, x2); res = _mm256_maskz_scalef_pbh (m16, x1, x2); @@ -185,6 +270,10 @@ avx10_2_test (void) res1 = _mm_mask_scalef_pbh (res1, m8, x3, x4); res1 = _mm_maskz_scalef_pbh (m8, x3, x4); + res2 = _mm512_fmadd_pbh (res2, x5, x6); + res2 = _mm512_mask_fmadd_pbh (res2, m32, x5, x6); + res2 = _mm512_mask3_fmadd_pbh (res2, x5, x6, m32); + res2 = _mm512_maskz_fmadd_pbh (m32, res2, x5, x6); res = _mm256_fmadd_pbh (res, x1, x2); res = _mm256_mask_fmadd_pbh (res, m16, x1, x2); res = _mm256_mask3_fmadd_pbh (res, x1, x2, m16); @@ -194,6 +283,10 @@ avx10_2_test (void) res1 = _mm_mask3_fmadd_pbh (res1, x3, x4, m8); res1 = _mm_maskz_fmadd_pbh (m8,res1, x3, x4); + res2 = _mm512_fmsub_pbh (res2, x5, x6); + res2 = _mm512_mask_fmsub_pbh (res2, m32, x5, x6); + res2 = _mm512_mask3_fmsub_pbh (res2, x5, x6, m32); + res2 = _mm512_maskz_fmsub_pbh (m32,res2, x5, x6); res = _mm256_fmsub_pbh (res, x1, x2); res = _mm256_mask_fmsub_pbh (res, m16, x1, x2); res = _mm256_mask3_fmsub_pbh (res, x1, x2, m16); @@ -203,6 +296,10 @@ avx10_2_test (void) res1 = _mm_mask3_fmsub_pbh (res1, x3, x4, m8); res1 = _mm_maskz_fmsub_pbh (m8,res1, x3, x4); + res2 = _mm512_fnmadd_pbh (res2, x5, x6); + res2 = _mm512_mask_fnmadd_pbh (res2, m32, x5, x6); + res2 = _mm512_mask3_fnmadd_pbh (res2, x5, x6, m32); + res2 = _mm512_maskz_fnmadd_pbh (m32,res2, x5, x6); res = _mm256_fnmadd_pbh (res, x1, x2); res = _mm256_mask_fnmadd_pbh (res, m16, x1, x2); res = _mm256_mask3_fnmadd_pbh (res, x1, x2, m16); @@ -212,6 +309,10 @@ avx10_2_test (void) res1 = _mm_mask3_fnmadd_pbh (res1, x3, x4, m8); res1 = _mm_maskz_fnmadd_pbh (m8,res1, x3, x4); + res2 = _mm512_fnmsub_pbh (res2, x5, x6); + res2 = _mm512_mask_fnmsub_pbh (res2, m32, x5, x6); + res2 = _mm512_mask3_fnmsub_pbh (res2, x5, x6, m32); + res2 = _mm512_maskz_fnmsub_pbh (m32,res2, x5, x6); res = _mm256_fnmsub_pbh (res, x1, x2); res = _mm256_mask_fnmsub_pbh (res, m16, x1, x2); res = _mm256_mask3_fnmsub_pbh (res, x1, x2, m16); @@ -221,48 +322,71 @@ avx10_2_test (void) res1 = _mm_mask3_fnmsub_pbh (res1, x3, x4, m8); res1 = _mm_maskz_fnmsub_pbh (m8,res1, x3, x4); + res2 = _mm512_rsqrt_pbh (x5); + res2 = _mm512_mask_rsqrt_pbh (res2, m32, x5); + res2 = _mm512_maskz_rsqrt_pbh (m32, x5); res = _mm256_rsqrt_pbh (x1); res = _mm256_mask_rsqrt_pbh (res, m16, x1); res = _mm256_maskz_rsqrt_pbh (m16, x1); res1 = _mm_rsqrt_pbh (x3); res1 = _mm_mask_rsqrt_pbh (res1, m8, x3); res1 = _mm_maskz_rsqrt_pbh (m8, x3); - + + res2 = _mm512_sqrt_pbh (x5); + res2 = _mm512_mask_sqrt_pbh (res2, m32, x5); + res2 = _mm512_maskz_sqrt_pbh (m32, x5); res = _mm256_sqrt_pbh (x1); res = _mm256_mask_sqrt_pbh (res, m16, x1); res = _mm256_maskz_sqrt_pbh (m16, x1); res1 = _mm_sqrt_pbh (x3); res1 = _mm_mask_sqrt_pbh (res1, m8, x3); res1 = _mm_maskz_sqrt_pbh (m8, x3); - + + res2 = _mm512_rcp_pbh (x5); + res2 = _mm512_mask_rcp_pbh (res2, m32, x5); + res2 = _mm512_maskz_rcp_pbh (m32, x5); res = _mm256_rcp_pbh (x1); res = _mm256_mask_rcp_pbh (res, m16, x1); res = _mm256_maskz_rcp_pbh (m16, x1); res1 = _mm_rcp_pbh (x3); res1 = _mm_mask_rcp_pbh (res1, m8, x3); res1 = _mm_maskz_rcp_pbh (m8, x3); - + + res2 = _mm512_getexp_pbh (x5); + res2 = _mm512_mask_getexp_pbh (res2, m32, x5); + res2 = _mm512_maskz_getexp_pbh (m32, x5); res = _mm256_getexp_pbh (x1); res = _mm256_mask_getexp_pbh (res, m16, x1); res = _mm256_maskz_getexp_pbh (m16, x1); res1 = _mm_getexp_pbh (x3); res1 = _mm_mask_getexp_pbh (res1, m8, x3); res1 = _mm_maskz_getexp_pbh (m8, x3); - + + res2 = _mm512_roundscale_pbh (x5, IMM); + res2 = _mm512_mask_roundscale_pbh (res2, m32, x5, IMM); + res2 = _mm512_maskz_roundscale_pbh (m32, x5, IMM); res = _mm256_roundscale_pbh (x1, IMM); res = _mm256_mask_roundscale_pbh (res, m16, x1, IMM); res = _mm256_maskz_roundscale_pbh (m16, x1, IMM); res1 = _mm_roundscale_pbh (x3, IMM); res1 = _mm_mask_roundscale_pbh (res1, m8, x3, IMM); res1 = _mm_maskz_roundscale_pbh (m8, x3, IMM); - + + res2 = _mm512_reduce_pbh (x5, IMM); + res2 = _mm512_mask_reduce_pbh (res2, m32, x5, IMM); + res2 = _mm512_maskz_reduce_pbh (m32, x5, IMM); res = _mm256_reduce_pbh (x1, IMM); res = _mm256_mask_reduce_pbh (res, m16, x1, IMM); res = _mm256_maskz_reduce_pbh (m16, x1, IMM); res1 = _mm_reduce_pbh (x3, IMM); res1 = _mm_mask_reduce_pbh (res1, m8, x3, IMM); res1 = _mm_maskz_reduce_pbh (m8, x3, IMM); - + + res2 = _mm512_getmant_pbh (x5, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); + res2 = _mm512_mask_getmant_pbh (res2, m32, x5, _MM_MANT_NORM_p75_1p5, + _MM_MANT_SIGN_src); + res2 = _mm512_maskz_getmant_pbh (m32, x5, _MM_MANT_NORM_p75_1p5, + _MM_MANT_SIGN_src); res = _mm256_getmant_pbh (x1, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); res = _mm256_mask_getmant_pbh (res, m16, x1, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); @@ -274,11 +398,15 @@ avx10_2_test (void) res1 = _mm_maskz_getmant_pbh (m8, x3, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); + m32 = _mm512_fpclass_pbh_mask (x5, 13); + m32 = _mm512_mask_fpclass_pbh_mask (2, x5, 13); m16 = _mm256_fpclass_pbh_mask (x1, 13); m16 = _mm256_mask_fpclass_pbh_mask (2, x1, 13); m8 = _mm_fpclass_pbh_mask (x3, 13); m8 = _mm_mask_fpclass_pbh_mask (2, x3, 13); - + + m32 = _mm512_cmp_pbh_mask (x5, x6, 1); + m32 = _mm512_mask_cmp_pbh_mask (m32, x5, x6, 2); m16 = _mm256_cmp_pbh_mask (x1, x2, 1); m16 = _mm256_mask_cmp_pbh_mask (m16, x1, x2, 2); m8 = _mm_cmp_pbh_mask (x3, x4, 1); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-cmp-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-cmp-1.c index 79bddb5..652929c 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-cmp-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-cmp-1.c @@ -1,7 +1,8 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64-v3 -mavx10.2 -O2" } */ -/* { dg-final { scan-assembler-times "vcmpbf16" 10 } } */ +/* { dg-final { scan-assembler-times "vcmpbf16" 15 } } */ +typedef __bf16 v32bf __attribute__ ((__vector_size__ (64))); typedef __bf16 v16bf __attribute__ ((__vector_size__ (32))); typedef __bf16 v8bf __attribute__ ((__vector_size__ (16))); @@ -13,17 +14,22 @@ vec_cmp_##type##type##name (type a, type b) \ return a op b; \ } +VCMPMN (v32bf, <, lt) VCMPMN (v16bf, <, lt) VCMPMN (v8bf, <, lt) +VCMPMN (v32bf, <=, le) VCMPMN (v16bf, <=, le) VCMPMN (v8bf, <=, le) +VCMPMN (v32bf, >, gt) VCMPMN (v16bf, >, gt) VCMPMN (v8bf, >, gt) +VCMPMN (v32bf, >=, ge) VCMPMN (v16bf, >=, ge) VCMPMN (v8bf, >=, ge) +VCMPMN (v32bf, ==, eq) VCMPMN (v16bf, ==, eq) VCMPMN (v8bf, ==, eq) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-fma-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-fma-1.c index 05f86f7..95457ee 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-fma-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-fma-1.c @@ -1,5 +1,9 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64-v3 -mavx10.2 -O2" } */ +/* { dg-final { scan-assembler-times "vfmadd132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsub132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132bf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfmadd132bf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfmsub132bf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfnmadd132bf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ @@ -11,9 +15,34 @@ #include <immintrin.h> +typedef __bf16 v32bf __attribute__ ((__vector_size__ (64))); typedef __bf16 v16bf __attribute__ ((__vector_size__ (32))); typedef __bf16 v8bf __attribute__ ((__vector_size__ (16))); +v32bf +foo_madd (v32bf a, v32bf b, v32bf c) +{ + return a * b + c; +} + +v32bf +foo_msub (v32bf a, v32bf b, v32bf c) +{ + return a * b - c; +} + +v32bf +foo_nmadd (v32bf a, v32bf b, v32bf c) +{ + return -a * b + c; +} + +v32bf +foo_nmsub (v32bf a, v32bf b, v32bf c) +{ + return -a * b - c; +} + v16bf foo_madd_256 (v16bf a, v16bf b, v16bf c) { diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-operations-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-operations-1.c index 530167b..0b96577 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-operations-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-operations-1.c @@ -1,5 +1,9 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64-v3 -mavx10.2 -O2" } */ +/* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmulbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ /* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ @@ -8,14 +12,47 @@ /* { dg-final { scan-assembler-times "vaddbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vdivbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vsubbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrcpbf16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ #include <immintrin.h> +typedef __bf16 v32bf __attribute__ ((__vector_size__ (64))); typedef __bf16 v16bf __attribute__ ((__vector_size__ (32))); typedef __bf16 v8bf __attribute__ ((__vector_size__ (16))); +v32bf +foo_mul (v32bf a, v32bf b) +{ + return a * b; +} + +v32bf +foo_add (v32bf a, v32bf b) +{ + return a + b; +} + +v32bf +foo_div (v32bf a, v32bf b) +{ + return a / b; +} + +v32bf +foo_sub (v32bf a, v32bf b) +{ + return a - b; +} + +__attribute__((optimize("fast-math"))) +v32bf +foo_div_fast_math (v32bf a, v32bf b) +{ + return a / b; +} + v16bf foo_mul_256 (v16bf a, v16bf b) { diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-smaxmin-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-smaxmin-1.c index 703ea64..a61c071 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-smaxmin-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-bf16-vector-smaxmin-1.c @@ -1,7 +1,23 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64-v3 -mavx10.2 -Ofast" } */ -/* { dg-final { scan-assembler-times "vmaxbf16" 2 } } */ -/* { dg-final { scan-assembler-times "vminbf16" 2 } } */ +/* { dg-final { scan-assembler-times "vmaxbf16" 3 } } */ +/* { dg-final { scan-assembler-times "vminbf16" 3 } } */ + +void +maxbf16_512 (__bf16* dest, __bf16* src1, __bf16* src2) +{ + int i; + for (i = 0; i < 32; i++) + dest[i] = src1[i] > src2[i] ? src1[i] : src2[i]; +} + +void +minbf16_512 (__bf16* dest, __bf16* src1, __bf16* src2) +{ + int i; + for (i = 0; i < 32; i++) + dest[i] = src1[i] < src2[i] ? src1[i] : src2[i]; +} void maxbf16_256 (__bf16* dest, __bf16* src1, __bf16* src2) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-comibf-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-comibf-1.c index 3862f1e..532a9a0 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-comibf-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-comibf-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=x86-64-v3 -mavx10.2 -O2 -fno-trapping-math" } */ +/* { dg-options "-march=x86-64-v3 -mavx10.2 -O2 -fno-trapping-math -fno-shrink-wrap" } */ /* { dg-final { scan-assembler-times "vcomisbf16\[ \\t\]+\[^{}\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 6 } } */ /* { dg-final { scan-assembler-times {j[a-z]+\s} 6 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-convert-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-convert-1.c index 3d5e921..c5a2d6f 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-convert-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-convert-1.c @@ -6,84 +6,129 @@ /* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ps2phx\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2bf8\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2bf8\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2bf8\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2bf8\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2bf8\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2bf8\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2hf8\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2hf8\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2hf8\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2hf8\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2hf8\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2hf8\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvthf82ph\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvthf82ph\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvthf82ph\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvthf82ph\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvthf82ph\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvthf82ph\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvthf82ph\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvthf82ph\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvthf82ph\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2bf8x\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2bf8x\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2bf8x\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2bf8y\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2bf8y\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2bf8y\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2bf8\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2bf8\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2bf8\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2bf8sx\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2bf8sx\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2bf8sx\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2bf8sy\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2bf8sy\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2bf8sy\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2bf8s\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2bf8s\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2bf8s\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2hf8x\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2hf8x\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2hf8x\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2hf8y\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2hf8y\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2hf8y\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2hf8\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2hf8\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2hf8\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2hf8sx\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2hf8sx\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2hf8sx\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2hf8sy\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2hf8sy\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2hf8sy\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2hf8s\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2hf8s\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2hf8s\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpmovsxbw\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%ymm\[0-9\](?:\n|\[ \\t\]+#)" 2 } } */ /* { dg-final { scan-assembler-times "vpsllw\[ \t]\+\\\$8, %ymm\[0-9]\+, %ymm\[0-9]\+(?:\n|\[ \\t\]+#)" 2 } } */ /* { dg-final { scan-assembler-times "vpsllw\[ \t]\+\\\$8, %ymm\[0-9]\+, %ymm\[0-9]\+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ @@ -92,23 +137,26 @@ /* { dg-final { scan-assembler-times "vpsllw\[ \t]\+\\\$8, %xmm\[0-9]\+, %xmm\[0-9]\+(?:\n|\[ \\t\]+#)" 2 } } */ /* { dg-final { scan-assembler-times "vpsllw\[ \t]\+\\\$8, %xmm\[0-9]\+, %xmm\[0-9]\+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpmovsxbw\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpsllw\[ \t]\+\\\$8, %zmm\[0-9]\+, %zmm\[0-9]\+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vpsllw\[ \t]\+\\\$8, %zmm\[0-9]\+, %zmm\[0-9]\+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpmovsxbw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%zmm\[0-9\](?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vpmovsxbw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ #include <immintrin.h> -volatile __m128 x1,a1,b1; -volatile __m256 x2,a2,b2; +volatile __m128 a1,b1; +volatile __m256 a2,b2; +volatile __m512 a3,b3; volatile __m128h y,x128h,z; volatile __m256h y2,x256h,z2; +volatile __m512h y3,x512h,z4; volatile __m128i x128i,z3; -volatile __m256i x256i; +volatile __m256i x256i,z1; +volatile __m512i x512i; volatile __mmask8 m8; volatile __mmask16 m16; volatile __mmask32 m32; -const void *a; -__m128bh *b; -__m256bh *c; -__m128h *d; -__m256h *e; +volatile __mmask64 m64; void extern avx10_2_test (void) @@ -121,6 +169,13 @@ avx10_2_test (void) y2 = _mm256_mask_cvtx2ps_ph (y2, m16, a2, b2); y2 = _mm256_maskz_cvtx2ps_ph (m16, a2, b2); + y3 = _mm512_cvtx2ps_ph (a3, b3); + y3 = _mm512_mask_cvtx2ps_ph (y3, m32, a3, b3); + y3 = _mm512_maskz_cvtx2ps_ph (m32, a3, b3); + + y3 = _mm512_cvtx_round2ps_ph (a3, b3, 8); + y3 = _mm512_mask_cvtx_round2ps_ph (y3, m32, a3, b3, 8); + y3 = _mm512_maskz_cvtx_round2ps_ph (m32, a3, b3, 8); } void extern @@ -133,6 +188,10 @@ avx10_2_vcvtbiasph2bf8_test (void) x128i = _mm256_cvtbiasph_bf8 (x256i, x256h); x128i = _mm256_mask_cvtbiasph_bf8 (x128i, m16, x256i, x256h); x128i = _mm256_maskz_cvtbiasph_bf8 (m16, x256i, x256h); + + x256i = _mm512_cvtbiasph_bf8 (x512i, x512h); + x256i = _mm512_mask_cvtbiasph_bf8 (x256i, m32, x512i, x512h); + x256i = _mm512_maskz_cvtbiasph_bf8 (m32, x512i, x512h); } void extern @@ -145,6 +204,10 @@ avx10_2_vcvtbiasph2bf8s_test (void) x128i = _mm256_cvts_biasph_bf8 (x256i, x256h); x128i = _mm256_mask_cvts_biasph_bf8 (x128i, m16, x256i, x256h); x128i = _mm256_maskz_cvts_biasph_bf8 (m16, x256i, x256h); + + x256i = _mm512_cvts_biasph_bf8 (x512i, x512h); + x256i = _mm512_mask_cvts_biasph_bf8 (x256i, m32, x512i, x512h); + x256i = _mm512_maskz_cvts_biasph_bf8 (m32, x512i, x512h); } void extern @@ -157,6 +220,10 @@ avx10_2_vcvtbiasph2hf8_test (void) x128i = _mm256_cvtbiasph_hf8 (x256i, x256h); x128i = _mm256_mask_cvtbiasph_hf8 (x128i, m16, x256i, x256h); x128i = _mm256_maskz_cvtbiasph_hf8 (m16, x256i, x256h); + + x256i = _mm512_cvtbiasph_hf8 (x512i, x512h); + x256i = _mm512_mask_cvtbiasph_hf8 (x256i, m32, x512i, x512h); + x256i = _mm512_maskz_cvtbiasph_hf8 (m32, x512i, x512h); } void extern @@ -169,6 +236,10 @@ avx10_2_vcvtbiasph2hf8s_test (void) x128i = _mm256_cvts_biasph_hf8 (x256i, x256h); x128i = _mm256_mask_cvts_biasph_hf8 (x128i, m16, x256i, x256h); x128i = _mm256_maskz_cvts_biasph_hf8 (m16, x256i, x256h); + + x256i = _mm512_cvts_biasph_hf8 (x512i, x512h); + x256i = _mm512_mask_cvts_biasph_hf8 (x256i, m32, x512i, x512h); + x256i = _mm512_maskz_cvts_biasph_hf8 (m32, x512i, x512h); } void extern @@ -177,9 +248,14 @@ avx10_2_vcvt2ph2bf8_test (void) x128i = _mm_cvt2ph_bf8 (x128h, x128h); x128i = _mm_mask_cvt2ph_bf8 (x128i, m16, x128h, x128h); x128i = _mm_maskz_cvt2ph_bf8 (m16, x128h, x128h); + x256i = _mm256_cvt2ph_bf8 (x256h, x256h); x256i = _mm256_mask_cvt2ph_bf8 (x256i, m32, x256h, x256h); x256i = _mm256_maskz_cvt2ph_bf8 (m32, x256h, x256h); + + x512i = _mm512_cvt2ph_bf8 (x512h, x512h); + x512i = _mm512_mask_cvt2ph_bf8 (x512i, m64, x512h, x512h); + x512i = _mm512_maskz_cvt2ph_bf8 (m64, x512h, x512h); } void extern @@ -188,9 +264,14 @@ avx10_2_vcvt2ph2bf8s_test (void) x128i = _mm_cvts_2ph_bf8 (x128h, x128h); x128i = _mm_mask_cvts_2ph_bf8 (x128i, m16, x128h, x128h); x128i = _mm_maskz_cvts_2ph_bf8 (m16, x128h, x128h); + x256i = _mm256_cvts_2ph_bf8 (x256h, x256h); x256i = _mm256_mask_cvts_2ph_bf8 (x256i, m32, x256h, x256h); x256i = _mm256_maskz_cvts_2ph_bf8 (m32, x256h, x256h); + + x512i = _mm512_cvts_2ph_bf8 (x512h, x512h); + x512i = _mm512_mask_cvts_2ph_bf8 (x512i, m64, x512h, x512h); + x512i = _mm512_maskz_cvts_2ph_bf8 (m64, x512h, x512h); } void extern @@ -199,9 +280,14 @@ avx10_2_vcvt2ph2hf8_test (void) x128i = _mm_cvt2ph_hf8 (x128h, x128h); x128i = _mm_mask_cvt2ph_hf8 (x128i, m16, x128h, x128h); x128i = _mm_maskz_cvt2ph_hf8 (m16, x128h, x128h); + x256i = _mm256_cvt2ph_hf8 (x256h, x256h); x256i = _mm256_mask_cvt2ph_hf8 (x256i, m32, x256h, x256h); x256i = _mm256_maskz_cvt2ph_hf8 (m32, x256h, x256h); + + x512i = _mm512_cvt2ph_hf8 (x512h, x512h); + x512i = _mm512_mask_cvt2ph_hf8 (x512i, m64, x512h, x512h); + x512i = _mm512_maskz_cvt2ph_hf8 (m64, x512h, x512h); } void extern @@ -210,9 +296,14 @@ avx10_2_vcvt2ph2hf8s_test (void) x128i = _mm_cvts_2ph_hf8 (x128h, x128h); x128i = _mm_mask_cvts_2ph_hf8 (x128i, m16, x128h, x128h); x128i = _mm_maskz_cvts_2ph_hf8 (m16, x128h, x128h); + x256i = _mm256_cvts_2ph_hf8 (x256h, x256h); x256i = _mm256_mask_cvts_2ph_hf8 (x256i, m32, x256h, x256h); x256i = _mm256_maskz_cvts_2ph_hf8 (m32, x256h, x256h); + + x512i = _mm512_cvts_2ph_hf8 (x512h, x512h); + x512i = _mm512_mask_cvts_2ph_hf8 (x512i, m64, x512h, x512h); + x512i = _mm512_maskz_cvts_2ph_hf8 (m64, x512h, x512h); } void extern @@ -225,6 +316,10 @@ avx10_2_vcvthf82ph_test (void) x256h = _mm256_cvthf8_ph (x128i); x256h = _mm256_mask_cvthf8_ph (x256h, m16, x128i); x256h = _mm256_maskz_cvthf8_ph (m16, x128i); + + x512h = _mm512_cvthf8_ph (x256i); + x512h = _mm512_mask_cvthf8_ph (x512h, m32, x256i); + x512h = _mm512_maskz_cvthf8_ph (m32, x256i); } void extern @@ -237,6 +332,10 @@ avx10_2_vcvtph2bf8_test (void) x128i = _mm256_cvtph_bf8 (x256h); x128i = _mm256_mask_cvtph_bf8 (x128i, m16, x256h); x128i = _mm256_maskz_cvtph_bf8 (m16, x256h); + + x256i = _mm512_cvtph_bf8 (x512h); + x256i = _mm512_mask_cvtph_bf8 (x256i, m32, x512h); + x256i = _mm512_maskz_cvtph_bf8 (m32, x512h); } void extern @@ -249,6 +348,10 @@ avx10_2_vcvtph2bf8s_test (void) x128i = _mm256_cvts_ph_bf8 (x256h); x128i = _mm256_mask_cvts_ph_bf8 (x128i, m16, x256h); x128i = _mm256_maskz_cvts_ph_bf8 (m16, x256h); + + x256i = _mm512_cvts_ph_bf8 (x512h); + x256i = _mm512_mask_cvts_ph_bf8 (x256i, m32, x512h); + x256i = _mm512_maskz_cvts_ph_bf8 (m32, x512h); } void extern @@ -261,6 +364,10 @@ avx10_2_vcvtph2hf8_test (void) x128i = _mm256_cvtph_hf8 (x256h); x128i = _mm256_mask_cvtph_hf8 (x128i, m16, x256h); x128i = _mm256_maskz_cvtph_hf8 (m16, x256h); + + x256i = _mm512_cvtph_hf8 (x512h); + x256i = _mm512_mask_cvtph_hf8 (x256i, m32, x512h); + x256i = _mm512_maskz_cvtph_hf8 (m32, x512h); } void extern @@ -273,6 +380,10 @@ avx10_2_vcvtph2hf8s_test (void) x128i = _mm256_cvts_ph_hf8 (x256h); x128i = _mm256_mask_cvts_ph_hf8 (x128i, m16, x256h); x128i = _mm256_maskz_cvts_ph_hf8 (m16, x256h); + + x256i = _mm512_cvts_ph_hf8 (x512h); + x256i = _mm512_mask_cvts_ph_hf8 (x256i, m32, x512h); + x256i = _mm512_maskz_cvts_ph_hf8 (m32, x512h); } void extern @@ -285,4 +396,8 @@ avx10_2_cvtbf8_fp16_test (void) y2 = _mm256_cvtbf8_ph (z3); y2 = _mm256_mask_cvtbf8_ph (z2, m16, z3); y2 = _mm256_maskz_cvtbf8_ph (m16, z3); + + y3 = _mm512_cvtbf8_ph (z1); + y3 = _mm512_mask_cvtbf8_ph (z4, m32, z1); + y3 = _mm512_maskz_cvtbf8_ph (m32, z1); } diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-media-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-media-1.c index bdf6a6d..f82613b 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-media-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-media-1.c @@ -1,83 +1,125 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64-v3 -mavx10.2 -O2" } */ +/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbuuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbuuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbuuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbuuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbuuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpbuuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vdpphps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vdpphps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vdpphps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vdpphps\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vdpphps\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vdpphps\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vdpphps\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vdpphps\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vdpphps\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmpsadbw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmpsadbw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmpsadbw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmpsadbw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmpsadbw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmpsadbw\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ @@ -85,18 +127,26 @@ #include <immintrin.h> +volatile __m512 a1; +volatile __m512h b1,c1; +volatile __m512i x1,y2,z1; volatile __m256 a; volatile __m256h b,c; volatile __m256i x,y,z; volatile __m128 a_; volatile __m128h b_,c_; volatile __m128i x_,y_,z_; +volatile __mmask32 m32; volatile __mmask16 m16; volatile __mmask8 m; void extern avx10_2_test (void) { + x1 = _mm512_dpbssd_epi32 (x1, y2, z1); + x1 = _mm512_mask_dpbssd_epi32 (x1, m16, y2, z1); + x1 = _mm512_maskz_dpbssd_epi32 (m16, x1, y2, z1); + x = _mm256_dpbssd_epi32 (x, y, z); x = _mm256_mask_dpbssd_epi32 (x, m, y, z); x = _mm256_maskz_dpbssd_epi32 (m, x, y, z); @@ -105,6 +155,10 @@ avx10_2_test (void) x_ = _mm_mask_dpbssd_epi32 (x_, m, y_, z_); x_ = _mm_maskz_dpbssd_epi32 (m, x_, y_, z_); + x1 = _mm512_dpbssds_epi32 (x1, y2, z1); + x1 = _mm512_mask_dpbssds_epi32 (x1, m16, y2, z1); + x1 = _mm512_maskz_dpbssds_epi32 (m16, x1, y2, z1); + x = _mm256_dpbssds_epi32 (x, y, z); x = _mm256_mask_dpbssds_epi32 (x, m, y, z); x = _mm256_maskz_dpbssds_epi32 (m, x, y, z); @@ -113,6 +167,10 @@ avx10_2_test (void) x_ = _mm_mask_dpbssds_epi32 (x_, m, y_, z_); x_ = _mm_maskz_dpbssds_epi32 (m, x_, y_, z_); + x1 = _mm512_dpbsud_epi32 (x1, y2, z1); + x1 = _mm512_mask_dpbsud_epi32 (x1, m16, y2, z1); + x1 = _mm512_maskz_dpbsud_epi32 (m16, x1, y2, z1); + x = _mm256_dpbsud_epi32 (x, y, z); x = _mm256_mask_dpbsud_epi32 (x, m, y, z); x = _mm256_maskz_dpbsud_epi32 (m, x, y, z); @@ -121,6 +179,10 @@ avx10_2_test (void) x_ = _mm_mask_dpbsud_epi32 (x_, m, y_, z_); x_ = _mm_maskz_dpbsud_epi32 (m, x_, y_, z_); + x1 = _mm512_dpbsuds_epi32 (x1, y2, z1); + x1 = _mm512_mask_dpbsuds_epi32 (x1, m16, y2, z1); + x1 = _mm512_maskz_dpbsuds_epi32 (m16, x1, y2, z1); + x = _mm256_dpbsuds_epi32 (x, y, z); x = _mm256_mask_dpbsuds_epi32 (x, m, y, z); x = _mm256_maskz_dpbsuds_epi32 (m, x, y, z); @@ -129,6 +191,10 @@ avx10_2_test (void) x_ = _mm_mask_dpbsuds_epi32 (x_, m, y_, z_); x_ = _mm_maskz_dpbsuds_epi32 (m, x_, y_, z_); + x1 = _mm512_dpbuud_epi32 (x1, y2, z1); + x1 = _mm512_mask_dpbuud_epi32 (x1, m16, y2, z1); + x1 = _mm512_maskz_dpbuud_epi32 (m16, x1, y2, z1); + x = _mm256_dpbuud_epi32 (x, y, z); x = _mm256_mask_dpbuud_epi32 (x, m, y, z); x = _mm256_maskz_dpbuud_epi32 (m, x, y, z); @@ -137,6 +203,10 @@ avx10_2_test (void) x_ = _mm_mask_dpbuud_epi32 (x_, m, y_, z_); x_ = _mm_maskz_dpbuud_epi32 (m, x_, y_, z_); + x1 = _mm512_dpbuuds_epi32 (x1, y2, z1); + x1 = _mm512_mask_dpbuuds_epi32 (x1, m16, y2, z1); + x1 = _mm512_maskz_dpbuuds_epi32 (m16, x1, y2, z1); + x = _mm256_dpbuuds_epi32 (x, y, z); x = _mm256_mask_dpbuuds_epi32 (x, m, y, z); x = _mm256_maskz_dpbuuds_epi32 (m, x, y, z); @@ -145,6 +215,10 @@ avx10_2_test (void) x_ = _mm_mask_dpbuuds_epi32 (x_, m, y_, z_); x_ = _mm_maskz_dpbuuds_epi32 (m, x_, y_, z_); + x1 = _mm512_dpwsud_epi32 (x1, y2, z1); + x1 = _mm512_mask_dpwsud_epi32 (x1, m16, y2, z1); + x1 = _mm512_maskz_dpwsud_epi32 (m16, x1, y2, z1); + x = _mm256_dpwsud_epi32 (x, y, z); x = _mm256_mask_dpwsud_epi32 (x, m, y, z); x = _mm256_maskz_dpwsud_epi32 (m, x, y, z); @@ -153,6 +227,10 @@ avx10_2_test (void) x_ = _mm_mask_dpwsud_epi32 (x_, m, y_, z_); x_ = _mm_maskz_dpwsud_epi32 (m, x_, y_, z_); + x1 = _mm512_dpwsuds_epi32 (x1, y2, z1); + x1 = _mm512_mask_dpwsuds_epi32 (x1, m16, y2, z1); + x1 = _mm512_maskz_dpwsuds_epi32 (m16, x1, y2, z1); + x = _mm256_dpwsuds_epi32 (x, y, z); x = _mm256_mask_dpwsuds_epi32 (x, m, y, z); x = _mm256_maskz_dpwsuds_epi32 (m, x, y, z); @@ -161,6 +239,10 @@ avx10_2_test (void) x_ = _mm_mask_dpwsuds_epi32 (x_, m, y_, z_); x_ = _mm_maskz_dpwsuds_epi32 (m, x_, y_, z_); + x1 = _mm512_dpwusd_epi32 (x1, y2, z1); + x1 = _mm512_mask_dpwusd_epi32 (x1, m16, y2, z1); + x1 = _mm512_maskz_dpwusd_epi32 (m16, x1, y2, z1); + x = _mm256_dpwusd_epi32 (x, y, z); x = _mm256_mask_dpwusd_epi32 (x, m, y, z); x = _mm256_maskz_dpwusd_epi32 (m, x, y, z); @@ -169,6 +251,10 @@ avx10_2_test (void) x_ = _mm_mask_dpwusd_epi32 (x_, m, y_, z_); x_ = _mm_maskz_dpwusd_epi32 (m, x_, y_, z_); + x1 = _mm512_dpwusds_epi32 (x1, y2, z1); + x1 = _mm512_mask_dpwusds_epi32 (x1, m16, y2, z1); + x1 = _mm512_maskz_dpwusds_epi32 (m16, x1, y2, z1); + x = _mm256_dpwusds_epi32 (x, y, z); x = _mm256_mask_dpwusds_epi32 (x, m, y, z); x = _mm256_maskz_dpwusds_epi32 (m, x, y, z); @@ -177,6 +263,10 @@ avx10_2_test (void) x_ = _mm_mask_dpwusds_epi32 (x_, m, y_, z_); x_ = _mm_maskz_dpwusds_epi32 (m, x_, y_, z_); + x1 = _mm512_dpwuud_epi32 (x1, y2, z1); + x1 = _mm512_mask_dpwuud_epi32 (x1, m16, y2, z1); + x1 = _mm512_maskz_dpwuud_epi32 (m16, x1, y2, z1); + x = _mm256_dpwuud_epi32 (x, y, z); x = _mm256_mask_dpwuud_epi32 (x, m, y, z); x = _mm256_maskz_dpwuud_epi32 (m, x, y, z); @@ -185,6 +275,10 @@ avx10_2_test (void) x_ = _mm_mask_dpwuud_epi32 (x_, m, y_, z_); x_ = _mm_maskz_dpwuud_epi32 (m, x_, y_, z_); + x1 = _mm512_dpwuuds_epi32 (x1, y2, z1); + x1 = _mm512_mask_dpwuuds_epi32 (x1, m16, y2, z1); + x1 = _mm512_maskz_dpwuuds_epi32 (m16, x1, y2, z1); + x = _mm256_dpwuuds_epi32 (x, y, z); x = _mm256_mask_dpwuuds_epi32 (x, m, y, z); x = _mm256_maskz_dpwuuds_epi32 (m, x, y, z); @@ -193,6 +287,10 @@ avx10_2_test (void) x_ = _mm_mask_dpwuuds_epi32 (x_, m, y_, z_); x_ = _mm_maskz_dpwuuds_epi32 (m, x_, y_, z_); + a1 = _mm512_dpph_ps (a1, b1, c1); + a1 = _mm512_mask_dpph_ps (a1, m16, b1, c1); + a1 = _mm512_maskz_dpph_ps (m16, a1, b1, c1); + a = _mm256_dpph_ps (a, b, c); a = _mm256_mask_dpph_ps (a, m, b, c); a = _mm256_maskz_dpph_ps (m, a, b, c); @@ -201,8 +299,13 @@ avx10_2_test (void) a_ = _mm_mask_dpph_ps (a_, m, b_, c_); a_ = _mm_maskz_dpph_ps (m, a_, b_, c_); + x1 = _mm512_mpsadbw_epu8 (x1, y2, 1); + x1 = _mm512_mask_mpsadbw_epu8 (x1, m32, y2, z1, 1); + x1 = _mm512_maskz_mpsadbw_epu8 (m32, x1, y2, 1); + x = _mm256_mask_mpsadbw_epu8 (x, m16, y, z, 1); x = _mm256_maskz_mpsadbw_epu8 (m16, x, y, 1); + x_ = _mm_mask_mpsadbw_epu8 (x_, m, y_, z_, 1); x_ = _mm_maskz_mpsadbw_epu8 (m, x_, y_, 1); } diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-minmax-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-minmax-1.c index 77aacfa..b5ece28 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-minmax-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-minmax-1.c @@ -6,24 +6,36 @@ /* { dg-final { scan-assembler-times "vminmaxbf16\[ \\t\]+\[^\{\n\]*\[^\}\]%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxbf16\[ \\t\]+\[^\{\n\]*\[^\}\]%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxbf16\[ \\t\]+\[^\{\n\]*\[^\}\]%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vminmaxbf16\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vminmaxbf16\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vminmaxbf16\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxph\[ \\t\]+\[^\{\n\]*\[^\}\]%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxph\[ \\t\]+\[^\{\n\]*\[^\}\]%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxph\[ \\t\]+\[^\{\n\]*\[^\}\]%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxph\[ \\t\]+\[^\{\n\]*\[^\}\]%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxph\[ \\t\]+\[^\{\n\]*\[^\}\]%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxph\[ \\t\]+\[^\{\n\]*\[^\}\]%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vminmaxph\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vminmaxph\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vminmaxph\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 2 } } */ /* { dg-final { scan-assembler-times "vminmaxps\[ \\t\]+\[^\{\n\]*\[^\}\]%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxps\[ \\t\]+\[^\{\n\]*\[^\}\]%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxps\[ \\t\]+\[^\{\n\]*\[^\}\]%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxps\[ \\t\]+\[^\{\n\]*\[^\}\]%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxps\[ \\t\]+\[^\{\n\]*\[^\}\]%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxps\[ \\t\]+\[^\{\n\]*\[^\}\]%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vminmaxps\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vminmaxps\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vminmaxps\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 2 } } */ /* { dg-final { scan-assembler-times "vminmaxpd\[ \\t\]+\[^\{\n\]*\[^\}\]%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxpd\[ \\t\]+\[^\{\n\]*\[^\}\]%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxpd\[ \\t\]+\[^\{\n\]*\[^\}\]%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxpd\[ \\t\]+\[^\{\n\]*\[^\}\]%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxpd\[ \\t\]+\[^\{\n\]*\[^\}\]%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxpd\[ \\t\]+\[^\{\n\]*\[^\}\]%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vminmaxpd\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vminmaxpd\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vminmaxpd\[ \\t\]+\[^\{\n\]*\[^\}\]%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 2 } } */ /* { dg-final { scan-assembler-times "vminmaxsh\[ \\t\]+\[^\{\n\]*\[^\}\]%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxsh\[ \\t\]+\[^\{\n\]*\[^\}\]%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vminmaxsh\[ \\t\]+\[^\{\n\]*\[^\}\]%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ @@ -36,6 +48,10 @@ #include <immintrin.h> +volatile __m512bh z1; +volatile __m512h z2; +volatile __m512 z3; +volatile __m512d z4; volatile __m256bh y1_; volatile __m256h y2; volatile __m256 y3; @@ -44,6 +60,7 @@ volatile __m128bh x1; volatile __m128h x2; volatile __m128 x3; volatile __m128d x4; +volatile __mmask32 m32; volatile __mmask16 m16; volatile __mmask8 m8; @@ -56,36 +73,63 @@ avx10_2_test (void) y1_ = _mm256_minmax_pbh (y1_, y1_, 100); y1_ = _mm256_mask_minmax_pbh (y1_, m16, y1_, y1_, 100); y1_ = _mm256_maskz_minmax_pbh (m16, y1_, y1_, 100); + z1 = _mm512_minmax_pbh (z1, z1, 100); + z1 = _mm512_mask_minmax_pbh (z1, m32, z1, z1, 100); + z1 = _mm512_maskz_minmax_pbh (m32, z1, z1, 100); + x2 = _mm_minmax_ph (x2, x2, 100); x2 = _mm_mask_minmax_ph (x2, m8, x2, x2, 100); x2 = _mm_maskz_minmax_ph (m8, x2, x2, 100); y2 = _mm256_minmax_ph (y2, y2, 100); y2 = _mm256_mask_minmax_ph (y2, m16, y2, y2, 100); y2 = _mm256_maskz_minmax_ph (m16, y2, y2, 100); + z2 = _mm512_minmax_ph (z2, z2, 1); + z2 = _mm512_mask_minmax_ph (z2, m32, z2, z2, 1); + z2 = _mm512_maskz_minmax_ph (m32, z2, z2, 1); + z2 = _mm512_minmax_round_ph (z2, z2, 1, 4); + z2 = _mm512_mask_minmax_round_ph (z2, m32, z2, z2, 1, 4); + z2 = _mm512_maskz_minmax_round_ph (m32, z2, z2, 1, 4); + x3 = _mm_minmax_ps (x3, x3, 100); x3 = _mm_mask_minmax_ps (x3, m8, x3, x3, 100); x3 = _mm_maskz_minmax_ps (m8, x3, x3, 100); y3 = _mm256_minmax_ps (y3, y3, 100); y3 = _mm256_mask_minmax_ps (y3, m8, y3, y3, 100); y3 = _mm256_maskz_minmax_ps (m8, y3, y3, 100); + z3 = _mm512_minmax_ps (z3, z3, 1); + z3 = _mm512_mask_minmax_ps (z3, m16, z3, z3, 1); + z3 = _mm512_maskz_minmax_ps (m16, z3, z3, 1); + z3 = _mm512_minmax_round_ps (z3, z3, 1, 4); + z3 = _mm512_mask_minmax_round_ps (z3, m16, z3, z3, 1, 4); + z3 = _mm512_maskz_minmax_round_ps (m16, z3, z3, 1, 4); + x4 = _mm_minmax_pd (x4, x4, 100); x4 = _mm_mask_minmax_pd (x4, m8, x4, x4, 100); x4 = _mm_maskz_minmax_pd (m8, x4, x4, 100); y4 = _mm256_minmax_pd (y4, y4, 100); y4 = _mm256_mask_minmax_pd (y4, m8, y4, y4, 100); y4 = _mm256_maskz_minmax_pd (m8, y4, y4, 100); + z4 = _mm512_minmax_pd (z4, z4, 100); + z4 = _mm512_mask_minmax_pd (z4, m8, z4, z4, 100); + z4 = _mm512_maskz_minmax_pd (m8, z4, z4, 100); + z4 = _mm512_minmax_round_pd (z4, z4, 100, 4); + z4 = _mm512_mask_minmax_round_pd (z4, m8, z4, z4, 100, 4); + z4 = _mm512_maskz_minmax_round_pd (m8, z4, z4, 100, 4); + x2 = _mm_minmax_sh (x2, x2, 1); x2 = _mm_mask_minmax_sh (x2, m8, x2, x2, 1); x2 = _mm_maskz_minmax_sh (m8, x2, x2, 1); x2 = _mm_minmax_round_sh (x2, x2, 1, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); x2 = _mm_mask_minmax_round_sh (x2, m8, x2, x2, 1, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); x2 = _mm_maskz_minmax_round_sh (m8, x2, x2, 1, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); + x3 = _mm_minmax_ss (x3, x3, 1); x3 = _mm_mask_minmax_ss (x3, m8, x3, x3, 1); x3 = _mm_maskz_minmax_ss (m8, x3, x3, 1); x3 = _mm_minmax_round_ss (x3, x3, 1, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); x3 = _mm_mask_minmax_round_ss (x3, m8, x3, x3, 1, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); x3 = _mm_maskz_minmax_round_ss (m8, x3, x3, 1, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); + x4 = _mm_minmax_sd (x4, x4, 1); x4 = _mm_mask_minmax_sd (x4, m8, x4, x4, 1); x4 = _mm_maskz_minmax_sd (m8, x4, x4, 1); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-movrs-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-movrs-1.c index e3f0bfd..9d1e8b7 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-movrs-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-movrs-1.c @@ -1,5 +1,17 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-march=x86-64-v3 -mavx10.2 -mmovrs -O2" } */ +/* { dg-final { scan-assembler-times "vmovrsb\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "vmovrsb\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}" 2 } } */ +/* { dg-final { scan-assembler-times "vmovrsb\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}{z}" 1 } } */ +/* { dg-final { scan-assembler-times "vmovrsd\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "vmovrsd\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}" 2 } } */ +/* { dg-final { scan-assembler-times "vmovrsd\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}{z}" 1 } } */ +/* { dg-final { scan-assembler-times "vmovrsq\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "vmovrsq\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}" 2 } } */ +/* { dg-final { scan-assembler-times "vmovrsq\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}{z}" 1 } } */ +/* { dg-final { scan-assembler-times "vmovrsw\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+" 3 } } */ +/* { dg-final { scan-assembler-times "vmovrsw\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}" 2 } } */ +/* { dg-final { scan-assembler-times "vmovrsw\[ \\t\]\+\\(%(?:r|e).x\\), %zmm\[0-9\]+{%k\[1-7\]}{z}" 1 } } */ /* { dg-final { scan-assembler-times "vmovrsb\[ \\t\]\+\\(%(?:r|e).x\\), %ymm\[0-9\]+" 3 } } */ /* { dg-final { scan-assembler-times "vmovrsb\[ \\t\]\+\\(%(?:r|e).x\\), %ymm\[0-9\]+{%k\[1-7\]}" 2 } } */ /* { dg-final { scan-assembler-times "vmovrsb\[ \\t\]\+\\(%(?:r|e).x\\), %ymm\[0-9\]+{%k\[1-7\]}{z}" 1 } } */ @@ -27,41 +39,57 @@ #include <immintrin.h> +__m512i *px; +volatile __m512i x; __m256i *px1; volatile __m256i x1; __m128i *px2; volatile __m128i x2; -volatile __mmask32 m1; -volatile __mmask8 m2; -volatile __mmask16 m3; +volatile __mmask8 m8; +volatile __mmask16 m16; +volatile __mmask32 m32; +volatile __mmask64 m64; void extern avx10_movrs_test (void) { + x = _mm512_loadrs_epi8(px); + x = _mm512_mask_loadrs_epi8(x, m64, px); + x = _mm512_maskz_loadrs_epi8(m64, px); + x = _mm512_loadrs_epi32(px); + x = _mm512_mask_loadrs_epi32(x, m16, px); + x = _mm512_maskz_loadrs_epi32(m16, px); + x = _mm512_loadrs_epi64(px); + x = _mm512_mask_loadrs_epi64(x, m8, px); + x = _mm512_maskz_loadrs_epi64(m8, px); + x = _mm512_loadrs_epi16(px); + x = _mm512_mask_loadrs_epi16(x, m32, px); + x = _mm512_maskz_loadrs_epi16(m32, px); + x1 = _mm256_loadrs_epi8(px1); - x1 = _mm256_mask_loadrs_epi8(x1, m1, px1); - x1 = _mm256_maskz_loadrs_epi8(m1, px1); + x1 = _mm256_mask_loadrs_epi8(x1, m32, px1); + x1 = _mm256_maskz_loadrs_epi8(m32, px1); x1 = _mm256_loadrs_epi32(px1); - x1 = _mm256_mask_loadrs_epi32(x1, m2, px1); - x1 = _mm256_maskz_loadrs_epi32(m2, px1); + x1 = _mm256_mask_loadrs_epi32(x1, m8, px1); + x1 = _mm256_maskz_loadrs_epi32(m8, px1); x1 = _mm256_loadrs_epi64(px1); - x1 = _mm256_mask_loadrs_epi64(x1, m2, px1); - x1 = _mm256_maskz_loadrs_epi64(m2, px1); + x1 = _mm256_mask_loadrs_epi64(x1, m8, px1); + x1 = _mm256_maskz_loadrs_epi64(m8, px1); x1 = _mm256_loadrs_epi16(px1); - x1 = _mm256_mask_loadrs_epi16(x1, m3, px1); - x1 = _mm256_maskz_loadrs_epi16(m3, px1); + x1 = _mm256_mask_loadrs_epi16(x1, m16, px1); + x1 = _mm256_maskz_loadrs_epi16(m16, px1); x2 = _mm_loadrs_epi8(px2); - x2 = _mm_mask_loadrs_epi8(x2, m3, px2); - x2 = _mm_maskz_loadrs_epi8(m3, px2); + x2 = _mm_mask_loadrs_epi8(x2, m16, px2); + x2 = _mm_maskz_loadrs_epi8(m16, px2); x2 = _mm_loadrs_epi32(px2); - x2 = _mm_mask_loadrs_epi32(x2, m2, px2); - x2 = _mm_maskz_loadrs_epi32(m2, px2); + x2 = _mm_mask_loadrs_epi32(x2, m8, px2); + x2 = _mm_maskz_loadrs_epi32(m8, px2); x2 = _mm_loadrs_epi64(px2); - x2 = _mm_mask_loadrs_epi64(x2, m2, px2); - x2 = _mm_maskz_loadrs_epi64(m2, px2); + x2 = _mm_mask_loadrs_epi64(x2, m8, px2); + x2 = _mm_maskz_loadrs_epi64(m8, px2); x2 = _mm_loadrs_epi16(px2); - x2 = _mm_mask_loadrs_epi16(x2, m2, px2); - x2 = _mm_maskz_loadrs_epi16(m2, px2); + x2 = _mm_mask_loadrs_epi16(x2, m8, px2); + x2 = _mm_maskz_loadrs_epi16(m8, px2); } diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-satcvt-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-satcvt-1.c index 4ae1fc1..7b1c247 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-satcvt-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-satcvt-1.c @@ -1,5 +1,57 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ +/* { dg-final { scan-assembler-times "vcvtph2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2ibs\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2ibs\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2iubs\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2iubs\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvttph2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2ibs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2ibs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvttph2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2iubs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2iubs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtps2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2ibs\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2ibs\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtps2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2iubs\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2iubs\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvttps2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2ibs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2ibs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvttps2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2iubs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2iubs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbf162ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbf162ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbf162ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbf162iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbf162iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtbf162iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttbf162ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttbf162ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttbf162ibs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttbf162iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttbf162iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttbf162iubs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2ibs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2ibs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvtph2ibs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ @@ -72,6 +124,54 @@ /* { dg-final { scan-assembler-times "vcvttbf162iubs\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvttbf162iubs\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvttbf162iubs\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2dqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2dqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2dqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2dqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2dqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2dqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2qqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2qqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2qqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2qqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2qqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2qqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2udqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2udqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2udqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2udqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2udqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2udqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2uqqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2uqqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2uqqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2uqqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2uqqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2uqqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2dqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2dqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2dqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2dqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2dqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2dqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2qqs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2qqs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2qqs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2qqs\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2qqs\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2qqs\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2udqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2udqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2udqs\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2udqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2udqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2udqs\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2uqqs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2uqqs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2uqqs\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2uqqs\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2uqqs\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2uqqs\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvttpd2dqsy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvttpd2dqsy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcvttpd2dqsy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ @@ -149,8 +249,14 @@ volatile __m256h xh; volatile __m256i xi; volatile __m256d xd; volatile __m256bh xbh; +volatile __m512 z; +volatile __m512h zh; +volatile __m512i zi; +volatile __m512d zd; +volatile __m512bh zbh; volatile __mmask8 m8; volatile __mmask16 m16; +volatile __mmask32 m32; volatile int i; volatile unsigned int ui; volatile long long ll; @@ -159,6 +265,78 @@ volatile unsigned long long ull; void extern avx10_2_test (void) { + zi = _mm512_ipcvts_ph_epi8 (zh); + zi = _mm512_mask_ipcvts_ph_epi8 (zi, m32, zh); + zi = _mm512_maskz_ipcvts_ph_epi8 (m32, zh); + zi = _mm512_ipcvts_roundph_epi8 (zh, 4); + zi = _mm512_mask_ipcvts_roundph_epi8 (zi, m32, zh, 8); + zi = _mm512_maskz_ipcvts_roundph_epi8 (m32, zh, 11); + + zi = _mm512_ipcvts_ph_epu8 (zh); + zi = _mm512_mask_ipcvts_ph_epu8 (zi, m32, zh); + zi = _mm512_maskz_ipcvts_ph_epu8 (m32, zh); + zi = _mm512_ipcvts_roundph_epu8 (zh, 4); + zi = _mm512_mask_ipcvts_roundph_epu8 (zi, m32, zh, 8); + zi = _mm512_maskz_ipcvts_roundph_epu8 (m32, zh, 11); + + zi = _mm512_ipcvtts_ph_epi8 (zh); + zi = _mm512_mask_ipcvtts_ph_epi8 (zi, m32, zh); + zi = _mm512_maskz_ipcvtts_ph_epi8 (m32, zh); + zi = _mm512_ipcvtts_roundph_epi8 (zh, 4); + zi = _mm512_mask_ipcvtts_roundph_epi8 (zi, m32, zh, 8); + zi = _mm512_maskz_ipcvtts_roundph_epi8 (m32, zh, 8); + + zi = _mm512_ipcvtts_ph_epu8 (zh); + zi = _mm512_mask_ipcvtts_ph_epu8 (zi, m32, zh); + zi = _mm512_maskz_ipcvtts_ph_epu8 (m32, zh); + zi = _mm512_ipcvtts_roundph_epu8 (zh, 4); + zi = _mm512_mask_ipcvtts_roundph_epu8 (zi, m32, zh, 8); + zi = _mm512_maskz_ipcvtts_roundph_epu8 (m32, zh, 8); + + zi = _mm512_ipcvts_ps_epi8 (z); + zi = _mm512_mask_ipcvts_ps_epi8 (zi, m16, z); + zi = _mm512_maskz_ipcvts_ps_epi8 (m16, z); + zi = _mm512_ipcvts_roundps_epi8 (z, 4); + zi = _mm512_mask_ipcvts_roundps_epi8 (zi, m16, z, 8); + zi = _mm512_maskz_ipcvts_roundps_epi8 (m16, z, 11); + + zi = _mm512_ipcvts_ps_epu8 (z); + zi = _mm512_mask_ipcvts_ps_epu8 (zi, m16, z); + zi = _mm512_maskz_ipcvts_ps_epu8 (m16, z); + zi = _mm512_ipcvts_roundps_epu8 (z, 4); + zi = _mm512_mask_ipcvts_roundps_epu8 (zi, m16, z, 8); + zi = _mm512_maskz_ipcvts_roundps_epu8 (m16, z, 11); + + zi = _mm512_ipcvtts_ps_epi8 (z); + zi = _mm512_mask_ipcvtts_ps_epi8 (zi, m16, z); + zi = _mm512_maskz_ipcvtts_ps_epi8 (m16, z); + zi = _mm512_ipcvtts_roundps_epi8 (z, 4); + zi = _mm512_mask_ipcvtts_roundps_epi8 (zi, m16, z, 8); + zi = _mm512_maskz_ipcvtts_roundps_epi8 (m16, z, 8); + + zi = _mm512_ipcvtts_ps_epu8 (z); + zi = _mm512_mask_ipcvtts_ps_epu8 (zi, m16, z); + zi = _mm512_maskz_ipcvtts_ps_epu8 (m16, z); + zi = _mm512_ipcvtts_roundps_epu8 (z, 4); + zi = _mm512_mask_ipcvtts_roundps_epu8 (zi, m16, z, 8); + zi = _mm512_maskz_ipcvtts_roundps_epu8 (m16, z, 8); + + zi = _mm512_ipcvts_bf16_epi8 (zbh); + zi = _mm512_mask_ipcvts_bf16_epi8 (zi, m32, zbh); + zi = _mm512_maskz_ipcvts_bf16_epi8 (m32, zbh); + + zi = _mm512_ipcvts_bf16_epu8 (zbh); + zi = _mm512_mask_ipcvts_bf16_epu8 (zi, m32, zbh); + zi = _mm512_maskz_ipcvts_bf16_epu8 (m32, zbh); + + zi = _mm512_ipcvtts_bf16_epi8 (zbh); + zi = _mm512_mask_ipcvtts_bf16_epi8 (zi, m32, zbh); + zi = _mm512_maskz_ipcvtts_bf16_epi8 (m32, zbh); + + zi = _mm512_ipcvtts_bf16_epu8 (zbh); + zi = _mm512_mask_ipcvtts_bf16_epu8 (zi, m32, zbh); + zi = _mm512_maskz_ipcvtts_bf16_epu8 (m32, zbh); + xi = _mm256_ipcvts_ph_epi8 (xh); xi = _mm256_mask_ipcvts_ph_epi8 (xi, m16, xh); xi = _mm256_maskz_ipcvts_ph_epi8 (m16, xh); @@ -255,6 +433,62 @@ avx10_2_test (void) hxi = _mm_mask_ipcvtts_bf16_epu8 (hxi, m8, hxbh); hxi = _mm_maskz_ipcvtts_bf16_epu8 (m8, hxbh); + xi = _mm512_cvtts_pd_epi32 (zd); + xi = _mm512_mask_cvtts_pd_epi32 (xi, m8, zd); + xi = _mm512_maskz_cvtts_pd_epi32 (m8, zd); + xi = _mm512_cvtts_roundpd_epi32 (zd, 8); + xi = _mm512_mask_cvtts_roundpd_epi32 (xi, m8, zd, 8); + xi = _mm512_maskz_cvtts_roundpd_epi32 (m8, zd, 8); + + zi = _mm512_cvtts_pd_epi64 (zd); + zi = _mm512_mask_cvtts_pd_epi64 (zi, m8, zd); + zi = _mm512_maskz_cvtts_pd_epi64 (m8, zd); + zi = _mm512_cvtts_roundpd_epi64 (zd, 8); + zi = _mm512_mask_cvtts_roundpd_epi64 (zi, m8, zd, 8); + zi = _mm512_maskz_cvtts_roundpd_epi64 (m8, zd, 8); + + xi = _mm512_cvtts_pd_epu32 (zd); + xi = _mm512_mask_cvtts_pd_epu32 (xi, m8, zd); + xi = _mm512_maskz_cvtts_pd_epu32 (m8, zd); + xi = _mm512_cvtts_roundpd_epu32 (zd, 8); + xi = _mm512_mask_cvtts_roundpd_epu32 (xi, m8, zd, 8); + xi = _mm512_maskz_cvtts_roundpd_epu32 (m8, zd, 8); + + zi = _mm512_cvtts_pd_epu64 (zd); + zi = _mm512_mask_cvtts_pd_epu64 (zi, m8, zd); + zi = _mm512_maskz_cvtts_pd_epu64 (m8, zd); + zi = _mm512_cvtts_roundpd_epu64 (zd, 8); + zi = _mm512_mask_cvtts_roundpd_epu64 (zi, m8, zd, 8); + zi = _mm512_maskz_cvtts_roundpd_epu64 (m8, zd, 8); + + zi = _mm512_cvtts_ps_epi32 (z); + zi = _mm512_mask_cvtts_ps_epi32 (zi, m16, z); + zi = _mm512_maskz_cvtts_ps_epi32 (m16, z); + zi = _mm512_cvtts_roundps_epi32 (z, 8); + zi = _mm512_mask_cvtts_roundps_epi32 (zi, m16, z, 8); + zi = _mm512_maskz_cvtts_roundps_epi32 (m16, z, 8); + + zi = _mm512_cvtts_ps_epi64 (x); + zi = _mm512_mask_cvtts_ps_epi64 (zi, m8, x); + zi = _mm512_maskz_cvtts_ps_epi64 (m8, x); + zi = _mm512_cvtts_roundps_epi64 (x, 8); + zi = _mm512_mask_cvtts_roundps_epi64 (zi, m8, x, 8); + zi = _mm512_maskz_cvtts_roundps_epi64 (m8, x, 8); + + zi = _mm512_cvtts_ps_epu32 (z); + zi = _mm512_mask_cvtts_ps_epu32 (zi, m16, z); + zi = _mm512_maskz_cvtts_ps_epu32 (m16, z); + zi = _mm512_cvtts_roundps_epu32 (z, 8); + zi = _mm512_mask_cvtts_roundps_epu32 (zi, m16, z, 8); + zi = _mm512_maskz_cvtts_roundps_epu32 (m16, z, 8); + + zi = _mm512_cvtts_ps_epu64 (x); + zi = _mm512_mask_cvtts_ps_epu64 (zi, m8, x); + zi = _mm512_maskz_cvtts_ps_epu64 (m8, x); + zi = _mm512_cvtts_roundps_epu64 (x, 8); + zi = _mm512_mask_cvtts_roundps_epu64 (zi, m8, x, 8); + zi = _mm512_maskz_cvtts_roundps_epu64 (m8, x, 8); + hxi = _mm256_cvtts_pd_epi32 (xd); hxi = _mm256_mask_cvtts_pd_epi32 (hxi, m8, xd); hxi = _mm256_maskz_cvtts_pd_epi32 (m8, xd); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vaddbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vaddbf16-2.c index d880454..36f5bd7 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vaddbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vaddbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vaddbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vaddbf16-2.c" +#include "avx10_2-vaddbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vaddbf16-2.c" +#include "avx10_2-vaddbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vaddbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vaddbf16-2.h index 4aca46d..a65c647 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vaddbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vaddbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcmpbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcmpbf16-2.c index cb6506a..643fb26 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcmpbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcmpbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcmpbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcmpbf16-2.c" +#include "avx10_2-vcmpbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcmpbf16-2.c" +#include "avx10_2-vcmpbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcmpbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcmpbf16-2.h index 885cec7..2c0fde0 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcmpbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcmpbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2bf8-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2bf8-2.c index 9dd940c..dae2f44 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2bf8-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2bf8-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvt2ph2bf8-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvt2ph2bf8-2.c" +#include "avx10_2-vcvt2ph2bf8-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvt2ph2bf8-2.c" +#include "avx10_2-vcvt2ph2bf8-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2bf8-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2bf8-2.h index 5bd2b7f..b46540b 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2bf8-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2bf8-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #include "fp8-helper.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2bf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2bf8s-2.c index 2a9caca..badd865 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2bf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2bf8s-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvt2ph2bf8s-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvt2ph2bf8s-2.c" +#include "avx10_2-vcvt2ph2bf8s-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvt2ph2bf8s-2.c" +#include "avx10_2-vcvt2ph2bf8s-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2bf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2bf8s-2.h index 33d9c0c..398c67b 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2bf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2bf8s-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #include "fp8-helper.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2hf8-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2hf8-2.c index 80dc248..4555b3d 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2hf8-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2hf8-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvt2ph2hf8-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvt2ph2hf8-2.c" +#include "avx10_2-vcvt2ph2hf8-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvt2ph2hf8-2.c" +#include "avx10_2-vcvt2ph2hf8-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2hf8-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2hf8-2.h index b9fdbd4..89a2c7e 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2hf8-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2hf8-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #include "fp8-helper.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2hf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2hf8s-2.c index 30f6a60..ba62e547 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2hf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2hf8s-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvt2ph2hf8s-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvt2ph2hf8s-2.c" +#include "avx10_2-vcvt2ph2hf8s-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvt2ph2hf8s-2.c" +#include "avx10_2-vcvt2ph2hf8s-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2hf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2hf8s-2.h index b9fdfac..2556c3f 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2hf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ph2hf8s-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #include "fp8-helper.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ps2phx-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ps2phx-2.c index 125713c..27735c0 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ps2phx-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ps2phx-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvt2ps2phx-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvt2ps2phx-2.c" +#include "avx10_2-vcvt2ps2phx-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvt2ps2phx-2.c" +#include "avx10_2-vcvt2ps2phx-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ps2phx-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ps2phx-2.h index f9f799a..f7d4365 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ps2phx-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvt2ps2phx-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbf162ibs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbf162ibs-2.c index 824ec68..a420901 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbf162ibs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbf162ibs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvtbf162ibs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtbf162ibs-2.c" +#include "avx10_2-vcvtbf162ibs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtbf162ibs-2.c" +#include "avx10_2-vcvtbf162ibs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbf162ibs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbf162ibs-2.h index 4976892..9f984d1 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbf162ibs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbf162ibs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <math.h> #include <limits.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbf162iubs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbf162iubs-2.c index b8f9925..7fdae8f 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbf162iubs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbf162iubs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvtbf162iubs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtbf162iubs-2.c" +#include "avx10_2-vcvtbf162iubs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtbf162iubs-2.c" +#include "avx10_2-vcvtbf162iubs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbf162iubs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbf162iubs-2.h index 03bd36a..b5eb59f 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbf162iubs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbf162iubs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <math.h> #include <limits.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2bf8-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2bf8-2.c index e3f2a81..7c56893 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2bf8-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2bf8-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvtbiasph2bf8-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtbiasph2bf8-2.c" +#include "avx10_2-vcvtbiasph2bf8-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtbiasph2bf8-2.c" +#include "avx10_2-vcvtbiasph2bf8-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2bf8-2.h index 4d90dcf8..42a81d8 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2bf8-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #include "fp8-helper.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2bf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2bf8s-2.c index 2b9f81d..3d2851b 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2bf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2bf8s-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvtbiasph2bf8s-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtbiasph2bf8s-2.c" +#include "avx10_2-vcvtbiasph2bf8s-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtbiasph2bf8s-2.c" +#include "avx10_2-vcvtbiasph2bf8s-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2bf8s-2.h index 93de7ea..2477960 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2bf8s-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #include "fp8-helper.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2hf8-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2hf8-2.c index 27e5f21..ac832d2 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2hf8-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2hf8-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvtbiasph2hf8-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtbiasph2hf8-2.c" +#include "avx10_2-vcvtbiasph2hf8-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtbiasph2hf8-2.c" +#include "avx10_2-vcvtbiasph2hf8-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2hf8-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2hf8-2.h index 14a2251..629c8a7 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2hf8-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2hf8-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #include "fp8-helper.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2hf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2hf8s-2.c index b93a1f978..bff5282 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2hf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2hf8s-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvtbiasph2hf8s-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtbiasph2hf8s-2.c" +#include "avx10_2-vcvtbiasph2hf8s-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtbiasph2hf8s-2.c" +#include "avx10_2-vcvtbiasph2hf8s-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2hf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2hf8s-2.h index 0333f08..fdda376 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2hf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtbiasph2hf8s-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #include "fp8-helper.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvthf82ph-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvthf82ph-2.c index d647fde..d6f5040 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvthf82ph-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvthf82ph-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvthf82ph-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL -#define AVX512F_LEN 256 +#define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvthf82ph-2.c" +#include "avx10_2-vcvthf82ph-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvthf82ph-2.c" +#include "avx10_2-vcvthf82ph-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvthf82ph-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvthf82ph-2.h index 9301ee3..7e9e894 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvthf82ph-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvthf82ph-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #include "fp8-helper.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2bf8-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2bf8-2.c index 826b5ff..aa10ebe 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2bf8-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2bf8-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvtph2bf8-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtph2bf8-2.c" +#include "avx10_2-vcvtph2bf8-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtph2bf8-2.c" +#include "avx10_2-vcvtph2bf8-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2bf8-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2bf8-2.h index f42f856..2ea3710 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2bf8-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2bf8-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #include "fp8-helper.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2bf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2bf8s-2.c index c5b9576..471e702 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2bf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2bf8s-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvtph2bf8s-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtph2bf8s-2.c" +#include "avx10_2-vcvtph2bf8s-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtph2bf8s-2.c" +#include "avx10_2-vcvtph2bf8s-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2bf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2bf8s-2.h index c22e1aa..242975d 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2bf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2bf8s-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #include "fp8-helper.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2hf8-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2hf8-2.c index 00f2928..e260dca 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2hf8-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2hf8-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvtph2hf8-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtph2hf8-2.c" +#include "avx10_2-vcvtph2hf8-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtph2hf8-2.c" +#include "avx10_2-vcvtph2hf8-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2hf8-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2hf8-2.h index e328e9d..84aba75 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2hf8-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2hf8-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #include "fp8-helper.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2hf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2hf8s-2.c index a2fa0c8..06882b8 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2hf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2hf8s-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvtph2hf8s-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtph2hf8s-2.c" +#include "avx10_2-vcvtph2hf8s-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtph2hf8s-2.c" +#include "avx10_2-vcvtph2hf8s-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2hf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2hf8s-2.h index e6872e8..28604c6 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2hf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2hf8s-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #include "fp8-helper.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2ibs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2ibs-2.c index 2265f81..627829c 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2ibs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2ibs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvtph2ibs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtph2ibs-2.c" +#include "avx10_2-vcvtph2ibs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtph2ibs-2.c" +#include "avx10_2-vcvtph2ibs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2ibs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2ibs-2.h index 2bddbb1..62fd1c5 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2ibs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2ibs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <string.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2iubs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2iubs-2.c index c4b2b575..009fcaf 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2iubs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2iubs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvtph2iubs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtph2iubs-2.c" +#include "avx10_2-vcvtph2iubs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtph2iubs-2.c" +#include "avx10_2-vcvtph2iubs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2iubs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2iubs-2.h index df73fcd..aa6ed98 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2iubs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtph2iubs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <string.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtps2ibs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtps2ibs-2.c index fdf825b..f5bd1dc 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtps2ibs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtps2ibs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvtps2ibs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtps2ibs-2.c" +#include "avx10_2-vcvtps2ibs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtps2ibs-2.c" +#include "avx10_2-vcvtps2ibs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtps2ibs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtps2ibs-2.h index 2ab24b9..7b8f3aa 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtps2ibs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtps2ibs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <math.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtps2iubs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtps2iubs-2.c index a27d5c7..f84dfb8 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvtps2iubs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtps2iubs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvtps2iubs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtps2iubs-2.c" +#include "avx10_2-vcvtps2iubs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvtps2iubs-2.c" +#include "avx10_2-vcvtps2iubs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtps2iubs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtps2iubs-2.h index 2b02ee3..0ffb3f9 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtps2iubs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvtps2iubs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <math.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttbf162ibs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttbf162ibs-2.c index 0585048..38359cb 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttbf162ibs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttbf162ibs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvttbf162ibs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttbf162ibs-2.c" +#include "avx10_2-vcvttbf162ibs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttbf162ibs-2.c" +#include "avx10_2-vcvttbf162ibs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttbf162ibs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttbf162ibs-2.h index 38154c8..a102091 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttbf162ibs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttbf162ibs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <math.h> #include <limits.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttbf162iubs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttbf162iubs-2.c index 3082ca0..88ad987 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttbf162iubs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttbf162iubs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvttbf162iubs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttbf162iubs-2.c" +#include "avx10_2-vcvttbf162iubs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttbf162iubs-2.c" +#include "avx10_2-vcvttbf162iubs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttbf162iubs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttbf162iubs-2.h index 9ca0912..6cfa5cb 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttbf162iubs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttbf162iubs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <math.h> #include <limits.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2dqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2dqs-2.c index d23024d..7ea6a63 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2dqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2dqs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvttpd2dqs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttpd2dqs-2.c" +#include "avx10_2-vcvttpd2dqs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttpd2dqs-2.c" +#include "avx10_2-vcvttpd2dqs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttpd2dqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2dqs-2.h index f56e568..002112f 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttpd2dqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2dqs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <string.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2qqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2qqs-2.c index d7aa1e5..b4c6102 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2qqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2qqs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvttpd2qqs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttpd2qqs-2.c" +#include "avx10_2-vcvttpd2qqs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttpd2qqs-2.c" +#include "avx10_2-vcvttpd2qqs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttpd2qqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2qqs-2.h index 4400c7c..0652ddd 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttpd2qqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2qqs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <string.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2udqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2udqs-2.c index 88caedf..b7463ed 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2udqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2udqs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvttpd2udqs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttpd2udqs-2.c" +#include "avx10_2-vcvttpd2udqs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttpd2udqs-2.c" +#include "avx10_2-vcvttpd2udqs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttpd2udqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2udqs-2.h index f687d0e..abcf56e 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttpd2udqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2udqs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <string.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2uqqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2uqqs-2.c index 3304eeb..fbd674a 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2uqqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2uqqs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvttpd2uqqs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttpd2uqqs-2.c" +#include "avx10_2-vcvttpd2uqqs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttpd2uqqs-2.c" +#include "avx10_2-vcvttpd2uqqs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttpd2uqqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2uqqs-2.h index 7b44cdd..664e59a 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttpd2uqqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2uqqs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <string.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttph2ibs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttph2ibs-2.c index dfa110c..312de25 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttph2ibs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttph2ibs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvttph2ibs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttph2ibs-2.c" +#include "avx10_2-vcvttph2ibs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttph2ibs-2.c" +#include "avx10_2-vcvttph2ibs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2ibs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttph2ibs-2.h index 13eb9f0..43446ed 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2ibs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttph2ibs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <string.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttph2iubs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttph2iubs-2.c index 500e323..19f67fb 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttph2iubs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttph2iubs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvttph2iubs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttph2iubs-2.c" +#include "avx10_2-vcvttph2iubs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttph2iubs-2.c" +#include "avx10_2-vcvttph2iubs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttph2iubs-2.h index 1db5a89..f77a8a6 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttph2iubs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <string.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2dqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2dqs-2.c index d2ef60b..bf34da9 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2dqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2dqs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvttps2dqs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttps2dqs-2.c" +#include "avx10_2-vcvttps2dqs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttps2dqs-2.c" +#include "avx10_2-vcvttps2dqs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2dqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2dqs-2.h index 0e9ee27..1209922 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2dqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2dqs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <string.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2ibs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2ibs-2.c index 7002945..1bf53e9 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2ibs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2ibs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvttps2ibs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttps2ibs-2.c" +#include "avx10_2-vcvttps2ibs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttps2ibs-2.c" +#include "avx10_2-vcvttps2ibs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2ibs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2ibs-2.h index c2dc7fe..bac56b8 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2ibs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2ibs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <math.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2iubs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2iubs-2.c index 4c05d3c..3cc711c 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2iubs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2iubs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvttps2iubs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttps2iubs-2.c" +#include "avx10_2-vcvttps2iubs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttps2iubs-2.c" +#include "avx10_2-vcvttps2iubs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2iubs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2iubs-2.h index 5f5ee8a..38f94bc 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2iubs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2iubs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <math.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2qqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2qqs-2.c index a7882ad..d5fcbe4 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2qqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2qqs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvttps2qqs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttps2qqs-2.c" +#include "avx10_2-vcvttps2qqs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttps2qqs-2.c" +#include "avx10_2-vcvttps2qqs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2qqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2qqs-2.h index 473fffa..7c247a0 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2qqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2qqs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <string.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2udqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2udqs-2.c index 66b654e..01ab0cd 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2udqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2udqs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvttps2udqs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttps2udqs-2.c" +#include "avx10_2-vcvttps2udqs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttps2udqs-2.c" +#include "avx10_2-vcvttps2udqs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2udqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2udqs-2.h index 5d7ee3c..5e7bddb 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2udqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2udqs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <string.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2uqqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2uqqs-2.c index 3f32060..8776a6c 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2uqqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2uqqs-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vcvttps2uqqs-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttps2uqqs-2.c" +#include "avx10_2-vcvttps2uqqs-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vcvttps2uqqs-2.c" +#include "avx10_2-vcvttps2uqqs-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2uqqs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2uqqs-2.h index 99ab0ce..dd05903 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2uqqs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2uqqs-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <limits.h> #include <string.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vdivbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vdivbf16-2.c index 69d5019..cf6a22b 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vdivbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vdivbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vdivbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vdivbf16-2.c" +#include "avx10_2-vdivbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vdivbf16-2.c" +#include "avx10_2-vdivbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vdivbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vdivbf16-2.h index ff68470..db64814 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vdivbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vdivbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vdpphps-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vdpphps-2.c index e2f422d..01c30dc 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vdpphps-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vdpphps-2.c @@ -1,16 +1,21 @@ -/* { dg-do run } */ +/* { dg-do run } */ /* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ +/* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vdpphps-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL -#define AVX512F_LEN 256 +#define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vdpphps-2.c" +#include "avx10_2-vdpphps-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF -#undef AVX512F_LEN -#undef AVX512F_LEN_HALF - -#define AVX512F_LEN 128 +#define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vdpphps-2.c" +#include "avx10_2-vdpphps-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vdpphps-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vdpphps-2.h index 8f815ce..3aad99a 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vdpphps-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vdpphps-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #define SRC_SIZE (AVX512F_LEN / 16) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vfmaddXXXbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vfmaddXXXbf16-2.c index 85041d4..6e27b19 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vfmaddXXXbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vfmaddXXXbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vfmaddXXXbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vfmaddXXXbf16-2.c" +#include "avx10_2-vfmaddXXXbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vfmaddXXXbf16-2.c" +#include "avx10_2-vfmaddXXXbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vfmaddXXXbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vfmaddXXXbf16-2.h index 6a50ede..fea8572 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vfmaddXXXbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vfmaddXXXbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vfmsubXXXbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vfmsubXXXbf16-2.c index 761d5d1..bcb2362 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vfmsubXXXbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vfmsubXXXbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vfmsubXXXbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vfmsubXXXbf16-2.c" +#include "avx10_2-vfmsubXXXbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vfmsubXXXbf16-2.c" +#include "avx10_2-vfmsubXXXbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vfmsubXXXbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vfmsubXXXbf16-2.h index 5869c5c..df49e80 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vfmsubXXXbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vfmsubXXXbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vfnmaddXXXbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vfnmaddXXXbf16-2.c index 9b260aa..c41a263 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vfnmaddXXXbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vfnmaddXXXbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vfnmaddXXXbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vfnmaddXXXbf16-2.c" +#include "avx10_2-vfnmaddXXXbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vfnmaddXXXbf16-2.c" +#include "avx10_2-vfnmaddXXXbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vfnmaddXXXbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vfnmaddXXXbf16-2.h index 2173cd3..fb55f39 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vfnmaddXXXbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vfnmaddXXXbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vfnmsubXXXbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vfnmsubXXXbf16-2.c index 86539f7..6a984c7 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vfnmsubXXXbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vfnmsubXXXbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vfnmsubXXXbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vfnmsubXXXbf16-2.c" +#include "avx10_2-vfnmsubXXXbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vfnmsubXXXbf16-2.c" +#include "avx10_2-vfnmsubXXXbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vfnmsubXXXbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vfnmsubXXXbf16-2.h index dc323fa..2d51ea4 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vfnmsubXXXbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vfnmsubXXXbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vfpclassbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vfpclassbf16-2.c index 40baeca..996782b 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vfpclassbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vfpclassbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vfpclassbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vfpclassbf16-2.c" +#include "avx10_2-vfpclassbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vfpclassbf16-2.c" +#include "avx10_2-vfpclassbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vfpclassbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vfpclassbf16-2.h index 1e8609d..f843f36 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vfpclassbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vfpclassbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vgetexpbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vgetexpbf16-2.c index e6a707c..4c05ccc 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vgetexpbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vgetexpbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vgetexpbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vgetexpbf16-2.c" +#include "avx10_2-vgetexpbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vgetexpbf16-2.c" +#include "avx10_2-vgetexpbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vgetexpbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vgetexpbf16-2.h index a920db5..9240857 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vgetexpbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vgetexpbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vgetmantbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vgetmantbf16-2.c index 9cdec14..bb455d6 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vgetmantbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vgetmantbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vgetmantbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vgetmantbf16-2.c" +#include "avx10_2-vgetmantbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vgetmantbf16-2.c" +#include "avx10_2-vgetmantbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vgetmantbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vgetmantbf16-2.h index 82e3663..be7eb4e 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vgetmantbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vgetmantbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vmaxbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vmaxbf16-2.c index 950870f..9b840c6 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vmaxbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vmaxbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vmaxbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vmaxbf16-2.c" +#include "avx10_2-vmaxbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vmaxbf16-2.c" +#include "avx10_2-vmaxbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vmaxbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vmaxbf16-2.h index 75236c6..d556ece 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vmaxbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vmaxbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vminbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vminbf16-2.c index 9786127..c7a3d33 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vminbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vminbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vminbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vminbf16-2.c" +#include "avx10_2-vminbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vminbf16-2.c" +#include "avx10_2-vminbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vminbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vminbf16-2.h index 3ca03cf..a5a1835 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vminbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vminbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxbf16-2.c index 0c181d9..b396d2c 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxbf16-2.c @@ -3,11 +3,15 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vminmaxbf16-2.h" + +#undef AVX512F_LEN + #define AVX512VL #define AVX512F_LEN 256 -#include "avx10_2-512-vminmaxbf16-2.c" +#include "avx10_2-vminmaxbf16-2.h" #undef AVX512F_LEN #define AVX512F_LEN 128 -#include "avx10_2-512-vminmaxbf16-2.c" +#include "avx10_2-vminmaxbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vminmaxbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxbf16-2.h index b1a7bed..42b7110 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vminmaxbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxbf16-2.h @@ -1,11 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-fsignaling-nans -mfpmath=sse -O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include <stdbool.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxpd-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxpd-2.c index 106083d..5be5053 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxpd-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxpd-2.c @@ -3,11 +3,15 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vminmaxpd-2.h" + +#undef AVX512F_LEN + #define AVX512VL #define AVX512F_LEN 256 -#include "avx10_2-512-vminmaxpd-2.c" +#include "avx10_2-vminmaxpd-2.h" #undef AVX512F_LEN #define AVX512F_LEN 128 -#include "avx10_2-512-vminmaxpd-2.c" +#include "avx10_2-vminmaxpd-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vminmaxpd-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxpd-2.h index 7bb531f..d595b6d 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vminmaxpd-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxpd-2.h @@ -1,11 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-fsignaling-nans -mfpmath=sse -O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 64) #include <stdbool.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxph-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxph-2.c index d465e7a..b4f3737 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxph-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxph-2.c @@ -3,13 +3,15 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vminmaxph-2.h" + +#undef AVX512F_LEN + #define AVX512VL #define AVX512F_LEN 256 -typedef _Float16 __m256h __attribute__ ((__vector_size__ (32), __may_alias__)); -#include "avx10_2-512-vminmaxph-2.c" +#include "avx10_2-vminmaxph-2.h" #undef AVX512F_LEN #define AVX512F_LEN 128 -typedef _Float16 __m128h __attribute__ ((__vector_size__ (16), __may_alias__)); -#include "avx10_2-512-vminmaxph-2.c" +#include "avx10_2-vminmaxph-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vminmaxph-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxph-2.h index 7647f8e..a215d96 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vminmaxph-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxph-2.h @@ -1,11 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-fsignaling-nans -mfpmath=sse -O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include <stdbool.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxps-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxps-2.c index 88aaf5b..41962c0 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxps-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxps-2.c @@ -3,11 +3,15 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vminmaxps-2.h" + +#undef AVX512F_LEN + #define AVX512VL #define AVX512F_LEN 256 -#include "avx10_2-512-vminmaxps-2.c" +#include "avx10_2-vminmaxps-2.h" #undef AVX512F_LEN #define AVX512F_LEN 128 -#include "avx10_2-512-vminmaxps-2.c" +#include "avx10_2-vminmaxps-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vminmaxps-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxps-2.h index 1eaa0b2..9ed09a6 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vminmaxps-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxps-2.h @@ -1,11 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-fsignaling-nans -mfpmath=sse -O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 32) #include <stdbool.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vmpsadbw-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vmpsadbw-2.c index fdf68e6..a925141 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vmpsadbw-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vmpsadbw-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vmpsadbw-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vmpsadbw-2.c" +#include "avx10_2-vmpsadbw-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vmpsadbw-2.c" +#include "avx10_2-vmpsadbw-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vmpsadbw-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vmpsadbw-2.h index a0a90f7..062594b 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vmpsadbw-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vmpsadbw-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SRC_SIZE (AVX512F_LEN / 8) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vmulbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vmulbf16-2.c index 568c0a9..d0f93d0 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vmulbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vmulbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vmulbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vmulbf16-2.c" +#include "avx10_2-vmulbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vmulbf16-2.c" +#include "avx10_2-vmulbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vmulbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vmulbf16-2.h index fe65d95..1b89350c 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vmulbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vmulbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbssd-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbssd-2.c index 256d10e..20ebdd5 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbssd-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbssd-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vpdpbssd-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpbssd-2.c" +#include "avx10_2-vpdpbssd-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpbssd-2.c" +#include "avx10_2-vpdpbssd-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbssd-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbssd-2.h index 493cd2b..046af0e 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbssd-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbssd-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #define SRC_SIZE (AVX512F_LEN / 8) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbssds-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbssds-2.c index 88ab613..4983cb9 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbssds-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbssds-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vpdpbssds-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpbssds-2.c" +#include "avx10_2-vpdpbssds-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpbssds-2.c" +#include "avx10_2-vpdpbssds-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbssds-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbssds-2.h index 479b893..e120ce1 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbssds-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbssds-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #define SRC_SIZE (AVX512F_LEN / 8) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbsud-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbsud-2.c index cdbd57c..967a96c 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbsud-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbsud-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vpdpbsud-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpbsud-2.c" +#include "avx10_2-vpdpbsud-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpbsud-2.c" +#include "avx10_2-vpdpbsud-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbsud-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbsud-2.h index d0c090d..d3f91b7 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbsud-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbsud-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #define SRC_SIZE (AVX512F_LEN / 8) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbsuds-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbsuds-2.c index 5e9937a..e03b228 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbsuds-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbsuds-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vpdpbsuds-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpbsuds-2.c" +#include "avx10_2-vpdpbsuds-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpbsuds-2.c" +#include "avx10_2-vpdpbsuds-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbsuds-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbsuds-2.h index 8d89c33..dd038fb 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbsuds-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbsuds-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #define SRC_SIZE (AVX512F_LEN / 8) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbuud-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbuud-2.c index 73e3f71..c6a0793 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbuud-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbuud-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vpdpbuud-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpbuud-2.c" +#include "avx10_2-vpdpbuud-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpbuud-2.c" +#include "avx10_2-vpdpbuud-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbuud-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbuud-2.h index 37a4a54..cc3927a 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbuud-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbuud-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #define SRC_SIZE (AVX512F_LEN / 8) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbuuds-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbuuds-2.c index 09c1c81..455943b 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbuuds-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbuuds-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vpdpbuuds-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpbuuds-2.c" +#include "avx10_2-vpdpbuuds-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpbuuds-2.c" +#include "avx10_2-vpdpbuuds-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbuuds-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbuuds-2.h index 8b18d6f..7721f0a 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbuuds-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpbuuds-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #define SRC_SIZE (AVX512F_LEN / 8) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwsud-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwsud-2.c index f68d3ed..eced929 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwsud-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwsud-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vpdpwsud-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpwsud-2.c" +#include "avx10_2-vpdpwsud-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpwsud-2.c" +#include "avx10_2-vpdpwsud-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwsud-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwsud-2.h index 824f814..99d3e14 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwsud-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwsud-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #define SRC_SIZE (AVX512F_LEN / 16) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwsuds-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwsuds-2.c index 3b3f5df..d551309 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwsuds-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwsuds-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vpdpwsuds-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpwsuds-2.c" +#include "avx10_2-vpdpwsuds-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpwsuds-2.c" +#include "avx10_2-vpdpwsuds-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwsuds-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwsuds-2.h index 7e51349..dd7d98c 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwsuds-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwsuds-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #define SRC_SIZE (AVX512F_LEN / 16) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwusd-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwusd-2.c index 209e62d..194f263d 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwusd-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwusd-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vpdpwusd-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpwusd-2.c" +#include "avx10_2-vpdpwusd-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpwusd-2.c" +#include "avx10_2-vpdpwusd-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwusd-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwusd-2.h index 4727d91..e8a6e6a 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwusd-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwusd-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #define SRC_SIZE (AVX512F_LEN / 16) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwusds-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwusds-2.c index 6e9692b..d87f0af 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwusds-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwusds-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vpdpwusds-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpwusds-2.c" +#include "avx10_2-vpdpwusds-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpwusds-2.c" +#include "avx10_2-vpdpwusds-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwusds-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwusds-2.h index 9f965df..5c294e0 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwusds-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwusds-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #define SRC_SIZE (AVX512F_LEN / 16) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwuud-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwuud-2.c index 8feb5d7..4b32bfd 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwuud-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwuud-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vpdpwuud-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpwuud-2.c" +#include "avx10_2-vpdpwuud-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpwuud-2.c" +#include "avx10_2-vpdpwuud-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwuud-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwuud-2.h index bf0a564..3e8b694 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwuud-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwuud-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #define SRC_SIZE (AVX512F_LEN / 16) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwuuds-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwuuds-2.c index 930839e..091d0be 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwuuds-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwuuds-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vpdpwuuds-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpwuuds-2.c" +#include "avx10_2-vpdpwuuds-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vpdpwuuds-2.c" +#include "avx10_2-vpdpwuuds-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwuuds-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwuuds-2.h index c075e0e..f4ff08a 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwuuds-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vpdpwuuds-2.h @@ -1,13 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif - #include "avx10-helper.h" #define SRC_SIZE (AVX512F_LEN / 16) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vrcpbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vrcpbf16-2.c index 367b2cf..ea4cd6c 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vrcpbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vrcpbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vrcpbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vrcpbf16-2.c" +#include "avx10_2-vrcpbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vrcpbf16-2.c" +#include "avx10_2-vrcpbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vrcpbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vrcpbf16-2.h index 28c7ada..bd0c3d2 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vrcpbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vrcpbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vreducebf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vreducebf16-2.c index 318e430..21ed844 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vreducebf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vreducebf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vreducebf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vreducebf16-2.c" +#include "avx10_2-vreducebf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vreducebf16-2.c" +#include "avx10_2-vreducebf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vreducebf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vreducebf16-2.h index d506389..e920e10 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vreducebf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vreducebf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vrndscalebf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vrndscalebf16-2.c index 5720438..66b0911 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vrndscalebf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vrndscalebf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vrndscalebf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vrndscalebf16-2.c" +#include "avx10_2-vrndscalebf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vrndscalebf16-2.c" +#include "avx10_2-vrndscalebf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vrndscalebf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vrndscalebf16-2.h index 1b29fc6..6a973c6 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vrndscalebf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vrndscalebf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vrsqrtbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vrsqrtbf16-2.c index 6083c86..9cebca9 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vrsqrtbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vrsqrtbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vrsqrtbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vrsqrtbf16-2.c" +#include "avx10_2-vrsqrtbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vrsqrtbf16-2.c" +#include "avx10_2-vrsqrtbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vrsqrtbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vrsqrtbf16-2.h index 444b332..14811bc 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vrsqrtbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vrsqrtbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <math.h> #define SIZE (AVX512F_LEN / 16) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vscalefbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vscalefbf16-2.c index 81b24f3..28f85bc 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vscalefbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vscalefbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vscalefbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vscalefbf16-2.c" +#include "avx10_2-vscalefbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vscalefbf16-2.c" +#include "avx10_2-vscalefbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vscalefbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vscalefbf16-2.h index b1c5f4b..08565f2 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vscalefbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vscalefbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vsqrtbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vsqrtbf16-2.c index 5188e05..288c22b 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vsqrtbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vsqrtbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vsqrtbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vsqrtbf16-2.c" +#include "avx10_2-vsqrtbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vsqrtbf16-2.c" +#include "avx10_2-vsqrtbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vsqrtbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vsqrtbf16-2.h index 12f87b3..30e1bd2 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vsqrtbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vsqrtbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #include <math.h> #define SIZE (AVX512F_LEN / 16) diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vsubbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vsubbf16-2.c index 16f444a..09f05a0 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-vsubbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vsubbf16-2.c @@ -3,14 +3,19 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 +#include "avx10_2-vsubbf16-2.h" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + #define AVX512VL #define AVX512F_LEN 256 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vsubbf16-2.c" +#include "avx10_2-vsubbf16-2.h" #undef AVX512F_LEN #undef AVX512F_LEN_HALF #define AVX512F_LEN 128 #define AVX512F_LEN_HALF 128 -#include "avx10_2-512-vsubbf16-2.c" +#include "avx10_2-vsubbf16-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vsubbf16-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-vsubbf16-2.h index 16a5ace..379d840 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vsubbf16-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-vsubbf16-2.h @@ -1,12 +1,3 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx10.2" } */ -/* { dg-require-effective-target avx10_2 } */ - -#ifndef AVX10_2 -#define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT -#endif #include "avx10-helper.h" #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vmovdqu16-1.c b/gcc/testsuite/gcc.target/i386/avx512bw-vmovdqu16-1.c index 8603a19..ee8e5cf 100644 --- a/gcc/testsuite/gcc.target/i386/avx512bw-vmovdqu16-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512bw-vmovdqu16-1.c @@ -16,11 +16,11 @@ /* { dg-final { scan-assembler-times "vmovdqu16\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmovdqu16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmovdqu16\[ \\t\]+\[^\{\n\]*\\)\[^\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "(?:vmovdqu16|vinserti128)\[ \\t\]+\[^\{\n\]*\\)\[^\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vmovdqu16\[ \\t\]+\[^\{\n\]*\\)\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "(?:vmovdqu|vinserti128)\[ \\t\]+\[^\{\n\]*\\)\[^\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\{\n\]*\\)\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmovdqu16\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "(?:vmovdqu16|vextracti128)\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vmovdqu16\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "(?:vmovdqu|vextracti128)\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vmovdqu8-1.c b/gcc/testsuite/gcc.target/i386/avx512bw-vmovdqu8-1.c index d1e3392..4c4cddb 100644 --- a/gcc/testsuite/gcc.target/i386/avx512bw-vmovdqu8-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512bw-vmovdqu8-1.c @@ -16,9 +16,9 @@ /* { dg-final { scan-assembler-times "vmovdqu8\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmovdqu8\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmovdqu8\[ \\t\]+\[^\{\n\]*\\)\[^\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vmovdqu8\[ \\t\]+\[^\{\n\]*\\)\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\{\n\]*\\)\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vmovdqu8\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vmovdqu8\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-helper.h b/gcc/testsuite/gcc.target/i386/avx512f-helper.h index 41f09e3..f008981 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-helper.h +++ b/gcc/testsuite/gcc.target/i386/avx512f-helper.h @@ -97,7 +97,7 @@ MAKE_MASK_ZERO(bf16_bf, __bf16) /* Function which calculates result. */ #define CALC EVAL(calc_, AVX512F_LEN,) -#if !defined(AVX512VL) || defined(AVX10_512BIT) +#if !defined(AVX512VL) #define AVX512F_LEN 512 #define AVX512F_LEN_HALF 256 #endif diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr103750-3.c b/gcc/testsuite/gcc.target/i386/avx512f-pr103750-3.c new file mode 100644 index 0000000..9965e63 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-pr103750-3.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v4 -mprefer-vector-width=256 -Ofast" } */ +/* { dg-final { scan-assembler-not "kmov" } } */ + +void +foo (double* a, double* __restrict b, double* c, double* d, int n) +{ + for (int i = 0; i != n; i++) + { + double tmp = 0.0; + if (c[i] > d[i]) + tmp = b[i]; + a[i] = tmp; + } +} + +void +foo1 (double* a, double* __restrict b, double* c, double* d, int n) +{ + for (int i = 0; i != n; i++) + { + double tmp = 0.0; + if (c[i] > d[i]) + a[i] = b[i]; + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-13.c b/gcc/testsuite/gcc.target/i386/avx512fp16-13.c index 2416c67..92ac197 100644 --- a/gcc/testsuite/gcc.target/i386/avx512fp16-13.c +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-13.c @@ -71,7 +71,7 @@ load256u_ph (void const *p) return _mm256_loadu_ph (p); } -/* { dg-final { scan-assembler-times "vmovdqu16\[ \\t\]*\[^,\]*,\[^\{\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]*\[^,\]*,\[^\{\n\]*%ymm\[0-9\]" 1 } } */ __m128h __attribute__ ((noinline, noclone)) @@ -80,7 +80,7 @@ load128u_ph (void const *p) return _mm_loadu_ph (p); } -/* { dg-final { scan-assembler-times "vmovdqu16\[ \\t\]*\[^,\]*,\[^\{\n\]*%xmm\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]*\[^,\]*,\[^\{\n\]*%xmm\[0-9\]" 1 } } */ void __attribute__ ((noinline, noclone)) @@ -89,7 +89,7 @@ store512u_ph (void *p, __m512h a) return _mm512_storeu_ph (p, a); } -/* { dg-final { scan-assembler-times "vmovdqu16\[ \\t\]*\[^\{\n\]*%zmm\[0-9\], *\[^,\]*" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]*\[^\{\n\]*%zmm\[0-9\], *\[^,\]*" 1 } } */ void __attribute__ ((noinline, noclone)) @@ -98,7 +98,7 @@ store256u_ph (void *p, __m256h a) return _mm256_storeu_ph (p, a); } -/* { dg-final { scan-assembler-times "vmovdqu16\[ \\t\]*\[^\{\n\]*%ymm\[0-9\], *\[^,\]*" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]*\[^\{\n\]*%ymm\[0-9\], *\[^,\]*" 1 } } */ void __attribute__ ((noinline, noclone)) @@ -107,7 +107,7 @@ storeu_ph (void *p, __m128h a) return _mm_storeu_ph (p, a); } -/* { dg-final { scan-assembler-times "vmovdqu16\[ \\t\]*\[^\{\n\]*%xmm\[0-9\], *\[^,\]*" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]*\[^\{\n\]*%xmm\[0-9\], *\[^,\]*" 1 } } */ __m512h __attribute__ ((noinline, noclone)) diff --git a/gcc/testsuite/gcc.target/i386/cold-attribute-4.c b/gcc/testsuite/gcc.target/i386/cold-attribute-4.c index 37a41e9..e0808c5 100644 --- a/gcc/testsuite/gcc.target/i386/cold-attribute-4.c +++ b/gcc/testsuite/gcc.target/i386/cold-attribute-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2" } */ +/* { dg-options "-Oz" } */ #include <string.h> int diff --git a/gcc/testsuite/gcc.target/i386/crc-builtin-crc32.c b/gcc/testsuite/gcc.target/i386/crc-builtin-crc32.c new file mode 100644 index 0000000..0b4ff97 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/crc-builtin-crc32.c @@ -0,0 +1,22 @@ +/* PR target/120719 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcrc32" } */ + +#include <stdint-gcc.h> + +int32_t rev_crc32_data8 (int8_t v) +{ + return __builtin_rev_crc32_data8 (0xffffffff, v, 0x1EDC6F41); +} + +int32_t rev_crc32_data16 (int16_t v) +{ + return __builtin_rev_crc32_data16 (0xffffffff, v, 0x1EDC6F41); +} + +int32_t rev_crc32_data32 (int32_t v) +{ + return __builtin_rev_crc32_data32 (0xffffffff, v, 0x1EDC6F41); +} + +/* { dg-final { scan-assembler-times "\tcrc32" 3 } } */ diff --git a/gcc/testsuite/gcc.target/i386/interrupt-16.c b/gcc/testsuite/gcc.target/i386/interrupt-16.c index cb45ba5..ca4441b 100644 --- a/gcc/testsuite/gcc.target/i386/interrupt-16.c +++ b/gcc/testsuite/gcc.target/i386/interrupt-16.c @@ -18,5 +18,5 @@ foo (int i) /* { dg-final { scan-assembler-not "(push|pop)(l|q)\[\\t \]*%(r|e)bp" } } */ /* { dg-final { scan-assembler-not "(push|pop)l\[\\t \]*%edi" { target ia32 } } } */ /* { dg-final { scan-assembler-not "(push|pop)q\[\\t \]*%r\[0-9\]+" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-times "pushq\[\\t \]*%rdi" 1 { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-times "popq\[\\t \]*%rdi" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "(pushq.*%rdi|subq.*\\\$8,.*%rsp)" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "(popq.*%rdi|addq.*\\\$8,.*%rsp)" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/keylocker-aesdecwide128kl.c b/gcc/testsuite/gcc.target/i386/keylocker-aesdecwide128kl.c index 93806e5..e73ba35 100644 --- a/gcc/testsuite/gcc.target/i386/keylocker-aesdecwide128kl.c +++ b/gcc/testsuite/gcc.target/i386/keylocker-aesdecwide128kl.c @@ -19,14 +19,14 @@ /* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\\n\\r\]*%xmm5,\[^\\n\\r\]*80\[^\\n\\r\]*" } } */ /* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\\n\\r\]*%xmm6,\[^\\n\\r\]*96\[^\\n\\r\]*" } } */ /* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\\n\\r\]*%xmm7,\[^\\n\\r\]*112\[^\\n\\r\]*" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm2, %xmm2" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm3, %xmm3" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm4, %xmm4" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm5, %xmm5" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm6, %xmm6" } } */ /* { dg-final { scan-assembler "pxor\[ \t\]+%xmm7, %xmm7" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm0" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm1" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm2" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm3" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm4" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm5" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm6" } } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/keylocker-aesdecwide256kl.c b/gcc/testsuite/gcc.target/i386/keylocker-aesdecwide256kl.c index f9ccc82..33cd998 100644 --- a/gcc/testsuite/gcc.target/i386/keylocker-aesdecwide256kl.c +++ b/gcc/testsuite/gcc.target/i386/keylocker-aesdecwide256kl.c @@ -19,14 +19,14 @@ /* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\\n\\r\]*%xmm5,\[^\\n\\r\]*80\[^\\n\\r\]*" } } */ /* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\\n\\r\]*%xmm6,\[^\\n\\r\]*96\[^\\n\\r\]*" } } */ /* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\\n\\r\]*%xmm7,\[^\\n\\r\]*112\[^\\n\\r\]*" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm2, %xmm2" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm3, %xmm3" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm4, %xmm4" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm5, %xmm5" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm6, %xmm6" } } */ /* { dg-final { scan-assembler "pxor\[ \t\]+%xmm7, %xmm7" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm0" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm1" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm2" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm3" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm4" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm5" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm6" } } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/keylocker-aesencwide128kl.c b/gcc/testsuite/gcc.target/i386/keylocker-aesencwide128kl.c index c0fcd28..75106e5 100644 --- a/gcc/testsuite/gcc.target/i386/keylocker-aesencwide128kl.c +++ b/gcc/testsuite/gcc.target/i386/keylocker-aesencwide128kl.c @@ -19,14 +19,14 @@ /* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\\n\\r\]*%xmm5,\[^\\n\\r\]*80\[^\\n\\r\]*" } } */ /* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\\n\\r\]*%xmm6,\[^\\n\\r\]*96\[^\\n\\r\]*" } } */ /* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\\n\\r\]*%xmm7,\[^\\n\\r\]*112\[^\\n\\r\]*" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm2, %xmm2" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm3, %xmm3" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm4, %xmm4" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm5, %xmm5" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm6, %xmm6" } } */ /* { dg-final { scan-assembler "pxor\[ \t\]+%xmm7, %xmm7" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm0" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm1" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm2" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm3" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm4" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm5" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm6" } } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/keylocker-aesencwide256kl.c b/gcc/testsuite/gcc.target/i386/keylocker-aesencwide256kl.c index 31463a8..2787732 100644 --- a/gcc/testsuite/gcc.target/i386/keylocker-aesencwide256kl.c +++ b/gcc/testsuite/gcc.target/i386/keylocker-aesencwide256kl.c @@ -19,14 +19,14 @@ /* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\\n\\r\]*%xmm5,\[^\\n\\r\]*80\[^\\n\\r\]*" } } */ /* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\\n\\r\]*%xmm6,\[^\\n\\r\]*96\[^\\n\\r\]*" } } */ /* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\\n\\r\]*%xmm7,\[^\\n\\r\]*112\[^\\n\\r\]*" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm2, %xmm2" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm3, %xmm3" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm4, %xmm4" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm5, %xmm5" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm6, %xmm6" } } */ /* { dg-final { scan-assembler "pxor\[ \t\]+%xmm7, %xmm7" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm0" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm1" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm2" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm3" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm4" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm5" } } */ +/* { dg-final { scan-assembler "movdqa\[ \t\]+%xmm7, %xmm6" } } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-1.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-1.c new file mode 100644 index 0000000..b1f6678 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-1.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mno-sse -mmemcpy-strategy=unrolled_loop:256:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** movq 221\(%rsi\), %rax +** xorl %edx, %edx +** movq %rax, 221\(%rdi\) +** movq 229\(%rsi\), %rax +** movq %rax, 229\(%rdi\) +** movq 237\(%rsi\), %rax +** movq %rax, 237\(%rdi\) +** movq 245\(%rsi\), %rax +** movq %rax, 245\(%rdi\) +**.L[0-9]+: +** movl %edx, %eax +** addl \$32, %edx +** movq \(%rsi,%rax\), %r10 +** movq 8\(%rsi,%rax\), %r9 +** movq 16\(%rsi,%rax\), %r8 +** movq 24\(%rsi,%rax\), %rcx +** movq %r10, \(%rdi,%rax\) +** movq %r9, 8\(%rdi,%rax\) +** movq %r8, 16\(%rdi,%rax\) +** movq %rcx, 24\(%rdi,%rax\) +** cmpl \$224, %edx +** jb .L[0-9]+ +** ret +**... +*/ + +void +foo (char *dest, char *src) +{ + __builtin_memcpy (dest, src, 253); +} + +/* { dg-final { scan-assembler-not "rep mov" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-2.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-2.c new file mode 100644 index 0000000..0d0e348 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-2.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** xorl %edx, %edx +**.L[0-9]+: +** movl %edx, %eax +** addl \$64, %edx +** movdqa src\(%rax\), %xmm3 +** movdqa src\+16\(%rax\), %xmm2 +** movdqa src\+32\(%rax\), %xmm1 +** movdqa src\+48\(%rax\), %xmm0 +** movaps %xmm3, dest\(%rax\) +** movaps %xmm2, dest\+16\(%rax\) +** movaps %xmm1, dest\+32\(%rax\) +** movaps %xmm0, dest\+48\(%rax\) +** cmpl \$256, %edx +** jb .L[0-9]+ +** movdqa src\(%rdx\), %xmm0 +** movaps %xmm0, dest\(%rdx\) +** ret +**... +*/ + +#define SIZE (16 + 1) * 16 + +char dest[SIZE]; +char src[SIZE]; + +void +foo (void) +{ + __builtin_memcpy (dest, src, SIZE); +} + +/* { dg-final { scan-assembler-not "rep mov" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-3.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-3.c new file mode 100644 index 0000000..e5aca32 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-3.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** xorl %edx, %edx +**.L[0-9]+: +** movl %edx, %eax +** addl \$64, %edx +** movdqa src\(%rax\), %xmm3 +** movdqa src\+16\(%rax\), %xmm2 +** movdqa src\+32\(%rax\), %xmm1 +** movdqa src\+48\(%rax\), %xmm0 +** movaps %xmm3, dest\(%rax\) +** movaps %xmm2, dest\+16\(%rax\) +** movaps %xmm1, dest\+32\(%rax\) +** movaps %xmm0, dest\+48\(%rax\) +** cmpl \$256, %edx +** jb .L[0-9]+ +** movdqa src\(%rdx\), %xmm0 +** movaps %xmm0, dest\(%rdx\) +** movdqu src\+15\(%rdx\), %xmm0 +** movups %xmm0, dest\+15\(%rdx\) +** ret +**... +*/ + +#define SIZE 16 * 16 + 31 + +char dest[SIZE]; +char src[SIZE]; + +void +foo (void) +{ + __builtin_memcpy (dest, src, SIZE); +} + +/* { dg-final { scan-assembler-not "rep mov" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-4.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-4.c new file mode 100644 index 0000000..27f7bed --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-4.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** xorl %edx, %edx +**.L[0-9]+: +** movl %edx, %eax +** subl \$-128, %edx +** vmovdqa src\(%rax\), %ymm3 +** vmovdqa src\+32\(%rax\), %ymm2 +** vmovdqa src\+64\(%rax\), %ymm1 +** vmovdqa src\+96\(%rax\), %ymm0 +** vmovdqa %ymm3, dest\(%rax\) +** vmovdqa %ymm2, dest\+32\(%rax\) +** vmovdqa %ymm1, dest\+64\(%rax\) +** vmovdqa %ymm0, dest\+96\(%rax\) +** cmpl \$512, %edx +** jb .L[0-9]+ +** vmovdqa src\(%rdx\), %ymm0 +** vmovdqa %ymm0, dest\(%rdx\) +** vzeroupper +** ret +**... +*/ + +#define SIZE (16 + 1) * 32 + +char dest[SIZE]; +char src[SIZE]; + +void +foo (void) +{ + __builtin_memcpy (dest, src, SIZE); +} + +/* { dg-final { scan-assembler-not "rep mov" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-5.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-5.c new file mode 100644 index 0000000..34a7408 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-5.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** xorl %edx, %edx +**.L[0-9]+: +** movl %edx, %eax +** subl \$-128, %edx +** vmovdqa src\(%rax\), %ymm3 +** vmovdqa src\+32\(%rax\), %ymm2 +** vmovdqa src\+64\(%rax\), %ymm1 +** vmovdqa src\+96\(%rax\), %ymm0 +** vmovdqa %ymm3, dest\(%rax\) +** vmovdqa %ymm2, dest\+32\(%rax\) +** vmovdqa %ymm1, dest\+64\(%rax\) +** vmovdqa %ymm0, dest\+96\(%rax\) +** cmpl \$512, %edx +** jb .L[0-9]+ +** vmovdqa src\(%rdx\), %ymm0 +** vmovdqa %ymm0, dest\(%rdx\) +** vmovdqu src\+31\(%rdx\), %ymm0 +** vmovdqu %ymm0, dest\+31\(%rdx\) +** vzeroupper +** ret +**... +*/ + +#define SIZE 16 * 32 + 32 + 31 + +char dest[SIZE]; +char src[SIZE]; + +void +foo (void) +{ + __builtin_memcpy (dest, src, SIZE); +} + +/* { dg-final { scan-assembler-not "rep mov" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-6.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-6.c new file mode 100644 index 0000000..aa5d90d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-6.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** xorl %edx, %edx +**.L[0-9]+: +** movl %edx, %eax +** addl \$256, %edx +** vmovdqa64 src\(%rax\), %zmm3 +** vmovdqa64 src\+64\(%rax\), %zmm2 +** vmovdqa64 src\+128\(%rax\), %zmm1 +** vmovdqa64 src\+192\(%rax\), %zmm0 +** vmovdqa64 %zmm3, dest\(%rax\) +** vmovdqa64 %zmm2, dest\+64\(%rax\) +** vmovdqa64 %zmm1, dest\+128\(%rax\) +** vmovdqa64 %zmm0, dest\+192\(%rax\) +** cmpl \$1024, %edx +** jb .L[0-9]+ +** vmovdqa64 src\(%rdx\), %zmm0 +** vmovdqa64 %zmm0, dest\(%rdx\) +** vzeroupper +** ret +**... +*/ + +#define SIZE (16 + 1) * 64 + +char dest[SIZE] __attribute__((aligned(64))); +char src[SIZE] __attribute__((aligned(64))); + +void +foo (void) +{ + __builtin_memcpy (dest, src, SIZE); +} + +/* { dg-final { scan-assembler-not "rep mov" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120683-7.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-7.c new file mode 100644 index 0000000..63d8a15 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120683-7.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** xorl %edx, %edx +**.L[0-9]+: +** movl %edx, %eax +** addl \$256, %edx +** vmovdqa64 src\(%rax\), %zmm3 +** vmovdqa64 src\+64\(%rax\), %zmm2 +** vmovdqa64 src\+128\(%rax\), %zmm1 +** vmovdqa64 src\+192\(%rax\), %zmm0 +** vmovdqa64 %zmm3, dest\(%rax\) +** vmovdqa64 %zmm2, dest\+64\(%rax\) +** vmovdqa64 %zmm1, dest\+128\(%rax\) +** vmovdqa64 %zmm0, dest\+192\(%rax\) +** cmpl \$1024, %edx +** jb .L[0-9]+ +** vmovdqa src\(%rdx\), %ymm0 +** vmovdqa %ymm0, dest\(%rdx\) +** vmovdqu src\+31\(%rdx\), %ymm0 +** vmovdqu %ymm0, dest\+31\(%rdx\) +** vzeroupper +** ret +**... +*/ + +#define SIZE 16 * 64 + 63 + +char dest[SIZE] __attribute__((aligned(64))); +char src[SIZE] __attribute__((aligned(64))); + +void +foo (void) +{ + __builtin_memcpy (dest, src, SIZE); +} + +/* { dg-final { scan-assembler-not "rep mov" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120708-1.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120708-1.c new file mode 100644 index 0000000..d4fe2adc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120708-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-options "-O2 -march=atom -minline-all-stringops -mstringop-strategy=vector_loop" } */ +/* { dg-final { scan-assembler-not "movdqa" } } */ + +char a[2048]; +char b[2048]; +void t (void) +{ + __builtin_memcpy (a, b, 2048); +} diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120708-2.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120708-2.c new file mode 100644 index 0000000..9a6fcfd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120708-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-options "-O2 -march=atom -minline-all-stringops -mstringop-strategy=vector_loop" } */ +/* { dg-final { scan-assembler-not "movdqa" } } */ + +char *a; +char *b; +void t (void) +{ + __builtin_memcpy (a, b, 2048); +} diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120708-3.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120708-3.c new file mode 100644 index 0000000..010ac24 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120708-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-options "-O2 -march=atom -mmemcpy-strategy=vector_loop:-1:align" } */ +/* { dg-final { scan-assembler-not "movdqa" } } */ + +char a[2048]; +char b[2048]; +void t (void) +{ + __builtin_memcpy (a, b, 2048); +} diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120708-4.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120708-4.c new file mode 100644 index 0000000..87a58ef --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120708-4.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-options "-O2 -march=atom -mmemcpy-strategy=vector_loop:3000:align,libcall:-1:align" } */ +/* { dg-final { scan-assembler-not "movdqa" } } */ + +char a[2048]; +char b[2048]; +void t (void) +{ + __builtin_memcpy (a, b, 2048); +} diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120708-5.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120708-5.c new file mode 100644 index 0000000..19e0600 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120708-5.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -mprefer-vector-width=128 -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ + +#define SIZE (16 + 1) * 16 + +char dest[SIZE]; +char src[SIZE]; + +void +foo (void) +{ + __builtin_memcpy (dest, src, SIZE); +} + +/* { dg-final { scan-assembler-times "vmovdqa\[ \t]\+\[^\n\r]*%xmm\[0-9\]\+" 10 } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-pr120708-6.c b/gcc/testsuite/gcc.target/i386/memcpy-pr120708-6.c new file mode 100644 index 0000000..17b101f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-pr120708-6.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -mprefer-vector-width=256 -mmemcpy-strategy=vector_loop:2048:noalign,libcall:-1:noalign" } */ + +#define SIZE (16 + 1) * 32 + +char dest[SIZE]; +char src[SIZE]; + +void +foo (void) +{ + __builtin_memcpy (dest, src, SIZE); +} + +/* { dg-final { scan-assembler-times "vmovdqa\[ \t]\+\[^\n\r]*%ymm\[0-9\]\+" 10 } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-strategy-1.c b/gcc/testsuite/gcc.target/i386/memcpy-strategy-1.c index 6ac80c9..b298673 100644 --- a/gcc/testsuite/gcc.target/i386/memcpy-strategy-1.c +++ b/gcc/testsuite/gcc.target/i386/memcpy-strategy-1.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { *-*-* } { "-march=*" } { "-march=atom" } } */ -/* { dg-options "-O2 -march=atom -mmemcpy-strategy=vector_loop:-1:align" } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -mtune-ctrl=^sse_typeless_stores -mmemcpy-strategy=vector_loop:-1:align" } */ /* { dg-final { scan-assembler-times "movdqa" 8 } } */ char a[2048]; diff --git a/gcc/testsuite/gcc.target/i386/memcpy-strategy-12.c b/gcc/testsuite/gcc.target/i386/memcpy-strategy-12.c new file mode 100644 index 0000000..c60cef0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-strategy-12.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic -mno-sse -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** movq 221\(%rsi\), %rax +** xorl %edx, %edx +** movq %rax, 221\(%rdi\) +** movq 229\(%rsi\), %rax +** movq %rax, 229\(%rdi\) +** movq 237\(%rsi\), %rax +** movq %rax, 237\(%rdi\) +** movq 245\(%rsi\), %rax +** movq %rax, 245\(%rdi\) +**.L[0-9]+: +** movl %edx, %eax +** addl \$32, %edx +** movq \(%rsi,%rax\), %r10 +** movq 8\(%rsi,%rax\), %r9 +** movq 16\(%rsi,%rax\), %r8 +** movq 24\(%rsi,%rax\), %rcx +** movq %r10, \(%rdi,%rax\) +** movq %r9, 8\(%rdi,%rax\) +** movq %r8, 16\(%rdi,%rax\) +** movq %rcx, 24\(%rdi,%rax\) +** cmpl \$224, %edx +** jb .L[0-9]+ +** ret +**... +*/ + +void +foo (char *dest, char *src) +{ + __builtin_memcpy (dest, src, 253); +} + +/* { dg-final { scan-assembler-not "rep mov" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-strategy-13.c b/gcc/testsuite/gcc.target/i386/memcpy-strategy-13.c new file mode 100644 index 0000000..109bd67 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-strategy-13.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic -mno-avx" } */ +/* { dg-final { scan-assembler "jmp\tmemcpy" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\tmemcpy" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "rep movsb" } } */ + +void +foo (char *dest, char *src) +{ + __builtin_memcpy (dest, src, 257); +} diff --git a/gcc/testsuite/gcc.target/i386/memcpy-strategy-2.c b/gcc/testsuite/gcc.target/i386/memcpy-strategy-2.c index c103896..18e260b 100644 --- a/gcc/testsuite/gcc.target/i386/memcpy-strategy-2.c +++ b/gcc/testsuite/gcc.target/i386/memcpy-strategy-2.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { *-*-* } { "-march=*" } { "-march=atom" } } */ -/* { dg-options "-O2 -march=atom -mmemcpy-strategy=vector_loop:3000:align,libcall:-1:align" } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -mtune-ctrl=^sse_typeless_stores -mmemcpy-strategy=vector_loop:3000:align,libcall:-1:align" } */ /* { dg-final { scan-assembler-times "movdqa" 8 } } */ char a[2048]; diff --git a/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-1.c b/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-1.c index 93f428a..cec8c90 100644 --- a/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-1.c +++ b/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-1.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { *-*-* } { "-march=*" } { "-march=atom" } } */ -/* { dg-options "-O2 -march=atom -minline-all-stringops -mstringop-strategy=vector_loop" } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -mtune-ctrl=^sse_typeless_stores -minline-all-stringops -mstringop-strategy=vector_loop" } */ /* { dg-final { scan-assembler-times "movdqa" 8 } } */ char a[2048]; diff --git a/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-2.c b/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-2.c index ab23540..314eb3d 100644 --- a/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-2.c +++ b/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-2.c @@ -1,7 +1,6 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { *-*-* } { "-march=*" } { "-march=atom" } } */ -/* { dg-options "-O2 -march=atom -minline-all-stringops -mstringop-strategy=vector_loop" } */ -/* { dg-final { scan-assembler-times "movdqa" 4} } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -mtune-ctrl=^sse_typeless_stores -minline-all-stringops -mstringop-strategy=vector_loop" } */ +/* { dg-final { scan-assembler-times "movdqa" 4 } } */ char *a; char *b; diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-1.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-1.c new file mode 100644 index 0000000..06e3892 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-1.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** pxor %xmm0, %xmm0 +** xorl %eax, %eax +** movups %xmm0, 190\(%rdi\) +** movups %xmm0, 206\(%rdi\) +** movups %xmm0, 222\(%rdi\) +** movups %xmm0, 238\(%rdi\) +**.L[0-9]+: +** movl %eax, %edx +** addl \$64, %eax +** movups %xmm0, \(%rdi,%rdx\) +** movups %xmm0, 16\(%rdi,%rdx\) +** movups %xmm0, 32\(%rdi,%rdx\) +** movups %xmm0, 48\(%rdi,%rdx\) +** cmpl \$192, %eax +** jb .L[0-9]+ +** ret +**... +*/ + +void +foo (char *dest) +{ + __builtin_memset (dest, 0, 254); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-10.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-10.c new file mode 100644 index 0000000..36a924d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-10.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-sse -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=unrolled_loop:256:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** movq \$0, 48\(%rdi\) +** movq \$0, \(%rdi\) +** movq \$0, 8\(%rdi\) +** movq \$0, 16\(%rdi\) +** movq \$0, 24\(%rdi\) +** movq \$0, 32\(%rdi\) +** movq \$0, 40\(%rdi\) +** movq \$0, 53\(%rdi\) +** ret +**... +*/ + +void +foo (char *dest) +{ + __builtin_memset (dest, 0, 61); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-11.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-11.c new file mode 100644 index 0000000..4868e56 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-11.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-sse -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=unrolled_loop:256:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** movabsq \$289360691352306692, %rax +** movq %rax, 48\(%rdi\) +** movq %rax, \(%rdi\) +** movq %rax, 8\(%rdi\) +** movq %rax, 16\(%rdi\) +** movq %rax, 24\(%rdi\) +** movq %rax, 32\(%rdi\) +** movq %rax, 40\(%rdi\) +** movq %rax, 53\(%rdi\) +** ret +**... +*/ + +void +foo (char *dest) +{ + __builtin_memset (dest, 4, 61); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-12.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-12.c new file mode 100644 index 0000000..9112897 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-12.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-sse -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=unrolled_loop:256:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** movabsq \$72340172838076673, %rax +** movzbl %sil, %esi +** imulq %rax, %rsi +** movq %rsi, 48\(%rdi\) +** movq %rsi, \(%rdi\) +** movq %rsi, 8\(%rdi\) +** movq %rsi, 16\(%rdi\) +** movq %rsi, 24\(%rdi\) +** movq %rsi, 32\(%rdi\) +** movq %rsi, 40\(%rdi\) +** movq %rsi, 53\(%rdi\) +** ret +**... +*/ + +void +foo (char *dest, int c) +{ + __builtin_memset (dest, c, 61); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-13.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-13.c new file mode 100644 index 0000000..69ec6c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-13.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** pxor %xmm0, %xmm0 +** xorl %eax, %eax +**.L[0-9]+: +** movl %eax, %edx +** addl \$64, %eax +** movaps %xmm0, dest\(%rdx\) +** movaps %xmm0, dest\+16\(%rdx\) +** movaps %xmm0, dest\+32\(%rdx\) +** movaps %xmm0, dest\+48\(%rdx\) +** cmpl \$192, %eax +** jb .L[0-9]+ +** movaps %xmm0, dest\(%rax\) +** movaps %xmm0, dest\+16\(%rax\) +** movaps %xmm0, dest\+32\(%rax\) +** ret +**... +*/ + +char dest[240]; + +void +foo (void) +{ + __builtin_memset (dest, 0, sizeof (dest)); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-14.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-14.c new file mode 100644 index 0000000..209cd67 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-14.c @@ -0,0 +1,91 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB0: +** .cfi_startproc +** pxor %xmm0, %xmm0 +** cmpq \$64, %rsi +** jnb .L2 +** testb \$32, %sil +** jne .L19 +** testb \$16, %sil +** jne .L20 +** testb \$8, %sil +** jne .L21 +** testb \$4, %sil +** jne .L22 +** testq %rsi, %rsi +** jne .L23 +**.L1: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L2: +** movups %xmm0, -64\(%rdi,%rsi\) +** movups %xmm0, -48\(%rdi,%rsi\) +** movups %xmm0, -32\(%rdi,%rsi\) +** movups %xmm0, -16\(%rdi,%rsi\) +** subq \$1, %rsi +** cmpq \$64, %rsi +** jb .L1 +** andq \$-64, %rsi +** xorl %eax, %eax +**.L9: +** movups %xmm0, \(%rdi,%rax\) +** movups %xmm0, 16\(%rdi,%rax\) +** movups %xmm0, 32\(%rdi,%rax\) +** movups %xmm0, 48\(%rdi,%rax\) +** addq \$64, %rax +** cmpq %rsi, %rax +** jb .L9 +** ret +** .p2align 4,,10 +** .p2align 3 +**.L23: +** movb \$0, \(%rdi\) +** testb \$2, %sil +** je .L1 +** xorl %eax, %eax +** movw %ax, -2\(%rdi,%rsi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L19: +** movups %xmm0, \(%rdi\) +** movups %xmm0, 16\(%rdi\) +** movups %xmm0, -32\(%rdi,%rsi\) +** movups %xmm0, -16\(%rdi,%rsi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L20: +** movups %xmm0, \(%rdi\) +** movups %xmm0, -16\(%rdi,%rsi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L21: +** movq \$0, \(%rdi\) +** movq \$0, -8\(%rdi,%rsi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L22: +** movl \$0, \(%rdi\) +** movl \$0, -4\(%rdi,%rsi\) +** ret +** .cfi_endproc +**... +*/ + +void +foo (char *dest, __SIZE_TYPE__ n) +{ + __builtin_memset (dest, 0, n); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-15.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-15.c new file mode 100644 index 0000000..d19188f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-15.c @@ -0,0 +1,103 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB0: +** .cfi_startproc +** vpxor %xmm0, %xmm0, %xmm0 +** cmpq \$128, %rsi +** jnb .L2 +** testb \$64, %sil +** jne .L22 +** testb \$32, %sil +** jne .L23 +** testb \$16, %sil +** jne .L24 +** testb \$8, %sil +** jne .L25 +** testb \$4, %sil +** jne .L26 +** testq %rsi, %rsi +** jne .L27 +**.L20: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L2: +** vmovdqu %ymm0, -128\(%rdi,%rsi\) +** vmovdqu %ymm0, -96\(%rdi,%rsi\) +** vmovdqu %ymm0, -64\(%rdi,%rsi\) +** vmovdqu %ymm0, -32\(%rdi,%rsi\) +** subq \$1, %rsi +** cmpq \$128, %rsi +** jb .L19 +** andq \$-128, %rsi +** xorl %eax, %eax +**.L10: +** vmovdqu %ymm0, \(%rdi,%rax\) +** vmovdqu %ymm0, 32\(%rdi,%rax\) +** vmovdqu %ymm0, 64\(%rdi,%rax\) +** vmovdqu %ymm0, 96\(%rdi,%rax\) +** subq \$-128, %rax +** cmpq %rsi, %rax +** jb .L10 +**.L19: +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L27: +** movb \$0, \(%rdi\) +** testb \$2, %sil +** je .L20 +** xorl %eax, %eax +** movw %ax, -2\(%rdi,%rsi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L22: +** vmovdqu %ymm0, \(%rdi\) +** vmovdqu %ymm0, 32\(%rdi\) +** vmovdqu %ymm0, -64\(%rdi,%rsi\) +** vmovdqu %ymm0, -32\(%rdi,%rsi\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L23: +** vmovdqu %ymm0, \(%rdi\) +** vmovdqu %ymm0, -32\(%rdi,%rsi\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L24: +** vmovdqu %xmm0, \(%rdi\) +** vmovdqu %xmm0, -16\(%rdi,%rsi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L25: +** movq \$0, \(%rdi\) +** movq \$0, -8\(%rdi,%rsi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L26: +** movl \$0, \(%rdi\) +** movl \$0, -4\(%rdi,%rsi\) +** ret +** .cfi_endproc +**... +*/ + +void +foo (char *dest, __SIZE_TYPE__ n) +{ + __builtin_memset (dest, 0, n); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-16.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-16.c new file mode 100644 index 0000000..539714c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-16.c @@ -0,0 +1,112 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB0: +** .cfi_startproc +** vpxor %xmm0, %xmm0, %xmm0 +** cmpq \$256, %rsi +** jnb .L2 +** testb \$-128, %sil +** jne .L23 +** testb \$64, %sil +** jne .L24 +** testb \$32, %sil +** jne .L25 +** testb \$16, %sil +** jne .L26 +** testb \$8, %sil +** jne .L27 +** testb \$4, %sil +** jne .L28 +** testq %rsi, %rsi +** jne .L29 +**.L21: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L2: +** vmovdqu64 %zmm0, -256\(%rdi,%rsi\) +** vmovdqu64 %zmm0, -192\(%rdi,%rsi\) +** vmovdqu64 %zmm0, -128\(%rdi,%rsi\) +** vmovdqu64 %zmm0, -64\(%rdi,%rsi\) +** subq \$1, %rsi +** cmpq \$256, %rsi +** jb .L20 +** xorb %sil, %sil +** xorl %eax, %eax +**.L11: +** vmovdqu64 %zmm0, \(%rdi,%rax\) +** vmovdqu64 %zmm0, 64\(%rdi,%rax\) +** vmovdqu64 %zmm0, 128\(%rdi,%rax\) +** vmovdqu64 %zmm0, 192\(%rdi,%rax\) +** addq \$256, %rax +** cmpq %rsi, %rax +** jb .L11 +**.L20: +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L29: +** movb \$0, \(%rdi\) +** testb \$2, %sil +** je .L21 +** xorl %eax, %eax +** movw %ax, -2\(%rdi,%rsi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L23: +** vmovdqu64 %zmm0, \(%rdi\) +** vmovdqu64 %zmm0, 64\(%rdi\) +** vmovdqu64 %zmm0, -128\(%rdi,%rsi\) +** vmovdqu64 %zmm0, -64\(%rdi,%rsi\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L24: +** vmovdqu64 %zmm0, \(%rdi\) +** vmovdqu64 %zmm0, -64\(%rdi,%rsi\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L25: +** vmovdqu %ymm0, \(%rdi\) +** vmovdqu %ymm0, -32\(%rdi,%rsi\) +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L26: +** vmovdqu %xmm0, \(%rdi\) +** vmovdqu %xmm0, -16\(%rdi,%rsi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L27: +** movq \$0, \(%rdi\) +** movq \$0, -8\(%rdi,%rsi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L28: +** movl \$0, \(%rdi\) +** movl \$0, -4\(%rdi,%rsi\) +** ret +** .cfi_endproc +**... +*/ + +void +foo (char *dest, __SIZE_TYPE__ n) +{ + __builtin_memset (dest, 0, n); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-17.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-17.c new file mode 100644 index 0000000..f58cb28 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-17.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** pxor %xmm0, %xmm0 +** xorl %eax, %eax +**.L[0-9]+: +** movl %eax, %edx +** addl \$64, %eax +** movaps %xmm0, dest\(%rdx\) +** movaps %xmm0, dest\+16\(%rdx\) +** movaps %xmm0, dest\+32\(%rdx\) +** movaps %xmm0, dest\+48\(%rdx\) +** cmpl \$128, %eax +** jb .L[0-9]+ +** movq \$0, dest\+48\(%rax\) +** movaps %xmm0, dest\(%rax\) +** movaps %xmm0, dest\+16\(%rax\) +** movaps %xmm0, dest\+32\(%rax\) +** ret +**... +*/ + +char dest[184]; + +void +foo (void) +{ + __builtin_memset (dest, 0, sizeof (dest)); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-18.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-18.c new file mode 100644 index 0000000..a127028 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-18.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** pxor %xmm0, %xmm0 +** xorl %eax, %eax +**.L[0-9]+: +** movl %eax, %edx +** addl \$64, %eax +** movaps %xmm0, dest\(%rdx\) +** movaps %xmm0, dest\+16\(%rdx\) +** movaps %xmm0, dest\+32\(%rdx\) +** movaps %xmm0, dest\+48\(%rdx\) +** cmpl \$128, %eax +** jb .L[0-9]+ +** movaps %xmm0, dest\+32\(%rax\) +** movaps %xmm0, dest\(%rax\) +** movl \$0, dest\+47\(%rax\) +** movaps %xmm0, dest\+16\(%rax\) +** ret +**... +*/ + +char dest[179]; + +void +foo (void) +{ + __builtin_memset (dest, 0, sizeof (dest)); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-19.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-19.c new file mode 100644 index 0000000..8dd5ae6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-19.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** pxor %xmm0, %xmm0 +** xorl %eax, %eax +**.L[0-9]+: +** movl %eax, %edx +** addl \$64, %eax +** movaps %xmm0, dest\(%rdx\) +** movaps %xmm0, dest\+16\(%rdx\) +** movaps %xmm0, dest\+32\(%rdx\) +** movaps %xmm0, dest\+48\(%rdx\) +** cmpl \$128, %eax +** jb .L[0-9]+ +** movb \$0, dest\+48\(%rax\) +** movaps %xmm0, dest\(%rax\) +** movaps %xmm0, dest\+16\(%rax\) +** movaps %xmm0, dest\+32\(%rax\) +** ret +**... +*/ + +char dest[177]; + +void +foo (void) +{ + __builtin_memset (dest, 0, sizeof (dest)); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-2.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-2.c new file mode 100644 index 0000000..3b84b29 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-2.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** vpxor %xmm0, %xmm0, %xmm0 +** vmovdqu %ymm0, 192\(%rdi\) +** vmovdqu %ymm0, \(%rdi\) +** vmovdqu %ymm0, 32\(%rdi\) +** vmovdqu %ymm0, 64\(%rdi\) +** vmovdqu %ymm0, 96\(%rdi\) +** vmovdqu %ymm0, 128\(%rdi\) +** vmovdqu %ymm0, 160\(%rdi\) +** vmovdqu %ymm0, 222\(%rdi\) +** vzeroupper +** ret +**... +*/ + +void +foo (char *dest) +{ + __builtin_memset (dest, 0, 254); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-20.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-20.c new file mode 100644 index 0000000..b8b9cb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-20.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** movd %edi, %xmm0 +** punpcklbw %xmm0, %xmm0 +** punpcklwd %xmm0, %xmm0 +** pshufd \$0, %xmm0, %xmm0 +** movaps %xmm0, dest\+160\(%rip\) +** movaps %xmm0, dest\(%rip\) +** movaps %xmm0, dest\+16\(%rip\) +** movaps %xmm0, dest\+32\(%rip\) +** movaps %xmm0, dest\+48\(%rip\) +** movaps %xmm0, dest\+64\(%rip\) +** movaps %xmm0, dest\+80\(%rip\) +** movaps %xmm0, dest\+96\(%rip\) +** movaps %xmm0, dest\+112\(%rip\) +** movaps %xmm0, dest\+128\(%rip\) +** movaps %xmm0, dest\+144\(%rip\) +** movd %xmm0, dest\+175\(%rip\) +** ret +**... +*/ + +char dest[179]; + +void +foo (int c) +{ + __builtin_memset (dest, c, sizeof (dest)); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-21.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-21.c new file mode 100644 index 0000000..3c7bb7c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-21.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** movd %edi, %xmm0 +** movb %dil, dest\+176\(%rip\) +** punpcklbw %xmm0, %xmm0 +** punpcklwd %xmm0, %xmm0 +** pshufd \$0, %xmm0, %xmm0 +** movaps %xmm0, dest\(%rip\) +** movaps %xmm0, dest\+16\(%rip\) +** movaps %xmm0, dest\+32\(%rip\) +** movaps %xmm0, dest\+48\(%rip\) +** movaps %xmm0, dest\+64\(%rip\) +** movaps %xmm0, dest\+80\(%rip\) +** movaps %xmm0, dest\+96\(%rip\) +** movaps %xmm0, dest\+112\(%rip\) +** movaps %xmm0, dest\+128\(%rip\) +** movaps %xmm0, dest\+144\(%rip\) +** movaps %xmm0, dest\+160\(%rip\) +** ret +**... +*/ + +char dest[177]; + +void +foo (int c) +{ + __builtin_memset (dest, c, sizeof (dest)); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-22.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-22.c new file mode 100644 index 0000000..96a21c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-22.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=rep_8byte:8192:align,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** movl \$25, %ecx +** xorl %eax, %eax +** movl \$dest, %edi +** rep stosq +** movl \$0, \(%rdi\) +** ret +**... +*/ + +#define SIZE 204 + +char dest[SIZE]; + +void +foo (void) +{ + __builtin_memset (dest, 0, sizeof (dest)); +} diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-23.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-23.c new file mode 100644 index 0000000..f3f5d80 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-23.c @@ -0,0 +1,67 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -minline-all-stringops -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB0: +** .cfi_startproc +** movzbl %dil, %edi +** movl \$p, %eax +** movabsq \$72340172838076673, %rdx +** imulq %rdx, %rdi +** movq %rdi, %xmm0 +** punpcklqdq %xmm0, %xmm0 +** cmpq \$64, %rsi +** jnb .L18 +**.L2: +** movq %rsi, %rcx +** andl \$63, %ecx +** je .L1 +** xorl %edx, %edx +** andl \$1, %esi +** je .L5 +** movl \$1, %edx +** movb %dil, \(%rax\) +** cmpq %rcx, %rdx +** jnb .L19 +**.L5: +** movb %dil, \(%rax,%rdx\) +** movb %dil, 1\(%rax,%rdx\) +** addq \$2, %rdx +** cmpq %rcx, %rdx +** jb .L5 +**.L1: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L18: +** movq %rsi, %rdx +** xorl %eax, %eax +** andq \$-64, %rdx +**.L3: +** movaps %xmm0, p\(%rax\) +** addq \$64, %rax +** movaps %xmm0, p-48\(%rax\) +** movaps %xmm0, p-32\(%rax\) +** movaps %xmm0, p-16\(%rax\) +** cmpq %rdx, %rax +** jb .L3 +** addq \$p, %rax +** jmp .L2 +**.L19: +** ret +** .cfi_endproc +**... +*/ + + +#define WRITE_CHUNK 256 +char p[WRITE_CHUNK]; + +void +foo (int c, __SIZE_TYPE__ nbyte) +{ + __builtin_memset (p, c, nbyte); +} diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-3.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-3.c new file mode 100644 index 0000000..faa47ca --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-3.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** vpxor %xmm0, %xmm0, %xmm0 +** vmovdqu8 %zmm0, 128\(%rdi\) +** vmovdqu8 %zmm0, \(%rdi\) +** vmovdqu8 %zmm0, 64\(%rdi\) +** vmovdqu8 %zmm0, 190\(%rdi\) +** vzeroupper +** ret +**... +*/ + +void +foo (char *dest) +{ + __builtin_memset (dest, 0, 254); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-4.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-4.c new file mode 100644 index 0000000..dc3aa57b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-4.c @@ -0,0 +1,93 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB0: +** .cfi_startproc +** movabsq \$289360691352306692, %rax +** movq %rax, %xmm0 +** punpcklqdq %xmm0, %xmm0 +** cmpq \$64, %rsi +** jnb .L2 +** testb \$32, %sil +** jne .L19 +** testb \$16, %sil +** jne .L20 +** testb \$8, %sil +** jne .L21 +** testb \$4, %sil +** jne .L22 +** testq %rsi, %rsi +** jne .L23 +**.L1: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L2: +** movups %xmm0, -64\(%rdi,%rsi\) +** movups %xmm0, -48\(%rdi,%rsi\) +** movups %xmm0, -32\(%rdi,%rsi\) +** movups %xmm0, -16\(%rdi,%rsi\) +** subq \$1, %rsi +** cmpq \$64, %rsi +** jb .L1 +** andq \$-64, %rsi +** xorl %eax, %eax +**.L9: +** movups %xmm0, \(%rdi,%rax\) +** movups %xmm0, 16\(%rdi,%rax\) +** movups %xmm0, 32\(%rdi,%rax\) +** movups %xmm0, 48\(%rdi,%rax\) +** addq \$64, %rax +** cmpq %rsi, %rax +** jb .L9 +** ret +** .p2align 4,,10 +** .p2align 3 +**.L23: +** movb \$4, \(%rdi\) +** testb \$2, %sil +** je .L1 +** movl \$1028, %eax +** movw %ax, -2\(%rdi,%rsi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L19: +** movups %xmm0, \(%rdi\) +** movups %xmm0, 16\(%rdi\) +** movups %xmm0, -32\(%rdi,%rsi\) +** movups %xmm0, -16\(%rdi,%rsi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L20: +** movups %xmm0, \(%rdi\) +** movups %xmm0, -16\(%rdi,%rsi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L21: +** movq %rax, \(%rdi\) +** movq %rax, -8\(%rdi,%rsi\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L22: +** movl \$67372036, \(%rdi\) +** movl \$67372036, -4\(%rdi,%rsi\) +** ret +** .cfi_endproc +**... +*/ + +void +foo (char *dest, __SIZE_TYPE__ n) +{ + __builtin_memset (dest, 4, n); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-5.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-5.c new file mode 100644 index 0000000..a324f8e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-5.c @@ -0,0 +1,102 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB0: +** .cfi_startproc +** movabsq \$289360691352306692, %rax +** vmovq %rax, %xmm1 +** vpbroadcastq %xmm1, %ymm0 +** cmpq \$128, %rsi +** jnb .L2 +** testb \$64, %sil +** jne .L21 +** testb \$32, %sil +** jne .L22 +** testb \$16, %sil +** jne .L23 +** testb \$8, %sil +** jne .L24 +** testb \$4, %sil +** jne .L25 +** testq %rsi, %rsi +** jne .L26 +**.L19: +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L2: +** vmovdqu %ymm0, -128\(%rdi,%rsi\) +** vmovdqu %ymm0, -96\(%rdi,%rsi\) +** vmovdqu %ymm0, -64\(%rdi,%rsi\) +** vmovdqu %ymm0, -32\(%rdi,%rsi\) +** subq \$1, %rsi +** cmpq \$128, %rsi +** jb .L19 +** andq \$-128, %rsi +** xorl %eax, %eax +**.L10: +** vmovdqu %ymm0, \(%rdi,%rax\) +** vmovdqu %ymm0, 32\(%rdi,%rax\) +** vmovdqu %ymm0, 64\(%rdi,%rax\) +** vmovdqu %ymm0, 96\(%rdi,%rax\) +** subq \$-128, %rax +** cmpq %rsi, %rax +** jb .L10 +** jmp .L19 +** .p2align 4,,10 +** .p2align 3 +**.L26: +** movb \$4, \(%rdi\) +** testb \$2, %sil +** je .L19 +** movl \$1028, %eax +** movw %ax, -2\(%rdi,%rsi\) +** jmp .L19 +** .p2align 4,,10 +** .p2align 3 +**.L21: +** vmovdqu %ymm0, \(%rdi\) +** vmovdqu %ymm0, 32\(%rdi\) +** vmovdqu %ymm0, -64\(%rdi,%rsi\) +** vmovdqu %ymm0, -32\(%rdi,%rsi\) +** jmp .L19 +** .p2align 4,,10 +** .p2align 3 +**.L22: +** vmovdqu %ymm0, \(%rdi\) +** vmovdqu %ymm0, -32\(%rdi,%rsi\) +** jmp .L19 +** .p2align 4,,10 +** .p2align 3 +**.L23: +** vmovdqu %xmm0, \(%rdi\) +** vmovdqu %xmm0, -16\(%rdi,%rsi\) +** jmp .L19 +** .p2align 4,,10 +** .p2align 3 +**.L24: +** movq %rax, \(%rdi\) +** movq %rax, -8\(%rdi,%rsi\) +** jmp .L19 +** .p2align 4,,10 +** .p2align 3 +**.L25: +** movl \$67372036, \(%rdi\) +** movl \$67372036, -4\(%rdi,%rsi\) +** jmp .L19 +** .cfi_endproc +**... +*/ + +void +foo (char *dest, __SIZE_TYPE__ n) +{ + __builtin_memset (dest, 4, n); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-6.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-6.c new file mode 100644 index 0000000..64e7589 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-6.c @@ -0,0 +1,109 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB0: +** .cfi_startproc +** movabsq \$289360691352306692, %rax +** vpbroadcastq %rax, %zmm0 +** cmpq \$256, %rsi +** jnb .L2 +** testb \$-128, %sil +** jne .L22 +** testb \$64, %sil +** jne .L23 +** testb \$32, %sil +** jne .L24 +** testb \$16, %sil +** jne .L25 +** testb \$8, %sil +** jne .L26 +** testb \$4, %sil +** jne .L27 +** testq %rsi, %rsi +** jne .L28 +**.L20: +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L2: +** vmovdqu64 %zmm0, -256\(%rdi,%rsi\) +** vmovdqu64 %zmm0, -192\(%rdi,%rsi\) +** vmovdqu64 %zmm0, -128\(%rdi,%rsi\) +** vmovdqu64 %zmm0, -64\(%rdi,%rsi\) +** subq \$1, %rsi +** cmpq \$256, %rsi +** jb .L20 +** xorb %sil, %sil +** xorl %eax, %eax +**.L11: +** vmovdqu64 %zmm0, \(%rdi,%rax\) +** vmovdqu64 %zmm0, 64\(%rdi,%rax\) +** vmovdqu64 %zmm0, 128\(%rdi,%rax\) +** vmovdqu64 %zmm0, 192\(%rdi,%rax\) +** addq \$256, %rax +** cmpq %rsi, %rax +** jb .L11 +** jmp .L20 +** .p2align 4,,10 +** .p2align 3 +**.L28: +** movb \$4, \(%rdi\) +** testb \$2, %sil +** je .L20 +** movl \$1028, %eax +** movw %ax, -2\(%rdi,%rsi\) +** jmp .L20 +** .p2align 4,,10 +** .p2align 3 +**.L22: +** vmovdqu64 %zmm0, \(%rdi\) +** vmovdqu64 %zmm0, 64\(%rdi\) +** vmovdqu64 %zmm0, -128\(%rdi,%rsi\) +** vmovdqu64 %zmm0, -64\(%rdi,%rsi\) +** jmp .L20 +** .p2align 4,,10 +** .p2align 3 +**.L23: +** vmovdqu64 %zmm0, \(%rdi\) +** vmovdqu64 %zmm0, -64\(%rdi,%rsi\) +** jmp .L20 +** .p2align 4,,10 +** .p2align 3 +**.L24: +** vmovdqu %ymm0, \(%rdi\) +** vmovdqu %ymm0, -32\(%rdi,%rsi\) +** jmp .L20 +** .p2align 4,,10 +** .p2align 3 +**.L25: +** vmovdqu %xmm0, \(%rdi\) +** vmovdqu %xmm0, -16\(%rdi,%rsi\) +** jmp .L20 +** .p2align 4,,10 +** .p2align 3 +**.L26: +** movq %rax, \(%rdi\) +** movq %rax, -8\(%rdi,%rsi\) +** jmp .L20 +** .p2align 4,,10 +** .p2align 3 +**.L27: +** movl \$67372036, \(%rdi\) +** movl \$67372036, -4\(%rdi,%rsi\) +** jmp .L20 +** .cfi_endproc +**... +*/ + +void +foo (char *dest, __SIZE_TYPE__ n) +{ + __builtin_memset (dest, 4, n); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-7.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-7.c new file mode 100644 index 0000000..022f6f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-7.c @@ -0,0 +1,94 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB0: +** .cfi_startproc +** movabsq \$72340172838076673, %rax +** movzbl %sil, %esi +** imulq %rax, %rsi +** movq %rsi, %xmm0 +** punpcklqdq %xmm0, %xmm0 +** cmpq \$64, %rdx +** jnb .L2 +** testb \$32, %dl +** jne .L19 +** testb \$16, %dl +** jne .L20 +** testb \$8, %dl +** jne .L21 +** testb \$4, %dl +** jne .L22 +** testq %rdx, %rdx +** jne .L23 +**.L1: +** ret +** .p2align 4,,10 +** .p2align 3 +**.L2: +** movups %xmm0, -64\(%rdi,%rdx\) +** movups %xmm0, -48\(%rdi,%rdx\) +** movups %xmm0, -32\(%rdi,%rdx\) +** movups %xmm0, -16\(%rdi,%rdx\) +** subq \$1, %rdx +** cmpq \$64, %rdx +** jb .L1 +** andq \$-64, %rdx +** xorl %eax, %eax +**.L9: +** movups %xmm0, \(%rdi,%rax\) +** movups %xmm0, 16\(%rdi,%rax\) +** movups %xmm0, 32\(%rdi,%rax\) +** movups %xmm0, 48\(%rdi,%rax\) +** addq \$64, %rax +** cmpq %rdx, %rax +** jb .L9 +** ret +** .p2align 4,,10 +** .p2align 3 +**.L23: +** movb %sil, \(%rdi\) +** testb \$2, %dl +** je .L1 +** movw %si, -2\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L19: +** movups %xmm0, \(%rdi\) +** movups %xmm0, 16\(%rdi\) +** movups %xmm0, -32\(%rdi,%rdx\) +** movups %xmm0, -16\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L20: +** movups %xmm0, \(%rdi\) +** movups %xmm0, -16\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L21: +** movq %rsi, \(%rdi\) +** movq %rsi, -8\(%rdi,%rdx\) +** ret +** .p2align 4,,10 +** .p2align 3 +**.L22: +** movl %esi, \(%rdi\) +** movl %esi, -4\(%rdi,%rdx\) +** ret +** .cfi_endproc +**... +*/ + +void +foo (char *dest, int c, __SIZE_TYPE__ n) +{ + __builtin_memset (dest, c, n); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-8.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-8.c new file mode 100644 index 0000000..5254e21 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-8.c @@ -0,0 +1,103 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB0: +** .cfi_startproc +** movabsq \$72340172838076673, %rax +** movzbl %sil, %esi +** imulq %rax, %rsi +** vmovq %rsi, %xmm1 +** vpbroadcastq %xmm1, %ymm0 +** cmpq \$128, %rdx +** jnb .L2 +** testb \$64, %dl +** jne .L21 +** testb \$32, %dl +** jne .L22 +** testb \$16, %dl +** jne .L23 +** testb \$8, %dl +** jne .L24 +** testb \$4, %dl +** jne .L25 +** testq %rdx, %rdx +** jne .L26 +**.L19: +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L2: +** vmovdqu %ymm0, -128\(%rdi,%rdx\) +** vmovdqu %ymm0, -96\(%rdi,%rdx\) +** vmovdqu %ymm0, -64\(%rdi,%rdx\) +** vmovdqu %ymm0, -32\(%rdi,%rdx\) +** subq \$1, %rdx +** cmpq \$128, %rdx +** jb .L19 +** andq \$-128, %rdx +** xorl %eax, %eax +**.L10: +** vmovdqu %ymm0, \(%rdi,%rax\) +** vmovdqu %ymm0, 32\(%rdi,%rax\) +** vmovdqu %ymm0, 64\(%rdi,%rax\) +** vmovdqu %ymm0, 96\(%rdi,%rax\) +** subq \$-128, %rax +** cmpq %rdx, %rax +** jb .L10 +** jmp .L19 +** .p2align 4,,10 +** .p2align 3 +**.L26: +** movb %sil, \(%rdi\) +** testb \$2, %dl +** je .L19 +** movw %si, -2\(%rdi,%rdx\) +** jmp .L19 +** .p2align 4,,10 +** .p2align 3 +**.L21: +** vmovdqu %ymm0, \(%rdi\) +** vmovdqu %ymm0, 32\(%rdi\) +** vmovdqu %ymm0, -64\(%rdi,%rdx\) +** vmovdqu %ymm0, -32\(%rdi,%rdx\) +** jmp .L19 +** .p2align 4,,10 +** .p2align 3 +**.L22: +** vmovdqu %ymm0, \(%rdi\) +** vmovdqu %ymm0, -32\(%rdi,%rdx\) +** jmp .L19 +** .p2align 4,,10 +** .p2align 3 +**.L23: +** vmovdqu %xmm0, \(%rdi\) +** vmovdqu %xmm0, -16\(%rdi,%rdx\) +** jmp .L19 +** .p2align 4,,10 +** .p2align 3 +**.L24: +** movq %rsi, \(%rdi\) +** movq %rsi, -8\(%rdi,%rdx\) +** jmp .L19 +** .p2align 4,,10 +** .p2align 3 +**.L25: +** movl %esi, \(%rdi\) +** movl %esi, -4\(%rdi,%rdx\) +** jmp .L19 +** .cfi_endproc +**... +*/ + +void +foo (char *dest, int c, __SIZE_TYPE__ n) +{ + __builtin_memset (dest, c, n); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120683-9.c b/gcc/testsuite/gcc.target/i386/memset-pr120683-9.c new file mode 100644 index 0000000..1719de6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120683-9.c @@ -0,0 +1,110 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign -minline-all-stringops" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB0: +** .cfi_startproc +** movabsq \$72340172838076673, %rax +** movzbl %sil, %esi +** imulq %rax, %rsi +** vpbroadcastq %rsi, %zmm0 +** cmpq \$256, %rdx +** jnb .L2 +** testb \$-128, %dl +** jne .L22 +** testb \$64, %dl +** jne .L23 +** testb \$32, %dl +** jne .L24 +** testb \$16, %dl +** jne .L25 +** testb \$8, %dl +** jne .L26 +** testb \$4, %dl +** jne .L27 +** testq %rdx, %rdx +** jne .L28 +**.L20: +** vzeroupper +** ret +** .p2align 4,,10 +** .p2align 3 +**.L2: +** vmovdqu64 %zmm0, -256\(%rdi,%rdx\) +** vmovdqu64 %zmm0, -192\(%rdi,%rdx\) +** vmovdqu64 %zmm0, -128\(%rdi,%rdx\) +** vmovdqu64 %zmm0, -64\(%rdi,%rdx\) +** subq \$1, %rdx +** cmpq \$256, %rdx +** jb .L20 +** xorb %dl, %dl +** xorl %eax, %eax +**.L11: +** vmovdqu64 %zmm0, \(%rdi,%rax\) +** vmovdqu64 %zmm0, 64\(%rdi,%rax\) +** vmovdqu64 %zmm0, 128\(%rdi,%rax\) +** vmovdqu64 %zmm0, 192\(%rdi,%rax\) +** addq \$256, %rax +** cmpq %rdx, %rax +** jb .L11 +** jmp .L20 +** .p2align 4,,10 +** .p2align 3 +**.L28: +** movb %sil, \(%rdi\) +** testb \$2, %dl +** je .L20 +** movw %si, -2\(%rdi,%rdx\) +** jmp .L20 +** .p2align 4,,10 +** .p2align 3 +**.L22: +** vmovdqu64 %zmm0, \(%rdi\) +** vmovdqu64 %zmm0, 64\(%rdi\) +** vmovdqu64 %zmm0, -128\(%rdi,%rdx\) +** vmovdqu64 %zmm0, -64\(%rdi,%rdx\) +** jmp .L20 +** .p2align 4,,10 +** .p2align 3 +**.L23: +** vmovdqu64 %zmm0, \(%rdi\) +** vmovdqu64 %zmm0, -64\(%rdi,%rdx\) +** jmp .L20 +** .p2align 4,,10 +** .p2align 3 +**.L24: +** vmovdqu %ymm0, \(%rdi\) +** vmovdqu %ymm0, -32\(%rdi,%rdx\) +** jmp .L20 +** .p2align 4,,10 +** .p2align 3 +**.L25: +** vmovdqu %xmm0, \(%rdi\) +** vmovdqu %xmm0, -16\(%rdi,%rdx\) +** jmp .L20 +** .p2align 4,,10 +** .p2align 3 +**.L26: +** movq %rsi, \(%rdi\) +** movq %rsi, -8\(%rdi,%rdx\) +** jmp .L20 +** .p2align 4,,10 +** .p2align 3 +**.L27: +** movl %esi, \(%rdi\) +** movl %esi, -4\(%rdi,%rdx\) +** jmp .L20 +** .cfi_endproc +**... +*/ + +void +foo (char *dest, int c, __SIZE_TYPE__ n) +{ + __builtin_memset (dest, c, n); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120708-1.c b/gcc/testsuite/gcc.target/i386/memset-pr120708-1.c new file mode 100644 index 0000000..fba0588 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120708-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -mprefer-vector-width=128 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ + +void +foo (char *dest) +{ + __builtin_memset (dest, 0, 254); +} + +/* { dg-final { scan-assembler "vmovdqu\[ \t]\+%xmm\[0-9\]+, \\(\[^\n\r]*\\)" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr120708-2.c b/gcc/testsuite/gcc.target/i386/memset-pr120708-2.c new file mode 100644 index 0000000..d9a3e7e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr120708-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -mprefer-vector-width=256 -mmemset-strategy=vector_loop:256:noalign,libcall:-1:noalign" } */ + +void +foo (char *dest) +{ + __builtin_memset (dest, 0, 254); +} + +/* { dg-final { scan-assembler "vmovdqu\[ \t]\+%ymm\[0-9\]+, \\(\[^\n\r]*\\)" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr70308-1a.c b/gcc/testsuite/gcc.target/i386/memset-pr70308-1a.c new file mode 100644 index 0000000..5cc4eee --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr70308-1a.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** subq \$16, %rsp +** .cfi_def_cfa_offset 24 +** pxor %xmm0, %xmm0 +** movaps %xmm0, -120\(%rsp\) +** movaps %xmm0, -104\(%rsp\) +** movaps %xmm0, -88\(%rsp\) +** movaps %xmm0, -72\(%rsp\) +** movaps %xmm0, -56\(%rsp\) +** movaps %xmm0, -40\(%rsp\) +** movaps %xmm0, -24\(%rsp\) +** movaps %xmm0, -8\(%rsp\) +** xorl %eax, %eax +** addq \$16, %rsp +** .cfi_def_cfa_offset 8 +** ret +**... +*/ + +extern int scanf (const char *, ...); +extern void *memset (void *, int, __SIZE_TYPE__); + +int +foo (void) +{ + char buf[128]; + +#if USE_SCANF + if (scanf("%s", buf) != 1) + return 42; +#endif + + memset (buf,0, sizeof (buf)); + asm volatile("": : :"memory"); + return 0; +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-pr70308-1b.c b/gcc/testsuite/gcc.target/i386/memset-pr70308-1b.c new file mode 100644 index 0000000..15996ea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-pr70308-1b.c @@ -0,0 +1,61 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -fasynchronous-unwind-tables -fdwarf2-cfi-asm -fomit-frame-pointer -DUSE_SCANF" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** subq \$136, %rsp +** .cfi_def_cfa_offset 144 +** xorl %eax, %eax +** movl \$.LC[0-9]+, %edi +** movq %rsp, %rsi +** call scanf +** cmpl \$1, %eax +** je .L[0-9]+ +** movl \$42, %eax +** addq \$136, %rsp +** .cfi_remember_state +** .cfi_def_cfa_offset 8 +** ret +** .p2align 4,,10 +** .p2align 3 +**.L[0-9]+: +** .cfi_restore_state +** pxor %xmm0, %xmm0 +** movaps %xmm0, \(%rsp\) +** movaps %xmm0, 16\(%rsp\) +** movaps %xmm0, 32\(%rsp\) +** movaps %xmm0, 48\(%rsp\) +** movaps %xmm0, 64\(%rsp\) +** movaps %xmm0, 80\(%rsp\) +** movaps %xmm0, 96\(%rsp\) +** movaps %xmm0, 112\(%rsp\) +** xorl %eax, %eax +** addq \$136, %rsp +** .cfi_def_cfa_offset 8 +** ret +**... +*/ + +extern int scanf (const char *, ...); +extern void *memset (void *, int, __SIZE_TYPE__); + +int +foo (void) +{ + char buf[128]; + +#if USE_SCANF + if (scanf("%s", buf) != 1) + return 42; +#endif + + memset (buf,0, sizeof (buf)); + asm volatile("": : :"memory"); + return 0; +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-25.c b/gcc/testsuite/gcc.target/i386/memset-strategy-25.c new file mode 100644 index 0000000..7bd5d43 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-25.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic -mno-sse -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** movq \$0, 221\(%rdi\) +** xorl %eax, %eax +** movq \$0, 229\(%rdi\) +** movq \$0, 237\(%rdi\) +** movq \$0, 245\(%rdi\) +**.L[0-9]+: +** movl %eax, %edx +** addl \$32, %eax +** movq \$0, \(%rdi,%rdx\) +** movq \$0, 8\(%rdi,%rdx\) +** movq \$0, 16\(%rdi,%rdx\) +** movq \$0, 24\(%rdi,%rdx\) +** cmpl \$224, %eax +** jb .L[0-9]+ +** ret +**... +*/ + +void +foo (char *dest) +{ + __builtin_memset (dest, 0, 253); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-26.c b/gcc/testsuite/gcc.target/i386/memset-strategy-26.c new file mode 100644 index 0000000..c53bce5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-26.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic -mno-sse" } */ +/* { dg-final { scan-assembler-not "jmp\tmemset" } } */ +/* { dg-final { scan-assembler-not "rep stosb" } } */ + +struct foo +{ + char buf[41]; +}; + +void +zero(struct foo *f) +{ + __builtin_memset(f->buf, 0, sizeof(f->buf)); +} diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-27.c b/gcc/testsuite/gcc.target/i386/memset-strategy-27.c new file mode 100644 index 0000000..685d6e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-27.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic -mno-avx" } */ +/* { dg-final { scan-assembler "jmp\tmemset" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\tmemset" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "rep stosb" } } */ + +void +foo (char *dest) +{ + __builtin_memset (dest, 0, 257); +} diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-28.c b/gcc/testsuite/gcc.target/i386/memset-strategy-28.c new file mode 100644 index 0000000..eef113f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-28.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic -mno-sse -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** movq \$0, \(%rdi\) +** movq \$0, 8\(%rdi\) +** movq \$0, 16\(%rdi\) +** movq \$0, 24\(%rdi\) +** movq \$0, 32\(%rdi\) +** movq \$0, 40\(%rdi\) +** movq \$0, 48\(%rdi\) +** movq \$0, 56\(%rdi\) +** movb \$0, 64\(%rdi\) +** ret +**... +*/ + +void +foo (char *dest) +{ + __builtin_memset (dest, 0, 65); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-29.c b/gcc/testsuite/gcc.target/i386/memset-strategy-29.c new file mode 100644 index 0000000..a33bf92 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-29.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic -mno-sse -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**... +**.LFB[0-9]+: +** .cfi_startproc +** movq \$0, 49\(%rdi\) +** xorl %eax, %eax +** movq \$0, 57\(%rdi\) +** movq \$0, 65\(%rdi\) +** movq \$0, 73\(%rdi\) +**.L[0-9]+: +** movl %eax, %edx +** addl \$32, %eax +** movq \$0, \(%rdi,%rdx\) +** movq \$0, 8\(%rdi,%rdx\) +** movq \$0, 16\(%rdi,%rdx\) +** movq \$0, 24\(%rdi,%rdx\) +** cmpl \$64, %eax +** jb .L[0-9]+ +** ret +**... +*/ + +void +foo (char *dest) +{ + __builtin_memset (dest, 0, 81); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-30.c b/gcc/testsuite/gcc.target/i386/memset-strategy-30.c new file mode 100644 index 0000000..f3912f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-30.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic -mno-sse -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**... +**.LFB[0-9]+: +** .cfi_startproc +** movq \$0, 63\(%rdi\) +** xorl %eax, %eax +** movq \$0, 71\(%rdi\) +** movq \$0, 79\(%rdi\) +** movq \$0, 87\(%rdi\) +**.L[0-9]+: +** movl %eax, %edx +** addl \$32, %eax +** movq \$0, \(%rdi,%rdx\) +** movq \$0, 8\(%rdi,%rdx\) +** movq \$0, 16\(%rdi,%rdx\) +** movq \$0, 24\(%rdi,%rdx\) +** cmpl \$64, %eax +** jb .L[0-9]+ +** ret +**... +*/ + +void +foo (char *dest) +{ + __builtin_memset (dest, 0, 95); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-31.c b/gcc/testsuite/gcc.target/i386/memset-strategy-31.c new file mode 100644 index 0000000..4791c4d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-31.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic -mno-avx -msse2" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +**... +** pxor %xmm0, %xmm0 +** xorl %eax, %eax +** movups %xmm0, 190\(%rdi\) +** movups %xmm0, 206\(%rdi\) +** movups %xmm0, 222\(%rdi\) +** movups %xmm0, 238\(%rdi\) +**.L[0-9]+: +** movl %eax, %edx +** addl \$64, %eax +** movups %xmm0, \(%rdi,%rdx\) +** movups %xmm0, 16\(%rdi,%rdx\) +** movups %xmm0, 32\(%rdi,%rdx\) +** movups %xmm0, 48\(%rdi,%rdx\) +** cmpl \$192, %eax +** jb .L[0-9]+ +**... +*/ + +void +foo (char *dest) +{ + __builtin_memset (dest, 0, 254); +} + +/* { dg-final { scan-assembler-not "rep stos" } } */ diff --git a/gcc/testsuite/gcc.target/i386/memset-vector_loop-1.c b/gcc/testsuite/gcc.target/i386/memset-vector_loop-1.c index d6fdc98..5bb30a8 100644 --- a/gcc/testsuite/gcc.target/i386/memset-vector_loop-1.c +++ b/gcc/testsuite/gcc.target/i386/memset-vector_loop-1.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { *-*-* } { "-march=*" } { "-march=atom" } } */ -/* { dg-options "-O2 -march=atom -minline-all-stringops -mstringop-strategy=vector_loop" } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -mtune-ctrl=^sse_typeless_stores -minline-all-stringops -mstringop-strategy=vector_loop" } */ /* { dg-final { scan-assembler-times "movdqa" 4 } } */ char a[2048]; diff --git a/gcc/testsuite/gcc.target/i386/memset-vector_loop-2.c b/gcc/testsuite/gcc.target/i386/memset-vector_loop-2.c index bce8be0..6e31070 100644 --- a/gcc/testsuite/gcc.target/i386/memset-vector_loop-2.c +++ b/gcc/testsuite/gcc.target/i386/memset-vector_loop-2.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { *-*-* } { "-march=*" } { "-march=atom" } } */ -/* { dg-options "-O2 -march=atom -minline-all-stringops -mstringop-strategy=vector_loop" } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic -mtune-ctrl=^sse_typeless_stores -mstringop-strategy=vector_loop" } */ /* { dg-final { scan-assembler-times "movdqa" 4} } */ char *a; diff --git a/gcc/testsuite/gcc.target/i386/mvc17.c b/gcc/testsuite/gcc.target/i386/mvc17.c index 8b83c1a..dbf35ac 100644 --- a/gcc/testsuite/gcc.target/i386/mvc17.c +++ b/gcc/testsuite/gcc.target/i386/mvc17.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-require-ifunc "" } */ /* { dg-options "-O2 -march=x86-64" } */ -/* { dg-final { scan-assembler-times "rep mov" 1 } } */ +/* { dg-final { scan-assembler-not "rep mov" } } */ __attribute__((target_clones("default","arch=icelake-server"))) void diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-1.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-1.c index 599c2a3..e535485 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-1.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-1.c @@ -26,5 +26,7 @@ foo (void *frame) } } -/* { dg-final { scan-assembler-not "push" } } */ -/* { dg-final { scan-assembler-not "pop" } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*" 1 } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-10.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-10.c index 87766c6..6c54144 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-10.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-10.c @@ -18,7 +18,7 @@ foo (void) /* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ /* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)cx" 1 } } */ /* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)dx" 1 } } */ -/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ /* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)si" 1 } } */ /* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)di" 1 } } */ /* { dg-final { scan-assembler-times "pushq\[\\t \]*%r8" 1 { target { ! ia32 } } } } */ @@ -33,7 +33,7 @@ foo (void) /* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ /* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)cx" 1 } } */ /* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)dx" 1 } } */ -/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ /* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)si" 1 } } */ /* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)di" 1 } } */ /* { dg-final { scan-assembler-times "popq\[\\t \]*%r8" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-16.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-16.c index 112d176..a5589e2 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-16.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move" } */ +/* { dg-options "-O2 -fomit-frame-pointer -mtune-ctrl=^prologue_using_move,^epilogue_using_move" } */ typedef void (*fn_t) (void) __attribute__ ((no_callee_saved_registers)); diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-18.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-18.c index e710100..128b9c4 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-18.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-18.c @@ -19,7 +19,7 @@ foo (uintptr_t p) /* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ /* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ /* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ -/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ /* { dg-final { scan-assembler-times "pushl\[\\t \]*%esi" 1 { target ia32 } } } */ /* { dg-final { scan-assembler-not "pushq\[\\t \]*%rsi" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-times "pushl\[\\t \]*%edi" 1 { target ia32 } } } */ @@ -36,7 +36,7 @@ foo (uintptr_t p) /* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ /* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ /* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ -/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ /* { dg-final { scan-assembler-times "popl\[\\t \]*%esi" 1 { target ia32 } } } */ /* { dg-final { scan-assembler-not "popq\[\\t \]*%rsi" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-times "popl\[\\t \]*%edi" 1 { target ia32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-19a.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-19a.c new file mode 100644 index 0000000..12f35cf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-19a.c @@ -0,0 +1,164 @@ +/* { dg-do compile { target { *-*-linux* && lp64 } } } */ +/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mno-apxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* end must be empty. */ + +/* +**end: +**.LFB[0-9]+: +** .cfi_startproc +** ret +** .cfi_endproc +**... +*/ + +#define NEXT { op_t *op = next; [[gnu::musttail]] return (*op)(op + 1); } +#ifdef __x86_64__ +# define CLOBBER asm("" ::: "r12","r13","r14","r15","rbx") +#else +# define CLOBBER asm("" ::: "ebx") +#endif +#define DONT_SAVE_REGS __attribute__((no_callee_saved_registers)) +#define SAVE_REGS __attribute__((no_caller_saved_registers)) + +typedef DONT_SAVE_REGS void (*op_t)(void *next); + +extern int accumulator; + +static DONT_SAVE_REGS void end(void *next) +{ +} + +/* inc doesn't have any callee saved registers. */ + +/* +**inc: +**.LFB[0-9]+: +** .cfi_startproc +** addl \$1, accumulator\(%rip\) +** movq \(%rdi\), %rax +** addq \$8, %rdi +** jmp \*%rax +** .cfi_endproc +**... +*/ + +static DONT_SAVE_REGS void inc(void *next) +{ + accumulator += 1; + CLOBBER; + NEXT; +} + +/* dec doesn't have any callee saved registers. */ + +/* +**dec: +**.LFB[0-9]+: +** .cfi_startproc +** subl \$1, accumulator\(%rip\) +** movq \(%rdi\), %rax +** addq \$8, %rdi +** jmp \*%rax +** .cfi_endproc +**... +*/ + +static DONT_SAVE_REGS void dec(void *next) +{ + accumulator -= 1; + CLOBBER; + NEXT; +} + +op_t code[] = { inc, inc, dec, end, }; + +/* start must save and restore all caller saved registers. */ + +/* +**start: +**.LFB[0-9]+: +** .cfi_startproc +** subq \$376, %rsp +**... +** movq %rdi, 304\(%rsp\) +**... +** movl \$code\+8, %edi +** movq %rax, 264\(%rsp\) +** movq %rdx, 272\(%rsp\) +** movq %rcx, 280\(%rsp\) +** movq %rbx, 288\(%rsp\) +** movq %rsi, 296\(%rsp\) +** movq %r8, 312\(%rsp\) +** movq %r9, 320\(%rsp\) +** movq %r10, 328\(%rsp\) +** movq %r11, 336\(%rsp\) +** movq %r12, 344\(%rsp\) +** movq %r13, 352\(%rsp\) +** movq %r14, 360\(%rsp\) +** movq %r15, 368\(%rsp\) +** movaps %xmm0, \(%rsp\) +** movaps %xmm1, 16\(%rsp\) +** movaps %xmm2, 32\(%rsp\) +** movaps %xmm3, 48\(%rsp\) +** movaps %xmm4, 64\(%rsp\) +** movaps %xmm5, 80\(%rsp\) +** movaps %xmm6, 96\(%rsp\) +** movaps %xmm7, 112\(%rsp\) +** movaps %xmm8, 128\(%rsp\) +** movaps %xmm9, 144\(%rsp\) +** movaps %xmm10, 160\(%rsp\) +** movaps %xmm11, 176\(%rsp\) +** movaps %xmm12, 192\(%rsp\) +** movaps %xmm13, 208\(%rsp\) +** movaps %xmm14, 224\(%rsp\) +** movaps %xmm15, 240\(%rsp\) +**... +** call \*code\(%rip\) +** movaps \(%rsp\), %xmm0 +** movaps 16\(%rsp\), %xmm1 +** movaps 32\(%rsp\), %xmm2 +** movaps 48\(%rsp\), %xmm3 +** movaps 64\(%rsp\), %xmm4 +** movaps 80\(%rsp\), %xmm5 +** movaps 96\(%rsp\), %xmm6 +** movaps 112\(%rsp\), %xmm7 +** movaps 128\(%rsp\), %xmm8 +** movaps 144\(%rsp\), %xmm9 +** movaps 160\(%rsp\), %xmm10 +** movaps 176\(%rsp\), %xmm11 +** movaps 192\(%rsp\), %xmm12 +** movaps 208\(%rsp\), %xmm13 +** movq 264\(%rsp\), %rax +** movq 272\(%rsp\), %rdx +** movq 280\(%rsp\), %rcx +** movq 288\(%rsp\), %rbx +** movq 296\(%rsp\), %rsi +** movq 304\(%rsp\), %rdi +** movq 312\(%rsp\), %r8 +** movq 320\(%rsp\), %r9 +** movq 328\(%rsp\), %r10 +** movq 336\(%rsp\), %r11 +** movq 344\(%rsp\), %r12 +** movq 352\(%rsp\), %r13 +** movq 360\(%rsp\), %r14 +** movq 368\(%rsp\), %r15 +** movaps 224\(%rsp\), %xmm14 +** movaps 240\(%rsp\), %xmm15 +** addq \$376, %rsp +**... +** ret +** .cfi_endproc +**... +*/ + +/* This function should have normal ABI to interoperate with others */ +SAVE_REGS void start() +{ + void *next = code; + + // musttail doesn't work here because the registers need to be restored + code[0](code + 1); +} diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-19b.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-19b.c new file mode 100644 index 0000000..c9343a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-19b.c @@ -0,0 +1,129 @@ +/* { dg-do compile { target { *-*-linux* && maybe_x32 } } } */ +/* { dg-options "-O2 -mx32 -fno-pic -mtune=generic -msse2 -mno-apxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* end must be empty. */ + +/* +**end: +**.LFB[0-9]+: +** .cfi_startproc +** ret +** .cfi_endproc +**... +*/ + +/* inc doesn't have any callee saved registers. */ + +/* +**inc: +**.LFB[0-9]+: +** .cfi_startproc +** addl \$1, accumulator\(%rip\) +** movq %rdi, %rax +** movl \(%eax\), %eax +** leal 4\(%rdi\), %edi +** jmp \*%rax +** .cfi_endproc +**... +*/ + +/* dec doesn't have any callee saved registers. */ + +/* +**dec: +**.LFB[0-9]+: +** .cfi_startproc +** subl \$1, accumulator\(%rip\) +** movq %rdi, %rax +** movl \(%eax\), %eax +** leal 4\(%rdi\), %edi +** jmp \*%rax +** .cfi_endproc +**... +*/ + +/* start must save and restore all caller saved registers. */ + +/* +**start: +**.LFB[0-9]+: +** .cfi_startproc +** subl \$376, %esp +**... +** movq %rax, 256\(%rsp\) +** movq %rdx, 264\(%rsp\) +** movq %rcx, 272\(%rsp\) +** movq %rbx, 280\(%rsp\) +** movq %rsi, 288\(%rsp\) +** movq %rdi, 296\(%rsp\) +**... +** movl \$code\+4, %edi +** movq %rbp, 304\(%rsp\) +** movq %r8, 312\(%rsp\) +** movq %r9, 320\(%rsp\) +** movq %r10, 328\(%rsp\) +** movq %r11, 336\(%rsp\) +** movq %r12, 344\(%rsp\) +** movq %r13, 352\(%rsp\) +** movq %r14, 360\(%rsp\) +** movq %r15, 368\(%rsp\) +** movaps %xmm0, \(%rsp\) +** movaps %xmm1, 16\(%rsp\) +** movaps %xmm2, 32\(%rsp\) +** movaps %xmm3, 48\(%rsp\) +** movaps %xmm4, 64\(%rsp\) +** movaps %xmm5, 80\(%rsp\) +** movaps %xmm6, 96\(%rsp\) +** movaps %xmm7, 112\(%rsp\) +** movaps %xmm8, 128\(%rsp\) +** movaps %xmm9, 144\(%rsp\) +** movaps %xmm10, 160\(%rsp\) +** movaps %xmm11, 176\(%rsp\) +** movaps %xmm12, 192\(%rsp\) +** movaps %xmm13, 208\(%rsp\) +** movaps %xmm14, 224\(%rsp\) +** movaps %xmm15, 240\(%rsp\) +**... +** movl code\(%rip\), %ebp +** call \*%rbp +** movaps \(%rsp\), %xmm0 +** movaps 16\(%rsp\), %xmm1 +** movaps 32\(%rsp\), %xmm2 +** movaps 48\(%rsp\), %xmm3 +** movaps 64\(%rsp\), %xmm4 +** movaps 80\(%rsp\), %xmm5 +** movaps 96\(%rsp\), %xmm6 +** movaps 112\(%rsp\), %xmm7 +** movaps 128\(%rsp\), %xmm8 +** movaps 144\(%rsp\), %xmm9 +** movaps 160\(%rsp\), %xmm10 +** movaps 176\(%rsp\), %xmm11 +** movaps 192\(%rsp\), %xmm12 +** movaps 208\(%rsp\), %xmm13 +** movaps 224\(%rsp\), %xmm14 +** movaps 240\(%rsp\), %xmm15 +** movq 256\(%rsp\), %rax +** movq 264\(%rsp\), %rdx +** movq 272\(%rsp\), %rcx +** movq 280\(%rsp\), %rbx +** movq 288\(%rsp\), %rsi +** movq 296\(%rsp\), %rdi +** movq 304\(%rsp\), %rbp +** movq 312\(%rsp\), %r8 +** movq 320\(%rsp\), %r9 +** movq 328\(%rsp\), %r10 +** movq 336\(%rsp\), %r11 +** movq 344\(%rsp\), %r12 +** movq 352\(%rsp\), %r13 +** movq 360\(%rsp\), %r14 +** movq 368\(%rsp\), %r15 +** addl \$376, %esp +**... +** ret +** .cfi_endproc +**... +*/ + +#include "no-callee-saved-19a.c" diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-19c.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-19c.c new file mode 100644 index 0000000..05aca9f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-19c.c @@ -0,0 +1,92 @@ +/* { dg-do compile { target { *-*-linux* && ia32 } } } */ +/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* end must be empty. */ + +/* +**end: +**.LFB[0-9]+: +** .cfi_startproc +** ret +** .cfi_endproc +**... +*/ + +/* inc doesn't have any callee saved registers. */ + +/* +**inc: +**.LFB[0-9]+: +** .cfi_startproc +** addl \$1, accumulator +** movl 4\(%esp\), %eax +** leal 4\(%eax\), %edx +** movl %edx, 4\(%esp\) +** jmp \*\(%eax\) +** .cfi_endproc +**... +*/ + +/* dec doesn't have any callee saved registers. */ + +/* +**dec: +**.LFB[0-9]+: +** .cfi_startproc +** subl \$1, accumulator +** movl 4\(%esp\), %eax +** leal 4\(%eax\), %edx +** movl %edx, 4\(%esp\) +** jmp \*\(%eax\) +** .cfi_endproc +**... +*/ + +/* start must save and restore all caller saved registers. */ + +/* +**start: +**.LFB[0-9]+: +** .cfi_startproc +**... +** movl %eax, 144\(%esp\) +** movl %edx, 148\(%esp\) +** movl %ecx, 152\(%esp\) +** movl %ebx, 156\(%esp\) +** movl %esi, 160\(%esp\) +** movl %edi, 164\(%esp\) +** movaps %xmm0, 12\(%esp\) +** movaps %xmm1, 28\(%esp\) +** movaps %xmm2, 44\(%esp\) +** movaps %xmm3, 60\(%esp\) +** movaps %xmm4, 76\(%esp\) +** movaps %xmm5, 92\(%esp\) +** movaps %xmm6, 108\(%esp\) +** movaps %xmm7, 124\(%esp\) +**... +** pushl \$code\+4 +**... +** call \*code +** movaps 16\(%esp\), %xmm0 +** movaps 32\(%esp\), %xmm1 +** movaps 48\(%esp\), %xmm2 +** movaps 64\(%esp\), %xmm3 +** movaps 80\(%esp\), %xmm4 +** movaps 96\(%esp\), %xmm5 +** movaps 112\(%esp\), %xmm6 +** movaps 128\(%esp\), %xmm7 +** movl 148\(%esp\), %eax +** movl 152\(%esp\), %edx +** movl 156\(%esp\), %ecx +** movl 160\(%esp\), %ebx +** movl 164\(%esp\), %esi +** movl 168\(%esp\), %edi +**... +** ret +** .cfi_endproc +**... +*/ + +#include "no-callee-saved-19a.c" diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-19d.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-19d.c new file mode 100644 index 0000000..b3caa3d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-19d.c @@ -0,0 +1,157 @@ +/* { dg-do compile { target { *-*-linux* && lp64 } } } */ +/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mapxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* end must be empty. */ + +/* +**end: +**.LFB[0-9]+: +** .cfi_startproc +** ret +** .cfi_endproc +**... +*/ + +/* inc doesn't have any callee saved registers. */ + +/* +**inc: +**.LFB[0-9]+: +** .cfi_startproc +** addl \$1, accumulator\(%rip\) +** movq \(%rdi\), %rax +** addq \$8, %rdi +** jmp \*%rax +** .cfi_endproc +**... +*/ + +/* dec doesn't have any callee saved registers. */ + +/* +**dec: +**.LFB[0-9]+: +** .cfi_startproc +** subl \$1, accumulator\(%rip\) +** movq \(%rdi\), %rax +** addq \$8, %rdi +** jmp \*%rax +** .cfi_endproc +**... +*/ + +/* start must save and restore all caller saved registers. */ + +/* +**start: +**.LFB[0-9]+: +** .cfi_startproc +** subq \$504, %rsp +**... +** movq %rax, 264\(%rsp\) +** movq %rdx, 272\(%rsp\) +** movq %rcx, 280\(%rsp\) +** movq %rbx, 288\(%rsp\) +** movq %rsi, 296\(%rsp\) +** movq %rdi, 304\(%rsp\) +**... +** movl \$code\+8, %edi +** movq %r8, 312\(%rsp\) +** movq %r9, 320\(%rsp\) +** movq %r10, 328\(%rsp\) +** movq %r11, 336\(%rsp\) +** movq %r12, 344\(%rsp\) +** movq %r13, 352\(%rsp\) +** movq %r14, 360\(%rsp\) +** movq %r15, 368\(%rsp\) +** movq %r16, 376\(%rsp\) +** movq %r17, 384\(%rsp\) +** movq %r18, 392\(%rsp\) +** movq %r19, 400\(%rsp\) +** movq %r20, 408\(%rsp\) +** movq %r21, 416\(%rsp\) +** movq %r22, 424\(%rsp\) +** movq %r23, 432\(%rsp\) +** movq %r24, 440\(%rsp\) +** movq %r25, 448\(%rsp\) +** movq %r26, 456\(%rsp\) +** movq %r27, 464\(%rsp\) +** movq %r28, 472\(%rsp\) +** movq %r29, 480\(%rsp\) +** movq %r30, 488\(%rsp\) +** movq %r31, 496\(%rsp\) +**... +** movaps %xmm0, \(%rsp\) +** movaps %xmm1, 16\(%rsp\) +** movaps %xmm2, 32\(%rsp\) +** movaps %xmm3, 48\(%rsp\) +** movaps %xmm4, 64\(%rsp\) +** movaps %xmm5, 80\(%rsp\) +** movaps %xmm6, 96\(%rsp\) +** movaps %xmm7, 112\(%rsp\) +** movaps %xmm8, 128\(%rsp\) +** movaps %xmm9, 144\(%rsp\) +** movaps %xmm10, 160\(%rsp\) +** movaps %xmm11, 176\(%rsp\) +** movaps %xmm12, 192\(%rsp\) +** movaps %xmm13, 208\(%rsp\) +** movaps %xmm14, 224\(%rsp\) +** movaps %xmm15, 240\(%rsp\) +**... +** call \*code\(%rip\) +** movaps \(%rsp\), %xmm0 +** movaps 16\(%rsp\), %xmm1 +** movaps 32\(%rsp\), %xmm2 +** movaps 48\(%rsp\), %xmm3 +** movaps 64\(%rsp\), %xmm4 +** movaps 80\(%rsp\), %xmm5 +** movaps 96\(%rsp\), %xmm6 +** movaps 112\(%rsp\), %xmm7 +** movaps 128\(%rsp\), %xmm8 +** movaps 144\(%rsp\), %xmm9 +** movaps 160\(%rsp\), %xmm10 +** movaps 176\(%rsp\), %xmm11 +** movaps 192\(%rsp\), %xmm12 +** movaps 208\(%rsp\), %xmm13 +** movq 264\(%rsp\), %rax +** movq 272\(%rsp\), %rdx +** movq 280\(%rsp\), %rcx +** movq 288\(%rsp\), %rbx +** movq 296\(%rsp\), %rsi +** movq 304\(%rsp\), %rdi +** movq 312\(%rsp\), %r8 +** movq 320\(%rsp\), %r9 +** movq 328\(%rsp\), %r10 +** movq 336\(%rsp\), %r11 +** movq 344\(%rsp\), %r12 +** movq 352\(%rsp\), %r13 +** movq 360\(%rsp\), %r14 +** movq 368\(%rsp\), %r15 +** movq 376\(%rsp\), %r16 +** movq 384\(%rsp\), %r17 +** movaps 224\(%rsp\), %xmm14 +** movaps 240\(%rsp\), %xmm15 +** movq 392\(%rsp\), %r18 +** movq 400\(%rsp\), %r19 +** movq 408\(%rsp\), %r20 +** movq 416\(%rsp\), %r21 +** movq 424\(%rsp\), %r22 +** movq 432\(%rsp\), %r23 +** movq 440\(%rsp\), %r24 +** movq 448\(%rsp\), %r25 +** movq 456\(%rsp\), %r26 +** movq 464\(%rsp\), %r27 +** movq 472\(%rsp\), %r28 +** movq 480\(%rsp\), %r29 +** movq 488\(%rsp\), %r30 +** movq 496\(%rsp\), %r31 +** addq \$504, %rsp +**... +** ret +** .cfi_endproc +**... +*/ + +#include "no-callee-saved-19a.c" diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-19e.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-19e.c new file mode 100644 index 0000000..3fcb41f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-19e.c @@ -0,0 +1,162 @@ +/* { dg-do compile { target { *-*-linux* && maybe_x32 } } } */ +/* { dg-options "-O2 -mx32 -fno-pic -mtune=generic -msse2 -mapxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* end must be empty. */ + +/* +**end: +**.LFB[0-9]+: +** .cfi_startproc +** ret +** .cfi_endproc +**... +*/ + +/* inc doesn't have any callee saved registers. */ + +/* +**inc: +**.LFB[0-9]+: +** .cfi_startproc +** addl \$1, accumulator\(%rip\) +** movq %rdi, %rax +** movl \(%eax\), %eax +** leal 4\(%rdi\), %edi +** jmp \*%rax +** .cfi_endproc +**... +*/ + +/* dec doesn't have any callee saved registers. */ + +/* +**dec: +**.LFB[0-9]+: +** .cfi_startproc +** subl \$1, accumulator\(%rip\) +** movq %rdi, %rax +** movl \(%eax\), %eax +** leal 4\(%rdi\), %edi +** jmp \*%rax +** .cfi_endproc +**... +*/ + +/* start must save and restore all caller saved registers. */ + +/* +**start: +**.LFB[0-9]+: +** .cfi_startproc +** subl \$504, %esp +**... +** movq %rax, 256\(%rsp\) +** movq %rdx, 264\(%rsp\) +** movq %rcx, 272\(%rsp\) +** movq %rbx, 280\(%rsp\) +** movq %rsi, 288\(%rsp\) +** movq %rdi, 296\(%rsp\) +**... +** movl \$code\+4, %edi +** movq %rbp, 304\(%rsp\) +** movq %r8, 312\(%rsp\) +** movq %r9, 320\(%rsp\) +** movq %r10, 328\(%rsp\) +** movq %r11, 336\(%rsp\) +** movq %r12, 344\(%rsp\) +** movq %r13, 352\(%rsp\) +** movq %r14, 360\(%rsp\) +** movq %r15, 368\(%rsp\) +** movq %r16, 376\(%rsp\) +** movq %r17, 384\(%rsp\) +** movq %r18, 392\(%rsp\) +** movq %r19, 400\(%rsp\) +** movq %r20, 408\(%rsp\) +** movq %r21, 416\(%rsp\) +** movq %r22, 424\(%rsp\) +** movq %r23, 432\(%rsp\) +** movq %r24, 440\(%rsp\) +** movq %r25, 448\(%rsp\) +** movq %r26, 456\(%rsp\) +** movq %r27, 464\(%rsp\) +** movq %r28, 472\(%rsp\) +** movq %r29, 480\(%rsp\) +** movq %r30, 488\(%rsp\) +** movq %r31, 496\(%rsp\) +**... +** movl code\(%rip\), %ebp +** movaps %xmm0, \(%rsp\) +** movaps %xmm1, 16\(%rsp\) +** movaps %xmm2, 32\(%rsp\) +** movaps %xmm3, 48\(%rsp\) +** movaps %xmm4, 64\(%rsp\) +** movaps %xmm5, 80\(%rsp\) +** movaps %xmm6, 96\(%rsp\) +** movaps %xmm7, 112\(%rsp\) +** movaps %xmm8, 128\(%rsp\) +** movaps %xmm9, 144\(%rsp\) +** movaps %xmm10, 160\(%rsp\) +** movaps %xmm11, 176\(%rsp\) +** movaps %xmm12, 192\(%rsp\) +** movaps %xmm13, 208\(%rsp\) +** movaps %xmm14, 224\(%rsp\) +** movaps %xmm15, 240\(%rsp\) +**... +** call \*%rbp +** movaps \(%rsp\), %xmm0 +** movaps 16\(%rsp\), %xmm1 +** movaps 32\(%rsp\), %xmm2 +** movaps 48\(%rsp\), %xmm3 +** movaps 64\(%rsp\), %xmm4 +** movaps 80\(%rsp\), %xmm5 +** movaps 96\(%rsp\), %xmm6 +** movaps 112\(%rsp\), %xmm7 +** movaps 128\(%rsp\), %xmm8 +** movaps 144\(%rsp\), %xmm9 +** movaps 160\(%rsp\), %xmm10 +** movaps 176\(%rsp\), %xmm11 +** movaps 192\(%rsp\), %xmm12 +** movaps 208\(%rsp\), %xmm13 +** movaps 224\(%rsp\), %xmm14 +** movaps 240\(%rsp\), %xmm15 +** movq 256\(%rsp\), %rax +** movq 264\(%rsp\), %rdx +** movq 272\(%rsp\), %rcx +** movq 280\(%rsp\), %rbx +** movq 288\(%rsp\), %rsi +** movq 296\(%rsp\), %rdi +** movq 304\(%rsp\), %rbp +** movq 312\(%rsp\), %r8 +** movq 320\(%rsp\), %r9 +** movq 328\(%rsp\), %r10 +** movq 336\(%rsp\), %r11 +** movq 344\(%rsp\), %r12 +** movq 352\(%rsp\), %r13 +** movq 360\(%rsp\), %r14 +** movq 368\(%rsp\), %r15 +** movq 376\(%rsp\), %r16 +** movq 384\(%rsp\), %r17 +** movq 392\(%rsp\), %r18 +** movq 400\(%rsp\), %r19 +** movq 408\(%rsp\), %r20 +** movq 416\(%rsp\), %r21 +** movq 424\(%rsp\), %r22 +** movq 432\(%rsp\), %r23 +** movq 440\(%rsp\), %r24 +** movq 448\(%rsp\), %r25 +** movq 456\(%rsp\), %r26 +** movq 464\(%rsp\), %r27 +** movq 472\(%rsp\), %r28 +** movq 480\(%rsp\), %r29 +** movq 488\(%rsp\), %r30 +** movq 496\(%rsp\), %r31 +** addl \$504, %esp +**... +** ret +** .cfi_endproc +**... +*/ + +#include "no-callee-saved-19a.c" diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-2.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-2.c index 98e2701..e074ca5 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-2.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-2.c @@ -26,5 +26,7 @@ foo (void *frame) } } -/* { dg-final { scan-assembler-not "push" } } */ -/* { dg-final { scan-assembler-not "pop" } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*" 1 } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-3.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-3.c index 453272e..44ad0b2 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-3.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-3.c @@ -3,6 +3,6 @@ __attribute__ ((no_callee_saved_registers, no_caller_saved_registers)) void -foo (void) /* { dg-error "attributes are not compatible" } */ -{ +foo (void) +{ /* { dg-error "attributes are not compatible" } */ } diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-7.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-7.c index a1837fd..821d1e2 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-7.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-7.c @@ -17,7 +17,7 @@ foo (void) /* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ /* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ /* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ -/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ /* { dg-final { scan-assembler-times "pushl\[\\t \]*%esi" 1 { target ia32 } } } */ /* { dg-final { scan-assembler-not "pushq\[\\t \]*%rsi" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-times "pushl\[\\t \]*%edi" 1 { target ia32 } } } */ @@ -34,7 +34,7 @@ foo (void) /* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ /* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ /* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ -/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ /* { dg-final { scan-assembler-times "popl\[\\t \]*%esi" 1 { target ia32 } } } */ /* { dg-final { scan-assembler-not "popq\[\\t \]*%rsi" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-times "popl\[\\t \]*%edi" 1 { target ia32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-8.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-8.c index 90b98a2..ed3d96b 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-8.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-8.c @@ -18,7 +18,7 @@ foo (void) /* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ /* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ /* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ -/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ /* { dg-final { scan-assembler-times "pushl\[\\t \]*%esi" 1 { target ia32 } } } */ /* { dg-final { scan-assembler-not "pushq\[\\t \]*%rsi" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-times "pushl\[\\t \]*%edi" 1 { target ia32 } } } */ @@ -35,7 +35,7 @@ foo (void) /* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ /* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ /* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ -/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ /* { dg-final { scan-assembler-times "popl\[\\t \]*%esi" 1 { target ia32 } } } */ /* { dg-final { scan-assembler-not "popq\[\\t \]*%rsi" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-times "popl\[\\t \]*%edi" 1 { target ia32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-9.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-9.c index e261100..7730c59 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-9.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-9.c @@ -17,7 +17,7 @@ foo (fn_t bar) /* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ /* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ /* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ -/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ /* { dg-final { scan-assembler-times "pushl\[\\t \]*%esi" 1 { target ia32 } } } */ /* { dg-final { scan-assembler-not "pushq\[\\t \]*%rsi" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-times "pushl\[\\t \]*%edi" 1 { target ia32 } } } */ @@ -34,7 +34,7 @@ foo (fn_t bar) /* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ /* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ /* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ -/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ /* { dg-final { scan-assembler-times "popl\[\\t \]*%esi" 1 { target ia32 } } } */ /* { dg-final { scan-assembler-not "popq\[\\t \]*%rsi" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-times "popl\[\\t \]*%edi" 1 { target ia32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/noevex512-1.c b/gcc/testsuite/gcc.target/i386/noevex512-1.c deleted file mode 100644 index 89eb528..0000000 --- a/gcc/testsuite/gcc.target/i386/noevex512-1.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O0 -march=x86-64 -mavx512f -mno-evex512 -Wno-psabi" } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler-not ".%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__m512d -foo () -{ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/noevex512-2.c b/gcc/testsuite/gcc.target/i386/noevex512-2.c deleted file mode 100644 index 34740ff..0000000 --- a/gcc/testsuite/gcc.target/i386/noevex512-2.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mavx512bw -mno-evex512" } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ - -#include <immintrin.h> - -long long -foo (long long c) -{ - register long long a __asm ("k7") = c; - long long b = foo (a); - asm volatile ("" : "+k" (b)); - return b; -} diff --git a/gcc/testsuite/gcc.target/i386/noevex512-3.c b/gcc/testsuite/gcc.target/i386/noevex512-3.c deleted file mode 100644 index 10e00c2..0000000 --- a/gcc/testsuite/gcc.target/i386/noevex512-3.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -Wno-psabi -mavx512f" } */ -/* { dg-final { scan-assembler-not ".%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("no-evex512"))) __m512d -foo () -{ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/pr100865-10b.c b/gcc/testsuite/gcc.target/i386/pr100865-10b.c index f60d1bf..17847ac 100644 --- a/gcc/testsuite/gcc.target/i386/pr100865-10b.c +++ b/gcc/testsuite/gcc.target/i386/pr100865-10b.c @@ -4,4 +4,4 @@ #include "pr100865-10a.c" /* { dg-final { scan-assembler-times "vpbroadcastd\[\\t \]+%(?:r|e)\[^\n\]*, %ymm\[0-9\]+" 1 } } */ -/* { dg-final { scan-assembler-times "vmovdqu8\[\\t \]%ymm\[0-9\]+, " 8 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, " 8 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr100865-3.c b/gcc/testsuite/gcc.target/i386/pr100865-3.c index 433fd81..caa083c 100644 --- a/gcc/testsuite/gcc.target/i386/pr100865-3.c +++ b/gcc/testsuite/gcc.target/i386/pr100865-3.c @@ -11,6 +11,6 @@ foo (void) } /* { dg-final { scan-assembler-times "vpbroadcastd\[\\t \]+%(?:r|e)\[^\n\]*, %xmm\[0-9\]+" 1 } } */ -/* { dg-final { scan-assembler-times "vmovdqu8\[\\t \]%xmm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%xmm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ /* { dg-final { scan-assembler-not "vpbroadcastd\[\\t \]+%xmm\[0-9\]+, %xmm\[0-9\]+" } } */ /* { dg-final { scan-assembler-not "vmovdqa" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr100865-4b.c b/gcc/testsuite/gcc.target/i386/pr100865-4b.c index 6fd703e..7017de90 100644 --- a/gcc/testsuite/gcc.target/i386/pr100865-4b.c +++ b/gcc/testsuite/gcc.target/i386/pr100865-4b.c @@ -5,7 +5,7 @@ #include "pr100865-4a.c" /* { dg-final { scan-assembler-times "vpbroadcastd\[\\t \]+%(?:r|e)\[^\n\]*, %ymm\[0-9\]+" 1 } } */ -/* { dg-final { scan-assembler-times "vmovdqu8\[\\t \]%ymm\[0-9\]+, " 2 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, " 2 } } */ /* { dg-final { scan-assembler-times "vzeroupper" 1 } } */ /* { dg-final { scan-assembler-not "vpbroadcastd\[\\t \]+%xmm\[0-9\]+, %ymm\[0-9\]+" } } */ /* { dg-final { scan-assembler-not "vmovdqa" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr100865-5b.c b/gcc/testsuite/gcc.target/i386/pr100865-5b.c index 6c2b33d..8b8ed93 100644 --- a/gcc/testsuite/gcc.target/i386/pr100865-5b.c +++ b/gcc/testsuite/gcc.target/i386/pr100865-5b.c @@ -5,6 +5,6 @@ #include "pr100865-5a.c" /* { dg-final { scan-assembler-times "vpbroadcastd\[\\t \]+%(?:r|e)\[^\n\]*, %ymm\[0-9\]+" 1 } } */ -/* { dg-final { scan-assembler-times "vmovdqu16\[\\t \]%ymm\[0-9\]+, " 4 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, " 4 } } */ /* { dg-final { scan-assembler-not "vpbroadcastd\[\\t \]+%xmm\[0-9\]+, %ymm\[0-9\]+" } } */ /* { dg-final { scan-assembler-not "vmovdqa" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr103771-4.c b/gcc/testsuite/gcc.target/i386/pr103771-4.c new file mode 100644 index 0000000..299337d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr103771-4.c @@ -0,0 +1,82 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v4 -Ofast -fdump-tree-vect-details" } */ +/* { dg-final { scan-assembler-not "kshift" { target { ! ia32 } } } } */ +/* { dg-final { scan-tree-dump-times "loop vectorized using 64 byte vectors" 6 "vect" { target { ! ia32 } } } } */ + +void +foo (float* a, float* b, int* c, int* d, long long* __restrict e, int n) +{ + for (int i = 0 ; i != n; i++) + { + long long tmp = c[i]; + long long tmp2 = d[i]; + if (a[i] < b[i]) + tmp = tmp2; + e[i] = tmp; + } +} + +void +foo1 (double* a, double* b, long long* c, long long* d, int* __restrict e, int n) +{ + for (int i = 0 ; i != n; i++) + { + int tmp = (int)c[i]; + int tmp2 = (int)d[i]; + if (a[i] < b[i]) + tmp = tmp2; + e[i] = tmp; + } +} + +void +foo2 (float* a, float* b, int* c, int* d, double* __restrict e, int n) +{ + for (int i = 0 ; i != n; i++) + { + double tmp = c[i]; + double tmp2 = d[i]; + if (a[i] < b[i]) + tmp = tmp2; + e[i] = tmp; + } +} + +void +foo3 (double* a, double* b, long long* c, long long* d, float* __restrict e, int n) +{ + for (int i = 0 ; i != n; i++) + { + float tmp = c[i]; + float tmp2 = d[i]; + if (a[i] < b[i]) + tmp = tmp2; + e[i] = tmp; + } +} + +void +foo4 (int* a, int* b, int* c, int* d, double* __restrict e, int n) +{ + for (int i = 0 ; i != n; i++) + { + double tmp = c[i]; + double tmp2 = d[i]; + if (a[i] < b[i]) + tmp = tmp2; + e[i] = tmp; + } +} + +void +foo5 (long long* a, long long* b, long long* c, long long* d, float* __restrict e, int n) +{ + for (int i = 0 ; i != n; i++) + { + float tmp = c[i]; + float tmp2 = d[i]; + if (a[i] < b[i]) + tmp = tmp2; + e[i] = tmp; + } +} diff --git a/gcc/testsuite/gcc.target/i386/pr103771-5.c b/gcc/testsuite/gcc.target/i386/pr103771-5.c new file mode 100644 index 0000000..bf94f53 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr103771-5.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v4 -O3 -fno-trapping-math -fdump-tree-vect-details" } */ +/* { dg-final { scan-assembler-not "kshift" { target { ! ia32 } } } } */ +/* { dg-final { scan-tree-dump-times "loop vectorized using 64 byte vectors" 4 "vect" { target { ! ia32 } } } } */ + +void +foo (float* a, float* b, float* c, float* d, double* __restrict e, int n) +{ + for (int i = 0 ; i != n; i++) + { + float tmp = c[i] + d[i]; + if (a[i] < b[i]) + tmp = 0.0; + e[i] = tmp; + } +} + +void +foo1 (int* a, int* b, float* c, float* d, double* __restrict e, int n) +{ + for (int i = 0 ; i != n; i++) + { + float tmp = c[i] + d[i]; + if (a[i] < b[i]) + tmp = 0.0; + e[i] = tmp; + } +} + + +void +foo2 (double* a, double* b, double* c, double* d, float* __restrict e, int n) +{ + for (int i = 0 ; i != n; i++) + { + float tmp = c[i] + d[i]; + if (a[i] < b[i]) + tmp = 0.0; + e[i] = tmp; + } +} + +void +foo3 (long long* a, long long* b, double* c, double* d, float* __restrict e, int n) +{ + for (int i = 0 ; i != n; i++) + { + float tmp = c[i] + d[i]; + if (a[i] < b[i]) + tmp = 0.0; + e[i] = tmp; + } +} + diff --git a/gcc/testsuite/gcc.target/i386/pr103771-6.c b/gcc/testsuite/gcc.target/i386/pr103771-6.c new file mode 100644 index 0000000..92de6f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr103771-6.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v4 -O3 -fno-trapping-math -fdump-tree-vect-details" } */ +/* { dg-final { scan-tree-dump-not "vect_recog_cond_expr_convert_pattern" "vect" } } */ +/* { dg-final { scan-tree-dump-times "loop vectorized using 64 byte vectors" 1 "vect" { target { ! ia32 } } } } */ + +void +foo (float* a, float* b, float* c, float* d, double* __restrict e, int n) +{ + for (int i = 0 ; i != n; i++) + { + double tmp = c[i] + d[i]; + if (a[i] < b[i]) + tmp = 1.000000000000001; + e[i] = tmp; + } +} diff --git a/gcc/testsuite/gcc.target/i386/pr103785.c b/gcc/testsuite/gcc.target/i386/pr103785.c index 5503b96..49d6c56 100644 --- a/gcc/testsuite/gcc.target/i386/pr103785.c +++ b/gcc/testsuite/gcc.target/i386/pr103785.c @@ -11,7 +11,10 @@ struct wrapper_t struct wrapper_t **table; -__attribute__ ((weak, regparm (2))) +#ifndef __x86_64__ +__attribute__ ((regparm (2))) +#endif +__attribute__ ((weak)) void update (long k, long e) { diff --git a/gcc/testsuite/gcc.target/i386/pr104447.c b/gcc/testsuite/gcc.target/i386/pr104447.c index cb618c7..145ba90 100644 --- a/gcc/testsuite/gcc.target/i386/pr104447.c +++ b/gcc/testsuite/gcc.target/i386/pr104447.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-profiling "-pg" } */ /* { dg-options "-O2 -pg" } */ +/* { dg-additional-options "-mfentry -fno-pic" { target *-*-gnu* } } */ int bar (int x) diff --git a/gcc/testsuite/gcc.target/i386/pr108938-3.c b/gcc/testsuite/gcc.target/i386/pr108938-3.c index 757a0c4..47293d4 100644 --- a/gcc/testsuite/gcc.target/i386/pr108938-3.c +++ b/gcc/testsuite/gcc.target/i386/pr108938-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -ftree-vectorize -mno-movbe -mno-avx" } */ +/* { dg-options "-O2 -ftree-vectorize -mno-movbe -msse2 -mno-avx" } */ /* { dg-final { scan-assembler-times "bswap\[\t ]+" 2 { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-times "bswap\[\t ]+" 3 { target ia32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr110310.c b/gcc/testsuite/gcc.target/i386/pr110310.c index dce388a..6056439 100644 --- a/gcc/testsuite/gcc.target/i386/pr110310.c +++ b/gcc/testsuite/gcc.target/i386/pr110310.c @@ -9,5 +9,5 @@ void foo (int * __restrict a, int *b) /* We should vectorize the main loop with AVX512 and the epilog with SSE. */ -/* { dg-final { scan-tree-dump "optimized: loop vectorized using 64 byte vectors" "vect" } } */ -/* { dg-final { scan-tree-dump "optimized: loop vectorized using 16 byte vectors" "vect" } } */ +/* { dg-final { scan-tree-dump "loop vectorized using 64 byte vectors" "vect" } } */ +/* { dg-final { scan-tree-dump "loop vectorized using 16 byte vectors" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr111068.c b/gcc/testsuite/gcc.target/i386/pr111068.c index 70c1e9a..49a853d 100644 --- a/gcc/testsuite/gcc.target/i386/pr111068.c +++ b/gcc/testsuite/gcc.target/i386/pr111068.c @@ -1,7 +1,6 @@ /* PR target/111068 */ /* { dg-do compile } */ /* { dg-options "-ffloat-store -mavx10.1" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ typedef _Float16 __attribute__((__vector_size__ (8))) V; V u, v, w; diff --git a/gcc/testsuite/gcc.target/i386/pr111657-1.c b/gcc/testsuite/gcc.target/i386/pr111657-1.c index a4ba210..fa9f4cf 100644 --- a/gcc/testsuite/gcc.target/i386/pr111657-1.c +++ b/gcc/testsuite/gcc.target/i386/pr111657-1.c @@ -1,5 +1,26 @@ /* { dg-do assemble } */ /* { dg-options "-O2 -mno-sse -mtune=generic -save-temps" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**bar: +**... +**.L[0-9]+: +** movl %edx, %eax +** addl \$32, %edx +** movq %gs:m\(%rax\), %r9 +** movq %gs:m\+8\(%rax\), %r8 +** movq %gs:m\+16\(%rax\), %rsi +** movq %gs:m\+24\(%rax\), %rcx +** movq %r9, \(%rdi,%rax\) +** movq %r8, 8\(%rdi,%rax\) +** movq %rsi, 16\(%rdi,%rax\) +** movq %rcx, 24\(%rdi,%rax\) +** cmpl \$224, %edx +** jb .L[0-9]+ +**... +*/ typedef unsigned long uword __attribute__ ((mode (word))); @@ -8,5 +29,4 @@ struct a { uword arr[30]; }; __seg_gs struct a m; void bar (struct a *dst) { *dst = m; } -/* { dg-final { scan-assembler "gs\[ \t\]+rep\[; \t\]+movs(l|q)" { target { ! x32 } } } } */ -/* { dg-final { scan-assembler-not "gs\[ \t\]+rep\[; \t\]+movs(l|q)" { target x32 } } } */ +/* { dg-final { scan-assembler-not "rep movs" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr111889.c b/gcc/testsuite/gcc.target/i386/pr111889.c deleted file mode 100644 index 4f7682a..0000000 --- a/gcc/testsuite/gcc.target/i386/pr111889.c +++ /dev/null @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64" } */ - -#include <immintrin.h> - -__attribute__ ((target ("no-evex512,avx512vl"))) -__m256d foo (__m256d __W, __mmask8 __U, __m256d __A) -{ - return _mm256_mask_mov_pd (__W, __U, __A); -} diff --git a/gcc/testsuite/gcc.target/i386/pr111907.c b/gcc/testsuite/gcc.target/i386/pr111907.c deleted file mode 100644 index cadc9e4..0000000 --- a/gcc/testsuite/gcc.target/i386/pr111907.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-mavx512f -mno-evex512" } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ - -_Float128 -foo (_Float128 d, _Float128 e) -{ - return __builtin_copysignf128 (d, e); -} diff --git a/gcc/testsuite/gcc.target/i386/pr113122-3.c b/gcc/testsuite/gcc.target/i386/pr113122-3.c index 71aa240..87b76de 100644 --- a/gcc/testsuite/gcc.target/i386/pr113122-3.c +++ b/gcc/testsuite/gcc.target/i386/pr113122-3.c @@ -2,6 +2,7 @@ /* { dg-do assemble { target *-*-linux* } } */ /* { dg-require-effective-target masm_intel } */ /* { dg-options "-fprofile -O2 -masm=intel" } */ +/* { dg-additional-options "-mfentry -fno-pic" { target *-*-gnu* } } */ void func (void) diff --git a/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c b/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c index d34ebb7..d2753cb 100644 --- a/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c +++ b/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mvaes -mevex512 -mno-xsave -Wno-psabi" } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ +/* { dg-options "-O2 -mvaes -mno-xsave -Wno-psabi" } */ typedef __attribute__((__vector_size__(64))) char V; diff --git a/gcc/testsuite/gcc.target/i386/pr117304-1.c b/gcc/testsuite/gcc.target/i386/pr117304-1.c deleted file mode 100644 index 58fb53c..0000000 --- a/gcc/testsuite/gcc.target/i386/pr117304-1.c +++ /dev/null @@ -1,29 +0,0 @@ -/* PR target/117304 */ -/* { dg-do compile } */ -/* { dg-options "-O2 -mavx512f -mno-evex512" } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ - -typedef __attribute__((__vector_size__(32))) int __v8si; -typedef __attribute__((__vector_size__(32))) unsigned int __v8su; -typedef __attribute__((__vector_size__(64))) double __v8df; -typedef __attribute__((__vector_size__(64))) int __v16si; -typedef __attribute__((__vector_size__(64))) unsigned int __v16su; -typedef __attribute__((__vector_size__(64))) float __v16sf; -typedef float __m512 __attribute__ ((__vector_size__ (64), __may_alias__)); - -volatile __v8df df; -volatile __v16sf sf; -volatile __v8si hi; -volatile __v8su hui; -volatile __v16si i; -volatile __v16su ui; - -void -foo() -{ - hi ^= __builtin_ia32_cvttpd2dq512_mask(df, hi, 0, 4); /* { dg-error "implicit declaration of function '__builtin_ia32_cvttpd2dq512_mask'; did you mean '__builtin_ia32_\[^\n\r]*'?" } */ - hui ^= __builtin_ia32_cvttpd2udq512_mask(df, hui, 0, 4); /* { dg-error "implicit declaration of function '__builtin_ia32_cvttpd2udq512_mask'; did you mean '__builtin_ia32_\[^\n\r]*'?" } */ - ui ^= __builtin_ia32_cvttps2dq512_mask(sf, ui, 0, 4); /* { dg-error "implicit declaration of function '__builtin_ia32_cvttps2dq512_mask'; did you mean '__builtin_ia32_\[^\n\r]*'?" } */ - ui ^= __builtin_ia32_cvttps2udq512_mask(sf, ui, 0, 4); /* { dg-error "implicit declaration of function '__builtin_ia32_cvttps2udq512_mask'; did you mean '__builtin_ia32_\[^\n\r]*'?" } */ - __builtin_ia32_cvtudq2ps512_mask(ui, sf, 0, 4); /* { dg-error "implicit declaration of function '__builtin_ia32_cvtudq2ps512_mask'; did you mean '__builtin_ia32_\[^\n\r]*'?" } */ -} diff --git a/gcc/testsuite/gcc.target/i386/pr117946.c b/gcc/testsuite/gcc.target/i386/pr117946.c index b46921c..c36b4ef 100644 --- a/gcc/testsuite/gcc.target/i386/pr117946.c +++ b/gcc/testsuite/gcc.target/i386/pr117946.c @@ -1,7 +1,6 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-require-effective-target dfp } */ /* { dg-options "-O -favoid-store-forwarding -mavx10.1 -mprefer-avx128 --param=store-forwarding-max-distance=128 -Wno-psabi" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ typedef __attribute__((__vector_size__ (64))) _Decimal32 V; void diff --git a/gcc/testsuite/gcc.target/i386/pr118994-1.c b/gcc/testsuite/gcc.target/i386/pr118994-1.c new file mode 100644 index 0000000..5f40aba --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr118994-1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512bw -mavx512vl -O2 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times "\.AVG_CEIL" 6 "optimized"} } */ + +#define VecRoundingAvg(a, b) ((a >> 1) + (b >> 1) + ((a | b) & 1)) + +typedef unsigned char GccU8x16Vec __attribute__((__vector_size__(16))); +typedef unsigned short GccU16x8Vec __attribute__((__vector_size__(16))); +typedef unsigned char GccU8x32Vec __attribute__((__vector_size__(32))); +typedef unsigned short GccU16x16Vec __attribute__((__vector_size__(32))); +typedef unsigned char GccU8x64Vec __attribute__((__vector_size__(64))); +typedef unsigned short GccU16x32Vec __attribute__((__vector_size__(64))); + +GccU8x16Vec U8x16VecRoundingAvg(GccU8x16Vec a, GccU8x16Vec b) { + return VecRoundingAvg(a, b); +} + +GccU16x8Vec U16x8VecRoundingAvg(GccU16x8Vec a, GccU16x8Vec b) { + return VecRoundingAvg(a, b); +} + +GccU8x32Vec U8x32VecRoundingAvg(GccU8x32Vec a, GccU8x32Vec b) { + return VecRoundingAvg(a, b); +} + +GccU16x16Vec U16x16VecRoundingAvg(GccU16x16Vec a, GccU16x16Vec b) { + return VecRoundingAvg(a, b); +} + +GccU8x64Vec U8x64VecRoundingAvg(GccU8x64Vec a, GccU8x64Vec b) { + return VecRoundingAvg(a, b); +} + +GccU16x32Vec U16x32VecRoundingAvg(GccU16x32Vec a, GccU16x32Vec b) { + return VecRoundingAvg(a, b); +} + diff --git a/gcc/testsuite/gcc.target/i386/pr118994-2.c b/gcc/testsuite/gcc.target/i386/pr118994-2.c new file mode 100644 index 0000000..ba90e0a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr118994-2.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512bw -mavx512vl -O2 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times "\.AVG_CEIL" 6 "optimized"} } */ + +#define VecRoundingAvg(a, b) ((a | b) - ((a ^ b) >> 1)) + +typedef unsigned char GccU8x16Vec __attribute__((__vector_size__(16))); +typedef unsigned short GccU16x8Vec __attribute__((__vector_size__(16))); +typedef unsigned char GccU8x32Vec __attribute__((__vector_size__(32))); +typedef unsigned short GccU16x16Vec __attribute__((__vector_size__(32))); +typedef unsigned char GccU8x64Vec __attribute__((__vector_size__(64))); +typedef unsigned short GccU16x32Vec __attribute__((__vector_size__(64))); + +GccU8x16Vec U8x16VecRoundingAvg(GccU8x16Vec a, GccU8x16Vec b) { + return VecRoundingAvg(a, b); +} + +GccU16x8Vec U16x8VecRoundingAvg(GccU16x8Vec a, GccU16x8Vec b) { + return VecRoundingAvg(a, b); +} + +GccU8x32Vec U8x32VecRoundingAvg(GccU8x32Vec a, GccU8x32Vec b) { + return VecRoundingAvg(a, b); +} + +GccU16x16Vec U16x16VecRoundingAvg(GccU16x16Vec a, GccU16x16Vec b) { + return VecRoundingAvg(a, b); +} + +GccU8x64Vec U8x64VecRoundingAvg(GccU8x64Vec a, GccU8x64Vec b) { + return VecRoundingAvg(a, b); +} + +GccU16x32Vec U16x32VecRoundingAvg(GccU16x32Vec a, GccU16x32Vec b) { + return VecRoundingAvg(a, b); +} + diff --git a/gcc/testsuite/gcc.target/i386/pr119386-1.c b/gcc/testsuite/gcc.target/i386/pr119386-1.c index 9a0dc64..7a56eac 100644 --- a/gcc/testsuite/gcc.target/i386/pr119386-1.c +++ b/gcc/testsuite/gcc.target/i386/pr119386-1.c @@ -1,7 +1,9 @@ /* PR target/119386 */ /* { dg-do compile { target *-*-linux* } } */ /* { dg-options "-O2 -fpic -pg" } */ -/* { dg-final { scan-assembler "call\[ \t\]+mcount@PLT" } } */ +/* { dg-additional-options "-mfentry" { target { *-*-gnu* && { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+mcount@PLT" { target ia32 } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+__fentry__@PLT" { target { *-*-gnu* && { ! ia32 } } } } } */ int main () diff --git a/gcc/testsuite/gcc.target/i386/pr119386-2.c b/gcc/testsuite/gcc.target/i386/pr119386-2.c index 3ea978e..cddaaf0 100644 --- a/gcc/testsuite/gcc.target/i386/pr119386-2.c +++ b/gcc/testsuite/gcc.target/i386/pr119386-2.c @@ -1,7 +1,8 @@ /* PR target/119386 */ /* { dg-do compile { target *-*-linux* } } */ /* { dg-options "-O2 -fpic -fno-plt -pg" } */ -/* { dg-final { scan-assembler "call\[ \t\]+\\*mcount@GOTPCREL\\(" { target { ! ia32 } } } } */ +/* { dg-additional-options "-mfentry" { target { *-*-gnu* && { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*__fentry__@GOTPCREL" { target { *-*-gnu* && { ! ia32 } } } } } */ /* { dg-final { scan-assembler "call\[ \t\]+\\*mcount@GOT\\(" { target ia32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr119784a.c b/gcc/testsuite/gcc.target/i386/pr119784a.c index 8a119d4..a3b7e4a 100644 --- a/gcc/testsuite/gcc.target/i386/pr119784a.c +++ b/gcc/testsuite/gcc.target/i386/pr119784a.c @@ -11,14 +11,12 @@ ** .cfi_startproc ** subq \$248, %rsp **... -** movq %rax, \(%rsp\) -** movq %rdx, 8\(%rsp\) -** movq %rcx, 16\(%rsp\) -** movq %rbx, 24\(%rsp\) -** movq %rsi, 32\(%rsp\) -** movq %rdi, 40\(%rsp\) -**... -** movq %rbp, 48\(%rsp\) +** movq %rax, 8\(%rsp\) +** movq %rdx, 16\(%rsp\) +** movq %rcx, 24\(%rsp\) +** movq %rbx, 32\(%rsp\) +** movq %rsi, 40\(%rsp\) +** movq %rdi, 48\(%rsp\) ** movq %r8, 56\(%rsp\) ** movq %r9, 64\(%rsp\) ** movq %r10, 72\(%rsp\) @@ -45,13 +43,12 @@ ** movq %r31, 240\(%rsp\) **... ** call \*code\(%rip\) -** movq \(%rsp\), %rax -** movq 8\(%rsp\), %rdx -** movq 16\(%rsp\), %rcx -** movq 24\(%rsp\), %rbx -** movq 32\(%rsp\), %rsi -** movq 40\(%rsp\), %rdi -** movq 48\(%rsp\), %rbp +** movq 8\(%rsp\), %rax +** movq 16\(%rsp\), %rdx +** movq 24\(%rsp\), %rcx +** movq 32\(%rsp\), %rbx +** movq 40\(%rsp\), %rsi +** movq 48\(%rsp\), %rdi ** movq 56\(%rsp\), %r8 ** movq 64\(%rsp\), %r9 ** movq 72\(%rsp\), %r10 diff --git a/gcc/testsuite/gcc.target/i386/pr119795.c b/gcc/testsuite/gcc.target/i386/pr119795.c new file mode 100644 index 0000000..03c91cc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119795.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-O -fschedule-insns -favoid-store-forwarding" } */ + +unsigned a, b, c; + +void +foo (_BitInt(2) b2, unsigned _BitInt(255) by, unsigned _BitInt(5) b5, + unsigned _BitInt(256) *ret) +{ + unsigned _BitInt(255) bx = b2; + by += 0x80000000000000000000000000000000wb; + __builtin_memmove (&b, &c, 3); + unsigned d = b; + unsigned e = __builtin_stdc_rotate_right (0x1uwb % b5, a); + unsigned _BitInt(256) r = by + bx + d + e; + *ret = r; +} + +int +main () +{ + unsigned _BitInt(256) x; + foo (0, -1, 2, &x); + if (x != 0x80000000000000000000000000000000wb) + __builtin_abort(); +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/i386/pr119884.c b/gcc/testsuite/gcc.target/i386/pr119884.c new file mode 100644 index 0000000..34d5b68 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119884.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-dse -favoid-store-forwarding" } */ + +typedef __attribute__((__vector_size__(64))) char V; +char c; +V v; + +char +foo() +{ + v *= c; + return v[0]; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/i386/pr120032-1.c b/gcc/testsuite/gcc.target/i386/pr120032-1.c new file mode 100644 index 0000000..c515124 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120032-1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlzcnt" } */ + +unsigned int +ZSTD_countLeadingZeros32_fallback(unsigned int val) +{ + static const unsigned int DeBruijnClz[32] + = { 0, 9, 1, 10, 13, 21, 2, 29, + 11, 14, 16, 18, 22, 25, 3, 30, + 8, 12, 20, 28, 15, 17, 24, 7, + 19, 27, 23, 6, 26, 5, 4, 31}; + if (val == 0) + __builtin_abort (); + val |= val >> 1; + val |= val >> 2; + val |= val >> 4; + val |= val >> 8; + val |= val >> 16; + return 31 - DeBruijnClz[(val * 0x07C4ACDDU) >> 27]; +} + +/* { dg-final { scan-assembler "lzcnt" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120032-2.c b/gcc/testsuite/gcc.target/i386/pr120032-2.c new file mode 100644 index 0000000..ea2ad40 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120032-2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlzcnt" } */ + +unsigned int +ZSTD_countLeadingZeros32_fallback(unsigned int val) +{ + static const unsigned char DeBruijnClz[32] + = { 0, 9, 1, 10, 13, 21, 2, 29, + 11, 14, 16, 18, 22, 25, 3, 30, + 8, 12, 20, 28, 15, 17, 24, 7, + 19, 27, 23, 6, 26, 5, 4, 31}; + if (val == 0) + __builtin_abort (); + val |= val >> 1; + val |= val >> 2; + val |= val >> 4; + val |= val >> 8; + val |= val >> 16; + return 31 - DeBruijnClz[(val * 0x07C4ACDDU) >> 27]; +} + +/* { dg-final { scan-assembler "lzcnt" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120032-3.c b/gcc/testsuite/gcc.target/i386/pr120032-3.c new file mode 100644 index 0000000..9523bbb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120032-3.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlzcnt" } */ + +unsigned int +ZSTD_countLeadingZeros32_fallback(unsigned int val) +{ + static const unsigned int DeBruijnClz[32] + = { 0, 9, 1, 10, 13, 21, 2, 29, + 11, 14, 16, 18, 22, 25, 3, 30, + 8, 12, 20, 28, 15, 17, 24, 7, + 19, 27, 23, 6, 26, 5, 4, 31}; + val |= val >> 1; + val |= val >> 2; + val |= val >> 4; + val |= val >> 8; + val |= val >> 16; + return 31 - DeBruijnClz[(val * 0x07C4ACDDU) >> 27]; +} + +/* { dg-final { scan-assembler "lzcnt" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120360.c b/gcc/testsuite/gcc.target/i386/pr120360.c new file mode 100644 index 0000000..69c510e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120360.c @@ -0,0 +1,36 @@ +/* PR target/120360 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-stack-protector -masm=att" } */ +/* { dg-additional-options "-fno-pic" { target { ! *-*-darwin* } } } */ +/* { dg-final { scan-assembler-times "\tjn*s\t" 3 } } */ +/* { dg-final { scan-assembler-times "\tcmp\[lq]\t%" 1 } } */ +/* { dg-final { scan-assembler-times "\tcmp\[lq]\t\\\$-1234," 1 } } */ +/* { dg-final { scan-assembler-times "\tcmp\[lq]\t\\\$2345," 1 } } */ +/* { dg-final { scan-assembler-not "\tadd\[lq]\t" { target { ! *-*-darwin* } } } } */ +/* { dg-final { scan-assembler-not "\tsub\[lq]\t" { target { ! *-*-darwin* } } } } */ + +void qux (unsigned long); + +void +foo (unsigned long x, unsigned long y) +{ + unsigned long z = x - y; + if ((long) z < 0) + qux (x); +} + +void +bar (unsigned long x) +{ + unsigned long z = x + 1234; + if ((long) z < 0) + qux (x); +} + +void +baz (unsigned long x) +{ + unsigned long z = x - 2345; + if ((long) z < 0) + qux (x); +} diff --git a/gcc/testsuite/gcc.target/i386/pr120427-1.c b/gcc/testsuite/gcc.target/i386/pr120427-1.c new file mode 100644 index 0000000..7f1690e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120427-1.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=sapphirerapids" } */ +/* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]+\\\$0, \[0-9\]*\\(" } } */ + +struct __pthread_mutex_s +{ + int __lock; + unsigned int __count; + int __owner; + unsigned int __nusers; + int __kind; + short __spins; + short __elision; + void *p[2]; +}; +typedef union +{ + struct __pthread_mutex_s __data; + char __size[40]; + long int __align; +} pthread_mutex_t; +typedef struct { pthread_mutex_t mutex; } __rtld_lock_recursive_t; +void +foo (__rtld_lock_recursive_t *lock, int i) +{ + lock[i] = (__rtld_lock_recursive_t) {{ { 0, 0, 0, 0, 1, + 0, 0, { ((void *)0) , ((void *)0) } } }}; +} diff --git a/gcc/testsuite/gcc.target/i386/pr120427-2.c b/gcc/testsuite/gcc.target/i386/pr120427-2.c new file mode 100644 index 0000000..a380c12 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120427-2.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=sapphirerapids" } */ +/* { dg-final { scan-assembler-not "or\[lq\]?\[\\t \]+\\\$-1, \[0-9\]*\\(" } } */ + +struct __pthread_mutex_s +{ + int __lock; + unsigned int __count; + int __owner; + unsigned int __nusers; + int __kind; + short __spins; + short __elision; + void *p[2]; +}; +typedef union +{ + struct __pthread_mutex_s __data; + char __size[40]; + long int __align; +} pthread_mutex_t; +typedef struct { pthread_mutex_t mutex; } __rtld_lock_recursive_t; +void +foo (__rtld_lock_recursive_t *lock, int i) +{ + lock[i] = (__rtld_lock_recursive_t) {{ { -1, -1, -1, -1, 1, + -1, -1, { ((void *)-1) , ((void *)-1) } } }}; +} diff --git a/gcc/testsuite/gcc.target/i386/pr120427-3.c b/gcc/testsuite/gcc.target/i386/pr120427-3.c new file mode 100644 index 0000000..951cb1f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120427-3.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef int SItype __attribute__ ((mode (SI))); +typedef unsigned int USItype __attribute__ ((mode (SI))); +typedef unsigned int UDItype __attribute__ ((mode (DI))); +typedef UDItype __attribute__ ((__may_alias__)) bar_t; + +static inline __attribute__((__always_inline__)) SItype +bar (const bar_t **p, SItype prec) +{ + bar_t mslimb = 0; + SItype i = 20; + SItype n = ((USItype) prec) % 4; + if (n) + { + prec -= n; + if (prec == 0) + return 1; + mslimb = (*p)[i]; + } + while (mslimb == 0) + { + prec -= 4; + if (prec == 0) + return 1; + --i; + mslimb = (*p)[i]; + } + return prec; +} +UDItype +foo (const bar_t *i, SItype iprec) +{ + iprec = bar (&i, iprec); + USItype aiprec = iprec < 0 ? -iprec : iprec; + bar_t msb = *i; + UDItype mantissa = 0; + if (aiprec % 4) + msb &= ((bar_t) 1 << aiprec) - 1; + if (aiprec >= 54) + mantissa = (UDItype) msb << 32; + + return (mantissa ^ (UDItype) 0x20000000000000); +} diff --git a/gcc/testsuite/gcc.target/i386/pr120427-4.c b/gcc/testsuite/gcc.target/i386/pr120427-4.c new file mode 100644 index 0000000..2b453b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120427-4.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include "cold-attribute-4.c" + +/* { dg-final { scan-assembler "movl" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120427-5.c b/gcc/testsuite/gcc.target/i386/pr120427-5.c new file mode 100644 index 0000000..7199aef --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120427-5.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-Oz" } */ + +long long +func1 (void) +{ + return -1; +} +/* { dg-final { scan-assembler-times "pushq\[ \\t\]+\\\$-1" 1 } } */ +/* { dg-final { scan-assembler-times "popq\[ \\t\]+%rax" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120434-1.c b/gcc/testsuite/gcc.target/i386/pr120434-1.c new file mode 100644 index 0000000..889b6f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120434-1.c @@ -0,0 +1,28 @@ +/* PR middle-end/120434 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic -masm=att" } */ +/* { dg-final { scan-assembler-times "\tsar\[lq]\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tshr\[lq]\t" 2 } } */ + +[[gnu::noipa]] int +foo (int x) +{ + return x / 200; +} + +[[gnu::noipa]] int +bar (int x) +{ + if (x < 0) + __builtin_unreachable (); + return x / 200; +} + +[[gnu::noipa]] int +baz (int x) +{ + if (x >= 0) + return x / 200; + else + return 24; +} diff --git a/gcc/testsuite/gcc.target/i386/pr120434-2.c b/gcc/testsuite/gcc.target/i386/pr120434-2.c new file mode 100644 index 0000000..4381e3b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120434-2.c @@ -0,0 +1,15 @@ +/* PR middle-end/120434 */ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mtune=generic -masm=att" } */ +/* { dg-final { scan-assembler-not "\tmovslq\t%edi, %rdi" } } */ +/* { dg-final { scan-assembler "\tmovl\t%edi, %edi" } } */ + +extern unsigned long long foo (unsigned long long x); + +unsigned long long +bar (int x) +{ + if (x < 50) + return 0; + return foo (x); +} diff --git a/gcc/testsuite/gcc.target/i386/pr120553.c b/gcc/testsuite/gcc.target/i386/pr120553.c new file mode 100644 index 0000000..abbf58c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120553.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +long long foo (long long c) { return c >= 0 ? 0x400000000ll : -1ll; } + +/* { dg-final { scan-assembler "bts" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120689.c b/gcc/testsuite/gcc.target/i386/pr120689.c new file mode 100644 index 0000000..cd10cdb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120689.c @@ -0,0 +1,17 @@ +/* PR target/120689 */ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mtune=generic -fno-stack-protector -masm=att" } */ +/* { dg-final { scan-assembler-not "\t\(movzbl\|shrl\|salq\|orq\)\t" } } */ + +struct S { char a, b, c; }; + +[[gnu::noipa]] +void foo (struct S x, struct S y, struct S z) +{ +} + +void +bar (struct S x, struct S y, struct S z) +{ + [[gnu::musttail]] return foo (x, y, z); +} diff --git a/gcc/testsuite/gcc.target/i386/pr120728.c b/gcc/testsuite/gcc.target/i386/pr120728.c new file mode 100644 index 0000000..93d2cd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120728.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4" } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+, " 3 } } */ +/* { dg-final { scan-assembler-not "vmovdqu8" } } */ +/* { dg-final { scan-assembler-not "vmovdqu16" } } */ + +typedef char __v32qi __attribute__ ((__vector_size__ (32))); +typedef char __v32qi_u __attribute__ ((__vector_size__ (32), + __aligned__ (1))); +typedef short __v16hi __attribute__ ((__vector_size__ (32))); +typedef short __v16hi_u __attribute__ ((__vector_size__ (32), + __aligned__ (1))); +typedef _Float16 __v16hf __attribute__ ((__vector_size__ (32))); +typedef _Float16 __v16hf_u __attribute__ ((__vector_size__ (32), + __aligned__ (1))); + +extern __v32qi_u v1; +extern __v16hi_u v2; +extern __v16hf_u v3; + +void +foo (__v32qi x1, __v16hi x2, __v16hf x3) +{ + v1 = x1; + v2 = x2; + v3 = x3; +} diff --git a/gcc/testsuite/gcc.target/i386/pr120741.c b/gcc/testsuite/gcc.target/i386/pr120741.c new file mode 100644 index 0000000..b59a58c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120741.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mstack-arg-probe" } */ + +short __mingw_swformat_format; +__builtin_va_list __mingw_swformat_arg; +int __mingw_swformat_fc; +typedef struct { + void *fp; + int bch[1024]; +} _IFP; +void __mingw_swformat(_IFP *s) { + if (s->fp) + while (__mingw_swformat_format) + if (__mingw_swformat_fc == 'A') + *__builtin_va_arg(__mingw_swformat_arg, double *) = 0; +} +void +__mingw_vswscanf (void) +{ + _IFP ifp; + __mingw_swformat(&ifp); +} diff --git a/gcc/testsuite/gcc.target/i386/pr120840-1a.c b/gcc/testsuite/gcc.target/i386/pr120840-1a.c new file mode 100644 index 0000000..cc58003 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120840-1a.c @@ -0,0 +1,83 @@ +/* { dg-do run } */ +/* { dg-options "-save-temps -O2 -fno-omit-frame-pointer -mtune-ctrl=prologue_using_move,epilogue_using_move,use_leave" } */ + +#ifndef DONT_SAVE_REGS1 +# define DONT_SAVE_REGS1 __attribute__((no_callee_saved_registers)) +#endif +#ifndef DONT_SAVE_REGS2 +# define DONT_SAVE_REGS2 __attribute__((no_callee_saved_registers)) +#endif + +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-linux*" } {^\t?\.} } } */ + +/* +**do_test: +**.LFB[0-9]+: +**... +** leave +**... +** ret +**... +*/ + +#include <stdlib.h> + +DONT_SAVE_REGS1 +__attribute__ ((weak, __optimize__ ("-fomit-frame-pointer"))) +void +continuation (int arg1, int arg2, int arg3, int arg4, int arg5, int arg6) +{ + /* Clobber frame pointer register. */ + asm ("xor %%ebp, %%ebp" ::: "ebp"); + + if (arg1 != 17) + abort (); + if (arg2 != 8) + abort (); + if (arg3 != 20) + abort (); + if (arg4 != -3) + abort (); + if (arg5 != -4) + abort (); + if (arg6 != 26) + abort (); +} + +DONT_SAVE_REGS2 +__attribute__ ((weak, __optimize__ ("-fomit-frame-pointer"))) +void +entry (int arg1, int arg2, int arg3, int arg4, int arg5, int arg6) +{ + /* Clobber frame pointer register. */ + asm ("xor %%ebp, %%ebp" ::: "ebp"); + + if (arg1 != 17) + abort (); + if (arg2 != 8) + abort (); + if (arg3 != 20) + abort (); + if (arg4 != -3) + abort (); + if (arg5 != -4) + abort (); + if (arg6 != 26) + abort (); + continuation (arg1, arg2, arg3, arg4, arg5, arg6); +} + +__attribute__ ((weak)) +void +do_test (void) +{ + entry (17, 8, 20, -3, -4, 26); +} + +int +main (void) +{ + do_test (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr120840-1b.c b/gcc/testsuite/gcc.target/i386/pr120840-1b.c new file mode 100644 index 0000000..a759e34 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120840-1b.c @@ -0,0 +1,20 @@ +/* { dg-do run } */ +/* { dg-options "-save-temps -O2 -fno-omit-frame-pointer -mtune-ctrl=prologue_using_move,epilogue_using_move,use_leave" } */ + +#define DONT_SAVE_REGS1 __attribute__((preserve_none)) +#define DONT_SAVE_REGS2 __attribute__((no_callee_saved_registers)) + +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-linux*" } {^\t?\.} } } */ + +/* +**do_test: +**.LFB[0-9]+: +**... +** leave +**... +** ret +**... +*/ + +#include "pr120840-1a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr120840-1c.c b/gcc/testsuite/gcc.target/i386/pr120840-1c.c new file mode 100644 index 0000000..84aa353 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120840-1c.c @@ -0,0 +1,20 @@ +/* { dg-do run } */ +/* { dg-options "-save-temps -O2 -fno-omit-frame-pointer -mtune-ctrl=prologue_using_move,epilogue_using_move,use_leave" } */ + +#define DONT_SAVE_REGS1 __attribute__((no_callee_saved_registers)) +#define DONT_SAVE_REGS2 __attribute__((preserve_none)) + +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-linux*" } {^\t?\.} } } */ + +/* +**do_test: +**.LFB[0-9]+: +**... +** leave +**... +** ret +**... +*/ + +#include "pr120840-1a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr120840-1d.c b/gcc/testsuite/gcc.target/i386/pr120840-1d.c new file mode 100644 index 0000000..a6b38a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120840-1d.c @@ -0,0 +1,20 @@ +/* { dg-do run } */ +/* { dg-options "-save-temps -O2 -fno-omit-frame-pointer -mtune-ctrl=prologue_using_move,epilogue_using_move,use_leave" } */ + +#define DONT_SAVE_REGS1 __attribute__((preserve_none)) +#define DONT_SAVE_REGS2 __attribute__((preserve_none)) + +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-linux*" } {^\t?\.} } } */ + +/* +**do_test: +**.LFB[0-9]+: +**... +** leave +**... +** ret +**... +*/ + +#include "pr120840-1a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr120881-1a.c b/gcc/testsuite/gcc.target/i386/pr120881-1a.c new file mode 100644 index 0000000..3d9ac0e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-1a.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target fpic } } */ +/* { dg-require-profiling "-pg" } */ +/* { dg-options "-O2 -pg -mno-fentry -fno-pic" } */ +/* { dg-message "'-pg' without '-mfentry' may be unreliable with shrink wrapping" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120881-1b.c b/gcc/testsuite/gcc.target/i386/pr120881-1b.c new file mode 100644 index 0000000..0826407 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-1b.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target { fpic && { ! ia32 } } } } */ +/* { dg-require-profiling "-pg" } */ +/* { dg-options "-O2 -pg -mno-fentry -fpic" } */ +/* { dg-message "'-pg' without '-mfentry' may be unreliable with shrink wrapping" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120881-1c.c b/gcc/testsuite/gcc.target/i386/pr120881-1c.c new file mode 100644 index 0000000..c21979f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-1c.c @@ -0,0 +1,3 @@ +/* { dg-do compile { target { fpic && ia32 } } } */ +/* { dg-require-profiling "-pg" } */ +/* { dg-options "-O2 -pg -mno-fentry -fpic" } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120881-1d.c b/gcc/testsuite/gcc.target/i386/pr120881-1d.c new file mode 100644 index 0000000..f74af23 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-1d.c @@ -0,0 +1,3 @@ +/* { dg-do compile { target { fpic && ia32 } } } */ +/* { dg-require-profiling "-pg" } */ +/* { dg-options "-O2 -pg -mno-fentry -fno-shrink-wrap -fno-pic" } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120881-2a.c b/gcc/testsuite/gcc.target/i386/pr120881-2a.c new file mode 100644 index 0000000..52e3e52 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-2a.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target fentry } } */ +/* { dg-options "-O2 -pg" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**f2: +**.LFB[0-9]+: +** .cfi_startproc +** call __fentry__ +**... +*/ + +extern void f1 (void); + +void +f2 (int count) +{ + for (int i = 0; i < count; ++i) + f1 (); +} diff --git a/gcc/testsuite/gcc.target/i386/pr120881-2b.c b/gcc/testsuite/gcc.target/i386/pr120881-2b.c new file mode 100644 index 0000000..43a12f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-2b.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-rtl-pro_and_epilogue -march=x86-64" } */ +/* { dg-final { scan-rtl-dump "Now spread 1 times" "pro_and_epilogue" } } */ + +#include "pr120881-2a.c" + diff --git a/gcc/testsuite/gcc.target/i386/pr120908.c b/gcc/testsuite/gcc.target/i386/pr120908.c new file mode 100644 index 0000000..10e5a46 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120908.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { lp64 && fpic } } } */ +/* { dg-options "-O2 -fpic -mtls-dialect=gnu -mcmodel=large" } */ + +extern __thread long bar1; +long * +foo1 (void) +{ + return &bar1; +} + +static __thread long bar2; +long * +foo2 (void) +{ + return &bar2; +} diff --git a/gcc/testsuite/gcc.target/i386/pr120936-1.c b/gcc/testsuite/gcc.target/i386/pr120936-1.c new file mode 100644 index 0000000..a20680d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120936-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target fpic } } */ +/* { dg-options "-O2 -pg -mno-fentry -fno-pic -fno-shrink-wrap" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +**... +** .cfi_.* +** call mcount +**... +*/ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/i386/pr120936-10.c b/gcc/testsuite/gcc.target/i386/pr120936-10.c new file mode 100644 index 0000000..ab95b08 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120936-10.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target { fpic && lp64 } } } */ +/* { dg-options "-O2 -mcmodel=large -pg -mno-fentry -fpic -fno-shrink-wrap" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^(1|\t?\.)} } } */ + +/* +**foo: +**.LFB[0-9]+: +**... +** .cfi_.* +**1: movabsq \$_GLOBAL_OFFSET_TABLE_-1b, %r11 +** leaq 1b\(%rip\), %r10 +** addq %r11, %r10 +** movabsq \$mcount@PLTOFF, %r11 +** addq %r11, %r10 +** call \*%r10 +**... +*/ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/i386/pr120936-11.c b/gcc/testsuite/gcc.target/i386/pr120936-11.c new file mode 100644 index 0000000..3e39dfe --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120936-11.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { fpic && lp64 } } } */ +/* { dg-options "-O2 -mrecord-mcount -mcmodel=large -pg -mno-fentry -fno-pic -fno-shrink-wrap" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^(1|\t?\.)} } } */ + +/* +**foo: +**.LFB[0-9]+: +**... +** .cfi_.* +**1: movabsq \$mcount, %r10 +** call \*%r10 +**... +*/ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/i386/pr120936-12.c b/gcc/testsuite/gcc.target/i386/pr120936-12.c new file mode 100644 index 0000000..b5a2aac --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120936-12.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target { fpic && lp64 } } } */ +/* { dg-options "-O2 -mcmodel=large -mrecord-mcount -pg -mno-fentry -fpic -fno-shrink-wrap" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^(1|\t?\.)} } } */ + +/* +**foo: +**.LFB[0-9]+: +**... +** .cfi_.* +**1: movabsq \$_GLOBAL_OFFSET_TABLE_-1b, %r11 +** leaq 1b\(%rip\), %r10 +** addq %r11, %r10 +** movabsq \$mcount@PLTOFF, %r11 +** addq %r11, %r10 +** call \*%r10 +**... +*/ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/i386/pr120936-2.c b/gcc/testsuite/gcc.target/i386/pr120936-2.c new file mode 100644 index 0000000..0835658 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120936-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target fpic } } */ +/* { dg-options "-O2 -pg -mno-fentry -fpic -fno-shrink-wrap" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +**... +** .cfi_.* +** call mcount@PLT +**... +*/ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/i386/pr120936-3.c b/gcc/testsuite/gcc.target/i386/pr120936-3.c new file mode 100644 index 0000000..dc0a8f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120936-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target fpic } } */ +/* { dg-options "-O2 -mnop-mcount -pg -mno-fentry -fno-pic -fno-shrink-wrap" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +**... +** .cfi_.* +** .byte 0x0f, 0x1f, 0x44, 0x00, 0x00 +**... +*/ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/i386/pr120936-4.c b/gcc/testsuite/gcc.target/i386/pr120936-4.c new file mode 100644 index 0000000..2420f0b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120936-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target fpic } } */ +/* { dg-options "-O2 -pg -mno-fentry -mrecord-mcount -fno-pic -fno-shrink-wrap" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^(1|\t?\.)} } } */ + +/* +**foo: +**.LFB[0-9]+: +**... +** .cfi_.* +**1: call mcount +**... +*/ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/i386/pr120936-5.c b/gcc/testsuite/gcc.target/i386/pr120936-5.c new file mode 100644 index 0000000..20ecd37 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120936-5.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target fpic } } */ +/* { dg-options "-O2 -pg -mrecord-mcount -mno-fentry -fpic -fno-shrink-wrap" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^(1|\t?\.)} } } */ + +/* +**foo: +**.LFB[0-9]+: +**... +** .cfi_.* +**1: call mcount@PLT +**... +*/ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/i386/pr120936-6.c b/gcc/testsuite/gcc.target/i386/pr120936-6.c new file mode 100644 index 0000000..6e2290f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120936-6.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target fpic } } */ +/* { dg-options "-O2 -mrecord-mcount -mnop-mcount -pg -mno-fentry -fno-pic -fno-shrink-wrap" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^(1|\t?\.)} } } */ + +/* +**foo: +**.LFB[0-9]+: +**... +** .cfi_.* +**1: .byte 0x0f, 0x1f, 0x44, 0x00, 0x00 +**... +*/ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/i386/pr120936-7.c b/gcc/testsuite/gcc.target/i386/pr120936-7.c new file mode 100644 index 0000000..0c86467 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120936-7.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */ +/* { dg-options "-O2 -pg -mno-fentry -fpic -fno-plt -fno-shrink-wrap" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +**... +** .cfi_.* +** call \*mcount@GOTPCREL\(%rip\) +**... +*/ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/i386/pr120936-8.c b/gcc/testsuite/gcc.target/i386/pr120936-8.c new file mode 100644 index 0000000..3f86781 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120936-8.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */ +/* { dg-options "-O2 -pg -mrecord-mcount -mno-fentry -fpic -fno-plt -fno-shrink-wrap" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^(1|\t?\.)} } } */ + +/* +**foo: +**.LFB[0-9]+: +**... +** .cfi_.* +**1: call \*mcount@GOTPCREL\(%rip\) +**... +*/ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/i386/pr120936-9.c b/gcc/testsuite/gcc.target/i386/pr120936-9.c new file mode 100644 index 0000000..3f4b387 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120936-9.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { fpic && lp64 } } } */ +/* { dg-options "-O2 -mcmodel=large -pg -mno-fentry -fno-pic -fno-shrink-wrap" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +**... +** .cfi_.* +** movabsq \$mcount, %r10 +** call \*%r10 +**... +*/ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/i386/pr121015.c b/gcc/testsuite/gcc.target/i386/pr121015.c new file mode 100644 index 0000000..57c8bff --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121015.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3" } */ + +extern union { + int i; + float f; +} int_as_float_u; + +extern int render_result_from_bake_w; +extern int render_result_from_bake_h_seed_pass; +extern float *render_result_from_bake_h_primitive; +extern float *render_result_from_bake_h_seed; + +float +int_as_float(int i) +{ + int_as_float_u.i = i; + return int_as_float_u.f; +} + +void +render_result_from_bake_h(int tx) +{ + while (render_result_from_bake_w) { + for (; tx < render_result_from_bake_w; tx++) + render_result_from_bake_h_primitive[1] = + render_result_from_bake_h_primitive[2] = int_as_float(-1); + if (render_result_from_bake_h_seed_pass) { + *render_result_from_bake_h_seed = 0; + } + } +} diff --git a/gcc/testsuite/gcc.target/i386/pr121062-1.c b/gcc/testsuite/gcc.target/i386/pr121062-1.c new file mode 100644 index 0000000..799f856 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3" } */ + +extern union { + int i; + float f; +} int_as_float_u; + +extern int render_result_from_bake_w; +extern int render_result_from_bake_h_seed_pass; +extern float *render_result_from_bake_h_primitive; +extern float *render_result_from_bake_h_seed; + +float +int_as_float(int i) +{ + int_as_float_u.i = i; + return int_as_float_u.f; +} + +void +render_result_from_bake_h(int tx) +{ + while (render_result_from_bake_w) { + for (; tx < render_result_from_bake_w; tx++) + render_result_from_bake_h_primitive[1] = + render_result_from_bake_h_primitive[2] = int_as_float(-1); + if (render_result_from_bake_h_seed_pass) { + *render_result_from_bake_h_seed = 0; + } + } +} + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+\\\$-1, %r\[a-z0-9\]+" 2 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-2.c b/gcc/testsuite/gcc.target/i386/pr121062-2.c new file mode 100644 index 0000000..723d68a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-Og -fno-dce -mtune=generic" } */ + +typedef int __attribute__((__vector_size__ (4))) S; +extern void bar (S); + +void +foo () +{ + bar ((S){-1}); +} + +/* { dg-final { scan-assembler-times "movl\[ \\t\]+\\\$-1, \\(%esp\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "movl\[ \\t\]+\\\$-1, %edi" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-3a.c b/gcc/testsuite/gcc.target/i386/pr121062-3a.c new file mode 100644 index 0000000..effd4ff --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-3a.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target fpic } } */ +/* { dg-options "-O2 -march=x86-64 -fpic" } */ + +typedef struct { + struct { + unsigned short lo4; + unsigned short lo3; + unsigned short lo2; + unsigned short lo1; + } i; +} BID_BINARY80LDOUBLE; +extern BID_BINARY80LDOUBLE __bid64_to_binary80_x_out; +void +__bid64_to_binary80 (void) +{ + __bid64_to_binary80_x_out.i.lo4 + = __bid64_to_binary80_x_out.i.lo3 + = __bid64_to_binary80_x_out.i.lo2 + = __bid64_to_binary80_x_out.i.lo1 = 65535; +} + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+%xmm\[0-9\]+, " 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "movq\[ \\t\]+\\\$-1, \\(%(e|r)\[a-z0-9\]+\\)" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-3b.c b/gcc/testsuite/gcc.target/i386/pr121062-3b.c new file mode 100644 index 0000000..eb89b5d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-3b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { fpic && lp64 } } } */ +/* { dg-options "-O2 -march=x86-64 -fno-pic -mcmodel=large" } */ + +#include "pr121062-3a.c" + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+\\\$-1, \\(%r\[a-z0-9\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-3c.c b/gcc/testsuite/gcc.target/i386/pr121062-3c.c new file mode 100644 index 0000000..4c07029 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-3c.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { fpic && lp64 } } } */ +/* { dg-options "-O2 -march=x86-64 -fpic -mcmodel=large" } */ + +#include "pr121062-3a.c" + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+\\\$-1, \\(%r\[a-z0-9\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-4.c b/gcc/testsuite/gcc.target/i386/pr121062-4.c new file mode 100644 index 0000000..77a0c2e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64" } */ + +typedef long long int __attribute__((__vector_size__ (8))) S; + +void +foo (S *c) +{ + *c = (S){0x12345678badbeefULL}; +} + + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+%xmm\[0-9\]+, " 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "movabsq\[ \\t\]+\\\$81985529250168559, %r\[a-z0-9\]+" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-5.c b/gcc/testsuite/gcc.target/i386/pr121062-5.c new file mode 100644 index 0000000..22c09a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-5.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64" } */ + +typedef int __attribute__((__vector_size__ (4))) S; + +void +foo (S *c) +{ + *c = (S){0x12345678}; +} + + +/* { dg-final { scan-assembler-times "movl\[ \\t\]+\\\$305419896, \\(%(e|r)\[a-z0-9\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-6.c b/gcc/testsuite/gcc.target/i386/pr121062-6.c new file mode 100644 index 0000000..780b496 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-6.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-Og -fno-dce -mtune=generic" } */ + +typedef int __attribute__((__vector_size__ (8))) S; + +void +foo (S *c) +{ + *c = (S){0x12345678,0xbadbeefULL}; +} + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+%xmm\[0-9\]+, " 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "movabsq\[ \\t\]+\\\$841538639400031864, %r\[a-z0-9\]+" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-7.c b/gcc/testsuite/gcc.target/i386/pr121062-7.c new file mode 100644 index 0000000..f1834f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-7.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64" } */ + +typedef __bf16 __attribute__((__vector_size__ (4))) S; + +void +foo (S *c) +{ + *c = (S){-0.1, 2.1}; +} + + +/* { dg-final { scan-assembler-times "movl\[ \\t\]+\\\$1074183629, \\(%(e|r)\[a-z0-9\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121208-1a.c b/gcc/testsuite/gcc.target/i386/pr121208-1a.c new file mode 100644 index 0000000..cb8bd0b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121208-1a.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fPIC -mno-80387 -mtls-dialect=gnu" } */ + +extern __thread int bar; +extern void func (void); + +__attribute__((no_caller_saved_registers)) +void +foo (int error) +{ + bar = 1; /* { dg-error -mtls-dialect=gnu2 } */ + if (error == 0) + func (); + bar = 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr121208-1b.c b/gcc/testsuite/gcc.target/i386/pr121208-1b.c new file mode 100644 index 0000000..037e9a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121208-1b.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fPIC -mno-80387 -mtls-dialect=gnu2" } */ + +#include "pr121208-1a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr121208-2a.c b/gcc/testsuite/gcc.target/i386/pr121208-2a.c new file mode 100644 index 0000000..c1891ae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121208-2a.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fPIC -mtls-dialect=gnu" } */ + +typedef unsigned int uword_t __attribute__ ((mode (__word__))); +extern __thread int bar; +extern void func (void); + +__attribute__((target("general-regs-only"))) +__attribute__((interrupt)) +void +foo (void *frame, uword_t error) +{ + bar = 1; /* { dg-error -mtls-dialect=gnu2 } */ + if (error == 0) + func (); + bar = 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr121208-2b.c b/gcc/testsuite/gcc.target/i386/pr121208-2b.c new file mode 100644 index 0000000..269b120 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121208-2b.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fPIC -mtls-dialect=gnu2" } */ + +#include "pr121208-2a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr121208-3a.c b/gcc/testsuite/gcc.target/i386/pr121208-3a.c new file mode 100644 index 0000000..26fe687 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121208-3a.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fPIC -mtls-dialect=gnu" } */ + +typedef unsigned int uword_t __attribute__ ((mode (__word__))); +extern __thread int bar; +extern void func (void); + +__attribute__((target("general-regs-only"))) +__attribute__((interrupt)) +void +foo (void *frame) +{ + bar = 1; /* { dg-error -mtls-dialect=gnu2 } */ + if (frame == 0) + func (); + bar = 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr121208-3b.c b/gcc/testsuite/gcc.target/i386/pr121208-3b.c new file mode 100644 index 0000000..b672d75 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121208-3b.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fPIC -mtls-dialect=gnu2" } */ + +#include "pr121208-3a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr121274.c b/gcc/testsuite/gcc.target/i386/pr121274.c new file mode 100644 index 0000000..16760cf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121274.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-march=x86-64-v4 -O2" } */ +/* { dg-final { scan-assembler-not "vpextrq" } } */ +/* { dg-final { scan-assembler-not "vpinsrq" } } */ + +typedef int v16si __attribute__((vector_size(64))); +typedef int v4si __attribute__((vector_size(16))); + +v4si f(v16si x) +{ + return __builtin_shufflevector(x, x, 0, 1, 2, 3); +} + +v4si g(v16si x) +{ +return __builtin_shufflevector(x, x, 4, 5, 6, 7); +} + +v4si f1(__int128 *x) +{ + __int128 t = *x; + asm("":"+x"(t)); + return (v4si)t; +} diff --git a/gcc/testsuite/gcc.target/i386/pr15184-2.c b/gcc/testsuite/gcc.target/i386/pr15184-2.c index cb8201f..dd50c42 100644 --- a/gcc/testsuite/gcc.target/i386/pr15184-2.c +++ b/gcc/testsuite/gcc.target/i386/pr15184-2.c @@ -1,4 +1,4 @@ -/* PR 15184 second two tests +/* PR 15184 second two tests */ /* { dg-do compile { target ia32 } } */ /* { dg-options "-O2 -march=pentiumpro" } */ /* { dg-additional-options "-fno-PIE" { target ia32 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr31985.c b/gcc/testsuite/gcc.target/i386/pr31985.c index a6de1b5..a0a9111 100644 --- a/gcc/testsuite/gcc.target/i386/pr31985.c +++ b/gcc/testsuite/gcc.target/i386/pr31985.c @@ -1,5 +1,5 @@ /* { dg-do compile { target ia32 } } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -fomit-frame-pointer" } */ void test_c (unsigned int a, unsigned int b, unsigned int c, unsigned int d) { diff --git a/gcc/testsuite/gcc.target/i386/pr36533.c b/gcc/testsuite/gcc.target/i386/pr36533.c index 8d71ece..8699d26 100644 --- a/gcc/testsuite/gcc.target/i386/pr36533.c +++ b/gcc/testsuite/gcc.target/i386/pr36533.c @@ -55,14 +55,22 @@ typedef struct S1 *s18; } S7; -__attribute__((regparm (3), noinline)) int +#ifndef __x86_64__ +__attribute__((regparm (3))) +#endif +__attribute__((noinline)) +int fn1 (const char *x, void *y, S1 *z) { asm volatile ("" : : : "memory"); return *x + (y != 0); } -__attribute__((regparm (3), noinline)) int +#ifndef __x86_64__ +__attribute__((regparm (3))) +#endif +__attribute__((noinline)) +int fn2 (const char *x, int y, S2 *z) { asm volatile ("" : : : "memory"); @@ -84,7 +92,11 @@ fn3 (S3 *p) return (S3 *) ((char *) p + fn4 (p->s9)); } -__attribute__((regparm (3), noinline)) int +#ifndef __x86_64__ +__attribute__((regparm (3))) +#endif +__attribute__((noinline)) +int fn5 (void) { asm volatile ("" : : : "memory"); @@ -116,7 +128,11 @@ fn6 (S3 *w, int x, S2 *y, S4 *z) return a; } -__attribute__((regparm (3), noinline)) unsigned int +#ifndef __x86_64__ +__attribute__((regparm (3))) +#endif +__attribute__((noinline)) +unsigned int test (void *u, S6 *v, S1 **w, S7 *x, S2 *y, S1 *z) { unsigned b = v->s17->s16; diff --git a/gcc/testsuite/gcc.target/i386/pr49095-2.c b/gcc/testsuite/gcc.target/i386/pr49095-2.c new file mode 100644 index 0000000..25bc6b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr49095-2.c @@ -0,0 +1,73 @@ +/* PR rtl-optimization/49095 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-Os -fno-shrink-wrap -masm=att -mapxf" } */ + +void foo (void *); + +int * +f1 (int *x) +{ + if (!--*x) + foo (x); + return x; +} + +int +g1 (int x) +{ + if (!--x) + foo ((void *) 0); + return x; +} + +#define F(T, OP, OPN) \ +T * \ +f##T##OPN (T *x, T y) \ +{ \ + *x OP y; \ + if (!*x) \ + foo (x); \ + return x; \ +} \ + \ +T \ +g##T##OPN (T x, T y) \ +{ \ + x OP y; \ + if (!x) \ + foo ((void *) 0); \ + return x; \ +} \ + \ +T * \ +h##T##OPN (T *x) \ +{ \ + *x OP 24; \ + if (!*x) \ + foo (x); \ + return x; \ +} \ + \ +T \ +i##T##OPN (T x, T y) \ +{ \ + x OP 24; \ + if (!x) \ + foo ((void *) 0); \ + return x; \ +} + +#define G(T) \ +F (T, +=, plus) \ +F (T, -=, minus) \ +F (T, &=, and) \ +F (T, |=, or) \ +F (T, ^=, xor) + +G (char) +G (short) +G (int) +G (long) + +/* { dg-final { scan-assembler-not "test\[lq\]" } } */ +/* { dg-final { scan-assembler-not "\\(%\[re\]di\\), %" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr59099.c b/gcc/testsuite/gcc.target/i386/pr59099.c index cf4a8da..21dfbc2 100644 --- a/gcc/testsuite/gcc.target/i386/pr59099.c +++ b/gcc/testsuite/gcc.target/i386/pr59099.c @@ -13,10 +13,17 @@ struct s }; -void* f (struct s *, struct s *) __attribute__ ((noinline, regparm(1))); +void* f (struct s *, struct s *) +#ifndef __x86_64__ +__attribute__ ((regparm(1))) +#endif +__attribute__ ((noinline)) +; void* +#ifndef __x86_64__ __attribute__ ((regparm(1))) +#endif f (struct s *p, struct s *p2) { void *gp, *gp1; diff --git a/gcc/testsuite/gcc.target/i386/pr64110.c b/gcc/testsuite/gcc.target/i386/pr64110.c index 99e3919..11a6929 100644 --- a/gcc/testsuite/gcc.target/i386/pr64110.c +++ b/gcc/testsuite/gcc.target/i386/pr64110.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=core-avx2" } */ -/* { dg-final { scan-assembler "vmovd\[\\t \]" } } */ +/* { dg-final { scan-assembler "vmovd\[\\t \]" { target { ! ilp32 } } } } */ int foo (void); int a; diff --git a/gcc/testsuite/gcc.target/i386/pr79173-13.c b/gcc/testsuite/gcc.target/i386/pr79173-13.c new file mode 100644 index 0000000..7d5818b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr79173-13.c @@ -0,0 +1,59 @@ +/* PR middle-end/79173 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -fno-stack-protector -masm=att -mapxf" } */ +/* { dg-final { scan-assembler-times "addq\t%r\[^\n\r]*, \\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 8\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 16\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 24\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "subq\t%r\[^\n\r]*, \\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 8\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 16\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 24\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "addl\t%e\[^\n\r]*, \\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 4\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 8\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 12\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "subl\t%e\[^\n\r]*, \\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 4\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 8\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 12\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ + +static unsigned long +uaddc (unsigned long x, unsigned long y, unsigned long carry_in, unsigned long *carry_out) +{ + unsigned long r; + unsigned long c1 = __builtin_add_overflow (x, y, &r); + unsigned long c2 = __builtin_add_overflow (r, carry_in, &r); + *carry_out = c1 + c2; + return r; +} + +static unsigned long +usubc (unsigned long x, unsigned long y, unsigned long carry_in, unsigned long *carry_out) +{ + unsigned long r; + unsigned long c1 = __builtin_sub_overflow (x, y, &r); + unsigned long c2 = __builtin_sub_overflow (r, carry_in, &r); + *carry_out = c1 + c2; + return r; +} + +void +foo (unsigned long *p, unsigned long *q) +{ + unsigned long c; + p[0] = uaddc (p[0], q[0], 0, &c); + p[1] = uaddc (p[1], q[1], c, &c); + p[2] = uaddc (p[2], q[2], c, &c); + p[3] = uaddc (p[3], q[3], c, &c); +} + +void +bar (unsigned long *p, unsigned long *q) +{ + unsigned long c; + p[0] = usubc (p[0], q[0], 0, &c); + p[1] = usubc (p[1], q[1], c, &c); + p[2] = usubc (p[2], q[2], c, &c); + p[3] = usubc (p[3], q[3], c, &c); +} diff --git a/gcc/testsuite/gcc.target/i386/pr79173-14.c b/gcc/testsuite/gcc.target/i386/pr79173-14.c new file mode 100644 index 0000000..de85051 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr79173-14.c @@ -0,0 +1,59 @@ +/* PR middle-end/79173 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -fno-stack-protector -masm=att -mapxf" } */ +/* { dg-final { scan-assembler-times "addq\t%r\[^\n\r]*, \\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 8\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 16\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 24\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "subq\t%r\[^\n\r]*, \\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 8\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 16\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 24\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "addl\t%e\[^\n\r]*, \\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 4\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 8\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 12\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "subl\t%e\[^\n\r]*, \\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 4\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 8\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 12\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ + +static unsigned long +uaddc (unsigned long x, unsigned long y, _Bool carry_in, _Bool *carry_out) +{ + unsigned long r; + _Bool c1 = __builtin_add_overflow (x, y, &r); + _Bool c2 = __builtin_add_overflow (r, carry_in, &r); + *carry_out = c1 | c2; + return r; +} + +static unsigned long +usubc (unsigned long x, unsigned long y, _Bool carry_in, _Bool *carry_out) +{ + unsigned long r; + _Bool c1 = __builtin_sub_overflow (x, y, &r); + _Bool c2 = __builtin_sub_overflow (r, carry_in, &r); + *carry_out = c1 | c2; + return r; +} + +void +foo (unsigned long *p, unsigned long *q) +{ + _Bool c; + p[0] = uaddc (p[0], q[0], 0, &c); + p[1] = uaddc (p[1], q[1], c, &c); + p[2] = uaddc (p[2], q[2], c, &c); + p[3] = uaddc (p[3], q[3], c, &c); +} + +void +bar (unsigned long *p, unsigned long *q) +{ + _Bool c; + p[0] = usubc (p[0], q[0], 0, &c); + p[1] = usubc (p[1], q[1], c, &c); + p[2] = usubc (p[2], q[2], c, &c); + p[3] = usubc (p[3], q[3], c, &c); +} diff --git a/gcc/testsuite/gcc.target/i386/pr79173-15.c b/gcc/testsuite/gcc.target/i386/pr79173-15.c new file mode 100644 index 0000000..c3017f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr79173-15.c @@ -0,0 +1,61 @@ +/* PR middle-end/79173 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -fno-stack-protector -masm=att -mapxf" } */ +/* { dg-final { scan-assembler-times "addq\t%r\[^\n\r]*, \\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 8\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 16\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 24\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "subq\t%r\[^\n\r]*, \\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 8\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 16\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 24\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "addl\t%e\[^\n\r]*, \\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 4\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 8\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 12\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "subl\t%e\[^\n\r]*, \\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 4\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 8\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 12\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ + +static unsigned long +uaddc (unsigned long x, unsigned long y, unsigned long carry_in, unsigned long *carry_out) +{ + unsigned long r; + unsigned long c1 = __builtin_add_overflow (x, y, &r); + unsigned long c2 = __builtin_add_overflow (r, carry_in, &r); + *carry_out = c1 + c2; + return r; +} + +static unsigned long +usubc (unsigned long x, unsigned long y, unsigned long carry_in, unsigned long *carry_out) +{ + unsigned long r; + unsigned long c1 = __builtin_sub_overflow (x, y, &r); + unsigned long c2 = __builtin_sub_overflow (r, carry_in, &r); + *carry_out = c1 + c2; + return r; +} + +unsigned long +foo (unsigned long *p, unsigned long *q) +{ + unsigned long c; + p[0] = uaddc (p[0], q[0], 0, &c); + p[1] = uaddc (p[1], q[1], c, &c); + p[2] = uaddc (p[2], q[2], c, &c); + p[3] = uaddc (p[3], q[3], c, &c); + return c; +} + +unsigned long +bar (unsigned long *p, unsigned long *q) +{ + unsigned long c; + p[0] = usubc (p[0], q[0], 0, &c); + p[1] = usubc (p[1], q[1], c, &c); + p[2] = usubc (p[2], q[2], c, &c); + p[3] = usubc (p[3], q[3], c, &c); + return c; +} diff --git a/gcc/testsuite/gcc.target/i386/pr79173-16.c b/gcc/testsuite/gcc.target/i386/pr79173-16.c new file mode 100644 index 0000000..91062fb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr79173-16.c @@ -0,0 +1,61 @@ +/* PR middle-end/79173 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -fno-stack-protector -masm=att -mapxf" } */ +/* { dg-final { scan-assembler-times "addq\t%r\[^\n\r]*, \\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 8\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 16\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 24\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "subq\t%r\[^\n\r]*, \\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 8\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 16\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 24\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "addl\t%e\[^\n\r]*, \\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 4\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 8\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 12\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "subl\t%e\[^\n\r]*, \\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 4\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 8\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 12\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ + +static unsigned long +uaddc (unsigned long x, unsigned long y, _Bool carry_in, _Bool *carry_out) +{ + unsigned long r; + _Bool c1 = __builtin_add_overflow (x, y, &r); + _Bool c2 = __builtin_add_overflow (r, carry_in, &r); + *carry_out = c1 ^ c2; + return r; +} + +static unsigned long +usubc (unsigned long x, unsigned long y, _Bool carry_in, _Bool *carry_out) +{ + unsigned long r; + _Bool c1 = __builtin_sub_overflow (x, y, &r); + _Bool c2 = __builtin_sub_overflow (r, carry_in, &r); + *carry_out = c1 ^ c2; + return r; +} + +_Bool +foo (unsigned long *p, unsigned long *q) +{ + _Bool c; + p[0] = uaddc (p[0], q[0], 0, &c); + p[1] = uaddc (p[1], q[1], c, &c); + p[2] = uaddc (p[2], q[2], c, &c); + p[3] = uaddc (p[3], q[3], c, &c); + return c; +} + +_Bool +bar (unsigned long *p, unsigned long *q) +{ + _Bool c; + p[0] = usubc (p[0], q[0], 0, &c); + p[1] = usubc (p[1], q[1], c, &c); + p[2] = usubc (p[2], q[2], c, &c); + p[3] = usubc (p[3], q[3], c, &c); + return c; +} diff --git a/gcc/testsuite/gcc.target/i386/pr79173-17.c b/gcc/testsuite/gcc.target/i386/pr79173-17.c new file mode 100644 index 0000000..e27f4b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr79173-17.c @@ -0,0 +1,32 @@ +/* PR middle-end/79173 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -fno-stack-protector -masm=att -mapxf" } */ +/* { dg-final { scan-assembler-times "addq\t%r\[^\n\r]*, \\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 8\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 16\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 24\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "addl\t%e\[^\n\r]*, \\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 4\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 8\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 12\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ + +static unsigned long +uaddc (unsigned long x, unsigned long y, unsigned long carry_in, unsigned long *carry_out) +{ + unsigned long r = x + y; + unsigned long c1 = r < x; + r += carry_in; + unsigned long c2 = r < carry_in; + *carry_out = c1 + c2; + return r; +} + +void +foo (unsigned long *p, unsigned long *q) +{ + unsigned long c; + p[0] = uaddc (p[0], q[0], 0, &c); + p[1] = uaddc (p[1], q[1], c, &c); + p[2] = uaddc (p[2], q[2], c, &c); + p[3] = uaddc (p[3], q[3], c, &c); +} diff --git a/gcc/testsuite/gcc.target/i386/pr79173-18.c b/gcc/testsuite/gcc.target/i386/pr79173-18.c new file mode 100644 index 0000000..2728ae7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr79173-18.c @@ -0,0 +1,33 @@ +/* PR middle-end/79173 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -fno-stack-protector -masm=att -mapxf" } */ +/* { dg-final { scan-assembler-times "addq\t%r\[^\n\r]*, \\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 8\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 16\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 24\\\(%rdi\\\)" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "addl\t%e\[^\n\r]*, \\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 4\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 8\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 12\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */ + +static unsigned long +uaddc (unsigned long x, unsigned long y, unsigned long carry_in, unsigned long *carry_out) +{ + unsigned long r = x + y; + unsigned long c1 = r < x; + r += carry_in; + unsigned long c2 = r < carry_in; + *carry_out = c1 + c2; + return r; +} + +unsigned long +foo (unsigned long *p, unsigned long *q) +{ + unsigned long c; + p[0] = uaddc (p[0], q[0], 0, &c); + p[1] = uaddc (p[1], q[1], c, &c); + p[2] = uaddc (p[2], q[2], c, &c); + p[3] = uaddc (p[3], q[3], c, &c); + return c; +} diff --git a/gcc/testsuite/gcc.target/i386/pr82699-1.c b/gcc/testsuite/gcc.target/i386/pr82699-1.c index 272d079..96e3ccb 100644 --- a/gcc/testsuite/gcc.target/i386/pr82699-1.c +++ b/gcc/testsuite/gcc.target/i386/pr82699-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fno-pic -fcf-protection -pg -fasynchronous-unwind-tables" } */ +/* { dg-options "-O2 -mfentry -fno-pic -fcf-protection -pg -fasynchronous-unwind-tables" } */ /* { dg-final { scan-assembler-times {\t\.cfi_startproc\n\tendbr} 1 } } */ extern int bar (int); diff --git a/gcc/testsuite/gcc.target/i386/pr90096.c b/gcc/testsuite/gcc.target/i386/pr90096.c index 74f052e..871e0ff 100644 --- a/gcc/testsuite/gcc.target/i386/pr90096.c +++ b/gcc/testsuite/gcc.target/i386/pr90096.c @@ -10,7 +10,7 @@ volatile __mmask64 m64; void foo (int i) { - x1 = _mm512_gf2p8affineinv_epi64_epi8 (x1, x2, 3); /* { dg-error "needs isa option -mevex512 -mgfni -mavx512f" } */ + x1 = _mm512_gf2p8affineinv_epi64_epi8 (x1, x2, 3); /* { dg-error "needs isa option -mgfni -mavx512f" } */ } #ifdef __x86_64__ diff --git a/gcc/testsuite/gcc.target/i386/pr90693-3.c b/gcc/testsuite/gcc.target/i386/pr90693-3.c new file mode 100644 index 0000000..601c83c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90693-3.c @@ -0,0 +1,5 @@ +/* PR tree-optimization/90693 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mpopcnt" } */ + +#include "pr90693.c" diff --git a/gcc/testsuite/gcc.target/i386/pr90693-4.c b/gcc/testsuite/gcc.target/i386/pr90693-4.c new file mode 100644 index 0000000..b149159 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90693-4.c @@ -0,0 +1,5 @@ +/* PR tree-optimization/90693 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mpopcnt" } */ + +#include "pr90693-2.c" diff --git a/gcc/testsuite/gcc.target/i386/pr90693-5.c b/gcc/testsuite/gcc.target/i386/pr90693-5.c new file mode 100644 index 0000000..0a6a637 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90693-5.c @@ -0,0 +1,5 @@ +/* PR tree-optimization/90693 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mabm" } */ + +#include "pr90693.c" diff --git a/gcc/testsuite/gcc.target/i386/pr90693-6.c b/gcc/testsuite/gcc.target/i386/pr90693-6.c new file mode 100644 index 0000000..4040b52 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90693-6.c @@ -0,0 +1,5 @@ +/* PR tree-optimization/90693 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mabm" } */ + +#include "pr90693-2.c" diff --git a/gcc/testsuite/gcc.target/i386/pr90773-15.c b/gcc/testsuite/gcc.target/i386/pr90773-15.c index 403cdb2..880f71d1 100644 --- a/gcc/testsuite/gcc.target/i386/pr90773-15.c +++ b/gcc/testsuite/gcc.target/i386/pr90773-15.c @@ -10,5 +10,5 @@ foo (int c) } /* { dg-final { scan-assembler-times "vpbroadcastb\[\\t \]+%.*, %xmm\[0-9\]+" 1 } } */ -/* { dg-final { scan-assembler-times "vmovdqu8\[\\t \]+%xmm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]+%xmm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ /* { dg-final { scan-assembler-times "movb\[\\t \]+%.*, 16\\(%\[\^,\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr90773-16.c b/gcc/testsuite/gcc.target/i386/pr90773-16.c index bb0aadb..77d5840 100644 --- a/gcc/testsuite/gcc.target/i386/pr90773-16.c +++ b/gcc/testsuite/gcc.target/i386/pr90773-16.c @@ -10,5 +10,5 @@ foo (void) } /* { dg-final { scan-assembler-times "(?:vpcmpeqd|vpternlogd)" 1 } } */ -/* { dg-final { scan-assembler-times "vmovdqu8\[\\t \]+%xmm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]+%xmm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ /* { dg-final { scan-assembler-times "movb\[\\t \]+\\\$-1, 16\\(%\[\^,\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr90773-17.c b/gcc/testsuite/gcc.target/i386/pr90773-17.c index 61b2bfd..68ff7e0 100644 --- a/gcc/testsuite/gcc.target/i386/pr90773-17.c +++ b/gcc/testsuite/gcc.target/i386/pr90773-17.c @@ -11,5 +11,5 @@ foo (void) } /* { dg-final { scan-assembler-times "vpbroadcastd" 1 } } */ -/* { dg-final { scan-assembler-times "vmovdqu8\[\\t \]+%xmm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]+%xmm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ /* { dg-final { scan-assembler-times "vmovd\[\\t \]+%xmm\[0-9\]+, 16\\(%\[\^,\]+\\)" 1 { xfail *-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr91384-1.c b/gcc/testsuite/gcc.target/i386/pr91384-1.c new file mode 100644 index 0000000..4f8823d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr91384-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mapxf" } */ + +void foo (void); +void bar (void); + +int +test (int a) +{ + int r; + + if (r = -a) + foo (); + else + bar (); + + return r; +} + +/* { dg-final { scan-assembler-not "testl" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr92080-10.c b/gcc/testsuite/gcc.target/i386/pr92080-10.c new file mode 100644 index 0000000..b67f9d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-10.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=sapphirerapids -Ofast" } */ +/* { dg-final { scan-assembler-times "vpbroadcastw" 1 } } */ + +extern short write_picture_p_Vid_0; +extern unsigned short *write_picture_p_2_0_0; +extern int write_picture_p_0, write_picture_p_1, write_picture_i; +void write_picture() { + unsigned short cr_val = 1 << write_picture_p_Vid_0; + for (; write_picture_p_1;) + for (; write_picture_i < write_picture_p_0; write_picture_i++) + write_picture_p_2_0_0[write_picture_i] = cr_val; +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-11.c b/gcc/testsuite/gcc.target/i386/pr92080-11.c new file mode 100644 index 0000000..8747fc4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-11.c @@ -0,0 +1,33 @@ +/* { dg-do run { target { avx512f_runtime } } } */ +/* { dg-options "-mavx512f -mtune=icelake-server -O3" } */ + +struct s { + char s[sizeof(long double)]; +}; + +union u { + long double d; + struct s s; +}; + +int main() +{ + union u x = {0}; +#if __SIZEOF_LONG_DOUBLE__ == 16 + x.s = (struct s){"xxxxxxxxxxxxxxxx"}; +#elif __SIZEOF_LONG_DOUBLE__ == 12 + x.s = (struct s){"xxxxxxxxxxxx"}; +#elif __SIZEOF_LONG_DOUBLE__ == 8 + x.s = (struct s){"xxxxxxxx"}; +#elif __SIZEOF_LONG_DOUBLE__ == 4 + x.s = (struct s){"xxxx"}; +#endif + + union u y = x; + + for (unsigned char *p = (unsigned char *)&y + sizeof y; + p-- > (unsigned char *)&y;) + if (*p != (unsigned char)'x') + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-12.c b/gcc/testsuite/gcc.target/i386/pr92080-12.c new file mode 100644 index 0000000..cb09eb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-12.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O3 -mno-mmx -march=icelake-server" } */ +/* { dg-final { scan-assembler-times "vpbroadcastb" 1 } } */ + +signed char a; +signed char f (int i, int j) +{ + signed char c; + while (i != 0) + { + a ^= j; + ++c; + ++i; + } + return c; +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-13.c b/gcc/testsuite/gcc.target/i386/pr92080-13.c new file mode 100644 index 0000000..24b7616 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-13.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { avx512f_runtime } } } */ +/* { dg-options "-mavx512f -mtune=icelake-server -O2 -save-temps" } */ +/* { dg-final { scan-assembler-times "vpbroadcastd" 2 } } */ + +#include <assert.h> + +#define CONTAINER_KIND union + +typedef CONTAINER_KIND container { int value; } container; + +void move(container* end, container* start) { + container* p; + for (p = end; p > start; p--) { + (p)->value = (p-1)->value; + } +} + +#define N 100 + +int main(int argc, char* argv[]) { + container vals[N]; + int i; + for (i=0; i<N; i++) { + vals[i].value = argc + i; + } + move(&vals[N-1], &vals[0]); + assert(vals[0].value == argc + 0); + for (i=1; i<N; i++) { + assert(vals[i].value == argc + i - 1); + } + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-14.c b/gcc/testsuite/gcc.target/i386/pr92080-14.c new file mode 100644 index 0000000..6be41b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-14.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v4 -O2" } */ +/* { dg-final { scan-assembler-times "vpbroadcastd" 1 } } */ + +typedef int v16si __attribute__((vector_size(64))); +typedef int v8si __attribute__((vector_size(32))); +typedef int v4si __attribute__((vector_size(16))); + +extern v16si sinksz; +extern v8si sinksy; +extern v4si sinksx; +extern v4si sinksx1; + +extern void bar (void); + +void +foo (char c, int i) +{ + sinksz = __extension__(v16si){c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c}; + if (i == 1) + { + sinksy = __extension__(v8si){c,c,c,c,c,c,c,c}; + bar (); + } + else if (i == 2) + { + sinksx = __extension__(v4si){c,c,c,c}; + bar (); + } + sinksx1 = __extension__(v4si){c,c,c,c}; +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-15.c b/gcc/testsuite/gcc.target/i386/pr92080-15.c new file mode 100644 index 0000000..fa55d82 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-15.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -march=x86-64-v4" } */ +/* { dg-final { scan-assembler-times "vpbroadcastd" 3 } } */ + +typedef int v4si __attribute__((vector_size(16))); +typedef int v8si __attribute__((vector_size(32))); +typedef int v16si __attribute__((vector_size(64))); + +extern v4si *s1; +extern v8si *s2; +extern v16si *s3; + +int +foo (int i, int j) +{ + if (j == 1) + s1[i] = __extension__(v4si){34, 34, 34, 34}; + else if (i == 1) + s2[j] = __extension__(v8si){34, 34, 34, 34, 34, 34, 34, 34}; + if ((i + j) == 1234) + i = foo (j, i); + s3[i + j] = __extension__(v16si){34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34}; + return i - j; +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-16.c b/gcc/testsuite/gcc.target/i386/pr92080-16.c new file mode 100644 index 0000000..c8ab084 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-16.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -march=x86-64-v4" } */ +/* { dg-final { scan-assembler-times "vpbroadcastd" 1 } } */ + +typedef int v4si __attribute__((vector_size(16))); +typedef int v8si __attribute__((vector_size(32))); +typedef int v16si __attribute__((vector_size(64))); + +extern v4si *s1; +extern v8si *s2; +extern v16si *s3; + +int +foo (int i, int j) +{ + if (j == 1) + { + s1[i] = __extension__(v4si){34, 34, 34, 34}; + s2[j] = __extension__(v8si){34, 34, 34, 34, 34, 34, 34, 34}; + s3[i + j] = __extension__(v16si){34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34}; + } + if ((i + j) == 1234) + i = foo (j, i); + return i - j; +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-17.c b/gcc/testsuite/gcc.target/i386/pr92080-17.c new file mode 100644 index 0000000..c1d5f42 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-17.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3 -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**foo: +**.LFB0: +** .cfi_startproc +** vpbroadcastw cost\(%rip\), %xmm0 +** vmovq %xmm0, cost1\(%rip\) +** vmovdqu %xmm0, cost2\(%rip\) +** ret +**... +*/ + +extern struct { + short cost[4]; +} cost1; +extern struct { + short cost[8]; +} cost2; +extern int cost; + +void +foo (void) +{ + cost1.cost[0] = cost; + cost1.cost[1] = cost; + cost1.cost[2] = cost; + cost1.cost[3] = cost; + cost2.cost[0] = cost; + cost2.cost[1] = cost; + cost2.cost[2] = cost; + cost2.cost[3] = cost; + cost2.cost[4] = cost; + cost2.cost[5] = cost; + cost2.cost[6] = cost; + cost2.cost[7] = cost; +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-18.c b/gcc/testsuite/gcc.target/i386/pr92080-18.c new file mode 100644 index 0000000..b4ec12e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-18.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4" } */ +/* { dg-final { scan-assembler-times "vbroadcastsd" 1 } } */ + +typedef double v2df __attribute__((vector_size(16))); +typedef double v4df __attribute__((vector_size(32))); +typedef double v8df __attribute__((vector_size(64))); + +extern v2df d1; +extern v4df d2; +extern v8df d3; + +void +foo () +{ + d1 = __extension__(v2df){2.34, 2.34}; + d2 = __extension__(v4df){2.34, 2.34, 2.34, 2.34}; + d3 = __extension__(v8df){2.34, 2.34, 2.34, 2.34, 2.34, 2.34, 2.34, 2.34}; +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-19.c b/gcc/testsuite/gcc.target/i386/pr92080-19.c new file mode 100644 index 0000000..b1a1bdb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-19.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4" } */ +/* { dg-final { scan-assembler-times "vpbroadcastq" 1 } } */ + +typedef long long v2di __attribute__((vector_size(16))); +typedef long long v4di __attribute__((vector_size(32))); +typedef long long v8di __attribute__((vector_size(64))); + +extern v2di d1; +extern v4di d2; +extern v8di d3; + +void +foo (long long a1, long long a2, long long a3, long long a4, + long long a5, long long a6, long long a7) +{ + d1 = __extension__(v2di){a7, a7}; + d2 = __extension__(v4di){a7, a7, a7, a7}; + d3 = __extension__(v8di){a7, a7, a7, a7, a7, a7, a7, a7}; +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-20.c b/gcc/testsuite/gcc.target/i386/pr92080-20.c new file mode 100644 index 0000000..542ef2a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-20.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4" } */ +/* { dg-final { scan-assembler-times "vbroadcastsd" 1 } } */ + +typedef double v2di __attribute__((vector_size(16))); +typedef double v4di __attribute__((vector_size(32))); +typedef double v8di __attribute__((vector_size(64))); + +extern v2di d1; +extern v4di d2; +extern v8di d3; + +void +foo (double a1, double a2, double a3, double a4, + double a5, double a6, double a7) +{ + d1 = __extension__(v2di){a7, a7}; + d2 = __extension__(v4di){a7, a7, a7, a7}; + d3 = __extension__(v8di){a7, a7, a7, a7, a7, a7, a7, a7}; +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-4.c b/gcc/testsuite/gcc.target/i386/pr92080-4.c new file mode 100644 index 0000000..ebe1384 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-4.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v4 -O2" } */ +/* { dg-final { scan-assembler-times "vpbroadcastb" 1 } } */ +/* { dg-final { scan-assembler-times "vpbroadcastd" 1 } } */ +/* { dg-final { scan-assembler-times "vpbroadcastw" 1 } } */ + +typedef int v16si __attribute__((vector_size(64))); +typedef int v8si __attribute__((vector_size(32))); +typedef int v4si __attribute__((vector_size(16))); + +typedef short v32hi __attribute__((vector_size(64))); +typedef short v16hi __attribute__((vector_size(32))); +typedef short v8hi __attribute__((vector_size(16))); + +typedef char v64qi __attribute__((vector_size(64))); +typedef char v32qi __attribute__((vector_size(32))); +typedef char v16qi __attribute__((vector_size(16))); + +extern v16si sinksz; +extern v8si sinksy; +extern v4si sinksx; +extern v32hi sinkhz; +extern v16hi sinkhy; +extern v8hi sinkhx; +extern v64qi sinkbz; +extern v32qi sinkby; +extern v16qi sinkbx; + +void foo(char c) { + sinksz = __extension__(v16si){c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c}; + sinksy = __extension__(v8si){c,c,c,c,c,c,c,c}; + sinksx = __extension__(v4si){c,c,c,c}; +} + +void foo1(char c) { + sinkhz = __extension__(v32hi){c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c, + c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c}; + sinkhy = __extension__(v16hi){c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c}; + sinkhx = __extension__(v8hi){c,c,c,c,c,c,c,c}; +} + +void foo2(char c) { + sinkbz = __extension__(v64qi){c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c, + c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c, + c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c, + c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c}; + sinkby = __extension__(v32qi){c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c, + c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c}; + sinkbx = __extension__(v16qi){c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c}; +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-5.c b/gcc/testsuite/gcc.target/i386/pr92080-5.c new file mode 100644 index 0000000..380cd33 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-5.c @@ -0,0 +1,109 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4" } */ +/* { dg-final { scan-assembler-times "vpbroadcastd" 3 } } */ +/* { dg-final { scan-assembler-times "vpbroadcastq" 1 } } */ +/* { dg-final { scan-assembler-times "vbroadcastsd" 1 } } */ +/* { dg-final { scan-assembler-times "vbroadcastss" 1 } } */ + +typedef long long v2di __attribute__((vector_size(16))); +typedef long long v4di __attribute__((vector_size(32))); +typedef long long v8di __attribute__((vector_size(64))); +typedef int v4si __attribute__((vector_size(16))); +typedef int v8si __attribute__((vector_size(32))); +typedef int v16si __attribute__((vector_size(64))); +typedef short v8hi __attribute__((vector_size(16))); +typedef short v16hi __attribute__((vector_size(32))); +typedef short v32hi __attribute__((vector_size(64))); +typedef char v16qi __attribute__((vector_size(16))); +typedef char v32qi __attribute__((vector_size(32))); +typedef char v64qi __attribute__((vector_size(64))); +typedef float v4sf __attribute__((vector_size(16))); +typedef float v8sf __attribute__((vector_size(32))); +typedef float v16sf __attribute__((vector_size(64))); +typedef double v2df __attribute__((vector_size(16))); +typedef double v4df __attribute__((vector_size(32))); +typedef double v8df __attribute__((vector_size(64))); + +extern v16qi b1; +extern v8hi h1; +extern v4si s1; +extern v2di l1; +extern v4sf f1; +extern v2df d1; +extern v32qi b2; +extern v16hi h2; +extern v8si s2; +extern v4di l2; +extern v8sf f2; +extern v4df d2; +extern v64qi b3; +extern v32hi h3; +extern v16si s3; +extern v8di l3; +extern v16sf f3; +extern v8df d3; + +void +foo1 () +{ + b1 = __extension__(v16qi){34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34}; + b2 = __extension__(v32qi){34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34}; + b3 = __extension__(v64qi){34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34}; +} + +void +foo2 () +{ + h1 = __extension__(v8hi){34, 34, 34, 34, 34, 34, 34, 34}; + h2 = __extension__(v16hi){34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34}; + h3 = __extension__(v32hi){34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34}; +} + +void +foo3 () +{ + s1 = __extension__(v4si){34, 34, 34, 34}; + s2 = __extension__(v8si){34, 34, 34, 34, 34, 34, 34, 34}; + s3 = __extension__(v16si){34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34}; +} + +void +foo4 () +{ + l1 = __extension__(v2di){34, 34}; + l2 = __extension__(v4di){34, 34, 34, 34}; + l3 = __extension__(v8di){34, 34, 34, 34, 34, 34, 34, 34}; +} + +void +foo5 () +{ + f1 = __extension__(v4sf){34, 34, 34, 34}; + f2 = __extension__(v8sf){34, 34, 34, 34, 34, 34, 34, 34}; + f3 = __extension__(v16sf){34, 34, 34, 34, 34, 34, 34, 34, + 34, 34, 34, 34, 34, 34, 34, 34}; +} + +void +foo6 () +{ + d1 = __extension__(v2df){34, 34}; + d2 = __extension__(v4df){34, 34, 34, 34}; + d3 = __extension__(v8df){34, 34, 34, 34, 34, 34, 34, 34}; +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-6.c b/gcc/testsuite/gcc.target/i386/pr92080-6.c new file mode 100644 index 0000000..e4cdbee --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-6.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v4 -O2" } */ +/* { dg-final { scan-assembler-times "vpbroadcastb" 1 } } */ + +#include <immintrin.h> + +extern __m512i sinkz; +extern __m256i sinky; +extern char f; + +void +foo(char c, int x) +{ + c += f; + sinkz = _mm512_set1_epi8(c); + if (x == 2) + f += 3; + sinky = _mm256_set1_epi8(c); +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-7.c b/gcc/testsuite/gcc.target/i386/pr92080-7.c new file mode 100644 index 0000000..8691684 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-7.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v4 -O2" } */ +/* { dg-final { scan-assembler-times "vpbroadcastb" 1 } } */ + +#include <immintrin.h> + +extern __m512i sinkz; +extern __m256i sinky; +extern char f; +extern void bar (void); + +void +foo(char c, int x) +{ + c += f; + sinkz = _mm512_set1_epi8(c); + if (x == 2) + bar (); + sinky = _mm256_set1_epi8(c); +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-8.c b/gcc/testsuite/gcc.target/i386/pr92080-8.c new file mode 100644 index 0000000..7ebb62c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v4 -O2" } */ +/* { dg-final { scan-assembler-times "vpbroadcastd" 1 } } */ +/* { dg-final { scan-assembler-times "vpbroadcastq" 1 } } */ + +typedef int v4si __attribute__((vector_size(16))); +typedef long long int v2di __attribute__((vector_size(16))); +extern v4si s; +extern v2di l; + +void +foo(void) +{ + l = __extension__(v2di){2,2}; + s = __extension__(v4si){2,2,2,2}; +} diff --git a/gcc/testsuite/gcc.target/i386/pr92080-9.c b/gcc/testsuite/gcc.target/i386/pr92080-9.c new file mode 100644 index 0000000..f44ab56 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92080-9.c @@ -0,0 +1,81 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v4 -O2" } */ +/* { dg-final { scan-assembler-times "vpbroadcastd" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqa\[\\t \]+" 8 } } */ +/* { dg-final { scan-assembler-times "vmovdqa64\[\\t \]+" 3 } } */ +/* { dg-final { scan-assembler-times "vmovdqa32\[\\t \]+" 1 } } */ + +typedef int v4si __attribute__((vector_size(16))); +typedef long long int v2di __attribute__((vector_size(16))); +typedef long long v2di __attribute__((vector_size(16))); +typedef long long v4di __attribute__((vector_size(32))); +typedef long long v8di __attribute__((vector_size(64))); +typedef int v4si __attribute__((vector_size(16))); +typedef int v8si __attribute__((vector_size(32))); +typedef int v16si __attribute__((vector_size(64))); +typedef short v8hi __attribute__((vector_size(16))); +typedef short v16hi __attribute__((vector_size(32))); +typedef short v32hi __attribute__((vector_size(64))); +typedef char v16qi __attribute__((vector_size(16))); +typedef char v32qi __attribute__((vector_size(32))); +typedef char v64qi __attribute__((vector_size(64))); + +extern v16qi b1; +extern v8hi h1; +extern v4si s1; +extern v2di l1; +extern v32qi b2; +extern v16hi h2; +extern v8si s2; +extern v4di l2; +extern v64qi b3; +extern v32hi h3; +extern v16si s3; +extern v8di l3; + +void +foo(void) +{ + b1 = __extension__(v16qi){0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22}; + h1 = __extension__(v8hi){0x2222, 0x2222, 0x2222, 0x2222, + 0x2222, 0x2222, 0x2222, 0x2222}; + s1 = __extension__(v4si){0x22222222,0x22222222,0x22222222,0x22222222}; + l1 = __extension__(v2di){0x2222222222222222ULL,0x2222222222222222ULL}; + b2 = __extension__(v32qi){0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22}; + h2 = __extension__(v16hi){0x2222, 0x2222, 0x2222, 0x2222, + 0x2222, 0x2222, 0x2222, 0x2222, + 0x2222, 0x2222, 0x2222, 0x2222, + 0x2222, 0x2222, 0x2222, 0x2222}; + s2 = __extension__(v8si){0x22222222,0x22222222,0x22222222,0x22222222, + 0x22222222,0x22222222,0x22222222,0x22222222}; + l2 = __extension__(v4di){0x2222222222222222ULL,0x2222222222222222ULL, + 0x2222222222222222ULL,0x2222222222222222ULL}; + b3 = __extension__(v64qi){0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22}; + h3 = __extension__(v32hi){0x2222, 0x2222, 0x2222, 0x2222, + 0x2222, 0x2222, 0x2222, 0x2222, + 0x2222, 0x2222, 0x2222, 0x2222, + 0x2222, 0x2222, 0x2222, 0x2222, + 0x2222, 0x2222, 0x2222, 0x2222, + 0x2222, 0x2222, 0x2222, 0x2222, + 0x2222, 0x2222, 0x2222, 0x2222, + 0x2222, 0x2222, 0x2222, 0x2222}; + s3 = __extension__(v16si){0x22222222,0x22222222,0x22222222,0x22222222, + 0x22222222,0x22222222,0x22222222,0x22222222, + 0x22222222,0x22222222,0x22222222,0x22222222, + 0x22222222,0x22222222,0x22222222,0x22222222}; + l3 = __extension__(v8di){0x2222222222222222ULL,0x2222222222222222ULL, + 0x2222222222222222ULL,0x2222222222222222ULL, + 0x2222222222222222ULL,0x2222222222222222ULL, + 0x2222222222222222ULL,0x2222222222222222ULL}; +} diff --git a/gcc/testsuite/gcc.target/i386/pr93492-3.c b/gcc/testsuite/gcc.target/i386/pr93492-3.c index b68da30..cdca595 100644 --- a/gcc/testsuite/gcc.target/i386/pr93492-3.c +++ b/gcc/testsuite/gcc.target/i386/pr93492-3.c @@ -10,4 +10,4 @@ f10_endbr (void) { } -/* { dg-final { scan-assembler "\t\.cfi_startproc\n\tendbr(32|64)\n.*\.LPFE0:\n\tnop\n1:\tcall\t\[^\n\]*__fentry__\[^\n\]*\n\tret\n" } } */ +/* { dg-final { scan-assembler "\t\.cfi_startproc\n\tendbr(32|64)\n.*\.LPFE0:\n\tnop\n\tcall\t\[^\n\]*__fentry__\[^\n\]*\n\tret\n" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr93492-5.c b/gcc/testsuite/gcc.target/i386/pr93492-5.c index ee9849a..cc71f67 100644 --- a/gcc/testsuite/gcc.target/i386/pr93492-5.c +++ b/gcc/testsuite/gcc.target/i386/pr93492-5.c @@ -9,4 +9,4 @@ foo (void) { } -/* { dg-final { scan-assembler "\t\.cfi_startproc\n.*\.LPFE0:\n\tnop\n1:\tcall\t\[^\n\]*__fentry__\[^\n\]*\n\tret\n" } } */ +/* { dg-final { scan-assembler "\t\.cfi_startproc\n.*\.LPFE0:\n\tnop\n\tcall\t\[^\n\]*__fentry__\[^\n\]*\n\tret\n" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr95483-5.c b/gcc/testsuite/gcc.target/i386/pr95483-5.c index b52e39d..a21ad01 100644 --- a/gcc/testsuite/gcc.target/i386/pr95483-5.c +++ b/gcc/testsuite/gcc.target/i386/pr95483-5.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mavx512bw -mavx512vl -O2" } */ -/* { dg-final { scan-assembler-times "(?:vmovdqu8|vinserti128)\[ \\t\]+\[^\{\n\]*\\)\[^\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "(?:vmovdqu8|vextracti128)\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "(?:vmovdqu|vinserti128)\[ \\t\]+\[^\{\n\]*\\)\[^\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "(?:vmovdqu|vextracti128)\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-1.c b/gcc/testsuite/gcc.target/i386/preserve-none-1.c new file mode 100644 index 0000000..25c6494 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -fomit-frame-pointer" } */ + +extern void boring(void); + +extern void continuation(void *, void *, void *, void *) + __attribute__((preserve_none)); + +__attribute__((preserve_none)) +void entry(void *a, void *b, void *c, void *d) +{ + boring(); + continuation(a, b, c, d); +} + +/* { dg-final { scan-assembler-not "movq" } } */ +/* { dg-final { scan-assembler "jmp\[\\t \]+_?continuation" } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-10.c b/gcc/testsuite/gcc.target/i386/preserve-none-10.c new file mode 100644 index 0000000..f22200a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-10.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef void (*fn_t) (void *) __attribute__ ((preserve_none)); + +void +foo (void *frame) +{ +} + +fn_t func = foo; /* { dg-error "incompatible pointer type" } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-11.c b/gcc/testsuite/gcc.target/i386/preserve-none-11.c new file mode 100644 index 0000000..3bc82ba --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-11.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef void (*fn_t) (void *) __attribute__ ((preserve_none)); + +__attribute__ ((preserve_none)) +void +foo (void *frame) +{ +} + +fn_t func = foo; diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-12.c b/gcc/testsuite/gcc.target/i386/preserve-none-12.c new file mode 100644 index 0000000..b2fd0ab --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-12.c @@ -0,0 +1,49 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move" } */ + +extern void bar (void) __attribute__ ((preserve_none)); + +void +foo (void) +{ + bar (); +} + +/* foo must save and restore all caller saved registers since bar won't + preserve any. */ +/* { dg-final { scan-assembler-not "jmp\[\\t \]+_?bar" } } */ +/* { dg-final { scan-assembler "call\[\\t \]+_?bar" } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)ax" } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ +/* { dg-final { scan-assembler-times "pushl\[\\t \]*%esi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%rsi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushl\[\\t \]*%edi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%rdi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r8" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r9" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r10" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r11" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r12" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r13" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r14" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r15" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)ax" } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ +/* { dg-final { scan-assembler-times "popl\[\\t \]*%esi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%rsi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popl\[\\t \]*%edi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%rdi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r8" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r9" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r10" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r11" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r12" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r13" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r14" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r15" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-13.c b/gcc/testsuite/gcc.target/i386/preserve-none-13.c new file mode 100644 index 0000000..d0f3099 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-13.c @@ -0,0 +1,50 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move" } */ + +typedef void (*fn_t) (void) __attribute__ ((preserve_none)); +extern fn_t bar; + +void +foo (void) +{ + bar (); +} + +/* foo must save and restore all caller saved registers since bar won't + preserve any. */ +/* { dg-final { scan-assembler-not "jmp" } } */ +/* { dg-final { scan-assembler "call\[\\t \]+" } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)ax" } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ +/* { dg-final { scan-assembler-times "pushl\[\\t \]*%esi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%rsi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushl\[\\t \]*%edi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%rdi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r8" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r9" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r10" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r11" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r12" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r13" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r14" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r15" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)ax" } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ +/* { dg-final { scan-assembler-times "popl\[\\t \]*%esi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%rsi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popl\[\\t \]*%edi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%rdi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r8" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r9" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r10" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r11" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r12" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r13" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r14" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r15" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-14.c b/gcc/testsuite/gcc.target/i386/preserve-none-14.c new file mode 100644 index 0000000..ca23b58 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-14.c @@ -0,0 +1,49 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move" } */ + +typedef void (*fn_t) (void) __attribute__ ((preserve_none)); + +void +foo (fn_t bar) +{ + bar (); +} + +/* foo must save and restore all caller saved registers since bar won't + preserve any. */ +/* { dg-final { scan-assembler-not "jmp" } } */ +/* { dg-final { scan-assembler "call\[\\t \]+" } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)ax" } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ +/* { dg-final { scan-assembler-times "pushl\[\\t \]*%esi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%rsi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushl\[\\t \]*%edi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%rdi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r8" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r9" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r10" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r11" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r12" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r13" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r14" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r15" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)ax" } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ +/* { dg-final { scan-assembler-times "popl\[\\t \]*%esi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%rsi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popl\[\\t \]*%edi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%rdi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r8" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r9" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r10" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r11" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r12" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r13" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r14" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r15" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-15.c b/gcc/testsuite/gcc.target/i386/preserve-none-15.c new file mode 100644 index 0000000..54527e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-15.c @@ -0,0 +1,46 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -mgeneral-regs-only -mtune-ctrl=^prologue_using_move,^epilogue_using_move" } */ + +extern void bar (void) __attribute__ ((preserve_none)); + +__attribute__ ((no_caller_saved_registers)) +void +foo (void) +{ + bar (); +} + +/* foo must save and restore all caller saved registers since bar won't + preserve any. */ +/* { dg-final { scan-assembler-not "jmp\[\\t \]+_?bar" } } */ +/* { dg-final { scan-assembler "call\[\\t \]+_?bar" } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)ax" 1 } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)cx" 1 } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)dx" 1 } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)si" 1 } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)di" 1 } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r8" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r9" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r10" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r11" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r12" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r13" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r14" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r15" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)ax" 1 } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)cx" 1 } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)dx" 1 } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)si" 1 } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)di" 1 } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r8" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r9" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r10" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r11" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r12" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r13" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r14" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r15" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-16.c b/gcc/testsuite/gcc.target/i386/preserve-none-16.c new file mode 100644 index 0000000..6800836 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-16.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +extern void foo (void); /* { dg-note "previous declaration" } */ + +__attribute__ ((preserve_none)) +void +foo (void) /* { dg-error "conflicting types" } */ +{ +} + diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-17.c b/gcc/testsuite/gcc.target/i386/preserve-none-17.c new file mode 100644 index 0000000..e105da1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-17.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +extern void foo (void) __attribute__ ((preserve_none)); /* { dg-note "previous declaration" } */ + +void +foo (void) /* { dg-error "conflicting types" } */ +{ +} + diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-18.c b/gcc/testsuite/gcc.target/i386/preserve-none-18.c new file mode 100644 index 0000000..a2ac5e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-18.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move" } */ +/* { dg-additional-options "-fno-PIE" { target ia32 } } */ + +extern void foo (void); + +__attribute__ ((preserve_none)) +void +bar (void) +{ + foo (); +} + +/* { dg-final { scan-assembler-not "push" } } */ +/* { dg-final { scan-assembler-not "pop" } } */ +/* { dg-final { scan-assembler-not "call\[\\t \]+_?foo" } } */ +/* { dg-final { scan-assembler "jmp\[\\t \]+_?foo" } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-19.c b/gcc/testsuite/gcc.target/i386/preserve-none-19.c new file mode 100644 index 0000000..5e9cbd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-19.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move" } */ +/* { dg-additional-options "-fno-PIE" { target ia32 } } */ + +extern void bar (void) __attribute__ ((preserve_none)); + +__attribute__ ((no_callee_saved_registers)) +void +foo (void) +{ + bar (); +} + +/* { dg-final { scan-assembler-not "push" } } */ +/* { dg-final { scan-assembler-not "pop" } } */ +/* { dg-final { scan-assembler "jmp\[\\t \]+_?bar" } } */ +/* { dg-final { scan-assembler-not "call\[\\t \]+_?bar" } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-2.c b/gcc/testsuite/gcc.target/i386/preserve-none-2.c new file mode 100644 index 0000000..027f181 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef void (*fn_t) (void *) __attribute__ ((preserve_none)); + +__attribute__ ((no_callee_saved_registers)) +void +foo (void *frame) +{ +} + +fn_t func = foo; /* { dg-error "incompatible pointer type" "" { target { ! ia32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-20.c b/gcc/testsuite/gcc.target/i386/preserve-none-20.c new file mode 100644 index 0000000..0070ee7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-20.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move" } */ +/* { dg-additional-options "-fno-PIE" { target ia32 } } */ + +typedef void (*fn_t) (void) __attribute__ ((no_callee_saved_registers)); +extern fn_t bar; + +__attribute__ ((preserve_none)) +void +foo (void) +{ + bar (); +} + +/* { dg-final { scan-assembler-not "push" } } */ +/* { dg-final { scan-assembler-not "pop" } } */ +/* { dg-final { scan-assembler "jmp" } } */ +/* { dg-final { scan-assembler-not "call\[\\t \]+" } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-21.c b/gcc/testsuite/gcc.target/i386/preserve-none-21.c new file mode 100644 index 0000000..4550d22 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-21.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move" } */ + +typedef void (*fn_t) (void) __attribute__ ((preserve_none)); + +__attribute__ ((no_callee_saved_registers)) +void +foo (fn_t bar) +{ + bar (); +} + +/* { dg-final { scan-assembler-not "push" } } */ +/* { dg-final { scan-assembler-not "pop" } } */ +/* { dg-final { scan-assembler "jmp" } } */ +/* { dg-final { scan-assembler-not "call\[\\t \]+" } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-22.c b/gcc/testsuite/gcc.target/i386/preserve-none-22.c new file mode 100644 index 0000000..6ec8d0c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-22.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move" } */ +/* { dg-additional-options "-fno-PIE" { target ia32 } } */ + +extern void foo (void) __attribute__ ((no_caller_saved_registers)); + +__attribute__ ((preserve_none)) +void +bar (void) +{ + foo (); +} + +/* { dg-final { scan-assembler-not "push" } } */ +/* { dg-final { scan-assembler-not "pop" } } */ +/* { dg-final { scan-assembler-not "call\[\\t \]+_?foo" } } */ +/* { dg-final { scan-assembler "jmp\[\\t \]+_?foo" } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-23.c b/gcc/testsuite/gcc.target/i386/preserve-none-23.c new file mode 100644 index 0000000..8e83879 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-23.c @@ -0,0 +1,51 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move" } */ + +#include <stdint.h> + +typedef void (*fn_t) (void) __attribute__ ((preserve_none)); + +void +foo (uintptr_t p) +{ + ((fn_t) p) (); +} + +/* foo must save and restore all caller saved registers since bar won't + preserve any. */ +/* { dg-final { scan-assembler-not "jmp" } } */ +/* { dg-final { scan-assembler "call\[\\t \]+" } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)ax" } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ +/* { dg-final { scan-assembler-not "push(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ +/* { dg-final { scan-assembler-times "pushl\[\\t \]*%esi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%rsi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushl\[\\t \]*%edi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%rdi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r8" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r9" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r10" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pushq\[\\t \]*%r11" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r12" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r13" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r14" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r15" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)ax" } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)cx" } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)dx" } } */ +/* { dg-final { scan-assembler-not "pop(?:l|q)\[\\t \]*%(?:e|r)bp" } } */ +/* { dg-final { scan-assembler-times "popl\[\\t \]*%esi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%rsi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popl\[\\t \]*%edi" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%rdi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r8" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r9" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r10" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "popq\[\\t \]*%r11" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r12" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r13" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r14" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "popq\[\\t \]*%r15" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-24.c b/gcc/testsuite/gcc.target/i386/preserve-none-24.c new file mode 100644 index 0000000..d7adfba --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-24.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +__attribute__ ((preserve_none, no_callee_saved_registers)) +void +foo (void) +{ /* { dg-error "attributes are not compatible" } */ +} diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-25.c b/gcc/testsuite/gcc.target/i386/preserve-none-25.c new file mode 100644 index 0000000..e22da50 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-25.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */ +/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mno-apxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**entry: +**.LFB[0-9]+: +** .cfi_startproc +** movq %rdi, %r12 +** movq %rsi, %r13 +** movq %rdx, %r14 +** movq %rcx, %r15 +** jmp continuation +** .cfi_endproc +**... +*/ + +extern void continuation (void *, void *, void *, void *) + __attribute__ ((preserve_none)); + +__attribute__ ((no_callee_saved_registers)) +void +entry (void *a, void *b, void *c, void *d) +{ + continuation (a, b, c, d); +} diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-26.c b/gcc/testsuite/gcc.target/i386/preserve-none-26.c new file mode 100644 index 0000000..926d127 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-26.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */ +/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mno-apxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**entry: +**.LFB[0-9]+: +** .cfi_startproc +** movq %r15, %rcx +** movq %r14, %rdx +** movq %r13, %rsi +** movq %r12, %rdi +** jmp continuation +** .cfi_endproc +**... +*/ + +extern void continuation (void *, void *, void *, void *) + __attribute__ ((no_callee_saved_registers)); + +__attribute__ ((preserve_none)) +void +entry (void *a, void *b, void *c, void *d) +{ + continuation(a, b, c, d); +} diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-27.c b/gcc/testsuite/gcc.target/i386/preserve-none-27.c new file mode 100644 index 0000000..17aa57d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-27.c @@ -0,0 +1,33 @@ +/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */ +/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mno-apxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**entry: +**.LFB[0-9]+: +** .cfi_startproc +**... +** movl %edi, %r12d +** movl %esi, %r13d +** movl %edx, %r14d +** pushq \$-559038737 +**... +** movl %ecx, %r15d +** movl %r9d, %esi +** movl %r8d, %edi +** xorl %eax, %eax +**... +** call continuation +**... +*/ + +extern void continuation (int, int, int, int, int, int, ...) + __attribute__ ((preserve_none)); + +__attribute__ ((no_callee_saved_registers)) +void +entry (int arg1, int arg2, int arg3, int arg4, int arg5, int arg6) +{ + continuation (arg1, arg2, arg3, arg4, arg5, arg6, 0xdeadbeef); +} diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-28.c b/gcc/testsuite/gcc.target/i386/preserve-none-28.c new file mode 100644 index 0000000..7042b8d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-28.c @@ -0,0 +1,48 @@ +/* { dg-do run { target { *-*-linux* && { ! ia32 } } } } */ +/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mno-apxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ + +#include <stdlib.h> + +__attribute__ ((preserve_none, weak)) +void +continuation (int arg1, int arg2, int arg3, int arg4, int arg5, int arg6) +{ + if (arg1 != 17) + abort (); + if (arg2 != 8) + abort (); + if (arg3 != 20) + abort (); + if (arg4 != -3) + abort (); + if (arg5 != -4) + abort (); + if (arg6 != 26) + abort (); +} + +__attribute__ ((no_callee_saved_registers, weak)) +void +entry (int arg1, int arg2, int arg3, int arg4, int arg5, int arg6) +{ + if (arg1 != 17) + abort (); + if (arg2 != 8) + abort (); + if (arg3 != 20) + abort (); + if (arg4 != -3) + abort (); + if (arg5 != -4) + abort (); + if (arg6 != 26) + abort (); + continuation (arg1, arg2, arg3, arg4, arg5, arg6); +} + +int +main (void) +{ + entry (17, 8, 20, -3, -4, 26); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-29.c b/gcc/testsuite/gcc.target/i386/preserve-none-29.c new file mode 100644 index 0000000..e6520fa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-29.c @@ -0,0 +1,57 @@ +/* { dg-do run { target { *-*-linux* && { ! ia32 } } } } */ +/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mno-apxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ + +#include <stdarg.h> +#include <stdlib.h> + +__attribute__ ((preserve_none, weak)) +void +continuation (int arg1, int arg2, int arg3, int arg4, int arg5, int arg6, + ...) +{ + int a; + va_list va_arglist; + va_start (va_arglist, arg6); + if (arg1 != 17) + abort (); + if (arg2 != 8) + abort (); + if (arg3 != 20) + abort (); + if (arg4 != -3) + abort (); + if (arg5 != -4) + abort (); + if (arg6 != 26) + abort (); + a = va_arg (va_arglist, int); + if (a != 0xdeadbeef) + abort (); + va_end (va_arglist); +} + +__attribute__ ((no_callee_saved_registers, weak)) +void +entry (int arg1, int arg2, int arg3, int arg4, int arg5, int arg6) +{ + if (arg1 != 17) + abort (); + if (arg2 != 8) + abort (); + if (arg3 != 20) + abort (); + if (arg4 != -3) + abort (); + if (arg5 != -4) + abort (); + if (arg6 != 26) + abort (); + continuation (arg1, arg2, arg3, arg4, arg5, arg6, 0xdeadbeef); +} + +int +main (void) +{ + entry (17, 8, 20, -3, -4, 26); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-3.c b/gcc/testsuite/gcc.target/i386/preserve-none-3.c new file mode 100644 index 0000000..df484a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move -fomit-frame-pointer -mnoreturn-no-callee-saved-registers" } */ + +extern void bar (void) __attribute__ ((preserve_none)); +extern void fn (void) __attribute__ ((noreturn)); + +__attribute__ ((noreturn)) +void +foo (void) +{ + bar (); + fn (); +} + +/* { dg-final { scan-assembler-not "push\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ +/* { dg-final { scan-assembler-not "pop\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ +/* { dg-final { scan-assembler-not "jmp\[\\t \]+_?bar" } } */ +/* { dg-final { scan-assembler "call\[\\t \]+_?bar" } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-30a.c b/gcc/testsuite/gcc.target/i386/preserve-none-30a.c new file mode 100644 index 0000000..2a21ef5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-30a.c @@ -0,0 +1,31 @@ +/* { dg-do compile { target { *-*-linux* && lp64 } } } */ +/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mno-apxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**entry: +**.LFB[0-9]+: +** .cfi_startproc +** subq \$8, %rsp +** .cfi_def_cfa_offset 16 +** call boring +** addq \$8, %rsp +** .cfi_def_cfa_offset 8 +** jmp \*continuation\(%rip\) +** .cfi_endproc +**... +*/ + +extern void boring (void); + +extern void (*continuation) (void *, void *, void *, void *) + __attribute__ ((preserve_none)); + +__attribute__ ((preserve_none)) +void +entry (void *a, void *b, void *c, void *d) +{ + boring (); + continuation (a, b, c, d); +} diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-30b.c b/gcc/testsuite/gcc.target/i386/preserve-none-30b.c new file mode 100644 index 0000000..425d0aa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-30b.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { *-*-linux* && maybe_x32 } } } */ +/* { dg-options "-O2 -mx32 -fno-pic -mtune=generic -msse2 -mno-apxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**entry: +**.LFB[0-9]+: +** .cfi_startproc +** subl \$8, %esp +** .cfi_def_cfa_offset 16 +** call boring +** movl continuation\(%rip\), %eax +** addl \$8, %esp +** .cfi_def_cfa_offset 8 +** jmp \*%rax +** .cfi_endproc +**... +*/ + +#include "preserve-none-30a.c" diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-4.c b/gcc/testsuite/gcc.target/i386/preserve-none-4.c new file mode 100644 index 0000000..35c3501 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move -fomit-frame-pointer -mnoreturn-no-callee-saved-registers" } */ + +typedef void (*fn_t) (void) __attribute__ ((preserve_none)); +extern fn_t bar; +extern void fn (void) __attribute__ ((noreturn)); + +__attribute__ ((noreturn)) +void +foo (void) +{ + bar (); + fn (); +} + +/* { dg-final { scan-assembler-not "push\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ +/* { dg-final { scan-assembler-not "pop\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ +/* { dg-final { scan-assembler-not "jmp" } } */ +/* { dg-final { scan-assembler "call\[\\t \]+" } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-5.c b/gcc/testsuite/gcc.target/i386/preserve-none-5.c new file mode 100644 index 0000000..1498886 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-5.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move -fomit-frame-pointer -mnoreturn-no-callee-saved-registers" } */ + +typedef void (*fn_t) (void) __attribute__ ((preserve_none)); +extern void fn (void) __attribute__ ((noreturn)); + +__attribute__ ((noreturn)) +void +foo (fn_t bar) +{ + bar (); + fn (); +} + +/* { dg-final { scan-assembler-not "push\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ +/* { dg-final { scan-assembler-not "pop\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ +/* { dg-final { scan-assembler-not "jmp" } } */ +/* { dg-final { scan-assembler "call\[\\t \]+" } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-6.c b/gcc/testsuite/gcc.target/i386/preserve-none-6.c new file mode 100644 index 0000000..037f9ec --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-6.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move -fomit-frame-pointer" } */ + +extern int bar (int) +#ifndef __x86_64__ +__attribute__ ((regparm(3))) +#endif +; + +__attribute__ ((preserve_none)) +void +foo (void *frame) +{ + int a,b,c,d,e,f,i; + a = bar (5); + b = bar (a); + c = bar (b); + d = bar (c); + e = bar (d); + f = bar (e); + for (i = 1; i < 10; i++) + { + a += bar (a + i) + bar (b + i) + + bar (c + i) + bar (d + i) + + bar (e + i) + bar (f + i); + } +} + +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*" 1 } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-7.c b/gcc/testsuite/gcc.target/i386/preserve-none-7.c new file mode 100644 index 0000000..2c80560 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-7.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move -fomit-frame-pointer" } */ + +extern int bar (int) __attribute__ ((no_caller_saved_registers)) +#ifndef __x86_64__ +__attribute__ ((regparm(3))) +#endif +; + +__attribute__ ((preserve_none)) +void +foo (void *frame) +{ + int a,b,c,d,e,f,i; + a = bar (5); + b = bar (a); + c = bar (b); + d = bar (c); + e = bar (d); + f = bar (e); + for (i = 1; i < 10; i++) + { + a += bar (a + i) + bar (b + i) + + bar (c + i) + bar (d + i) + + bar (e + i) + bar (f + i); + } +} + +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bp" 1 } } */ +/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*" 1 } } */ +/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-8.c b/gcc/testsuite/gcc.target/i386/preserve-none-8.c new file mode 100644 index 0000000..9309ceb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +__attribute__ ((preserve_none, no_caller_saved_registers)) +void +foo (void) +{ /* { dg-error "attributes are not compatible" } */ +} diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-9.c b/gcc/testsuite/gcc.target/i386/preserve-none-9.c new file mode 100644 index 0000000..f28ddeb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/preserve-none-9.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mgeneral-regs-only" } */ + +__attribute__ ((preserve_none, interrupt)) +void +foo (void *frame) /* { dg-error "attributes are not compatible" } */ +{ +} diff --git a/gcc/testsuite/gcc.target/i386/reduc-pshuf.c b/gcc/testsuite/gcc.target/i386/reduc-pshuf.c new file mode 100644 index 0000000..e46d2ba --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/reduc-pshuf.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=znver5 " } */ + +#define N 32 +#define T short +T +foo (T *a) +{ + T sum = 0; + for (int i = 0; i < N; i++) + sum += a[i]; + return sum; +} + +/* { dg-final { scan-assembler-times "vpsrl" 0 } } */ +/* { dg-final { scan-assembler-times "vpshuf" 3 } } */ diff --git a/gcc/testsuite/gcc.target/i386/shrink-wrap-separate-mingw.c b/gcc/testsuite/gcc.target/i386/shrink-wrap-separate-mingw.c new file mode 100644 index 0000000..58635e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/shrink-wrap-separate-mingw.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target *-*-mingw* *-*-cygwin* } } */ +/* { dg-options "-std=gnu99 -O2" } */ + +short __mingw_swformat_format; +__builtin_va_list __mingw_swformat_arg; +int __mingw_swformat_fc; +typedef struct { + void *fp; + int bch[1024]; +} _IFP; +void __mingw_swformat(_IFP *s) { + if (s->fp) + while (__mingw_swformat_format) + if (__mingw_swformat_fc == 'A') + *__builtin_va_arg(__mingw_swformat_arg, double *) = 0; +} +void +__mingw_vswscanf (void) +{ + _IFP ifp; + __mingw_swformat(&ifp); +} diff --git a/gcc/testsuite/gcc.target/i386/shrink_wrap_1.c b/gcc/testsuite/gcc.target/i386/shrink_wrap_1.c index 4b28667..30b82ab 100644 --- a/gcc/testsuite/gcc.target/i386/shrink_wrap_1.c +++ b/gcc/testsuite/gcc.target/i386/shrink_wrap_1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O2 -fdump-rtl-pro_and_epilogue -fno-stack-protector" } */ +/* { dg-options "-O2 -mmemset-strategy=rep_8byte:-1:align -fdump-rtl-pro_and_epilogue -fno-stack-protector" } */ enum machine_mode { diff --git a/gcc/testsuite/gcc.target/i386/shrink_wrap_separate_check_lea.c b/gcc/testsuite/gcc.target/i386/shrink_wrap_separate_check_lea.c new file mode 100644 index 0000000..d61de57 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/shrink_wrap_separate_check_lea.c @@ -0,0 +1,29 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -fdump-rtl-pro_and_epilogue" } */ + +/* Avoid inserting sub between test-je-jle to change EFlags, lea should be used here + xorl %eax, %eax + testl %edi, %edi + je .L11 + sub $16, %rsp ------> leaq -16(%rsp), %rsp + movq %r13, 8(%rsp) + movl $1, %r13d + jle .L4 +*/ +int foo (int num) +{ + if (!num) + return 0; + + register int r13 __asm ("r13") = 1; + + for ( int i = 0; i < num; i++) + { + register int r12 __asm ("r12") = 1; + asm volatile ("" : "+r" (r12), "+r" (r13)); + } + + return 1; +} +/* { dg-final { scan-rtl-dump "The components we wrap separately are \\\[sep 40\\\]" "pro_and_epilogue" } } */ +/* { dg-final { scan-assembler "lea(l|q).*(%rsp)" } } */ diff --git a/gcc/testsuite/gcc.target/i386/sibcall-8.c b/gcc/testsuite/gcc.target/i386/sibcall-8.c index 3ab3809..29ebfe5 100644 --- a/gcc/testsuite/gcc.target/i386/sibcall-8.c +++ b/gcc/testsuite/gcc.target/i386/sibcall-8.c @@ -1,23 +1,29 @@ /* { dg-do run } */ /* { dg-options "-O2" } */ +#ifndef __x86_64__ +#define REGPARM __attribute__((regparm(1))) +#else +#define REGPARM +#endif + extern void abort (void); -static int __attribute__((regparm(1))) +static int REGPARM bar(void *arg) { return arg != bar; } -static int __attribute__((noinline,noclone,regparm(1))) -foo(int (__attribute__((regparm(1))) **bar)(void*)) +static int __attribute__((noinline,noclone)) REGPARM +foo(int (REGPARM **bar)(void*)) { return (*bar)(*bar); } int main() { - int (__attribute__((regparm(1))) *p)(void*) = bar; + int (REGPARM *p)(void*) = bar; if (foo(&p)) abort(); return 0; diff --git a/gcc/testsuite/gcc.target/i386/sm4-avx10_2-512-1.c b/gcc/testsuite/gcc.target/i386/sm4-avx10_2-1b.c index e7f7934..e7f7934 100644 --- a/gcc/testsuite/gcc.target/i386/sm4-avx10_2-512-1.c +++ b/gcc/testsuite/gcc.target/i386/sm4-avx10_2-1b.c diff --git a/gcc/testsuite/gcc.target/i386/sm4-check.h b/gcc/testsuite/gcc.target/i386/sm4-check.h index 76c16db..c9d95ef 100644 --- a/gcc/testsuite/gcc.target/i386/sm4-check.h +++ b/gcc/testsuite/gcc.target/i386/sm4-check.h @@ -1,8 +1,8 @@ #include <stdlib.h> #include "m512-check.h" -#ifdef AVX10_2_512 -static void sm4_avx512f_test (void); +#ifdef AVX10_2 +static void sm4_avx10_test (void); #else static void sm4_test (void); #endif @@ -160,7 +160,7 @@ compute_sm4##name##4 (int *dst, int *src1, int *src2, int vl) \ if (check_union256i_d (res2, dst2)) \ abort (); -#define SM4_AVX512F_SIMULATE(name) \ +#define SM4_AVX10_SIMULATE(name) \ union512i_d src5, src6, res3; \ int dst3[16] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; \ \ @@ -181,8 +181,8 @@ static void __attribute__ ((noinline)) do_test (void) { -#ifdef AVX10_512BIT - sm4_avx512f_test (); +#ifdef AVX10_2 + sm4_avx10_test (); #else sm4_test (); #endif diff --git a/gcc/testsuite/gcc.target/i386/sm4key4-avx10_2-512-2.c b/gcc/testsuite/gcc.target/i386/sm4key4-avx10_2-2.c index 1c8b2c3..2cb638e 100644 --- a/gcc/testsuite/gcc.target/i386/sm4key4-avx10_2-512-2.c +++ b/gcc/testsuite/gcc.target/i386/sm4key4-avx10_2-2.c @@ -4,15 +4,13 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT #include "sm4-check.h" char key; SM4_FUNC (key); static void -sm4_avx512f_test (void) +sm4_avx10_test (void) { - SM4_AVX512F_SIMULATE (key); + SM4_AVX10_SIMULATE (key); } diff --git a/gcc/testsuite/gcc.target/i386/sm4rnds4-avx10_2-512-2.c b/gcc/testsuite/gcc.target/i386/sm4rnds4-avx10_2-2.c index 5418a53..b544c07 100644 --- a/gcc/testsuite/gcc.target/i386/sm4rnds4-avx10_2-512-2.c +++ b/gcc/testsuite/gcc.target/i386/sm4rnds4-avx10_2-2.c @@ -4,15 +4,13 @@ /* { dg-require-effective-target avx10_2 } */ #define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT #include "sm4-check.h" char rnds; SM4_FUNC (rnds); static void -sm4_avx512f_test (void) +sm4_avx10_test (void) { - SM4_AVX512F_SIMULATE (rnds); + SM4_AVX10_SIMULATE (rnds); } diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 3132eca..189e19e 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -849,37 +849,33 @@ /* sm3intrin.h */ #define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A, B, C, 1) -/* avx10_2-512mediaintrin.h */ +/* avx10_2mediaintrin.h */ #define __builtin_ia32_mpsadbw512(A, B, C) __builtin_ia32_mpsadbw512 (A, B, 1) #define __builtin_ia32_mpsadbw512_mask(A, B, C, D, E) __builtin_ia32_mpsadbw512_mask (A, B, 1, D, E) - -/* avx10_2mediaintrin.h */ -#define __builtin_ia32_mpsadbw128_mask(A, B, C, D, E) __builtin_ia32_mpsadbw128_mask (A, B, 1, D, E) #define __builtin_ia32_mpsadbw256_mask(A, B, C, D, E) __builtin_ia32_mpsadbw256_mask (A, B, 1, D, E) +#define __builtin_ia32_mpsadbw128_mask(A, B, C, D, E) __builtin_ia32_mpsadbw128_mask (A, B, 1, D, E) -/* avx10_2-512convertintrin.h */ +/* avx10_2convertintrin.h */ #define __builtin_ia32_vcvt2ps2phx512_mask_round(A, B, C, D, E) __builtin_ia32_vcvt2ps2phx512_mask_round(A, B, C, D, 8) -/* avx10_2-512bf16intrin.h */ -#define __builtin_ia32_rndscalebf16512_mask(A, B, C, D) __builtin_ia32_rndscalebf16512_mask(A, 123, C, D) -#define __builtin_ia32_reducebf16512_mask(A, B, C, D) __builtin_ia32_reducebf16512_mask(A, 123, C, D) -#define __builtin_ia32_getmantbf16512_mask(A, B, C, D) __builtin_ia32_getmantbf16512_mask(A, 1, C, D) -#define __builtin_ia32_fpclassbf16512_mask(A, B, C) __builtin_ia32_fpclassbf16512_mask(A, 1, C) -#define __builtin_ia32_cmpbf16512_mask(A, B, C, D) __builtin_ia32_cmpbf16512_mask(A, B, 1, D) - /* avx10_2bf16intrin.h */ +#define __builtin_ia32_rndscalebf16512_mask(A, B, C, D) __builtin_ia32_rndscalebf16512_mask(A, 123, C, D) #define __builtin_ia32_rndscalebf16256_mask(A, B, C, D) __builtin_ia32_rndscalebf16256_mask(A, 123, C, D) #define __builtin_ia32_rndscalebf16128_mask(A, B, C, D) __builtin_ia32_rndscalebf16128_mask(A, 123, C, D) +#define __builtin_ia32_reducebf16512_mask(A, B, C, D) __builtin_ia32_reducebf16512_mask(A, 123, C, D) #define __builtin_ia32_reducebf16256_mask(A, B, C, D) __builtin_ia32_reducebf16256_mask(A, 123, C, D) #define __builtin_ia32_reducebf16128_mask(A, B, C, D) __builtin_ia32_reducebf16128_mask(A, 123, C, D) +#define __builtin_ia32_getmantbf16512_mask(A, B, C, D) __builtin_ia32_getmantbf16512_mask(A, 1, C, D) #define __builtin_ia32_getmantbf16256_mask(A, B, C, D) __builtin_ia32_getmantbf16256_mask(A, 1, C, D) #define __builtin_ia32_getmantbf16128_mask(A, B, C, D) __builtin_ia32_getmantbf16128_mask(A, 1, C, D) +#define __builtin_ia32_fpclassbf16512_mask(A, B, C) __builtin_ia32_fpclassbf16512_mask(A, 1, C) #define __builtin_ia32_fpclassbf16256_mask(A, B, C) __builtin_ia32_fpclassbf16256_mask(A, 1, C) #define __builtin_ia32_fpclassbf16128_mask(A, B, C) __builtin_ia32_fpclassbf16128_mask(A, 1, C) +#define __builtin_ia32_cmpbf16512_mask(A, B, C, D) __builtin_ia32_cmpbf16512_mask(A, B, 1, D) #define __builtin_ia32_cmpbf16256_mask(A, B, C, D) __builtin_ia32_cmpbf16256_mask(A, B, 1, D) #define __builtin_ia32_cmpbf16128_mask(A, B, C, D) __builtin_ia32_cmpbf16128_mask(A, B, 1, D) -/* avx10_2-512satcvtintrin.h */ +/* avx10_2satcvtintrin.h */ #define __builtin_ia32_cvtph2ibs512_mask_round(A, B, C, D) __builtin_ia32_cvtph2ibs512_mask_round(A, B, C, 8) #define __builtin_ia32_cvtph2iubs512_mask_round(A, B, C, D) __builtin_ia32_cvtph2iubs512_mask_round(A, B, C, 8) #define __builtin_ia32_cvtps2ibs512_mask_round(A, B, C, D) __builtin_ia32_cvtps2ibs512_mask_round(A, B, C, 8) @@ -896,8 +892,6 @@ #define __builtin_ia32_cvttps2qqs512_mask_round(A, B, C, D) __builtin_ia32_cvttps2qqs512_mask_round(A, B, C, 8) #define __builtin_ia32_cvttps2udqs512_mask_round(A, B, C, D) __builtin_ia32_cvttps2udqs512_mask_round(A, B, C, 8) #define __builtin_ia32_cvttps2uqqs512_mask_round(A, B, C, D) __builtin_ia32_cvttps2uqqs512_mask_round(A, B, C, 8) - -/* avx10_2satcvtintrin.h */ #define __builtin_ia32_cvttsd2sis32_round(A, B) __builtin_ia32_cvttsd2sis32_round(A, 8) #define __builtin_ia32_cvttsd2usis32_round(A, B) __builtin_ia32_cvttsd2usis32_round(A, 8) #define __builtin_ia32_cvttss2sis32_round(A, B) __builtin_ia32_cvttss2sis32_round(A, 8) @@ -909,23 +903,21 @@ #define __builtin_ia32_cvttss2usis64_round(A, B) __builtin_ia32_cvttss2usis64_round(A, 8) #endif -/* avx10_2-512minmaxintrin.h */ +/* avx10_2minmaxintrin.h */ +#define __builtin_ia32_minmaxbf16512_mask(A, B, C, W, U) __builtin_ia32_minmaxbf16512_mask (A, B, 4, W, U) +#define __builtin_ia32_minmaxbf16256_mask(A, B, C, D, E) __builtin_ia32_minmaxbf16256_mask (A, B, 4, D, E) +#define __builtin_ia32_minmaxbf16128_mask(A, B, C, D, E) __builtin_ia32_minmaxbf16128_mask (A, B, 4, D, E) #define __builtin_ia32_minmaxpd512_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxpd512_mask_round (A, B, 4, D, E, 4) +#define __builtin_ia32_minmaxpd256_mask(A, B, C, D, E) __builtin_ia32_minmaxpd256_mask (A, B, 4, D, E) +#define __builtin_ia32_minmaxpd128_mask(A, B, C, D, E) __builtin_ia32_minmaxpd128_mask (A, B, 4, D, E) #define __builtin_ia32_minmaxph512_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxph512_mask_round (A, B, 4, D, E, 4) +#define __builtin_ia32_minmaxph256_mask(A, B, C, D, E) __builtin_ia32_minmaxph256_mask (A, B, 4, D, E) +#define __builtin_ia32_minmaxph128_mask(A, B, C, D, E) __builtin_ia32_minmaxph128_mask (A, B, 4, D, E) #define __builtin_ia32_minmaxps512_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxps512_mask_round (A, B, 4, D, E, 4) -#define __builtin_ia32_minmaxbf16512_mask(A, B, C, W, U) __builtin_ia32_minmaxbf16512_mask (A, B, 4, W, U) - -/* avx10_2minmaxintrin.h */ +#define __builtin_ia32_minmaxps256_mask(A, B, C, D, E) __builtin_ia32_minmaxps256_mask (A, B, 4, D, E) +#define __builtin_ia32_minmaxps128_mask(A, B, C, D, E) __builtin_ia32_minmaxps128_mask (A, B, 4, D, E) #define __builtin_ia32_minmaxsd_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxsd_mask_round (A, B, 4, D, E, 4) #define __builtin_ia32_minmaxsh_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxsh_mask_round (A, B, 4, D, E, 4) #define __builtin_ia32_minmaxss_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxss_mask_round (A, B, 4, D, E, 4) -#define __builtin_ia32_minmaxbf16128_mask(A, B, C, D, E) __builtin_ia32_minmaxbf16128_mask (A, B, 4, D, E) -#define __builtin_ia32_minmaxbf16256_mask(A, B, C, D, E) __builtin_ia32_minmaxbf16256_mask (A, B, 4, D, E) -#define __builtin_ia32_minmaxpd128_mask(A, B, C, D, E) __builtin_ia32_minmaxpd128_mask (A, B, 4, D, E) -#define __builtin_ia32_minmaxpd256_mask(A, B, C, D, E) __builtin_ia32_minmaxpd256_mask (A, B, 4, D, E) -#define __builtin_ia32_minmaxph128_mask(A, B, C, D, E) __builtin_ia32_minmaxph128_mask (A, B, 4, D, E) -#define __builtin_ia32_minmaxph256_mask(A, B, C, D, E) __builtin_ia32_minmaxph256_mask (A, B, 4, D, E) -#define __builtin_ia32_minmaxps128_mask(A, B, C, D, E) __builtin_ia32_minmaxps128_mask (A, B, 4, D, E) -#define __builtin_ia32_minmaxps256_mask(A, B, C, D, E) __builtin_ia32_minmaxps256_mask (A, B, 4, D, E) #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 8ae41c1..f3b7c112 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1020,64 +1020,60 @@ test_2 (_mm512_gf2p8affine_epi64_epi8, __m512i, __m512i, __m512i, 1) /* sm3intrin.h */ test_3 (_mm_sm3rnds2_epi32, __m128i, __m128i, __m128i, __m128i, 1) -/* avx10_2-512mediaintrin.h */ +/* avx10_2mediaintrin.h */ test_2 (_mm512_mpsadbw_epu8, __m512i, __m512i, __m512i, 1) test_3 (_mm512_maskz_mpsadbw_epu8, __m512i, __mmask32, __m512i, __m512i, 1) -test_4 (_mm512_mask_mpsadbw_epu8, __m512i, __m512i, __mmask32, __m512i, __m512i, 1) - -/* avx10_2mediaintrin.h */ -test_3 (_mm_maskz_mpsadbw_epu8, __m128i, __mmask8, __m128i, __m128i, 1) test_3 (_mm256_maskz_mpsadbw_epu8, __m256i, __mmask16, __m256i, __m256i, 1) -test_4 (_mm_mask_mpsadbw_epu8, __m128i, __m128i, __mmask8, __m128i, __m128i, 1) +test_3 (_mm_maskz_mpsadbw_epu8, __m128i, __mmask8, __m128i, __m128i, 1) +test_4 (_mm512_mask_mpsadbw_epu8, __m512i, __m512i, __mmask32, __m512i, __m512i, 1) test_4 (_mm256_mask_mpsadbw_epu8, __m256i, __m256i, __mmask16, __m256i, __m256i, 1) +test_4 (_mm_mask_mpsadbw_epu8, __m128i, __m128i, __mmask8, __m128i, __m128i, 1) -/* avx10_2-512convertintrin.h */ +/* avx10_2convertintrin.h */ test_2 (_mm512_cvtx_round2ps_ph, __m512h, __m512, __m512, 4) -/* avx10_2-512bf16intrin.h */ -test_1 (_mm512_roundscale_pbh, __m512bh, __m512bh, 123) -test_2 (_mm512_maskz_roundscale_pbh, __m512bh, __mmask32, __m512bh, 123) -test_3 (_mm512_mask_roundscale_pbh, __m512bh, __m512bh, __mmask32, __m512bh, 123) -test_1 (_mm512_reduce_pbh, __m512bh, __m512bh, 123) -test_2 (_mm512_maskz_reduce_pbh, __m512bh, __mmask32, __m512bh, 123) -test_3 (_mm512_mask_reduce_pbh, __m512bh, __m512bh, __mmask32, __m512bh, 123) -test_1x (_mm512_getmant_pbh, __m512bh, __m512bh, 1, 1) -test_2x (_mm512_maskz_getmant_pbh, __m512bh, __mmask32,__m512bh, 1, 1) -test_3x (_mm512_mask_getmant_pbh, __m512bh, __m512bh, __mmask32,__m512bh, 1, 1) -test_1 (_mm512_fpclass_pbh_mask, __mmask32, __m512bh, 13) -test_2 (_mm512_mask_fpclass_pbh_mask, __mmask32, __mmask32, __m512bh, 13) -test_2 (_mm512_cmp_pbh_mask, __mmask32, __m512bh, __m512bh, 1) -test_3 (_mm512_mask_cmp_pbh_mask, __mmask32, __mmask32,__m512bh, __m512bh, 1) - /* avx10_2bf16intrin.h */ +test_1 (_mm512_roundscale_pbh, __m512bh, __m512bh, 123) test_1 (_mm256_roundscale_pbh, __m256bh, __m256bh, 123) test_1 (_mm_roundscale_pbh, __m128bh, __m128bh, 123) +test_2 (_mm512_maskz_roundscale_pbh, __m512bh, __mmask32, __m512bh, 123) test_2 (_mm256_maskz_roundscale_pbh, __m256bh, __mmask16, __m256bh, 123) test_2 (_mm_maskz_roundscale_pbh, __m128bh, __mmask8, __m128bh, 123) +test_3 (_mm512_mask_roundscale_pbh, __m512bh, __m512bh, __mmask32, __m512bh, 123) test_3 (_mm256_mask_roundscale_pbh, __m256bh, __m256bh, __mmask16, __m256bh, 123) test_3 (_mm_mask_roundscale_pbh, __m128bh, __m128bh, __mmask8, __m128bh, 123) +test_1 (_mm512_reduce_pbh, __m512bh, __m512bh, 123) test_1 (_mm256_reduce_pbh, __m256bh, __m256bh, 123) test_1 (_mm_reduce_pbh, __m128bh, __m128bh, 123) +test_2 (_mm512_maskz_reduce_pbh, __m512bh, __mmask32, __m512bh, 123) test_2 (_mm256_maskz_reduce_pbh, __m256bh, __mmask16, __m256bh, 123) test_2 (_mm_maskz_reduce_pbh, __m128bh, __mmask8, __m128bh, 123) +test_3 (_mm512_mask_reduce_pbh, __m512bh, __m512bh, __mmask32, __m512bh, 123) test_3 (_mm256_mask_reduce_pbh, __m256bh, __m256bh, __mmask16, __m256bh, 123) test_3 (_mm_mask_reduce_pbh, __m128bh, __m128bh, __mmask8, __m128bh, 123) +test_1x (_mm512_getmant_pbh, __m512bh, __m512bh, 1, 1) test_1x (_mm256_getmant_pbh, __m256bh, __m256bh, 1, 1) test_1x (_mm_getmant_pbh, __m128bh, __m128bh, 1, 1) +test_2x (_mm512_maskz_getmant_pbh, __m512bh, __mmask32,__m512bh, 1, 1) test_2x (_mm256_maskz_getmant_pbh, __m256bh, __mmask16,__m256bh, 1, 1) test_2x (_mm_maskz_getmant_pbh, __m128bh, __mmask8, __m128bh, 1, 1) +test_3x (_mm512_mask_getmant_pbh, __m512bh, __m512bh, __mmask32,__m512bh, 1, 1) test_3x (_mm256_mask_getmant_pbh, __m256bh, __m256bh, __mmask16,__m256bh, 1, 1) test_3x (_mm_mask_getmant_pbh, __m128bh, __m128bh, __mmask8, __m128bh, 1, 1) +test_1 (_mm512_fpclass_pbh_mask, __mmask32, __m512bh, 13) test_1 (_mm256_fpclass_pbh_mask, __mmask16, __m256bh, 13) test_1 (_mm_fpclass_pbh_mask, __mmask8, __m128bh, 13) +test_2 (_mm512_mask_fpclass_pbh_mask, __mmask32, __mmask32, __m512bh, 13) test_2 (_mm256_mask_fpclass_pbh_mask, __mmask16, __mmask16, __m256bh, 13) test_2 (_mm_mask_fpclass_pbh_mask, __mmask8, __mmask8, __m128bh, 13) +test_2 (_mm512_cmp_pbh_mask, __mmask32, __m512bh, __m512bh, 1) test_2 (_mm256_cmp_pbh_mask, __mmask16, __m256bh, __m256bh, 1) test_2 (_mm_cmp_pbh_mask, __mmask8, __m128bh, __m128bh, 1) +test_3 (_mm512_mask_cmp_pbh_mask, __mmask32, __mmask32,__m512bh, __m512bh, 1) test_3 (_mm256_mask_cmp_pbh_mask, __mmask16, __mmask16, __m256bh, __m256bh, 1) test_3 (_mm_mask_cmp_pbh_mask, __mmask8, __mmask8, __m128bh, __m128bh, 1) -/* avx10_2-512satcvtintrin.h */ +/* avx10_2satcvtintrin.h */ test_1 (_mm512_ipcvts_roundph_epi8, __m512i, __m512h, 8) test_1 (_mm512_ipcvts_roundph_epu8, __m512i, __m512h, 8) test_1 (_mm512_ipcvts_roundps_epi8, __m512i, __m512, 8) @@ -1126,8 +1122,6 @@ test_3 (_mm512_mask_cvtts_roundps_epu32, __m512i, __m512i, __mmask16, __m512, 8) test_1 (_mm512_cvtts_roundps_epu64, __m512i, __m256, 8) test_2 (_mm512_maskz_cvtts_roundps_epu64, __m512i, __mmask8, __m256, 8) test_3 (_mm512_mask_cvtts_roundps_epu64, __m512i, __m512i, __mmask8, __m256, 8) - -/* avx10_2satcvtintrin.h */ test_1 (_mm_cvtts_roundsd_epi32, int, __m128d, 8) test_1 (_mm_cvtts_roundsd_epu32, unsigned int, __m128d, 8) test_1 (_mm_cvtts_roundss_epi32, int, __m128, 8) @@ -1139,7 +1133,7 @@ test_1 (_mm_cvtts_roundss_epi64, long long, __m128, 8) test_1 (_mm_cvtts_roundss_epu64, unsigned long long, __m128, 8) #endif -/* avx10_2-512minmaxintrin.h */ +/* avx10_2minmaxintrin.h */ test_2 (_mm512_minmax_pbh, __m512bh, __m512bh, __m512bh, 100) test_3 (_mm512_maskz_minmax_pbh, __m512bh, __mmask32, __m512bh, __m512bh, 100) test_4 (_mm512_mask_minmax_pbh, __m512bh, __m512bh, __mmask32, __m512bh, __m512bh, 100) @@ -1161,8 +1155,6 @@ test_4 (_mm512_mask_minmax_ps, __m512, __m512, __mmask16, __m512, __m512, 100) test_2 (_mm512_minmax_ph, __m512h, __m512h, __m512h, 100) test_3 (_mm512_maskz_minmax_ph, __m512h, __mmask32, __m512h, __m512h, 100) test_4 (_mm512_mask_minmax_ph, __m512h, __m512h, __mmask32, __m512h, __m512h, 100) - -/* avx10_2minmaxintrin.h */ test_2 (_mm256_minmax_pbh, __m256bh, __m256bh, __m256bh, 100) test_3 (_mm256_maskz_minmax_pbh, __m256bh, __mmask16, __m256bh, __m256bh, 100) test_4 (_mm256_mask_minmax_pbh, __m256bh, __m256bh, __mmask16, __m256bh, __m256bh, 100) diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index 16b059e..0cb0368 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -1061,64 +1061,60 @@ test_1 ( __bextri_u64, unsigned long long, unsigned long long, 1) /* sm3intrin.h */ test_3 (_mm_sm3rnds2_epi32, __m128i, __m128i, __m128i, __m128i, 1) -/* avx10_2-512mediaintrin.h */ +/* avx10_2mediaintrin.h */ test_2 (_mm512_mpsadbw_epu8, __m512i, __m512i, __m512i, 1) test_3 (_mm512_maskz_mpsadbw_epu8, __m512i, __mmask32, __m512i, __m512i, 1) -test_4 (_mm512_mask_mpsadbw_epu8, __m512i, __m512i, __mmask32, __m512i, __m512i, 1) - -/* avx10_2mediaintrin.h */ -test_3 (_mm_maskz_mpsadbw_epu8, __m128i, __mmask8, __m128i, __m128i, 1) test_3 (_mm256_maskz_mpsadbw_epu8, __m256i, __mmask16, __m256i, __m256i, 1) -test_4 (_mm_mask_mpsadbw_epu8, __m128i, __m128i, __mmask8, __m128i, __m128i, 1) +test_3 (_mm_maskz_mpsadbw_epu8, __m128i, __mmask8, __m128i, __m128i, 1) +test_4 (_mm512_mask_mpsadbw_epu8, __m512i, __m512i, __mmask32, __m512i, __m512i, 1) test_4 (_mm256_mask_mpsadbw_epu8, __m256i, __m256i, __mmask16, __m256i, __m256i, 1) +test_4 (_mm_mask_mpsadbw_epu8, __m128i, __m128i, __mmask8, __m128i, __m128i, 1) -/* avx10_2-512convertintrin.h */ +/* avx10_2convertintrin.h */ test_2 (_mm512_cvtx_round2ps_ph, __m512h, __m512, __m512, 4) -/* avx10_2-512bf16intrin.h */ -test_1 (_mm512_roundscale_pbh, __m512bh, __m512bh, 123) -test_2 (_mm512_maskz_roundscale_pbh, __m512bh, __mmask32, __m512bh, 123) -test_3 (_mm512_mask_roundscale_pbh, __m512bh, __m512bh, __mmask32, __m512bh, 123) -test_1 (_mm512_reduce_pbh, __m512bh, __m512bh, 123) -test_2 (_mm512_maskz_reduce_pbh, __m512bh, __mmask32, __m512bh, 123) -test_3 (_mm512_mask_reduce_pbh, __m512bh, __m512bh, __mmask32, __m512bh, 123) -test_1x (_mm512_getmant_pbh, __m512bh, __m512bh, 1, 1) -test_2x (_mm512_maskz_getmant_pbh, __m512bh, __mmask32,__m512bh, 1, 1) -test_3x (_mm512_mask_getmant_pbh, __m512bh, __m512bh, __mmask32,__m512bh, 1, 1) -test_1 (_mm512_fpclass_pbh_mask, __mmask32, __m512bh, 13) -test_2 (_mm512_mask_fpclass_pbh_mask, __mmask32, __mmask32, __m512bh, 13) -test_2 (_mm512_cmp_pbh_mask, __mmask32, __m512bh, __m512bh, 1) -test_3 (_mm512_mask_cmp_pbh_mask, __mmask32, __mmask32,__m512bh, __m512bh, 1) - /* avx10_2bf16intrin.h */ +test_1 (_mm512_roundscale_pbh, __m512bh, __m512bh, 123) test_1 (_mm256_roundscale_pbh, __m256bh, __m256bh, 123) test_1 (_mm_roundscale_pbh, __m128bh, __m128bh, 123) +test_2 (_mm512_maskz_roundscale_pbh, __m512bh, __mmask32, __m512bh, 123) test_2 (_mm256_maskz_roundscale_pbh, __m256bh, __mmask16, __m256bh, 123) test_2 (_mm_maskz_roundscale_pbh, __m128bh, __mmask8, __m128bh, 123) +test_3 (_mm512_mask_roundscale_pbh, __m512bh, __m512bh, __mmask32, __m512bh, 123) test_3 (_mm256_mask_roundscale_pbh, __m256bh, __m256bh, __mmask16, __m256bh, 123) test_3 (_mm_mask_roundscale_pbh, __m128bh, __m128bh, __mmask8, __m128bh, 123) +test_1 (_mm512_reduce_pbh, __m512bh, __m512bh, 123) test_1 (_mm256_reduce_pbh, __m256bh, __m256bh, 123) test_1 (_mm_reduce_pbh, __m128bh, __m128bh, 123) +test_2 (_mm512_maskz_reduce_pbh, __m512bh, __mmask32, __m512bh, 123) test_2 (_mm256_maskz_reduce_pbh, __m256bh, __mmask16, __m256bh, 123) test_2 (_mm_maskz_reduce_pbh, __m128bh, __mmask8, __m128bh, 123) +test_3 (_mm512_mask_reduce_pbh, __m512bh, __m512bh, __mmask32, __m512bh, 123) test_3 (_mm256_mask_reduce_pbh, __m256bh, __m256bh, __mmask16, __m256bh, 123) test_3 (_mm_mask_reduce_pbh, __m128bh, __m128bh, __mmask8, __m128bh, 123) +test_1x (_mm512_getmant_pbh, __m512bh, __m512bh, 1, 1) test_1x (_mm256_getmant_pbh, __m256bh, __m256bh, 1, 1) test_1x (_mm_getmant_pbh, __m128bh, __m128bh, 1, 1) +test_2x (_mm512_maskz_getmant_pbh, __m512bh, __mmask32,__m512bh, 1, 1) test_2x (_mm256_maskz_getmant_pbh, __m256bh, __mmask16,__m256bh, 1, 1) test_2x (_mm_maskz_getmant_pbh, __m128bh, __mmask8, __m128bh, 1, 1) +test_3x (_mm512_mask_getmant_pbh, __m512bh, __m512bh, __mmask32,__m512bh, 1, 1) test_3x (_mm256_mask_getmant_pbh, __m256bh, __m256bh, __mmask16,__m256bh, 1, 1) test_3x (_mm_mask_getmant_pbh, __m128bh, __m128bh, __mmask8, __m128bh, 1, 1) +test_1 (_mm512_fpclass_pbh_mask, __mmask32, __m512bh, 13) test_1 (_mm256_fpclass_pbh_mask, __mmask16, __m256bh, 13) test_1 (_mm_fpclass_pbh_mask, __mmask8, __m128bh, 13) +test_2 (_mm512_mask_fpclass_pbh_mask, __mmask32, __mmask32, __m512bh, 13) test_2 (_mm256_mask_fpclass_pbh_mask, __mmask16, __mmask16, __m256bh, 13) test_2 (_mm_mask_fpclass_pbh_mask, __mmask8, __mmask8, __m128bh, 13) +test_2 (_mm512_cmp_pbh_mask, __mmask32, __m512bh, __m512bh, 1) test_2 (_mm256_cmp_pbh_mask, __mmask16, __m256bh, __m256bh, 1) test_2 (_mm_cmp_pbh_mask, __mmask8, __m128bh, __m128bh, 1) +test_3 (_mm512_mask_cmp_pbh_mask, __mmask32, __mmask32,__m512bh, __m512bh, 1) test_3 (_mm256_mask_cmp_pbh_mask, __mmask16, __mmask16, __m256bh, __m256bh, 1) test_3 (_mm_mask_cmp_pbh_mask, __mmask8, __mmask8, __m128bh, __m128bh, 1) -/* avx10_2-512satcvtintrin.h */ +/* avx10_2satcvtintrin.h */ test_1 (_mm512_ipcvts_roundph_epi8, __m512i, __m512h, 8) test_1 (_mm512_ipcvts_roundph_epu8, __m512i, __m512h, 8) test_1 (_mm512_ipcvts_roundps_epi8, __m512i, __m512, 8) @@ -1167,8 +1163,6 @@ test_3 (_mm512_mask_cvtts_roundps_epu32, __m512i, __m512i, __mmask16, __m512, 8) test_1 (_mm512_cvtts_roundps_epu64, __m512i, __m256, 8) test_2 (_mm512_maskz_cvtts_roundps_epu64, __m512i, __mmask8, __m256, 8) test_3 (_mm512_mask_cvtts_roundps_epu64, __m512i, __m512i, __mmask8, __m256, 8) - -/* avx10_2satcvtintrin.h */ test_1 (_mm_cvtts_roundsd_epi32, int, __m128d, 8) test_1 (_mm_cvtts_roundsd_epu32, unsigned int, __m128d, 8) test_1 (_mm_cvtts_roundss_epi32, int, __m128, 8) @@ -1180,7 +1174,7 @@ test_1 (_mm_cvtts_roundss_epi64, long long, __m128, 8) test_1 (_mm_cvtts_roundss_epu64, unsigned long long, __m128, 8) #endif -/* avx10_2-512minmaxintrin.h */ +/* avx10_2minmaxintrin.h */ test_2 (_mm512_minmax_pbh, __m512bh, __m512bh, __m512bh, 100) test_3 (_mm512_maskz_minmax_pbh, __m512bh, __mmask32, __m512bh, __m512bh, 100) test_4 (_mm512_mask_minmax_pbh, __m512bh, __m512bh, __mmask32, __m512bh, __m512bh, 100) @@ -1202,8 +1196,6 @@ test_4 (_mm512_mask_minmax_ps, __m512, __m512, __mmask16, __m512, __m512, 100) test_2 (_mm512_minmax_ph, __m512h, __m512h, __m512h, 100) test_3 (_mm512_maskz_minmax_ph, __m512h, __mmask32, __m512h, __m512h, 100) test_4 (_mm512_mask_minmax_ph, __m512h, __m512h, __mmask32, __m512h, __m512h, 100) - -/* avx10_2minmaxintrin.h */ test_2 (_mm256_minmax_pbh, __m256bh, __m256bh, __m256bh, 100) test_3 (_mm256_maskz_minmax_pbh, __m256bh, __mmask16, __m256bh, __m256bh, 100) test_4 (_mm256_mask_minmax_pbh, __m256bh, __m256bh, __mmask16, __m256bh, __m256bh, 100) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index 2cfcf28..95db1f7 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -824,37 +824,33 @@ /* sm3intrin.h */ #define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A, B, C, 1) -/* avx10_2-512mediaintrin.h */ +/* avx10_2-mediaintrin.h */ #define __builtin_ia32_mpsadbw512(A, B, C) __builtin_ia32_mpsadbw512 (A, B, 1) #define __builtin_ia32_mpsadbw512_mask(A, B, C, D, E) __builtin_ia32_mpsadbw512_mask (A, B, 1, D, E) - -/* avx10_2-mediaintrin.h */ -#define __builtin_ia32_mpsadbw128_mask(A, B, C, D, E) __builtin_ia32_mpsadbw128_mask (A, B, 1, D, E) #define __builtin_ia32_mpsadbw256_mask(A, B, C, D, E) __builtin_ia32_mpsadbw256_mask (A, B, 1, D, E) +#define __builtin_ia32_mpsadbw128_mask(A, B, C, D, E) __builtin_ia32_mpsadbw128_mask (A, B, 1, D, E) -/* avx10_2-512convertintrin.h */ +/* avx10_2convertintrin.h */ #define __builtin_ia32_vcvt2ps2phx512_mask_round(A, B, C, D, E) __builtin_ia32_vcvt2ps2phx512_mask_round(A, B, C, D, 8) -/* avx10_2-512bf16intrin.h */ -#define __builtin_ia32_rndscalebf16512_mask(A, B, C, D) __builtin_ia32_rndscalebf16512_mask(A, 123, C, D) -#define __builtin_ia32_reducebf16512_mask(A, B, C, D) __builtin_ia32_reducebf16512_mask(A, 123, C, D) -#define __builtin_ia32_getmantbf16512_mask(A, B, C, D) __builtin_ia32_getmantbf16512_mask(A, 1, C, D) -#define __builtin_ia32_fpclassbf16512_mask(A, B, C) __builtin_ia32_fpclassbf16512_mask(A, 1, C) -#define __builtin_ia32_cmpbf16512_mask(A, B, C, D) __builtin_ia32_cmpbf16512_mask(A, B, 1, D) - /* avx10_2bf16intrin.h */ +#define __builtin_ia32_rndscalebf16512_mask(A, B, C, D) __builtin_ia32_rndscalebf16512_mask(A, 123, C, D) #define __builtin_ia32_rndscalebf16256_mask(A, B, C, D) __builtin_ia32_rndscalebf16256_mask(A, 123, C, D) #define __builtin_ia32_rndscalebf16128_mask(A, B, C, D) __builtin_ia32_rndscalebf16128_mask(A, 123, C, D) +#define __builtin_ia32_reducebf16512_mask(A, B, C, D) __builtin_ia32_reducebf16512_mask(A, 123, C, D) #define __builtin_ia32_reducebf16256_mask(A, B, C, D) __builtin_ia32_reducebf16256_mask(A, 123, C, D) #define __builtin_ia32_reducebf16128_mask(A, B, C, D) __builtin_ia32_reducebf16128_mask(A, 123, C, D) +#define __builtin_ia32_getmantbf16512_mask(A, B, C, D) __builtin_ia32_getmantbf16512_mask(A, 1, C, D) #define __builtin_ia32_getmantbf16256_mask(A, B, C, D) __builtin_ia32_getmantbf16256_mask(A, 1, C, D) #define __builtin_ia32_getmantbf16128_mask(A, B, C, D) __builtin_ia32_getmantbf16128_mask(A, 1, C, D) +#define __builtin_ia32_fpclassbf16512_mask(A, B, C) __builtin_ia32_fpclassbf16512_mask(A, 1, C) #define __builtin_ia32_fpclassbf16256_mask(A, B, C) __builtin_ia32_fpclassbf16256_mask(A, 1, C) #define __builtin_ia32_fpclassbf16128_mask(A, B, C) __builtin_ia32_fpclassbf16128_mask(A, 1, C) +#define __builtin_ia32_cmpbf16512_mask(A, B, C, D) __builtin_ia32_cmpbf16512_mask(A, B, 1, D) #define __builtin_ia32_cmpbf16256_mask(A, B, C, D) __builtin_ia32_cmpbf16256_mask(A, B, 1, D) #define __builtin_ia32_cmpbf16128_mask(A, B, C, D) __builtin_ia32_cmpbf16128_mask(A, B, 1, D) -/* avx10_2-512satcvtintrin.h */ +/* avx10_2satcvtintrin.h */ #define __builtin_ia32_cvtph2ibs512_mask_round(A, B, C, D) __builtin_ia32_cvtph2ibs512_mask_round(A, B, C, 8) #define __builtin_ia32_cvtph2iubs512_mask_round(A, B, C, D) __builtin_ia32_cvtph2iubs512_mask_round(A, B, C, 8) #define __builtin_ia32_cvtps2ibs512_mask_round(A, B, C, D) __builtin_ia32_cvtps2ibs512_mask_round(A, B, C, 8) @@ -871,8 +867,6 @@ #define __builtin_ia32_cvttps2qqs512_mask_round(A, B, C, D) __builtin_ia32_cvttps2qqs512_mask_round(A, B, C, 8) #define __builtin_ia32_cvttps2udqs512_mask_round(A, B, C, D) __builtin_ia32_cvttps2udqs512_mask_round(A, B, C, 8) #define __builtin_ia32_cvttps2uqqs512_mask_round(A, B, C, D) __builtin_ia32_cvttps2uqqs512_mask_round(A, B, C, 8) - -/* avx10_2satcvtintrin.h */ #define __builtin_ia32_cvttsd2sis32_round(A, B) __builtin_ia32_cvttsd2sis32_round(A, 8) #define __builtin_ia32_cvttsd2usis32_round(A, B) __builtin_ia32_cvttsd2usis32_round(A, 8) #define __builtin_ia32_cvttss2sis32_round(A, B) __builtin_ia32_cvttss2sis32_round(A, 8) @@ -884,24 +878,22 @@ #define __builtin_ia32_cvttss2usis64_round(A, B) __builtin_ia32_cvttss2usis64_round(A, 8) #endif -/* avx10_2-512minmaxintrin.h */ +/* avx10_2-minmaxintrin.h */ +#define __builtin_ia32_minmaxbf16512_mask(A, B, C, W, U) __builtin_ia32_minmaxbf16512_mask (A, B, 100, W, U) +#define __builtin_ia32_minmaxbf16256_mask(A, B, C, D, E) __builtin_ia32_minmaxbf16256_mask (A, B, 100, D, E) +#define __builtin_ia32_minmaxbf16128_mask(A, B, C, D, E) __builtin_ia32_minmaxbf16128_mask (A, B, 100, D, E) #define __builtin_ia32_minmaxpd512_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxpd512_mask_round (A, B, 100, D, E, 4) +#define __builtin_ia32_minmaxpd256_mask(A, B, C, D, E) __builtin_ia32_minmaxpd256_mask (A, B, 100, D, E) +#define __builtin_ia32_minmaxpd128_mask(A, B, C, D, E) __builtin_ia32_minmaxpd128_mask (A, B, 100, D, E) #define __builtin_ia32_minmaxph512_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxph512_mask_round (A, B, 100, D, E, 4) +#define __builtin_ia32_minmaxph256_mask(A, B, C, D, E) __builtin_ia32_minmaxph256_mask (A, B, 100, D, E) +#define __builtin_ia32_minmaxph128_mask(A, B, C, D, E) __builtin_ia32_minmaxph128_mask (A, B, 100, D, E) #define __builtin_ia32_minmaxps512_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxps512_mask_round (A, B, 100, D, E, 4) -#define __builtin_ia32_minmaxbf16512_mask(A, B, C, W, U) __builtin_ia32_minmaxbf16512_mask (A, B, 100, W, U) - -/* avx10_2-minmaxintrin.h */ +#define __builtin_ia32_minmaxps256_mask(A, B, C, D, E) __builtin_ia32_minmaxps256_mask (A, B, 100, D, E) +#define __builtin_ia32_minmaxps128_mask(A, B, C, D, E) __builtin_ia32_minmaxps128_mask (A, B, 100, D, E) #define __builtin_ia32_minmaxsd_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxsd_mask_round (A, B, 100, D, E, 4) #define __builtin_ia32_minmaxsh_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxsh_mask_round (A, B, 100, D, E, 4) #define __builtin_ia32_minmaxss_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxss_mask_round (A, B, 100, D, E, 4) -#define __builtin_ia32_minmaxbf16128_mask(A, B, C, D, E) __builtin_ia32_minmaxbf16128_mask (A, B, 100, D, E) -#define __builtin_ia32_minmaxbf16256_mask(A, B, C, D, E) __builtin_ia32_minmaxbf16256_mask (A, B, 100, D, E) -#define __builtin_ia32_minmaxpd128_mask(A, B, C, D, E) __builtin_ia32_minmaxpd128_mask (A, B, 100, D, E) -#define __builtin_ia32_minmaxpd256_mask(A, B, C, D, E) __builtin_ia32_minmaxpd256_mask (A, B, 100, D, E) -#define __builtin_ia32_minmaxph128_mask(A, B, C, D, E) __builtin_ia32_minmaxph128_mask (A, B, 100, D, E) -#define __builtin_ia32_minmaxph256_mask(A, B, C, D, E) __builtin_ia32_minmaxph256_mask (A, B, 100, D, E) -#define __builtin_ia32_minmaxps128_mask(A, B, C, D, E) __builtin_ia32_minmaxps128_mask (A, B, 100, D, E) -#define __builtin_ia32_minmaxps256_mask(A, B, C, D, E) __builtin_ia32_minmaxps256_mask (A, B, 100, D, E) #pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-tf32,amx-transpose,amx-fp8,movrs,amx-movrs") diff --git a/gcc/testsuite/gcc.target/i386/stack-clash-protection.c b/gcc/testsuite/gcc.target/i386/stack-clash-protection.c new file mode 100644 index 0000000..5be28cb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/stack-clash-protection.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fstack-clash-protection" } */ + +int flag; +void open(); +int getChar(); +typedef enum { QUOTE } CharType; +typedef enum { UNQ } State; +CharType getCharType(); +void expand() { + open(); + if (flag) + return; + int ch = getChar(); + State nextState = getCharType(); + if (nextState) + while (ch) + ; +} diff --git a/gcc/testsuite/gcc.target/i386/sw-1.c b/gcc/testsuite/gcc.target/i386/sw-1.c index b043227..025f0e1 100644 --- a/gcc/testsuite/gcc.target/i386/sw-1.c +++ b/gcc/testsuite/gcc.target/i386/sw-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mtune=generic -fshrink-wrap -fdump-rtl-pro_and_epilogue -fno-stack-protector" } */ +/* { dg-options "-O2 -mtune=generic -mstringop-strategy=rep_byte -fshrink-wrap -fdump-rtl-pro_and_epilogue -fno-stack-protector" } */ /* { dg-additional-options "-mno-avx" { target ia32 } } */ /* { dg-skip-if "No shrink-wrapping preformed" { x86_64-*-mingw* } } */ @@ -7,7 +7,10 @@ int c; int x[2000]; -__attribute__((regparm(1))) void foo (int a, int b) +#ifndef __x86_64__ +__attribute__((regparm(1))) +#endif +void foo (int a, int b) { int t[200]; if (a == 0 || c == 0) diff --git a/gcc/testsuite/gcc.target/i386/uintr-2.c b/gcc/testsuite/gcc.target/i386/uintr-2.c index 0a83c66..a0d2514 100644 --- a/gcc/testsuite/gcc.target/i386/uintr-2.c +++ b/gcc/testsuite/gcc.target/i386/uintr-2.c @@ -15,6 +15,6 @@ foo (void *frame, uword_t uirrv) void __attribute__((interrupt)) -UINTR_hanlder (struct __uintr_frame *frame, uword_t uirrv) +UINTR_handler (struct __uintr_frame *frame, uword_t uirrv) { } diff --git a/gcc/testsuite/gcc.target/i386/uintr-5.c b/gcc/testsuite/gcc.target/i386/uintr-5.c index 49cb2ec..7c7c12f 100644 --- a/gcc/testsuite/gcc.target/i386/uintr-5.c +++ b/gcc/testsuite/gcc.target/i386/uintr-5.c @@ -7,6 +7,6 @@ typedef unsigned int uword_t __attribute__ ((mode (__word__))); void -UINTR_hanlder (struct __uintr_frame *frame, uword_t uirrv) +UINTR_handler (struct __uintr_frame *frame, uword_t uirrv) { } diff --git a/gcc/testsuite/gcc.target/i386/vect-epilogues-1.c b/gcc/testsuite/gcc.target/i386/vect-epilogues-1.c new file mode 100644 index 0000000..a7f5f12 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-epilogues-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx2 -mno-avx512f -mtune=generic -fdump-tree-vect-optimized" } */ + +int test (signed char *data, int n) +{ + int sum = 0; + for (int i = 0; i < n; ++i) + sum += data[i]; + return sum; +} + +/* { dg-final { scan-tree-dump "loop vectorized using 32 byte vectors" "vect" } } */ +/* { dg-final { scan-tree-dump "loop vectorized using 16 byte vectors" "vect" } } */ +/* { dg-final { scan-tree-dump "loop vectorized using 8 byte vectors" "vect" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-epilogues-2.c b/gcc/testsuite/gcc.target/i386/vect-epilogues-2.c new file mode 100644 index 0000000..d6c06ed --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-epilogues-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx512bw -mtune=generic -fdump-tree-vect-optimized" } */ + +int test (signed char *data, int n) +{ + int sum = 0; + for (int i = 0; i < n; ++i) + sum += data[i]; + return sum; +} + +/* { dg-final { scan-tree-dump "loop vectorized using 64 byte vectors" "vect" } } */ +/* { dg-final { scan-tree-dump "loop vectorized using 32 byte vectors" "vect" } } */ +/* { dg-final { scan-tree-dump-not "loop vectorized using 16 byte vectors" "vect" } } */ +/* { dg-final { scan-tree-dump-not "loop vectorized using 8 byte vectors" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-epilogues-3.c b/gcc/testsuite/gcc.target/i386/vect-epilogues-3.c new file mode 100644 index 0000000..e88ab30 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-epilogues-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx512bw -mtune=znver4 --param vect-partial-vector-usage=0 -fdump-tree-vect-optimized" } */ + +int test (signed char *data, int n) +{ + int sum = 0; + for (int i = 0; i < n; ++i) + sum += data[i]; + return sum; +} + +/* { dg-final { scan-tree-dump "loop vectorized using 64 byte vectors" "vect" } } */ +/* { dg-final { scan-tree-dump "loop vectorized using 32 byte vectors" "vect" } } */ +/* { dg-final { scan-tree-dump "loop vectorized using 16 byte vectors" "vect" } } */ +/* { dg-final { scan-tree-dump "loop vectorized using 8 byte vectors" "vect" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-epilogues-4.c b/gcc/testsuite/gcc.target/i386/vect-epilogues-4.c new file mode 100644 index 0000000..498db6b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-epilogues-4.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx512bw -mtune=generic --param vect-partial-vector-usage=1 -fdump-tree-vect-optimized" } */ + +int test (signed char *data, int n) +{ + int sum = 0; + for (int i = 0; i < n; ++i) + sum += data[i]; + return sum; +} + +/* { dg-final { scan-tree-dump-times "loop vectorized using 64 byte vectors" 2 "vect" } } */ +/* { dg-final { scan-tree-dump-not "loop vectorized using 32 byte vectors" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-epilogues-5.c b/gcc/testsuite/gcc.target/i386/vect-epilogues-5.c new file mode 100644 index 0000000..d7c75df --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-epilogues-5.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx512bw -mtune=znver4 --param vect-partial-vector-usage=1 -fdump-tree-vect-optimized" } */ + +int test (signed char *data, int n) +{ + int sum = 0; + for (int i = 0; i < n; ++i) + sum += data[i]; + return sum; +} + +/* { dg-final { scan-tree-dump-times "loop vectorized using 64 byte vectors" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "epilogue loop vectorized using masked 64 byte vectors" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-not "loop vectorized using 32 byte vectors" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-mask-epilogue-1.c b/gcc/testsuite/gcc.target/i386/vect-mask-epilogue-1.c new file mode 100644 index 0000000..55519aa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-mask-epilogue-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=znver5 -fdump-tree-vect-optimized" } */ + +void bar (double *a, double *b, double c, int n, int m) +{ + for (int j = 0; j < m; ++j) + for (int i = 0; i < n; ++i) + a[j*n + i] = b[j*n + i] + c; +} + +/* { dg-final { scan-tree-dump "epilogue loop vectorized using masked 64 byte vectors" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-mask-epilogue-2.c b/gcc/testsuite/gcc.target/i386/vect-mask-epilogue-2.c new file mode 100644 index 0000000..3dc28b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-mask-epilogue-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=znver5 -fdump-tree-vect-optimized" } */ + +void foo (double *a, double b, double c, int n, int m) +{ + for (int j = 0; j < m; ++j) + for (int i = 0; i < n; ++i) + a[j*n + i] = a[j*n + i] * b + c; +} + +/* We do not want to use a masked epilogue for the inner loop as the next + outer iteration will possibly immediately read from elements masked of + the previous inner loop epilogue and that never forwards. */ +/* { dg-final { scan-tree-dump "epilogue loop vectorized using 32 byte vectors" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-pr82426-2.c b/gcc/testsuite/gcc.target/i386/vect-pr82426-2.c new file mode 100644 index 0000000..5259408 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-pr82426-2.c @@ -0,0 +1,31 @@ +/* i?86 does not have V2SF, x32 does though. */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O3 -mavx -mfma -ffp-contract=on" } */ + +struct Matrix +{ + float m11; + float m12; + float m21; + float m22; + float dx; + float dy; +}; + +struct Matrix multiply(const struct Matrix *a, const struct Matrix *b) +{ + struct Matrix out; + out.m11 = a->m11*b->m11 + a->m12*b->m21; + out.m12 = a->m11*b->m12 + a->m12*b->m22; + out.m21 = a->m21*b->m11 + a->m22*b->m21; + out.m22 = a->m21*b->m12 + a->m22*b->m22; + + out.dx = a->dx*b->m11 + a->dy*b->m21 + b->dx; + out.dy = a->dx*b->m12 + a->dy*b->m22 + b->dy; + return out; +} + +/* The whole kernel should be vectorized with V4SF and V2SF operations. */ +/* { dg-final { scan-assembler-times "vadd" 1 } } */ +/* { dg-final { scan-assembler-times "vmul" 2 } } */ +/* { dg-final { scan-assembler-times "vfma" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-pr82426.c b/gcc/testsuite/gcc.target/i386/vect-pr82426.c index 03b10ad..8ce8fe7 100644 --- a/gcc/testsuite/gcc.target/i386/vect-pr82426.c +++ b/gcc/testsuite/gcc.target/i386/vect-pr82426.c @@ -1,6 +1,6 @@ /* i?86 does not have V2SF, x32 does though. */ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O3 -mavx -mfma" } */ +/* { dg-options "-O3 -mavx -mfma -ffp-contract=fast" } */ struct Matrix { diff --git a/gcc/testsuite/gcc.target/i386/vect-pragma-target-1.c b/gcc/testsuite/gcc.target/i386/vect-pragma-target-1.c new file mode 100644 index 0000000..f5e71e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-pragma-target-1.c @@ -0,0 +1,194 @@ +/* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */ +/* { dg-options "-O0" } */ +/* { dg-final { scan-assembler-times "paddd.+xmm\[0-9]+" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd132ps.+ymm\[0-9]+" 1 } } */ +/* { dg-final { scan-assembler-times "vpaddw.+zmm\[0-9]+" 1 } } */ +#ifndef CHECK_DEFINES +#define CHECK_DEFINES 0 +#endif + +#define N 1024 + +/* Optimization flags and tree vectorizer shall be disabled at this point */ +#if CHECK_DEFINES && defined(__OPTIMIZE__) +#error "__OPTIMIZE__ is defined (not compiled with -O0?)" +#endif + +#pragma GCC push_options +#pragma GCC optimize ("O2", "tree-vectorize") + +/* Optimization flags and tree vectorizer shall be enabled at this point */ +#if CHECK_DEFINES && !defined(__OPTIMIZE__) +#error "__OPTIMIZE__ is not defined" +#endif + +#pragma GCC push_options +#pragma GCC target ("sse4.2") +#ifdef __cplusplus +namespace { +#endif + +/* Target flags up to including SSE4.2 shall be enabled at this point */ +#if CHECK_DEFINES && !defined(__SSE3__) +#error "Target flag (SSE3) is not defined" +#endif +#if CHECK_DEFINES && !defined(__SSSE3__) +#error "Target flag (SSSE3) is not defined" +#endif +#if CHECK_DEFINES && !defined(__SSE4_1__) +#error "Target flag (SSE4.1) is not defined" +#endif +#if CHECK_DEFINES && !defined(__SSE4_2__) +#error "Target flag (SSE4.2) is not defined" +#endif + +void +__attribute__((__noinline__, __used__)) +vec_saxpy_i32(int y[N], const int a[N], const int x[N]) +{ + int i; + for (i = 0; i < N; i++) + y[i] += a[i] * x[i]; +} + +#ifdef __cplusplus +} +#endif +#pragma GCC pop_options + +/* Target flags up to including SSE4.2 shall be disabled at this point */ +#if CHECK_DEFINES && defined(__SSE3__) +#error "Target flag (SSE3) is still defined" +#endif +#if CHECK_DEFINES && defined(__SSSE3__) +#error "Target flag (SSSE3) is still defined" +#endif +#if CHECK_DEFINES && defined(__SSE4_1__) +#error "Target flag (SSE4.1) is still defined" +#endif +#if CHECK_DEFINES && defined(__SSE4_2__) +#error "Target flag (SSE4.2) is still defined" +#endif + +#pragma GCC push_options +#pragma GCC target ("avx2", "fma") +#ifdef __cplusplus +struct A { +#endif + +/* Target flags up to including AVX2+FMA shall be enabled at this point */ +#if CHECK_DEFINES && !defined(__SSE3__) +#error "Target flag (SSE3) is not defined" +#endif +#if CHECK_DEFINES && !defined(__SSSE3__) +#error "Target flag (SSSE3) is not defined" +#endif +#if CHECK_DEFINES && !defined(__SSE4_1__) +#error "Target flag (SSE4.1) is not defined" +#endif +#if CHECK_DEFINES && !defined(__SSE4_2__) +#error "Target flag (SSE4.2) is not defined" +#endif +#if CHECK_DEFINES && !defined(__AVX__) +#error "Target flag (AVX) is not defined" +#endif +#if CHECK_DEFINES && !defined(__AVX2__) +#error "Target flag (AVX2) is not defined" +#endif +#if CHECK_DEFINES && !defined(__FMA__) +#error "Target flag (FMA) is not defined" +#endif + +void +__attribute__((__noinline__, __used__)) +vec_saxpy_f32(float y[N], const float a[N], const float x[N]) +{ + int i; + for (i = 0; i < N; i++) + y[i] += a[i] * x[i]; +} + +#ifdef __cplusplus +}; +#endif +#pragma GCC pop_options + +/* Target flags up to including AVX2+FMA shall be disabled at this point */ +#if CHECK_DEFINES && defined(__SSE3__) +#error "Target flag (SSE3) is still defined" +#endif +#if CHECK_DEFINES && defined(__SSSE3__) +#error "Target flag (SSSE3) is still defined" +#endif +#if CHECK_DEFINES && defined(__SSE4_1__) +#error "Target flag (SSE4.1) is still defined" +#endif +#if CHECK_DEFINES && defined(__SSE4_2__) +#error "Target flag (SSE4.2) is still defined" +#endif +#if CHECK_DEFINES && defined(__AVX__) +#error "Target flag (AVX) is still defined" +#endif +#if CHECK_DEFINES && defined(__AVX2__) +#error "Target flag (AVX2) is still defined" +#endif +#if CHECK_DEFINES && defined(__FMA__) +#error "Target flag (FMA) is still defined" +#endif + +#pragma GCC push_options +#pragma GCC target ("arch=x86-64-v4") +#ifdef __cplusplus +namespace avx512 { +struct A { +#endif + +/* Essential AVX512 target flags shall be enabled at this point */ +#if CHECK_DEFINES && !defined(__AVX512F__) +#error "Target flag (AVX512F) is not defined" +#endif +#if CHECK_DEFINES && !defined(__AVX512VL__) +#error "Target flag (AVX512VL) is not defined" +#endif +#if CHECK_DEFINES && !defined(__AVX512DQ__) +#error "Target flag (AVX512DQ) is not defined" +#endif +#if CHECK_DEFINES && !defined(__AVX512BW__) +#error "Target flag (AVX512BW) is not defined" +#endif + +void +__attribute__((__noinline__, __used__)) +vec_saxpy_i16(short y[N], const short a[N], const short x[N]) +{ + int i; + for (i = 0; i < N; i++) + y[i] += a[i] * x[i]; +} + +#ifdef __cplusplus +}; +} +#endif +#pragma GCC pop_options + +/* Essential AVX512 target flags shall be disabled at this point */ +#if CHECK_DEFINES && defined(__AVX512F__) +#error "Target flag (AVX512F) is still defined" +#endif +#if CHECK_DEFINES && defined(__AVX512VL__) +#error "Target flag (AVX512VL) is still defined" +#endif +#if CHECK_DEFINES && defined(__AVX512DQ__) +#error "Target flag (AVX512DQ) is still defined" +#endif +#if CHECK_DEFINES && defined(__AVX512BW__) +#error "Target flag (AVX512BW) is still defined" +#endif + +#pragma GCC pop_options + +/* Optimization flags and tree vectorizer shall be disabled at this point */ +#if CHECK_DEFINES && defined(__OPTIMIZE__) +#error "__OPTIMIZE__ is still defined" +#endif diff --git a/gcc/testsuite/gcc.target/i386/vect-pragma-target-2.c b/gcc/testsuite/gcc.target/i386/vect-pragma-target-2.c new file mode 100644 index 0000000..3496804 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-pragma-target-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */ +/* { dg-options "-O0" } */ +/* { dg-final { scan-assembler-times "paddd.+xmm\[0-9]+" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd132ps.+ymm\[0-9]+" 1 } } */ +/* { dg-final { scan-assembler-times "vpaddw.+zmm\[0-9]+" 1 } } */ +#define CHECK_DEFINES 1 +#include "vect-pragma-target-1.c" diff --git a/gcc/testsuite/gcc.target/i386/vnniint16-auto-vectorize-4.c b/gcc/testsuite/gcc.target/i386/vnniint16-auto-vectorize-4.c index 06a85a8..204348f1 100644 --- a/gcc/testsuite/gcc.target/i386/vnniint16-auto-vectorize-4.c +++ b/gcc/testsuite/gcc.target/i386/vnniint16-auto-vectorize-4.c @@ -5,8 +5,7 @@ #define N 512 #define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT +#define AVX10_SCALAR #define AVX512F_LEN 512 #define TEST test_512 diff --git a/gcc/testsuite/gcc.target/i386/vnniint8-auto-vectorize-4.c b/gcc/testsuite/gcc.target/i386/vnniint8-auto-vectorize-4.c index 76cca22..798e7fc 100644 --- a/gcc/testsuite/gcc.target/i386/vnniint8-auto-vectorize-4.c +++ b/gcc/testsuite/gcc.target/i386/vnniint8-auto-vectorize-4.c @@ -5,8 +5,7 @@ #define N 512 #define AVX10_2 -#define AVX10_2_512 -#define AVX10_512BIT +#define AVX10_SCALAR #define AVX512F_LEN 512 #define TEST test_512 diff --git a/gcc/testsuite/gcc.target/loongarch/pr121064.c b/gcc/testsuite/gcc.target/loongarch/pr121064.c new file mode 100644 index 0000000..a466c7a --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr121064.c @@ -0,0 +1,38 @@ +/* { dg-require-effective-target loongarch_sx_hw } */ +/* { dg-do run } */ +/* { dg-options "-march=loongarch64 -mfpu=64 -mlsx -O3" } */ + +typedef __INT32_TYPE__ int32_t; +typedef unsigned __INT32_TYPE__ uint32_t; + +__attribute__ ((noipa)) static int32_t +long_filter_ehigh_3830_1 (int32_t *buffer, int length) +{ + int i, j; + int32_t dotprod = 0; + int32_t delay[4] = { 0 }; + uint32_t coeffs[4] = { 0 }; + + for (i = 0; i < length; i++) + { + dotprod = 0; + for (j = 3; j >= 0; j--) + { + dotprod += delay[j] * coeffs[j]; + coeffs[j] += ((delay[j] >> 31) | 1); + } + for (j = 3; j > 0; j--) + delay[j] = delay[j - 1]; + delay[0] = buffer[i]; + } + + return dotprod; +} + +int +main () +{ + int32_t buffer[] = { -1, 1 }; + if (long_filter_ehigh_3830_1 (buffer, 2) != -1) + __builtin_trap (); +} diff --git a/gcc/testsuite/gcc.target/nvptx/abi-struct-arg.c b/gcc/testsuite/gcc.target/nvptx/abi-struct-arg.c index 54ae651..c2cc4de 100644 --- a/gcc/testsuite/gcc.target/nvptx/abi-struct-arg.c +++ b/gcc/testsuite/gcc.target/nvptx/abi-struct-arg.c @@ -3,12 +3,16 @@ /* Struct arg. Passed via pointer. */ +typedef struct {} empty; /* See 'gcc/doc/extend.texi', "Empty Structures". */ typedef struct {char a;} one; typedef struct {short a;} two; typedef struct {int a;} four; typedef struct {long long a;} eight; typedef struct {int a, b[12];} big; +/* { dg-final { scan-assembler-times ".extern .func dcl_aempty \\(.param.u64 %\[_a-z0-9\]*\\);" 1 } } */ +void dcl_aempty (empty); + /* { dg-final { scan-assembler-times ".extern .func dcl_aone \\(.param.u64 %\[_a-z0-9\]*\\);" 1 } } */ void dcl_aone (one); @@ -28,6 +32,7 @@ void dcl_abig (big); void test_1 (void) { + dcl_aempty (({empty t; t;})); dcl_aone (M (one, 1)); dcl_atwo (M (two, 2)); dcl_afour (M (four, 3)); @@ -35,6 +40,11 @@ void test_1 (void) dcl_abig (M (big, 5)); } +/* { dg-final { scan-assembler-times ".visible .func dfn_aempty \\(.param.u64 %\[_a-z0-9\]*\\)(?:;|\[\r\n\]+\{)" 2 } } */ +void dfn_aempty (empty empty) +{ +} + /* { dg-final { scan-assembler-times ".visible .func dfn_aone \\(.param.u64 %\[_a-z0-9\]*\\)(?:;|\[\r\n\]+\{)" 2 } } */ void dfn_aone (one one) { diff --git a/gcc/testsuite/gcc.target/nvptx/abi-struct-ret.c b/gcc/testsuite/gcc.target/nvptx/abi-struct-ret.c index d48a82d..13e5021 100644 --- a/gcc/testsuite/gcc.target/nvptx/abi-struct-ret.c +++ b/gcc/testsuite/gcc.target/nvptx/abi-struct-ret.c @@ -3,12 +3,16 @@ /* Struct return. Returned via pointer. */ +typedef struct {} empty; /* See 'gcc/doc/extend.texi', "Empty Structures". */ typedef struct {char a;} one; typedef struct {short a;} two; typedef struct {int a;} four; typedef struct {long long a;} eight; typedef struct {int a, b[12];} big; +/* { dg-final { scan-assembler-times ".extern .func dcl_rempty \\(.param.u64 %\[_a-z0-9\]*\\);" 1 } } */ +empty dcl_rempty (void); + /* { dg-final { scan-assembler-times ".extern .func dcl_rone \\(.param.u64 %\[_a-z0-9\]*\\);" 1 } } */ one dcl_rone (void); @@ -26,6 +30,7 @@ big dcl_rbig (void); void test_1 (void) { + dcl_rempty (); dcl_rone (); dcl_rtwo (); dcl_rfour (); @@ -35,6 +40,12 @@ void test_1 (void) #define M(T, v) ({T t; t.a = v; t;}) +/* { dg-final { scan-assembler-times ".visible .func dfn_rempty \\(.param.u64 %\[_a-z0-9\]*\\)(?:;|\[\r\n\]+\{)" 2 } } */ +empty dfn_rempty (void) +{ + return ({empty t; t;}); +} + /* { dg-final { scan-assembler-times ".visible .func dfn_rone \\(.param.u64 %\[_a-z0-9\]*\\)(?:;|\[\r\n\]+\{)" 2 } } */ one dfn_rone (void) { diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_100.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_100.c new file mode 100644 index 0000000..e759a11 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_100.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_100 -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_100a.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_100a.c new file mode 100644 index 0000000..153ed1e --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_100a.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_100a -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_100f.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_100f.c new file mode 100644 index 0000000..9bb9127 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_100f.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_100f -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_101.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_101.c new file mode 100644 index 0000000..06b3ceb --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_101.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_101 -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_101a.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_101a.c new file mode 100644 index 0000000..0cca3f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_101a.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_101a -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_101f.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_101f.c new file mode 100644 index 0000000..9548be5 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_101f.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_101f -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_103.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_103.c new file mode 100644 index 0000000..5731249 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_103.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_103 -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_103a.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_103a.c new file mode 100644 index 0000000..aea501e --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_103a.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_103a -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_103f.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_103f.c new file mode 100644 index 0000000..59d8987 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_103f.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_103f -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_120.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_120.c new file mode 100644 index 0000000..d28a671 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_120.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_120 -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_120a.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_120a.c new file mode 100644 index 0000000..613dd65 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_120a.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_120a -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_120f.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_120f.c new file mode 100644 index 0000000..1b23350 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_120f.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_120f -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_121.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_121.c new file mode 100644 index 0000000..240332b --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_121.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_121 -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_121a.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_121a.c new file mode 100644 index 0000000..1e7fb70 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_121a.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_121a -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_121f.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_121f.c new file mode 100644 index 0000000..2cbec51 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_121f.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_121f -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/or1k/call-1.c b/gcc/testsuite/gcc.target/or1k/call-1.c new file mode 100644 index 0000000..593e402 --- /dev/null +++ b/gcc/testsuite/gcc.target/or1k/call-1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcmodel=large" } */ + +/* Generate local and global function calls. */ + +extern int geti (void); + +__attribute__ ((noinline)) int +calc (int a, int b) +{ + return a * b + 255; +} + +int +main (void) +{ + return geti () + calc (3, 4); +} + +/* Ensure the 2 calls use register not immediate jumps. */ +/* { dg-final { scan-assembler-times "l.movhi\\s+" 2 } } */ +/* { dg-final { scan-assembler-times "l.jalr\\s+" 2 } } */ diff --git a/gcc/testsuite/gcc.target/or1k/got-1.c b/gcc/testsuite/gcc.target/or1k/got-1.c new file mode 100644 index 0000000..5357096 --- /dev/null +++ b/gcc/testsuite/gcc.target/or1k/got-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fPIC -mcmodel=large" } */ + +/* Generate references to the GOT. */ + +extern int geti (void); +extern int j; + +int +calc (int a) +{ + return a * j + geti (); +} + +/* Ensure the 2 references use gotha relocations and that the function call does + not use an immediate jump instruction. */ +/* { dg-final { scan-assembler-times "gotha" 2 } } */ +/* { dg-final { scan-assembler "l.jalr\\s+" } } */ diff --git a/gcc/testsuite/gcc.target/or1k/return-2.c b/gcc/testsuite/gcc.target/or1k/return-2.c index add3720..c072ae2 100644 --- a/gcc/testsuite/gcc.target/or1k/return-2.c +++ b/gcc/testsuite/gcc.target/or1k/return-2.c @@ -16,4 +16,4 @@ struct a getstruct (long aa) { /* Ensure our return value is returned on stack. */ /* { dg-final { scan-assembler-not "r12," } } */ /* { dg-final { scan-assembler "l.or\\s+r11, r3, r3" } } */ -/* { dg-final { scan-assembler-times "l.sw\\s+\\d+.r11.," 3 } } */ +/* { dg-final { scan-assembler-times "l.sw\\s+\\d+.r3.," 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/builtin_altivec_tr_stxvr_runnable.c b/gcc/testsuite/gcc.target/powerpc/builtin_altivec_tr_stxvr_runnable.c index 4b90437..fab7a52 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtin_altivec_tr_stxvr_runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/builtin_altivec_tr_stxvr_runnable.c @@ -27,10 +27,10 @@ int main () { int i; signed long sl; - signed char sc, expected_sc; - signed short ss, expected_ss; - signed int si, expected_si; - signed long long int sll, expected_sll; + signed char sc[2], expected_sc; + signed short ss[2], expected_ss; + signed int si[2], expected_si; + signed long long int sll[2], expected_sll; signed char *psc; signed short *pss; signed int *psi; @@ -41,56 +41,56 @@ main () { printf("Data to store [%d] = 0x%llx %llx\n", i, val.ull[1], val.ull[0]); #endif - psc = ≻ - pss = &ss; - psi = &si; - psll = &sll; + psc = &sc[0]; + pss = &ss[0]; + psi = &si[0]; + psll = &sll[0]; sl = 1; - sc = 0xA1; + sc[0] = 0xA1; expected_sc = 0xA1; __builtin_altivec_tr_stxvrbx (store_data, sl, psc); - if (expected_sc != sc & 0xFF) + if (expected_sc != sc[0] & 0xFF) #if DEBUG printf(" ERROR: Signed char = 0x%x doesn't match expected value 0x%x\n", - sc & 0xFF, expected_sc); + sc[0] & 0xFF, expected_sc); #else abort(); #endif - ss = 0x52; + ss[0] = 0x52; expected_ss = 0x1752; __builtin_altivec_tr_stxvrhx (store_data, sl, pss); - if (expected_ss != ss & 0xFFFF) + if (expected_ss != ss[0] & 0xFFFF) #if DEBUG printf(" ERROR: Signed short = 0x%x doesn't match expected value 0x%x\n", - ss, expected_ss) & 0xFFFF; + ss[0], expected_ss) & 0xFFFF; #else abort(); #endif - si = 0x21; + si[0] = 0x21; expected_si = 0x54321721; __builtin_altivec_tr_stxvrwx (store_data, sl, psi); - if (expected_si != si) + if (expected_si != si[0]) #if DEBUG printf(" ERROR: Signed int = 0x%x doesn't match expected value 0x%x\n", - si, expected_si); + si[0], expected_si); #else abort(); #endif - sll = 0x12FFULL; + sll[0] = 0x12FFULL; expected_sll = 0xdcba9876543217FF; __builtin_altivec_tr_stxvrdx (store_data, sl, psll); - if (expected_sll != sll) + if (expected_sll != sll[0]) #if DEBUG printf(" ERROR: Signed long long int = 0x%llx doesn't match expected value 0x%llx\n", - sll, expected_sll); + sll[0], expected_sll); #else abort(); #endif diff --git a/gcc/testsuite/gcc.target/powerpc/pr121007.c b/gcc/testsuite/gcc.target/powerpc/pr121007.c new file mode 100644 index 0000000..9e6b1be --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr121007.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ + +typedef struct { int a; } A; +unsigned char *a; +char b; +int c; +void foo (vector char, vector char, vector char); + +void +bar (long stride) +{ + vector char v0, v1, v2, v3, v5; + vector char r0 = __builtin_vec_vsx_ld (0, a); + vector char r2 = __builtin_vec_vsx_ld (2 * stride, a - 3); + vector char r3 = __builtin_vec_vsx_ld (3 * stride, a - 3); + vector char r4; + vector char r6 = __builtin_vec_vsx_ld (6 * stride, a - 3); + vector char r7 = __builtin_vec_vsx_ld (7 * stride, a - 3); + vector char r14, h, i, j; + if (b) + return; + v1 = __builtin_vec_vsx_ld (9 * stride, a); + v2 = __builtin_vec_vsx_ld (10 * stride, a - 3); + v3 = __builtin_vec_vsx_ld (11 * stride, a - 3); + r3 = __builtin_vec_mergeh (r3, v3); + v5 = __builtin_vec_mergel (r2, r6); + r14 = __builtin_vec_mergeh (r3, r7); + r4 = __builtin_vec_mergeh (v2, r14); + v0 = __builtin_vec_mergeh (r0, r4); + union { unsigned char a[16]; A b; } temp; + vector signed char k; + h = __builtin_vec_ld (0, temp.a); + i = __builtin_vec_splat (h, 1); + temp.b.a = c; + k = __builtin_vec_ld (0, (signed char *) temp.a); + j = __builtin_vec_and (i, (vector char) k); + foo (v1, v0, j); + foo (v1, v5, j); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c index 5095d50..312043b 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c @@ -1,8 +1,16 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-options "-O2 -mdejagnu-cpu=power7 -fno-inline-functions" } */ +/* { dg-options "-O2 -mdejagnu-cpu=power7 -fno-inline-functions -fno-ipa-icf" } */ /* { dg-require-effective-target powerpc_vsx } */ +/* PR testsuite/119382 + Note: Added -fno-ipa-icf to disable Interprocedural Identical Code + Folding (ICF). Without this, insert_di_0_v2 is merged with insert_di_0 + due to improved alias analysis introduced in commit r15-7961-gdc47161c1f32c3. + This results in the compiler replacing insert_di_0_v2 with a tail call to + insert_di_0, altering expected test behavior. Disabling ICF ensures correct + execution of the test. */ + /* Test simple extract/insert/slat operations. Make sure all types are supported with various options. */ diff --git a/gcc/testsuite/gcc.target/pru/mov64-subreg-1.c b/gcc/testsuite/gcc.target/pru/mov64-subreg-1.c new file mode 100644 index 0000000..9b60aa0 --- /dev/null +++ b/gcc/testsuite/gcc.target/pru/mov64-subreg-1.c @@ -0,0 +1,9 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os" } */ +/* { dg-final { object-size text == 8 } } */ + + +unsigned test(char a, unsigned long long b) +{ + return b; +} diff --git a/gcc/testsuite/gcc.target/pru/mov64-subreg-2.c b/gcc/testsuite/gcc.target/pru/mov64-subreg-2.c new file mode 100644 index 0000000..146cf94 --- /dev/null +++ b/gcc/testsuite/gcc.target/pru/mov64-subreg-2.c @@ -0,0 +1,8 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os" } */ +/* { dg-final { object-size text == 12 } } */ + +unsigned long long test(void) +{ + return 0xffffffff00000000UL; +} diff --git a/gcc/testsuite/gcc.target/pru/pragma-ctable_entry-2.c b/gcc/testsuite/gcc.target/pru/pragma-ctable_entry-2.c new file mode 100644 index 0000000..a1c707d --- /dev/null +++ b/gcc/testsuite/gcc.target/pru/pragma-ctable_entry-2.c @@ -0,0 +1,22 @@ +/* Test for base addresses with bit 31 set (PR121124). */ + +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +/* -O1 in the options is significant. Without it LBCO/SBCO operations may + not be optimized to the respective instructions. */ + + +#pragma ctable_entry 12 0x80beef00 + +unsigned int +test_ctable (unsigned int val1, unsigned int val2) +{ + ((volatile unsigned short int *)0x80beef00)[0] = val2; + ((volatile unsigned int *)0x80beef00)[val1] = val2; + return ((volatile unsigned int *)0x80beef00)[5]; +} + +/* { dg-final { scan-assembler "sbco\\tr15.b\[012\]?, 12, 0, 2" } } */ +/* { dg-final { scan-assembler "sbco\\tr15.b0, 12, r14, 4" } } */ +/* { dg-final { scan-assembler "lbco\\tr14.b0, 12, 20, 4" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c new file mode 100644 index 0000000..d3d84fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* PR target/120995 ICE unrecognized subword atomic cas */ +/* { dg-options "-O" } */ +/* { dg-add-options riscv_zacas } */ +/* { dg-add-options riscv_zabha } */ + +_Bool b; +void atomic_bool_cmpxchg() +{ + __sync_bool_compare_and_swap(&b, 1, 0); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c index 4cf617d..0dfe816 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c +++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c @@ -9,7 +9,7 @@ /* ** atomic_add_fetch_int_relaxed: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -23,7 +23,7 @@ void atomic_add_fetch_int_relaxed (int* bar, int baz) /* ** atomic_add_fetch_int_acquire: -** 1: +**... ** lr.w.aq\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -37,7 +37,7 @@ void atomic_add_fetch_int_acquire (int* bar, int baz) /* ** atomic_add_fetch_int_release: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -51,7 +51,7 @@ void atomic_add_fetch_int_release (int* bar, int baz) /* ** atomic_add_fetch_int_acq_rel: -** 1: +**... ** lr.w.aq\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -65,7 +65,7 @@ void atomic_add_fetch_int_acq_rel (int* bar, int baz) /* ** atomic_add_fetch_int_seq_cst: -** 1: +**... ** lr.w.aqrl\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c index 3fb16c0..658b040 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c +++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c @@ -9,7 +9,7 @@ /* ** atomic_add_fetch_int_relaxed: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -23,7 +23,7 @@ void atomic_add_fetch_int_relaxed (int* bar, int baz) /* ** atomic_add_fetch_int_acquire: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -37,7 +37,7 @@ void atomic_add_fetch_int_acquire (int* bar, int baz) /* ** atomic_add_fetch_int_release: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -51,7 +51,7 @@ void atomic_add_fetch_int_release (int* bar, int baz) /* ** atomic_add_fetch_int_acq_rel: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -65,7 +65,7 @@ void atomic_add_fetch_int_acq_rel (int* bar, int baz) /* ** atomic_add_fetch_int_seq_cst: -** 1: +**... ** lr.w.aqrl\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) diff --git a/gcc/testsuite/gcc.target/riscv/arch-53.c b/gcc/testsuite/gcc.target/riscv/arch-53.c index 8210978..43ab23a 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-53.c +++ b/gcc/testsuite/gcc.target/riscv/arch-53.c @@ -8,4 +8,4 @@ void foo(){} _ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0" _za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0" _zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0" -_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */ +_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-55.c b/gcc/testsuite/gcc.target/riscv/arch-55.c new file mode 100644 index 0000000..0e8a294 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-55.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g_sha -mabi=lp64d" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2" +"_d2p2_h1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_sha1p0" +"_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0" +"_ssstateen1p0\"" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/arch-56.c b/gcc/testsuite/gcc.target/riscv/arch-56.c new file mode 100644 index 0000000..e075f96 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-56.c @@ -0,0 +1,13 @@ +/* Check whether the second -march overrides the first. */ +/* { dg-do compile { target rv64 } } */ +/* { dg-options "-O3 -march=rv64gc -march=sifive-p670" } */ + +void +foo (char *a, char *b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = b[i] + 1; +} + +/* { dg-final { scan-assembler "vset" } } */ +/* { dg-final { scan-assembler "zvl128b" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-57.c b/gcc/testsuite/gcc.target/riscv/arch-57.c new file mode 100644 index 0000000..08d3761 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-57.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_smdbltrp -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicsr2p0_smdbltrp1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-58.c b/gcc/testsuite/gcc.target/riscv/arch-58.c new file mode 100644 index 0000000..1481da5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-58.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_ssdbltrp -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicsr2p0_ssdbltrp1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-59.c b/gcc/testsuite/gcc.target/riscv/arch-59.c new file mode 100644 index 0000000..511cf22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-59.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_smcntrpmf -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-60.c b/gcc/testsuite/gcc.target/riscv/arch-60.c new file mode 100644 index 0000000..ea599f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-60.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_svbare -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-rva23s.c b/gcc/testsuite/gcc.target/riscv/arch-rva23s.c new file mode 100644 index 0000000..215249d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-rva23s.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rva23s64 -mabi=lp64d" } */ + +void foo(){} + +/* { dg-final { scan-assembler-times ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0" +"_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0" +"_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0" +"_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0" +"_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0" +"_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0" +"_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0" +"_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0\" 1} } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-rvb23s.c b/gcc/testsuite/gcc.target/riscv/arch-rvb23s.c new file mode 100644 index 0000000..aa71f7d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-rvb23s.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rvb23s64 -mabi=lp64d" } */ + +void foo(){} + +/* { dg-final { scan-assembler-times ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0" +"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0" +"_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0" +"_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0" +"_zvl32b1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0" +"_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0\" 1} } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-shlocofideleg.c b/gcc/testsuite/gcc.target/riscv/arch-shlocofideleg.c new file mode 100644 index 0000000..de9f9fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-shlocofideleg.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_shlcofideleg -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-smcsrind.c b/gcc/testsuite/gcc.target/riscv/arch-smcsrind.c new file mode 100644 index 0000000..4d1c104 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-smcsrind.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_smcsrind -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-smrnmi.c b/gcc/testsuite/gcc.target/riscv/arch-smrnmi.c new file mode 100644 index 0000000..8e62540 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-smrnmi.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_smrnmi -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-ssccptr.c b/gcc/testsuite/gcc.target/riscv/arch-ssccptr.c new file mode 100644 index 0000000..902155a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-ssccptr.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_ssccptr -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c b/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c new file mode 100644 index 0000000..901b6bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_sscounterenw -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-sstvala.c b/gcc/testsuite/gcc.target/riscv/arch-sstvala.c new file mode 100644 index 0000000..21ea8a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-sstvala.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_sstvala -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-sstvecd.c b/gcc/testsuite/gcc.target/riscv/arch-sstvecd.c new file mode 100644 index 0000000..e76f7881 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-sstvecd.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_sstvecd -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c b/gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c new file mode 100644 index 0000000..6e151c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_ssu64xl -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c new file mode 100644 index 0000000..479246b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int m0, int m1) { +/* +** foo: +** ... +** addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0) +** ... +*/ + __asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory"); +} diff --git a/gcc/testsuite/gcc.target/riscv/cset-sext-sfb.c b/gcc/testsuite/gcc.target/riscv/cset-sext-sfb.c index 4a8477e..3d46306 100644 --- a/gcc/testsuite/gcc.target/riscv/cset-sext-sfb.c +++ b/gcc/testsuite/gcc.target/riscv/cset-sext-sfb.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ /* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fno-ssa-phiopt -fdump-rtl-ce1" { target { rv32 } } } */ /* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fno-ssa-phiopt -fdump-rtl-ce1" { target { rv64 } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c b/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c index 81ebf5f..15cc3ee 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c @@ -1,7 +1,7 @@ /* Verify proper errors are generated for conflicted interrupt type. */ /* { dg-do compile } */ /* { dg-options "" } */ -void __attribute__ ((interrupt ("user"))) +void __attribute__ ((interrupt ("supervisor"))) foo(void); void __attribute__ ((interrupt ("machine"))) diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-rnmi.c b/gcc/testsuite/gcc.target/riscv/interrupt-rnmi.c new file mode 100644 index 0000000..f340108 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/interrupt-rnmi.c @@ -0,0 +1,11 @@ +/* Verify the return instruction is mnret. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_smrnmi" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_smrnmi" { target { rv64 } } } */ + +void __attribute__ ((interrupt ("rnmi"))) +foo (void) +{ +} + +/* { dg-final { scan-assembler {\mmnret} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-umode.c b/gcc/testsuite/gcc.target/riscv/interrupt-umode.c deleted file mode 100644 index 042abf0..0000000 --- a/gcc/testsuite/gcc.target/riscv/interrupt-umode.c +++ /dev/null @@ -1,8 +0,0 @@ -/* Verify the return instruction is mret. */ -/* { dg-do compile } */ -/* { dg-options "" } */ -void __attribute__ ((interrupt ("user"))) -foo (void) -{ -} -/* { dg-final { scan-assembler {\muret} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c b/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c index 1ee7f6c..ab97b0f 100644 --- a/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c +++ b/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64 -mcmodel=large" } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -mcmodel=large -fno-pie" } */ int foo(int x, int y) { diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-kunminghu.c b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-kunminghu.c new file mode 100644 index 0000000..e3ae65c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-kunminghu.c @@ -0,0 +1,95 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xiangshan-kunminghu" } */ +/* XiangShan Kunminghu => rv64imafdcbvh_sdtrig_sha_shcounterenw_shgatpa + _shlcofideleg_shtvala_shvsatpa_shvstvala_shvstvecd + _smaia_smcsrind_smdbltrp_smmpm_smnpm_smrnmi_smstateen + _ssaia_ssccptr_sscofpmf_sscounterenw_sscsrind_ssdbltrp + _ssnpm_sspm_ssstateen_ssstrict_sstc_sstvala_sstvecd + _ssu64xl_supm_svade_svbare_svinval_svnapot_svpbmt + _za64rs_zacas_zawrs_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zcb + _zcmop_zfa_zfh_zfhmin_zic64b_zicbom_zicbop_zicboz_ziccif + _zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintpause + _zihpm_zimop_zkn_zknd_zkne_zknh_zksed_zksh_zkt_zvbb + _zvfh_zvfhmin_zvkt_zvl128b_zvl32b_zvl64b */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_v) \ + && defined(__riscv_zic64b) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_ziccif) \ + && defined(__riscv_zicclsm) \ + && defined(__riscv_ziccrse) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicond) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zimop) \ + && defined(__riscv_za64rs) \ + && defined(__riscv_zacas) \ + && defined(__riscv_zawrs) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_zbkb) \ + && defined(__riscv_zbkc) \ + && defined(__riscv_zbkx) \ + && defined(__riscv_zcb) \ + && defined(__riscv_zcmop) \ + && defined(__riscv_zfa) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zknd) \ + && defined(__riscv_zkne) \ + && defined(__riscv_zknh) \ + && defined(__riscv_zksed) \ + && defined(__riscv_zksh) \ + && defined(__riscv_zkt) \ + && defined(__riscv_zvbb) \ + && defined(__riscv_zvfh) \ + && defined(__riscv_zvkt) \ + && defined(__riscv_sdtrig) \ + && defined(__riscv_sha) \ + && defined(__riscv_shlcofideleg) \ + && defined(__riscv_smaia) \ + && defined(__riscv_smcsrind) \ + && defined(__riscv_smdbltrp) \ + && defined(__riscv_smmpm) \ + && defined(__riscv_smnpm) \ + && defined(__riscv_smrnmi) \ + && defined(__riscv_smstateen) \ + && defined(__riscv_ssaia) \ + && defined(__riscv_ssccptr) \ + && defined(__riscv_sscofpmf) \ + && defined(__riscv_sscounterenw) \ + && defined(__riscv_sscsrind) \ + && defined(__riscv_ssdbltrp) \ + && defined(__riscv_ssnpm) \ + && defined(__riscv_sspm) \ + && defined(__riscv_ssstrict) \ + && defined(__riscv_sstc) \ + && defined(__riscv_sstvala) \ + && defined(__riscv_sstvecd) \ + && defined(__riscv_ssu64xl) \ + && defined(__riscv_supm) \ + && defined(__riscv_svade) \ + && defined(__riscv_svbare) \ + && defined(__riscv_svinval) \ + && defined(__riscv_svnapot) \ + && defined(__riscv_svpbmt)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c index cb28baf..4ad82a8 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ /* { dg-options "-mcpu=xt-c908" { target { rv64 } } } */ /* XuanTie C908 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c index 1b1ee18..bb9e310 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ /* { dg-options "-mcpu=xt-c908v" { target { rv64 } } } */ /* XuanTie C908v => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c index 1e27665..397e7b1 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ /* { dg-options "-mcpu=xt-c910" { target { rv64 } } } */ /* XuanTie C910 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_xtheadba_ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c index 6a54f09..9e39c9f 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ /* { dg-options "-mcpu=xt-c910v2" { target { rv64 } } } */ /* XuanTie C910v2 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c index 6bcd687..4cce90a 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ /* { dg-options "-mcpu=xt-c920" { target { rv64 } } } */ /* XuanTie c920 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync_xtheadvector */ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c index 36a6267..1f21d07 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ /* { dg-options "-mcpu=xt-c920v2" { target { rv64 } } } */ /* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync_xtheadvdot */ diff --git a/gcc/testsuite/gcc.target/riscv/mipscondmov.c b/gcc/testsuite/gcc.target/riscv/mipscondmov.c new file mode 100644 index 0000000..5485133 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mipscondmov.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32imafd_xmipscmov" { target { rv32 } } } */ +/* { dg-options "-march=rv64imafd_xmipscmov -mabi=lp64d" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +#define MYTEST(name, mytype) \ +mytype test1_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a == b) ? c : d; } \ +mytype test2_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a != b) ? c : d; } \ +mytype test3_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a > b) ? c : d; } \ +mytype test4_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a >= b) ? c : d; } \ +mytype test5_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a < b) ? c : d; } \ +mytype test6_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a <= b) ? c : d; } \ +mytype test7_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a == 1) ? c : d; } \ +mytype test8_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a != 1) ? c : d; } \ +mytype test9_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a > 1) ? c : d; } \ +mytype test10_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a >= 1) ? c : d; } \ +mytype test11_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a < 1) ? c : d; } \ +mytype test12_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a <= 1) ? c : d; } + +MYTEST(1, long) +MYTEST(2, unsigned long) +MYTEST(3, int) +MYTEST(4, unsigned int) +MYTEST(5, short) +MYTEST(6, unsigned short) +MYTEST(7, signed char) +MYTEST(8, unsigned char) + +/* { dg-final { scan-assembler-times "mips.ccmov" 96 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/nozicond-1.c b/gcc/testsuite/gcc.target/riscv/nozicond-1.c new file mode 100644 index 0000000..35ab6fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/nozicond-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-additional-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ + + +long foo1 (long c) { return c >= 0 ? 1 : -1; } +long foo2 (long c) { return c < 0 ? -1 : 1; } + +/* { dg-final { scan-assembler-times {srai\t} 2 } } */ +/* { dg-final { scan-assembler-times {ori\t} 2 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/nozicond-2.c b/gcc/testsuite/gcc.target/riscv/nozicond-2.c new file mode 100644 index 0000000..f705253 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/nozicond-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-additional-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ + + +long foo1 (long c) { return c < 0 ? 1 : -1; } +long foo2 (long c) { return c >= 0 ? -1 : 1; } + +/* We don't support 4->3 splitters, so this fails. We could perhaps + try to catch it in the expander as a special case rather than waiting + for combine. */ +/* { dg-final { scan-assembler-times {srai\t} 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {ori\t} 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {not\t} 2 { xfail *-*-* } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/nozicond-3.c b/gcc/testsuite/gcc.target/riscv/nozicond-3.c new file mode 100644 index 0000000..5116742 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/nozicond-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-additional-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" } } */ + +long foo1 (long n) { return n / 4096; } + +/* { dg-final { scan-assembler-times {srai\t} 2 } } */ +/* { dg-final { scan-assembler-times {srli\t} 1 } } */ +/* { dg-final { scan-assembler-times {add\t} 1 } } */ +/* { dg-final { scan-assembler-not {czero} } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr114512.c b/gcc/testsuite/gcc.target/riscv/pr114512.c index 205071c..70146f5 100644 --- a/gcc/testsuite/gcc.target/riscv/pr114512.c +++ b/gcc/testsuite/gcc.target/riscv/pr114512.c @@ -47,22 +47,6 @@ _Bool my_isxdigit_2a(unsigned char ch) { return 1; } -_Bool my_isxdigit_3(unsigned char ch) { - utype mask1 = 0x7E00FFC0; - if (!((mask1 << (MASK - (ch & MASK))) >> MASK)) - return 0; - - return 1; -} - -_Bool my_isxdigit_3a(unsigned char ch) { - utype mask2 = 0x7E00FFC0; - if (!((mask2 << (MASK - ((ch >> 4) & MASK))) >> MASK)) - return 0; - - return 1; -} - _Bool my_isxdigit_1_parm(unsigned char ch, utype mask1) { if (!((mask1 >> (ch & MASK)) & 1)) return 0; @@ -91,19 +75,5 @@ _Bool my_isxdigit_2a_parm(unsigned char ch, utype mask2) { return 1; } -_Bool my_isxdigit_3_parm(unsigned char ch, utype mask1) { - if (!((mask1 << (MASK - (ch & MASK))) >> MASK)) - return 0; - - return 1; -} - -_Bool my_isxdigit_3a_parm(unsigned char ch, utype mask2) { - if (!((mask2 << (MASK - ((ch >> 4) & MASK))) >> MASK)) - return 0; - - return 1; -} - /* Each test should generate a single bext. */ -/* { dg-final { scan-assembler-times "bext\t" 12 } } */ +/* { dg-final { scan-assembler-times "bext\t" 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr118241-b.cc b/gcc/testsuite/gcc.target/riscv/pr118241-b.cc new file mode 100644 index 0000000..b2cc73f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr118241-b.cc @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64imafdc_zba_zbb_zbs_zicbom_zicbop -mabi=lp64d" } */ + +/* Reduced from libsanitizer::asan_allocator. */ + +enum a { c }; +class d; +struct e { + long count; + void *batch[]; +}; +template <typename> class f { +public: + void g() { + if (e *b = h->i()) + for (; b->count;) + if (6 < b->count) + __builtin_prefetch(b->batch[6]); + } + d *h; +}; +class d { +public: + e *i(); +}; +struct j { + f<int> k; + j(a); + void l() { k.g(); } +} a(c); +void m() { a.l(); } + +/* { dg-final { scan-assembler-times "prefetch.r\t0\\(\[a-x0-9\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr118241.c b/gcc/testsuite/gcc.target/riscv/pr118241.c new file mode 100644 index 0000000..768ea05 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr118241.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! riscv_abi_e } } } */ +/* { dg-options "-march=rv64gc_zicbop" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicbop" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void test1() { __builtin_prefetch((int *)2047); } +void test2() { __builtin_prefetch((int *)1024); } +void test3(char *x) { __builtin_prefetch(&x); } +void test4(char *x) { __builtin_prefetch(&x[2]); } +void test5(char *x) { __builtin_prefetch(&x[1024]); } + +/* So we expect test1, test3 and test4 to be a prefetch + with zero offset. test2 and test5 will have a 1k offset. */ +/* { dg-final { scan-assembler-times "prefetch.r\t0\\(\[a-x0-9\]+\\)" 3 } } */ +/* { dg-final { scan-assembler-times "prefetch.r\t1024" 2 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr119830.c b/gcc/testsuite/gcc.target/riscv/pr119830.c new file mode 100644 index 0000000..8c7cf3b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr119830.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb_zbs -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zbb_zbs -mabi=ilp32" { target { rv32 } } } */ + +#include <stdint.h> +void test(int32_t N, int16_t* A, int16_t val) { + int32_t i, j; + for (i = 0; i < N; i++) { + for (j = 0; j < N; j++) { + A[i * N + j] += val; + } + } +} diff --git a/gcc/testsuite/gcc.target/riscv/pr119971.c b/gcc/testsuite/gcc.target/riscv/pr119971.c index c3f23b0..0d73d4c 100644 --- a/gcc/testsuite/gcc.target/riscv/pr119971.c +++ b/gcc/testsuite/gcc.target/riscv/pr119971.c @@ -1,6 +1,6 @@ /* { dg-do compile { target rv64 } } */ /* { dg-options "-march=rv64gcb -mabi=lp64" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-Oz" "-Os" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Oz" "-Os" } } */ __attribute__ ((noipa)) unsigned foo (unsigned b, unsigned e, unsigned i) diff --git a/gcc/testsuite/gcc.target/riscv/pr120223.c b/gcc/testsuite/gcc.target/riscv/pr120223.c new file mode 100644 index 0000000..d6afd86 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120223.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target { ! riscv_abi_e } } } */ +/* { dg-options "-mcpu=thead-c906" } */ +long foo(long x) { return x ^ 0x80000000; } + diff --git a/gcc/testsuite/gcc.target/riscv/pr120333.c b/gcc/testsuite/gcc.target/riscv/pr120333.c new file mode 100644 index 0000000..17b376f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120333.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-march=rv64gcb -std=gnu23" } */ + +__attribute__ ((noipa)) _Bool +foo (unsigned char ch, unsigned long mask) { + return (mask << (0x3f - (ch & 0x3f))) >> 0x3f; +} + +int main() +{ + if (!foo (0x3f, 0x8000000000000000ul)) + __builtin_abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/riscv/pr120368.c b/gcc/testsuite/gcc.target/riscv/pr120368.c new file mode 100644 index 0000000..4fea8e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120368.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ + +int g; + +int +foo (int s, int v) +{ + __builtin_memset (&g, v >> (s & 31), sizeof(g)); + return g; +} + +int +main () +{ + int x = foo (-16, 0xdffff); + if (x != 0x0d0d0d0d) + __builtin_abort(); + __builtin_exit (0); +} diff --git a/gcc/testsuite/gcc.target/riscv/pr120659.c b/gcc/testsuite/gcc.target/riscv/pr120659.c new file mode 100644 index 0000000..91e6e42 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120659.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=sifive-x280 -mabi=lp64" } */ + +_Float16 f; +void foo() { f /= 3; } diff --git a/gcc/testsuite/gcc.target/riscv/pr120714.c b/gcc/testsuite/gcc.target/riscv/pr120714.c new file mode 100644 index 0000000..dd71a3e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120714.c @@ -0,0 +1,40 @@ +/* Test checking that the backtrace on large frame size with additional + SP shift in the prologue won't broken when compiled with the + -fstack-clash-protection option. */ +/* { dg-do run { target { *-*-linux* } } } */ +/* -O0 does not have enough optimizations. + -O2/-O3 does inline and reduces number of addresses in the backtrace. */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O2" "-O3" } } */ +/* { dg-options "-g -fstack-clash-protection" } */ + +#include <execinfo.h> + +#define MAX 4000 + +void goo () +{ + int addresses; + void *buffer[10]; + + addresses = backtrace (buffer, 10); + if (addresses != 6) + __builtin_abort (); +} + +int foo (int a) +{ + long long A[MAX]; + for (int i = 0; i < MAX; i++) + A[i] = i; + + goo (); + + return A[a % MAX]; +} + +int main () +{ + if (foo (20) != 20) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h new file mode 100644 index 0000000..2de7d7c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h @@ -0,0 +1,45 @@ +#ifndef HAVE_DEFINED_AVG_H +#define HAVE_DEFINED_AVG_H + +#include <stdint.h> + +#if __riscv_xlen == 64 +typedef unsigned __int128 uint128_t; +typedef signed __int128 int128_t; +#endif + +#define DEF_AVG_0(NT, WT, NAME) \ +__attribute__((noinline)) \ +void \ +test_##NAME##_##WT##_##NT##_0(NT * restrict a, NT * restrict b, \ + NT * restrict out, int n) \ +{ \ + for (int i = 0; i < n; i++) { \ + out[i] = (NT)(((WT)a[i] + (WT)b[i]) >> 1); \ + } \ +} +#define DEF_AVG_0_WRAP(NT, WT, NAME) DEF_AVG_0(NT, WT, NAME) + +#define RUN_AVG_0(NT, WT, NAME, a, b, out, n) \ + test_##NAME##_##WT##_##NT##_0(a, b, out, n) +#define RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) \ + RUN_AVG_0(NT, WT, NAME, a, b, out, n) + +#define DEF_AVG_1(NT, WT, NAME) \ +__attribute__((noinline)) \ +void \ +test_##NAME##_##WT##_##NT##_1(NT * restrict a, NT * restrict b, \ + NT * restrict out, int n) \ +{ \ + for (int i = 0; i < n; i++) { \ + out[i] = (NT)(((WT)a[i] + (WT)b[i] + 1) >> 1); \ + } \ +} +#define DEF_AVG_1_WRAP(NT, WT, NAME) DEF_AVG_1(NT, WT, NAME) + +#define RUN_AVG_1(NT, WT, NAME, a, b, out, n) \ + test_##NAME##_##WT##_##NT##_1(a, b, out, n) +#define RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) \ + RUN_AVG_1(NT, WT, NAME, a, b, out, n) + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c new file mode 100644 index 0000000..31d3b43 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int16_t +#define WT int32_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c new file mode 100644 index 0000000..7f30b9e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int16_t +#define WT int64_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c new file mode 100644 index 0000000..2e06d0a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int32_t +#define WT int64_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c new file mode 100644 index 0000000..ca23066 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int64_t +#define WT int128_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c new file mode 100644 index 0000000..dda84a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int8_t +#define WT int16_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c new file mode 100644 index 0000000..dfd2bb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int8_t +#define WT int32_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c new file mode 100644 index 0000000..d1060cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int8_t +#define WT int64_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c new file mode 100644 index 0000000..3d872a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int32_t +#define NT int16_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c new file mode 100644 index 0000000..eda9736 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int64_t +#define NT int16_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c new file mode 100644 index 0000000..21cbb94 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int64_t +#define NT int32_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c new file mode 100644 index 0000000..ee5330c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int128_t +#define NT int64_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c new file mode 100644 index 0000000..fd91b6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int16_t +#define NT int8_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c new file mode 100644 index 0000000..38f4920 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int32_t +#define NT int8_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c new file mode 100644 index 0000000..f65ee15 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int64_t +#define NT int8_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h new file mode 100644 index 0000000..49103f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h @@ -0,0 +1,361 @@ +#ifndef HAVE_DEFINED_AVG_DATA_H +#define HAVE_DEFINED_AVG_DATA_H + +#define N 16 + +#define TEST_AVG_DATA(T, NAME) test_##T##_##NAME##_data +#define TEST_AVG_DATA_WRAP(T, NAME) TEST_AVG_DATA(T, NAME) + +int8_t TEST_AVG_DATA(int8_t, avg_floor)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 4, 4, 4, 4, + }, + }, + { + { + 127, 127, 127, 127, + 127, 127, 127, 127, + -128, -128, -128, -128, + -128, -128, -128, -128, + }, + { + 126, 126, 126, 126, + -2, -2, -2, -2, + 127, 127, 127, 127, + -127, -127, -127, -127, + }, + { + 126, 126, 126, 126, + 62, 62, 62, 62, + -1, -1, -1, -1, + -128, -128, -128, -128, + }, + }, +}; + +int16_t TEST_AVG_DATA(int16_t, avg_floor)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 4, 4, 4, 4, + }, + }, + { + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + }, + { + 32766, 32766, 32766, 32766, + -2, -2, -2, -2, + 32767, 32767, 32767, 32767, + -32767, -32767, -32767, -32767, + }, + { + 32766, 32766, 32766, 32766, + 16382, 16382, 16382, 16382, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + }, + }, +}; + +int32_t TEST_AVG_DATA(int32_t, avg_floor)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 4, 4, 4, 4, + }, + }, + { + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 2147483646, 2147483646, 2147483646, 2147483646, + -2, -2, -2, -2, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483647, -2147483647, -2147483647, -2147483647, + }, + { + 2147483646, 2147483646, 2147483646, 2147483646, + 1073741822, 1073741822, 1073741822, 1073741822, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + }, +}; + +int64_t TEST_AVG_DATA(int64_t, avg_floor)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 4, 4, 4, 4, + }, + }, + { + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + -2ull, -2ull, -2ull, -2ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + }, + { + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + 4611686018427387902ull, 4611686018427387902ull, 4611686018427387902ull, 4611686018427387902ull, + -1ull, -1ull, -1ull, -1ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + }, +}; + +int8_t TEST_AVG_DATA(int8_t, avg_ceil)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 5, 5, 5, 5, + }, + }, + { + { + 127, 127, 127, 127, + 127, 127, 127, 127, + -128, -128, -128, -128, + -128, -128, -128, -128, + }, + { + 126, 126, 126, 126, + -2, -2, -2, -2, + 127, 127, 127, 127, + -127, -127, -127, -127, + }, + { + 127, 127, 127, 127, + 63, 63, 63, 63, + 0, 0, 0, 0, + -127, -127, -127, -127, + }, + }, +}; + +int16_t TEST_AVG_DATA(int16_t, avg_ceil)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 5, 5, 5, 5, + }, + }, + { + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + }, + { + 32766, 32766, 32766, 32766, + -2, -2, -2, -2, + 32767, 32767, 32767, 32767, + -32767, -32767, -32767, -32767, + }, + { + 32767, 32767, 32767, 32767, + 16383, 16383, 16383, 16383, + 0, 0, 0, 0, + -32767, -32767, -32767, -32767, + }, + }, +}; + +int32_t TEST_AVG_DATA(int32_t, avg_ceil)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 5, 5, 5, 5, + }, + }, + { + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 2147483646, 2147483646, 2147483646, 2147483646, + -2, -2, -2, -2, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483647, -2147483647, -2147483647, -2147483647, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 1073741823, 1073741823, 1073741823, 1073741823, + 0, 0, 0, 0, + -2147483647, -2147483647, -2147483647, -2147483647, + }, + }, +}; + +int64_t TEST_AVG_DATA(int64_t, avg_ceil)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 5, 5, 5, 5, + }, + }, + { + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + -2ull, -2ull, -2ull, -2ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 4611686018427387903ull, 4611686018427387903ull, 4611686018427387903ull, 4611686018427387903ull, + 0ull, 0ull, 0ull, 0ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + }, + }, +}; + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c new file mode 100644 index 0000000..fc7943c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int16_t +#define WT int32_t + +DEF_AVG_0_WRAP(NT, WT, avg_floor) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c new file mode 100644 index 0000000..e02e5df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int16_t +#define WT int64_t + +DEF_AVG_0_WRAP(NT, WT, avg_floor) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c new file mode 100644 index 0000000..e36e424 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int32_t +#define WT int64_t + +DEF_AVG_0_WRAP(NT, WT, avg_floor) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c new file mode 100644 index 0000000..3e2d97d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int64_t +#define WT int128_t + +DEF_AVG_0_WRAP(NT, WT, avg_floor) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c new file mode 100644 index 0000000..cdbb299 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int8_t +#define WT int16_t + +DEF_AVG_0_WRAP(NT, WT, avg_floor) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c new file mode 100644 index 0000000..53508b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int8_t +#define WT int32_t + +DEF_AVG_0_WRAP(NT, WT, avg_floor) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c new file mode 100644 index 0000000..9a6d1a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int8_t +#define WT int64_t + +DEF_AVG_0_WRAP(NT, WT, avg_floor) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i32.c new file mode 100644 index 0000000..92239a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int32_t +#define NT int16_t +#define NAME avg_floor + +DEF_AVG_0_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i64.c new file mode 100644 index 0000000..5716c29 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int64_t +#define NT int16_t +#define NAME avg_floor + +DEF_AVG_0_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i32-from-i64.c new file mode 100644 index 0000000..705e091 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i32-from-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int64_t +#define NT int32_t +#define NAME avg_floor + +DEF_AVG_0_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i64-from-i128.c new file mode 100644 index 0000000..91e9809 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i64-from-i128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int128_t +#define NT int64_t +#define NAME avg_floor + +DEF_AVG_0_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i16.c new file mode 100644 index 0000000..abe5c5b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int16_t +#define NT int8_t +#define NAME avg_floor + +DEF_AVG_0_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i32.c new file mode 100644 index 0000000..355b90f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int32_t +#define NT int8_t +#define NAME avg_floor + +DEF_AVG_0_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i64.c new file mode 100644 index 0000000..a9ae96f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int64_t +#define NT int8_t +#define NAME avg_floor + +DEF_AVG_0_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_run.h new file mode 100644 index 0000000..a6bbee9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_run.h @@ -0,0 +1,26 @@ +#ifndef HAVE_DEFINED_AVG_RUN_H +#define HAVE_DEFINED_AVG_RUN_H + +int +main () +{ + unsigned i, k; + NT out[N]; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + NT *a = TEST_DATA[i][0]; + NT *b = TEST_DATA[i][1]; + NT *expect = TEST_DATA[i][2]; + + TEST_RUN (NT, WT, NAME, a, b, out, N); + + for (k = 0; k < N; k++) + if (out[k] != expect[k]) + __builtin_abort (); + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c index 667f457..fab8e79 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie" } */ #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c index 1d8a19c..80bdb68 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie" } */ #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c index 0750d8e..a8be5ed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c @@ -3,13 +3,13 @@ #include "vdiv-template.h" -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvdiv\.vx} 3 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */ -/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfdiv\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfdiv\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 16 "optimized" } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 6 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c index 31b2284..7feee0e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c @@ -3,10 +3,10 @@ #include "vdiv-template.h" -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvdiv\.vx} 3 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */ /* Division by constant is done by calculating a reciprocal and then multiplying. Hence we do not expect 6 vfdivs. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c index 6015af9..766b17f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c @@ -3,13 +3,13 @@ #include "vdiv-template.h" -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdiv\.vx} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vx} 4 } } */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */ -/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfdiv\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfdiv\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 16 "optimized" } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 6 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c index ccaa2f8..c59c664 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c @@ -3,10 +3,10 @@ #include "vdiv-template.h" -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdiv\.vx} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vx} 4 } } */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */ /* Division by constant is done by calculating a reciprocal and then multiplying. Hence we do not expect 6 vfdivs. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c index a87a6c7..10de7c2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c @@ -2,10 +2,10 @@ #include "vrem-template.h" -/* { dg-final { scan-assembler-times {\tvrem\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvrem\.vx} 3 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vx} 3 } } */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvrem\.vx} } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvremu\.vx} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 16 "optimized" } } */ /* { dg-final { scan-assembler-not {\tvmv1r\.v} } } */ /* { dg-final { scan-assembler-not {\tvmv2r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c index 9381695..cf187a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c @@ -3,10 +3,10 @@ #include "vrem-template.h" -/* { dg-final { scan-assembler-times {\tvrem\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvrem\.vx} 4 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vx} 4 } } */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvrem\.vx} } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvremu\.vx} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 16 "optimized" } } */ /* { dg-final { scan-assembler-not {\tvmv1r\.v} } } */ /* { dg-final { scan-assembler-not {\tvmv2r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c index 1b6d50e..28b9235 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie" } */ #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c index 0b22e9a..b048949 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie" } */ #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/param-autovec-mode.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/param-autovec-mode.c new file mode 100644 index 0000000..1ee7eb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/param-autovec-mode.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-mode=V4QI -fdump-tree-vect-details" } */ + +/* By default we will use RVVM1SI mode for vectorization because N is not + known. Check that we use V4QI and create an epilogue when the autovec-mode + param is specified. */ + +void +foo (int *a, int *b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = b[i] + 1; +} + +/* { dg-final { scan-tree-dump "Choosing vector mode V4QI" "vect" } } */ +/* { dg-final { scan-tree-dump "Choosing epilogue vector mode RVVM1SI" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c new file mode 100644 index 0000000..2913f04 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target rvv_zvl256b_ok } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -O2" } */ + +unsigned char a = 5; +long long c[18]; + +static void d () +{ + for (short i = 0; i < 60; i += 65413) + for (char j = 0; j < 18; j++) + { + for (char k = 0; k < 18; k++) + a *= 143; + for (char k = 0; k < 6; k++) + for (char l = 0; l < 18; l++) + c[l] = 0; + } +} + +int main () +{ + d (); + if (a + c[0] != 69) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-1.c new file mode 100644 index 0000000..260e4c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-1.c @@ -0,0 +1,5 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvl256b -mabi=lp64d -O3" } */ + +#include "pr120652.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-2.c new file mode 100644 index 0000000..6f85942 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-2.c @@ -0,0 +1,5 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvl512b -mabi=lp64d -O3" } */ + +#include "pr120652.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-3.c new file mode 100644 index 0000000..9852b5d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-3.c @@ -0,0 +1,5 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvl1024b -mabi=lp64d -O3" } */ + +#include "pr120652.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652.h new file mode 100644 index 0000000..75f2716 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652.h @@ -0,0 +1,31 @@ +#ifndef HAVE_DEFINED_PR120652_H +#define HAVE_DEFINED_PR120652_H + +unsigned n; +char ab[6]; +unsigned ac; +unsigned ae; + +int ak(int bb) { +bd: + for (ac = -17; ac != 16; ac++) { + unsigned be = 95; + if (be <= n) { + char *bg = &ab[1]; + *bg ^= bb; + } else { + ae--; + for (n = 8; 0;) + goto bd; + } + } + return 0; +} + +int main() { + ak(7); + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h index 983c9b4..93c29f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h @@ -345,6 +345,31 @@ vec_sat_s_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_S_ADD_FMT_4_WRAP(T, out, op_1, op_2, N) \ RUN_VEC_SAT_S_ADD_FMT_4(T, out, op_1, op_2, N) +#define DEF_VEC_SAT_S_ADD_IMM_FMT_1(INDEX, T, UT, IMM, MIN, MAX) \ +void __attribute__((noinline)) \ +vec_sat_s_add_imm_##T##_fmt_1##_##INDEX (T *out, T *op_1, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T sum = (UT)x + (UT)IMM; \ + out[i] = (x ^ IMM) < 0 \ + ? sum \ + : (sum ^ x) >= 0 \ + ? sum \ + : x < 0 ? MIN : MAX; \ + } \ +} +#define DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(INDEX, T, UT, IMM, MIN, MAX) \ + DEF_VEC_SAT_S_ADD_IMM_FMT_1(INDEX, T, UT, IMM, MIN, MAX) + +#define RUN_VEC_SAT_S_ADD_IMM_FMT_1(INDEX, T, out, in, expect, IMM, N) \ + vec_sat_s_add_imm_##T##_fmt_1##_##INDEX (out, in, N); \ + VALIDATE_RESULT (out, expect, N) +#define RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(INDEX, T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_S_ADD_IMM_FMT_1(INDEX, T, out, in, expect, IMM, N) + /******************************************************************************/ /* Saturation Sub (Unsigned and Signed) */ /******************************************************************************/ @@ -360,6 +385,8 @@ vec_sat_u_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = (x - y) & (-(T)(x >= y)); \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_1(T) #define DEF_VEC_SAT_U_SUB_FMT_2(T) \ void __attribute__((noinline)) \ @@ -373,6 +400,8 @@ vec_sat_u_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = (x - y) & (-(T)(x > y)); \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_2(T) #define DEF_VEC_SAT_U_SUB_FMT_3(T) \ void __attribute__((noinline)) \ @@ -386,6 +415,8 @@ vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = x > y ? x - y : 0; \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_3(T) #define DEF_VEC_SAT_U_SUB_FMT_4(T) \ void __attribute__((noinline)) \ @@ -399,6 +430,8 @@ vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = x >= y ? x - y : 0; \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_4(T) #define DEF_VEC_SAT_U_SUB_FMT_5(T) \ void __attribute__((noinline)) \ @@ -412,6 +445,8 @@ vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = x < y ? 0 : x - y; \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_5(T) #define DEF_VEC_SAT_U_SUB_FMT_6(T) \ void __attribute__((noinline)) \ @@ -425,6 +460,8 @@ vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = x <= y ? 0 : x - y; \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_6(T) #define DEF_VEC_SAT_U_SUB_FMT_7(T) \ void __attribute__((noinline)) \ @@ -440,6 +477,8 @@ vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = ret & (T)(overflow - 1); \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_7(T) #define DEF_VEC_SAT_U_SUB_FMT_8(T) \ void __attribute__((noinline)) \ @@ -455,6 +494,8 @@ vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = ret & (T)-(!overflow); \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_8(T) #define DEF_VEC_SAT_U_SUB_FMT_9(T) \ void __attribute__((noinline)) \ @@ -470,6 +511,8 @@ vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = overflow ? 0 : ret; \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_9(T) #define DEF_VEC_SAT_U_SUB_FMT_10(T) \ void __attribute__((noinline)) \ @@ -485,6 +528,42 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = !overflow ? ret : 0; \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_10(T) + +#define DEF_VEC_SAT_U_SUB_FMT_11(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_11 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + T ret; \ + T overflow = __builtin_sub_overflow (x, y, &ret); \ + out[i] = overflow ? 0 : ret; \ + } \ +} +#define DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_11(T) + +#define DEF_VEC_SAT_U_SUB_FMT_12(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_12 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + T ret; \ + T overflow = __builtin_sub_overflow (x, y, &ret); \ + out[i] = !overflow ? ret : 0; \ + } \ +} +#define DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_12(T) #define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \ void __attribute__((noinline)) \ @@ -644,33 +723,63 @@ vec_sat_s_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_2(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_2(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_2(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_3(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_3(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_3(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_4(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_4(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_4(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_5(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_5(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_5(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_6(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_6(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_6(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_7(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_7(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_7(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_8(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_8(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_8(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_9(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_9(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_9(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_10(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) + +#define RUN_VEC_SAT_U_SUB_FMT_11(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_11(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11(T, out, op_1, op_2, N) + +#define RUN_VEC_SAT_U_SUB_FMT_12(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_12(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \ vec_sat_u_sub_##T1##_##T2##_fmt_zip(x, b, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h index ec4d64c..7647439 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h @@ -744,6 +744,498 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_sub_imm)[][2][N] = }, }; +uint8_t TEST_UNARY_DATA(uint8_t, ussub)[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +uint16_t TEST_UNARY_DATA(uint16_t, ussub)[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +uint32_t TEST_UNARY_DATA(uint32_t, ussub)[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +uint64_t TEST_UNARY_DATA(uint64_t, ussub)[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +int8_t TEST_UNARY_DATA(int8_t, sat_s_add_imm)[][2][N] = +{ + { /* For add imm -128 */ + { + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + }, + { + -128, -128, -28, -1, + -128, -128, -28, -1, + -128, -128, -28, -1, + -128, -128, -28, -1, + }, + }, + { /* For add imm 0 */ + { + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + }, + { + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + }, + }, + { /* For add imm 1 */ + { + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + }, + { + -127, 1, 101, 127, + -127, 1, 101, 127, + -127, 1, 101, 127, + -127, 1, 101, 127, + }, + }, + { /* For add imm 127 */ + { + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + }, + { + -1, 127, 127, 127, + -1, 127, 127, 127, + -1, 127, 127, 127, + -1, 127, 127, 127, + }, + }, +}; + +int16_t TEST_UNARY_DATA(int16_t, sat_s_add_imm)[][2][N] = +{ + { /* For add imm -32768 */ + { + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + }, + { + -32768, -32768, -32668, -1, + -32768, -32768, -32668, -1, + -32768, -32768, -32668, -1, + -32768, -32768, -32668, -1, + }, + }, + { /* For add imm 0 */ + { + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + }, + { + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + }, + }, + { /* For add imm 1 */ + { + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + }, + { + -32767, 1, 101, 32767, + -32767, 1, 101, 32767, + -32767, 1, 101, 32767, + -32767, 1, 101, 32767, + }, + }, + { /* For add imm 32767 */ + { + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + }, + { + -1, 32767, 32767, 32767, + -1, 32767, 32767, 32767, + -1, 32767, 32767, 32767, + -1, 32767, 32767, 32767, + }, + }, +}; + +int32_t TEST_UNARY_DATA(int32_t, sat_s_add_imm)[][2][N] = +{ + { /* For add imm -2147483648 */ + { + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + }, + { + -2147483648, -2147483648, -2147483548, -1, + -2147483648, -2147483648, -2147483548, -1, + -2147483648, -2147483648, -2147483548, -1, + -2147483648, -2147483648, -2147483548, -1, + }, + }, + { /* For add imm 0 */ + { + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + }, + { + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + }, + }, + { /* For add imm 1 */ + { + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + }, + { + -2147483647, 1, 101, 2147483647, + -2147483647, 1, 101, 2147483647, + -2147483647, 1, 101, 2147483647, + -2147483647, 1, 101, 2147483647, + }, + }, + { /* For add imm 2147483647 */ + { + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + }, + { + -1, 2147483647, 2147483647, 2147483647, + -1, 2147483647, 2147483647, 2147483647, + -1, 2147483647, 2147483647, 2147483647, + -1, 2147483647, 2147483647, 2147483647, + }, + }, +}; + +int64_t TEST_UNARY_DATA(int64_t, sat_s_add_imm)[][2][N] = +{ + { /* For add imm -9223372036854775808ll */ + { + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + }, + { + INT64_MIN, INT64_MIN, -9223372036854775708ll, -1, + INT64_MIN, INT64_MIN, -9223372036854775708ll, -1, + INT64_MIN, INT64_MIN, -9223372036854775708ll, -1, + INT64_MIN, INT64_MIN, -9223372036854775708ll, -1, + }, + }, + { /* For add imm 0 */ + { + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + }, + { + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + }, + }, + { /* For add imm 1 */ + { + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + }, + { + -INT64_MAX, 1, 101, INT64_MAX, + -INT64_MAX, 1, 101, INT64_MAX, + -INT64_MAX, 1, 101, INT64_MAX, + -INT64_MAX, 1, 101, INT64_MAX, + }, + }, + { /* For add imm 9223372036854775807ll */ + { + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + }, + { + -1, INT64_MAX, INT64_MAX, INT64_MAX, + -1, INT64_MAX, INT64_MAX, INT64_MAX, + -1, INT64_MAX, INT64_MAX, INT64_MAX, + -1, INT64_MAX, INT64_MAX, INT64_MAX, + }, + }, +}; + #define TEST_BINARY_DATA_NAME(T1, T2, NAME) test_bin_##T1##_##T2##_##NAME##_data #define TEST_BINARY_DATA_NAME_WRAP(T1, T2, NAME) \ TEST_BINARY_DATA_NAME(T1, T2, NAME) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c new file mode 100644 index 0000000..396c741 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, 9, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c new file mode 100644 index 0000000..da9e538 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, 9, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c new file mode 100644 index 0000000..e9af1a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int64_t, uint64_t, 9, INT64_MIN, INT64_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c new file mode 100644 index 0000000..66b9d7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, 9, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i16.c new file mode 100644 index 0000000..fbfa4e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i16.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T int16_t +#define RUN(INDEX, T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP (INDEX, T, out, in, expect, IMM, N) + +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(0, int16_t, uint16_t, -32768, INT16_MIN, INT16_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(1, int16_t, uint16_t, 0, INT16_MIN, INT16_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(2, int16_t, uint16_t, 1, INT16_MIN, INT16_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(3, int16_t, uint16_t, 32767, INT16_MIN, INT16_MAX) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_s_add_imm); + + RUN (0, T, out, d[0][0], d[0][1], -32768, N); + RUN (1, T, out, d[1][0], d[1][1], 0, N); + RUN (2, T, out, d[2][0], d[2][1], 1, N); + RUN (3, T, out, d[3][0], d[3][1], 32767, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i32.c new file mode 100644 index 0000000..5f1763c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i32.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T int32_t +#define RUN(INDEX, T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP (INDEX, T, out, in, expect, IMM, N) + +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(0, int32_t, uint32_t, -2147483648, INT32_MIN, INT32_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(1, int32_t, uint32_t, 0, INT32_MIN, INT32_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(2, int32_t, uint32_t, 1, INT32_MIN, INT32_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(3, int32_t, uint32_t, 2147483647, INT32_MIN, INT32_MAX) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_s_add_imm); + + RUN (0, T, out, d[0][0], d[0][1], -2147483648, N); + RUN (1, T, out, d[1][0], d[1][1], 0, N); + RUN (2, T, out, d[2][0], d[2][1], 1, N); + RUN (3, T, out, d[3][0], d[3][1], 2147483647, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i64.c new file mode 100644 index 0000000..435eb1b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i64.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T int64_t +#define RUN(INDEX, T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP (INDEX, T, out, in, expect, IMM, N) + +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(0, int64_t, uint64_t, INT64_MIN, INT64_MIN, INT64_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(1, int64_t, uint64_t, 0, INT64_MIN, INT64_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(2, int64_t, uint64_t, 1, INT64_MIN, INT64_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(3, int64_t, uint64_t, INT64_MAX, INT64_MIN, INT64_MAX) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_s_add_imm); + + RUN (0, T, out, d[0][0], d[0][1], INT64_MIN, N); + RUN (1, T, out, d[1][0], d[1][1], 0, N); + RUN (2, T, out, d[2][0], d[2][1], 1, N); + RUN (3, T, out, d[3][0], d[3][1], INT64_MAX, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i8.c new file mode 100644 index 0000000..535e873 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i8.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T int8_t +#define RUN(INDEX, T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP (INDEX, T, out, in, expect, IMM, N) + +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(0, int8_t, uint8_t, -128, INT8_MIN, INT8_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(1, int8_t, uint8_t, 0, INT8_MIN, INT8_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(2, int8_t, uint8_t, 1, INT8_MIN, INT8_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(3, int8_t, uint8_t, 127, INT8_MIN, INT8_MAX) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_s_add_imm); + + RUN (0, T, out, d[0][0], d[0][1], -128, N); + RUN (1, T, out, d[1][0], d[1][1], 0, N); + RUN (2, T, out, d[2][0], d[2][1], 1, N); + RUN (3, T, out, d[3][0], d[3][1], 127, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i16.c new file mode 100644 index 0000000..26e96fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, -32769, INT16_MIN, INT16_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1(1, int16_t, uint16_t, 32768, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i32.c new file mode 100644 index 0000000..519e72c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, -2147483649, INT32_MIN, INT32_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1(1, int32_t, uint32_t, 2147483648, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i8.c new file mode 100644 index 0000000..2b0af52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, 200, INT8_MIN, INT8_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1(1, int8_t, uint8_t, -300, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c new file mode 100644 index 0000000..57da9e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c new file mode 100644 index 0000000..b5264a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c new file mode 100644 index 0000000..1a68b5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint64_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c new file mode 100644 index 0000000..a1c5c19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c new file mode 100644 index 0000000..fd987e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c new file mode 100644 index 0000000..bc380fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c new file mode 100644 index 0000000..c03163f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint64_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c new file mode 100644 index 0000000..91e1909 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c index 97e5040..5878c5b6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 -DEF_VEC_SAT_U_SUB_FMT_1(T) +DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c index a5428c4..f74979f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 -DEF_VEC_SAT_U_SUB_FMT_1(T) +DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c index bdb65d9..1250e5b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 -DEF_VEC_SAT_U_SUB_FMT_1(T) +DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c index 3fe5fe3..a2a77dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c @@ -2,74 +2,15 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 -DEF_VEC_SAT_U_SUB_FMT_1(T) +DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c index 0f4129c..19c8fa0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 -DEF_VEC_SAT_U_SUB_FMT_10(T) +DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c index 8b995eb..ada136f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 -DEF_VEC_SAT_U_SUB_FMT_10(T) +DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c index d12d981..488c158 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 -DEF_VEC_SAT_U_SUB_FMT_10(T) +DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c index 384ef3e..127c27a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 -DEF_VEC_SAT_U_SUB_FMT_10(T) +DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c new file mode 100644 index 0000000..4b49467 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint16_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c new file mode 100644 index 0000000..80b55ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint32_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c new file mode 100644 index 0000000..6a89d0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint64_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c new file mode 100644 index 0000000..974493e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint8_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c new file mode 100644 index 0000000..28778b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint16_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c new file mode 100644 index 0000000..936a39a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint32_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c new file mode 100644 index 0000000..b8fa65b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint64_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c new file mode 100644 index 0000000..6bff1e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint8_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c index 5cf08ac..45bef88 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 -DEF_VEC_SAT_U_SUB_FMT_2(T) +DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c index 85c8454..6d8a653 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 -DEF_VEC_SAT_U_SUB_FMT_2(T) +DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c index 67d5ac5..0132d46 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 -DEF_VEC_SAT_U_SUB_FMT_2(T) +DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c index 809f07f..425f86f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 -DEF_VEC_SAT_U_SUB_FMT_2(T) +DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c index 57839a9..97a8e08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 -DEF_VEC_SAT_U_SUB_FMT_3(T) +DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c index ffb0dcc..9124899 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 -DEF_VEC_SAT_U_SUB_FMT_3(T) +DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c index 3966677..1e54ede 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 -DEF_VEC_SAT_U_SUB_FMT_3(T) +DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c index e795f62..d8d53b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 -DEF_VEC_SAT_U_SUB_FMT_3(T) +DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c index 0eecf82..b293823 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 -DEF_VEC_SAT_U_SUB_FMT_4(T) +DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c index 1d0d16b..f0f1c4f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 -DEF_VEC_SAT_U_SUB_FMT_4(T) +DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c index 98fdfa2..27c28e2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 -DEF_VEC_SAT_U_SUB_FMT_4(T) +DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c index 18a887d..7911825 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 -DEF_VEC_SAT_U_SUB_FMT_4(T) +DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c index ce44c04..6ae7b36 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 -DEF_VEC_SAT_U_SUB_FMT_5(T) +DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c index 36ae7b3..4e6b9e6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 -DEF_VEC_SAT_U_SUB_FMT_5(T) +DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c index 7b40ffd..6b26913 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 -DEF_VEC_SAT_U_SUB_FMT_5(T) +DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c index 3b0807f..2bd28cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 -DEF_VEC_SAT_U_SUB_FMT_5(T) +DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c index e972078..69b0be9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 -DEF_VEC_SAT_U_SUB_FMT_6(T) +DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c index 54e2848..2450586 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 -DEF_VEC_SAT_U_SUB_FMT_6(T) +DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c index 33f3be0..0b97910 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 -DEF_VEC_SAT_U_SUB_FMT_6(T) +DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c index 1376038..afb23f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 -DEF_VEC_SAT_U_SUB_FMT_6(T) +DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c index 83241ef..0466d4c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 -DEF_VEC_SAT_U_SUB_FMT_7(T) +DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c index f20bb21..14b8701 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 -DEF_VEC_SAT_U_SUB_FMT_7(T) +DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c index 4ad0afd..7e0afd8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 -DEF_VEC_SAT_U_SUB_FMT_7(T) +DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c index 3b33b13..40b1a6a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 -DEF_VEC_SAT_U_SUB_FMT_7(T) +DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c index b212550..bd33048 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 -DEF_VEC_SAT_U_SUB_FMT_8(T) +DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c index 1fb707c..36f78f5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 -DEF_VEC_SAT_U_SUB_FMT_8(T) +DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c index da8c09c..3bc5d5d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 -DEF_VEC_SAT_U_SUB_FMT_8(T) +DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c index 647607f..3964d1b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 -DEF_VEC_SAT_U_SUB_FMT_8(T) +DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c index 9bb0664..4c0809a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 -DEF_VEC_SAT_U_SUB_FMT_9(T) +DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c index f142b8b..3e700bd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 -DEF_VEC_SAT_U_SUB_FMT_9(T) +DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c index 574b91a..81b8dc8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 -DEF_VEC_SAT_U_SUB_FMT_9(T) +DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c index 2c8ee42..8bc52ae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 -DEF_VEC_SAT_U_SUB_FMT_9(T) +DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c index 2261872..b32907a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c @@ -6,5 +6,5 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ /* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c index 4250567..344080c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c @@ -6,5 +6,5 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ /* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c index 656aad7..492c316 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c @@ -6,5 +6,5 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ /* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c index 4dc5703..0fa1ea0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c @@ -72,7 +72,7 @@ f_vnx128qi (int8_t *out) *(vnx128qi *) out = v; } -/* { dg-final { scan-assembler-times {vmv.v.x\tv[0-9]+,\s*[a-x0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {vmv.v.x\tv[0-9]+,\s*[a-x0-9]+} 7 } } */ /* { dg-final { scan-assembler-times {slli\t[a-x0-9]+,\s*[a-x0-9]+,\s*8} 6 } } */ /* { dg-final { scan-assembler-times {or\t[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+} 6 } } */ /* { dg-final { scan-assembler-times {vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c index 30e60d5..4920fa6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c @@ -25,9 +25,8 @@ DEF_AVG_FLOOR (uint8_t, uint16_t, 512) DEF_AVG_FLOOR (uint8_t, uint16_t, 1024) DEF_AVG_FLOOR (uint8_t, uint16_t, 2048) -/* { dg-final { scan-assembler-times {vwadd\.vv} 10 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 10 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 10 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 20 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 10 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 10 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c index 33df429..c6a120b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c @@ -23,9 +23,8 @@ DEF_AVG_FLOOR (uint16_t, uint32_t, 256) DEF_AVG_FLOOR (uint16_t, uint32_t, 512) DEF_AVG_FLOOR (uint16_t, uint32_t, 1024) -/* { dg-final { scan-assembler-times {vwadd\.vv} 9 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 9 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 9 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 18 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 9 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 9 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c index 9058905..2838c1e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c @@ -21,9 +21,8 @@ DEF_AVG_FLOOR (uint32_t, uint64_t, 128) DEF_AVG_FLOOR (uint32_t, uint64_t, 256) DEF_AVG_FLOOR (uint32_t, uint64_t, 512) -/* { dg-final { scan-assembler-times {vwadd\.vv} 8 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 8 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 8 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 16 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 8 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 8 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c index 8d106aa..986a0ff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c @@ -25,11 +25,9 @@ DEF_AVG_CEIL (uint8_t, uint16_t, 512) DEF_AVG_CEIL (uint8_t, uint16_t, 1024) DEF_AVG_CEIL (uint8_t, uint16_t, 2048) -/* { dg-final { scan-assembler-times {vwadd\.vv} 10 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 10 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 10 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 20 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 10 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 10 } } */ -/* { dg-final { scan-assembler-times {vadd\.vi} 10 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c index 981abd5..c450f80 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c @@ -23,11 +23,9 @@ DEF_AVG_CEIL (uint16_t, uint32_t, 256) DEF_AVG_CEIL (uint16_t, uint32_t, 512) DEF_AVG_CEIL (uint16_t, uint32_t, 1024) -/* { dg-final { scan-assembler-times {vwadd\.vv} 9 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 9 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 9 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 18 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 9 } } */ -/* { dg-final { scan-assembler-times {vadd\.vi} 9 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 9 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c index bfe4ba3..3473e19 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c @@ -21,11 +21,9 @@ DEF_AVG_CEIL (uint16_t, uint32_t, 128) DEF_AVG_CEIL (uint16_t, uint32_t, 256) DEF_AVG_CEIL (uint16_t, uint32_t, 512) -/* { dg-final { scan-assembler-times {vwadd\.vv} 8 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 8 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 8 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 16 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 8 } } */ -/* { dg-final { scan-assembler-times {vadd\.vi} 8 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 8 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c new file mode 100644 index 0000000..811f26c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_0 (_Float16, +, +, add) +DEF_VF_MULOP_CASE_0 (_Float16, -, +, sub) +DEF_VF_MULOP_CASE_0 (_Float16, +, -, nadd) +DEF_VF_MULOP_CASE_0 (_Float16, -, -, nsub) +DEF_VF_MULOP_ACC_CASE_0 (_Float16, +, +, acc) +DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, +, sac) +DEF_VF_MULOP_ACC_CASE_0 (_Float16, +, -, nacc) +DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, -, nsac) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac) + +/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmsub.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c new file mode 100644 index 0000000..ca82ead --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_0 (float, +, +, add) +DEF_VF_MULOP_CASE_0 (float, -, +, sub) +DEF_VF_MULOP_CASE_0 (float, +, -, nadd) +DEF_VF_MULOP_CASE_0 (float, -, -, nsub) +DEF_VF_MULOP_ACC_CASE_0 (float, +, +, acc) +DEF_VF_MULOP_ACC_CASE_0 (float, -, +, sac) +DEF_VF_MULOP_ACC_CASE_0 (float, +, -, nacc) +DEF_VF_MULOP_ACC_CASE_0 (float, -, -, nsac) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac) + +/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmsub.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c new file mode 100644 index 0000000..4de038c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_0 (double, +, +, add) +DEF_VF_MULOP_CASE_0 (double, -, +, sub) +DEF_VF_MULOP_CASE_0 (double, +, -, nadd) +DEF_VF_MULOP_CASE_0 (double, -, -, nsub) +DEF_VF_MULOP_ACC_CASE_0 (double, +, +, acc) +DEF_VF_MULOP_ACC_CASE_0 (double, -, +, sac) +DEF_VF_MULOP_ACC_CASE_0 (double, +, -, nacc) +DEF_VF_MULOP_ACC_CASE_0 (double, -, -, nsac) + +/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmsub.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c new file mode 100644 index 0000000..3a39303 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=1" } */ + +#include "vf-1-f16.c" + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-times {fcvt.s.h} 4 } } */ +/* { dg-final { scan-assembler-times {vfmv.v.f} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c new file mode 100644 index 0000000..b4618ba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=1" } */ + +#include "vf-1-f32.c" + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-times {fcvt.d.s} 4 } } */ +/* { dg-final { scan-assembler-times {vfmv.v.f} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c new file mode 100644 index 0000000..a2ac67e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=1" } */ + +#include "vf-1-f64.c" + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c new file mode 100644 index 0000000..58afaa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_1 (_Float16, +, +, add, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (_Float16, -, +, sub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (_Float16, +, -, nadd, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (_Float16, -, -, nsub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, +, acc, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, +, sac, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, -, nacc, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, -, nsac, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac) + +/* { dg-final { scan-assembler {vfmadd.vf} } } */ +/* { dg-final { scan-assembler {vfmsub.vf} } } */ +/* { dg-final { scan-assembler {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler {vfmacc.vf} } } */ +/* { dg-final { scan-assembler {vfmsac.vf} } } */ +/* { dg-final { scan-assembler {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwnmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c new file mode 100644 index 0000000..0e95774 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_1 (float, +, +, add, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (float, -, +, sub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (float, +, -, nadd, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (float, -, -, nsub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_ACC_CASE_1 (float, +, +, acc, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (float, -, +, sac, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (float, +, -, nacc, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (float, -, -, nsac, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac) + +/* { dg-final { scan-assembler {vfmadd.vf} } } */ +/* { dg-final { scan-assembler {vfmsub.vf} } } */ +/* { dg-final { scan-assembler {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler {vfmacc.vf} } } */ +/* { dg-final { scan-assembler {vfmsac.vf} } } */ +/* { dg-final { scan-assembler {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwnmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c new file mode 100644 index 0000000..71bd7e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_1 (double, +, +, add, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (double, -, +, sub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (double, +, -, nadd, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (double, -, -, nsub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_ACC_CASE_1 (double, +, +, acc, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (double, -, +, sac, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (double, +, -, nacc, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (double, -, -, nsac, VF_MULOP_ACC_BODY_X128) + +/* { dg-final { scan-assembler {vfmadd.vf} } } */ +/* { dg-final { scan-assembler {vfmsub.vf} } } */ +/* { dg-final { scan-assembler {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler {vfmacc.vf} } } */ +/* { dg-final { scan-assembler {vfmsac.vf} } } */ +/* { dg-final { scan-assembler {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler {vfnmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c new file mode 100644 index 0000000..559df6c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf-3-f16.c" + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler {fcvt.s.h} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c new file mode 100644 index 0000000..03f9c5a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf-3-f32.c" + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler {fcvt.d.s} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c new file mode 100644 index 0000000..d71bdde --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf-3-f64.c" + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h new file mode 100644 index 0000000..b1a324f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h @@ -0,0 +1,162 @@ +#ifndef HAVE_DEFINED_VF_MULOP_H +#define HAVE_DEFINED_VF_MULOP_H + +#include <stdint.h> + +#define DEF_VF_MULOP_CASE_0(T, OP, NEG, NAME) \ + void test_vf_mulop_##NAME##_##T##_case_0 (T *restrict out, T *restrict in, \ + T f, unsigned n) \ + { \ + for (unsigned i = 0; i < n; i++) \ + out[i] = NEG (f * out[i] OP in[i]); \ + } +#define DEF_VF_MULOP_CASE_0_WRAP(T, OP, NEG, NAME) \ + DEF_VF_MULOP_CASE_0 (T, OP, NEG, NAME) +#define RUN_VF_MULOP_CASE_0(T, NAME, out, in, x, n) \ + test_vf_mulop_##NAME##_##T##_case_0(out, in, x, n) +#define RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) \ + RUN_VF_MULOP_CASE_0(T, NAME, out, in, x, n) + +#define DEF_VF_MULOP_ACC_CASE_0(T, OP, NEG, NAME) \ + T test_vf_mulop_acc_##NAME##_##T##_case_0 (T *restrict out, T *restrict in, \ + T f, unsigned n) \ + { \ + unsigned i; \ + for (i = 0; i < n; i++) \ + out[i] = NEG (f * in[i] OP out[i]); \ + /* Ensure that we get acc rather than add by reusing the multiplicand. */ \ + return in[i - 1]; \ + } +#define DEF_VF_MULOP_ACC_CASE_0_WRAP(T, OP, NEG, NAME) \ + DEF_VF_MULOP_ACC_CASE_0 (T, OP, NEG, NAME) +#define RUN_VF_MULOP_ACC_CASE_0(T, NAME, out, in, x, n) \ + test_vf_mulop_acc_##NAME##_##T##_case_0 (out, in, x, n) +#define RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, out, in, x, n) \ + RUN_VF_MULOP_ACC_CASE_0 (T, NAME, out, in, x, n) + +#define DEF_VF_MULOP_WIDEN_CASE_0(T1, T2, OP, NEG, NAME) \ + void test_vf_mulop_widen_##NAME##_##T1##_case_0 (T2 *restrict out, \ + T1 *restrict in, \ + T1 *restrict f, unsigned n) \ + { \ + for (unsigned i = 0; i < n; i++) \ + out[i] = NEG ((T2) * f * (T2) in[i] OP out[i]); \ + } +#define DEF_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, OP, NEG, NAME) \ + DEF_VF_MULOP_WIDEN_CASE_0 (T1, T2, OP, NEG, NAME) +#define RUN_VF_MULOP_WIDEN_CASE_0(T1, T2, NAME, out, in, x, n) \ + test_vf_mulop_widen_##NAME##_##T1##_case_0 (out, in, x, n) +#define RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, x, n) \ + RUN_VF_MULOP_WIDEN_CASE_0 (T1, T2, NAME, out, in, x, n) + +#define VF_MULOP_BODY(op, neg) \ + out[k + 0] = neg (tmp * out[k + 0] op in[k + 0]); \ + out[k + 1] = neg (tmp * out[k + 1] op in[k + 1]); \ + k += 2; + +#define VF_MULOP_BODY_X4(op, neg) \ + VF_MULOP_BODY (op, neg) \ + VF_MULOP_BODY (op, neg) + +#define VF_MULOP_BODY_X8(op, neg) \ + VF_MULOP_BODY_X4 (op, neg) \ + VF_MULOP_BODY_X4 (op, neg) + +#define VF_MULOP_BODY_X16(op, neg) \ + VF_MULOP_BODY_X8 (op, neg) \ + VF_MULOP_BODY_X8 (op, neg) + +#define VF_MULOP_BODY_X32(op, neg) \ + VF_MULOP_BODY_X16 (op, neg) \ + VF_MULOP_BODY_X16 (op, neg) + +#define VF_MULOP_BODY_X64(op, neg) \ + VF_MULOP_BODY_X32 (op, neg) \ + VF_MULOP_BODY_X32 (op, neg) + +#define VF_MULOP_BODY_X128(op, neg) \ + VF_MULOP_BODY_X64 (op, neg) \ + VF_MULOP_BODY_X64 (op, neg) + +#define DEF_VF_MULOP_CASE_1(T, OP, NEG, NAME, BODY) \ + void test_vf_mulop_##NAME##_##T##_case_1 (T *restrict out, T *restrict in, \ + T x, unsigned n) \ + { \ + unsigned k = 0; \ + T tmp = x + 3; \ + \ + while (k < n) \ + { \ + tmp = tmp * 0x3f; \ + BODY (OP, NEG) \ + } \ + } +#define DEF_VF_MULOP_CASE_1_WRAP(T, OP, NEG, NAME, BODY) \ + DEF_VF_MULOP_CASE_1 (T, OP, NEG, NAME, BODY) + +#define VF_MULOP_ACC_BODY(op, neg) \ + out[k + 0] = neg (tmp * in[k + 0] op out[k + 1]); \ + out[k + 1] = neg (tmp * in[k + 1] op out[k + 1]); \ + k += 2; + +#define VF_MULOP_ACC_BODY_X4(op, neg) \ + VF_MULOP_ACC_BODY (op, neg) \ + VF_MULOP_ACC_BODY (op, neg) + +#define VF_MULOP_ACC_BODY_X8(op, neg) \ + VF_MULOP_ACC_BODY_X4 (op, neg) \ + VF_MULOP_ACC_BODY_X4 (op, neg) + +#define VF_MULOP_ACC_BODY_X16(op, neg) \ + VF_MULOP_ACC_BODY_X8 (op, neg) \ + VF_MULOP_ACC_BODY_X8 (op, neg) + +#define VF_MULOP_ACC_BODY_X32(op, neg) \ + VF_MULOP_ACC_BODY_X16 (op, neg) \ + VF_MULOP_ACC_BODY_X16 (op, neg) + +#define VF_MULOP_ACC_BODY_X64(op, neg) \ + VF_MULOP_ACC_BODY_X32 (op, neg) \ + VF_MULOP_ACC_BODY_X32 (op, neg) + +#define VF_MULOP_ACC_BODY_X128(op, neg) \ + VF_MULOP_ACC_BODY_X64 (op, neg) \ + VF_MULOP_ACC_BODY_X64 (op, neg) + +#define VF_MULOP_ACC_BODY_X256(op, neg) \ + VF_MULOP_ACC_BODY_X128 (op, neg) \ + VF_MULOP_ACC_BODY_X128 (op, neg) + +#define DEF_VF_MULOP_ACC_CASE_1(T, OP, NEG, NAME, BODY) \ + void test_vf_mulop_acc_##NAME##_##T##_case_1 (T *restrict out, \ + T *restrict in, T x, \ + unsigned n) \ + { \ + unsigned k = 0; \ + T tmp = x + 3; \ + \ + while (k < n) \ + { \ + tmp = tmp * 0x3f; \ + BODY (OP, NEG) \ + } \ + } +#define DEF_VF_MULOP_ACC_CASE_1_WRAP(T, OP, NEG, NAME, BODY) \ + DEF_VF_MULOP_ACC_CASE_1 (T, OP, NEG, NAME, BODY) + +#define DEF_VF_MULOP_WIDEN_CASE_1(TYPE1, TYPE2, OP, NEG, NAME) \ + void test_vf_mulop_widen_##NAME##_##TYPE1##_##TYPE2##_case_1 ( \ + TYPE2 *__restrict dst, TYPE2 *__restrict dst2, TYPE2 *__restrict dst3, \ + TYPE2 *__restrict dst4, TYPE1 *__restrict a, TYPE1 *__restrict b, \ + TYPE1 *__restrict a2, TYPE1 *__restrict b2, int n) \ + { \ + for (int i = 0; i < n; i++) \ + { \ + dst[i] = NEG ((TYPE2) * a * (TYPE2) b[i] OP dst[i]); \ + dst2[i] = NEG ((TYPE2) * a2 * (TYPE2) b[i] OP dst2[i]); \ + dst3[i] = NEG ((TYPE2) * a2 * (TYPE2) a[i] OP dst3[i]); \ + dst4[i] = NEG ((TYPE2) * a * (TYPE2) b2[i] OP dst4[i]); \ + } \ + } + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_data.h new file mode 100644 index 0000000..ffa3d28 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_data.h @@ -0,0 +1,815 @@ +#ifndef HAVE_DEFINED_VF_MULOP_DATA_H +#define HAVE_DEFINED_VF_MULOP_DATA_H + +#define N 16 + +#define TEST_MULOP_DATA(T, NAME) test_##T##_##NAME##_data +#define TEST_MULOP_DATA_WRAP(T, NAME) TEST_MULOP_DATA(T, NAME) + + +_Float16 TEST_MULOP_DATA(_Float16, add)[][4][N] = +{ + { + { 0.30f16 }, + { + 1.48f16, 1.48f16, 1.48f16, 1.48f16, + 0.80f16, 0.80f16, 0.80f16, 0.80f16, + 0.62f16, 0.62f16, 0.62f16, 0.62f16, + 1.18f16, 1.18f16, 1.18f16, 1.18f16, + }, + { + 1.25f16, 1.25f16, 1.25f16, 1.25f16, + 1.89f16, 1.89f16, 1.89f16, 1.89f16, + 1.57f16, 1.57f16, 1.57f16, 1.57f16, + 1.21f16, 1.21f16, 1.21f16, 1.21f16, + }, + { + 1.85f16, 1.85f16, 1.85f16, 1.85f16, + 1.37f16, 1.37f16, 1.37f16, 1.37f16, + 1.09f16, 1.09f16, 1.09f16, 1.09f16, + 1.54f16, 1.54f16, 1.54f16, 1.54f16, + } + }, + { + { -0.505f16 }, + { + -2.38f16, -2.38f16, -2.38f16, -2.38f16, + -2.06f16, -2.06f16, -2.06f16, -2.06f16, + -1.69f16, -1.69f16, -1.69f16, -1.69f16, + -1.1f16, -1.1f16, -1.1f16, -1.1f16, + }, + { + -1.77f16, -1.77f16, -1.77f16, -1.77f16, + -1.6f16, -1.6f16, -1.6f16, -1.6f16, + -1.f16, -1.f16, -1.f16, -1.f16, + -1.23f16, -1.23f16, -1.23f16, -1.23f16, + }, + { + -1.49f16, -1.49f16, -1.49f16, -1.49f16, + -1.25f16, -1.25f16, -1.25f16, -1.25f16, + -1.18f16, -1.18f16, -1.18f16, -1.18f16, + -0.479f16, -0.479f16, -0.479f16, -0.479f16, + } + }, + { + { 4.95e-04f16 }, + { + 1.4266e-05f16, 1.4266e-05f16, 1.4266e-05f16, 1.4266e-05f16, + 1.8129e-05f16, 1.8129e-05f16, 1.8129e-05f16, 1.8129e-05f16, + -8.4710e-06f16, -8.4710e-06f16, -8.4710e-06f16, -8.4710e-06f16, + 3.7876e-05f16, 3.7876e-05f16, 3.7876e-05f16, 3.7876e-05f16, + }, + { + 2.2808e-02f16, 2.2808e-02f16, 2.2808e-02f16, 2.2808e-02f16, + 3.9633e-02f16, 3.9633e-02f16, 3.9633e-02f16, 3.9633e-02f16, + 9.9657e-02f16, 9.9657e-02f16, 9.9657e-02f16, 9.9657e-02f16, + 7.7189e-02f16, 7.7189e-02f16, 7.7189e-02f16, 7.7189e-02f16, + }, + { + 2.5547e-05f16, 2.5547e-05f16, 2.5547e-05f16, 2.5547e-05f16, + 3.7732e-05f16, 3.7732e-05f16, 3.7732e-05f16, 3.7732e-05f16, + 4.0820e-05f16, 4.0820e-05f16, 4.0820e-05f16, 4.0820e-05f16, + 7.6054e-05f16, 7.6054e-05f16, 7.6054e-05f16, 7.6054e-05f16, + } + }, +}; + +float TEST_MULOP_DATA(float, add)[][4][N] = +{ + { + { 43.71f }, + { + -410.28f, -410.28f, -410.28f, -410.28f, + -276.91f, -276.91f, -276.91f, -276.91f, + -103.38f, -103.38f, -103.38f, -103.38f, + -378.24f, -378.24f, -378.24f, -378.24f, + }, + { + 9.56f, 9.56f, 9.56f, 9.56f, + 6.39f, 6.39f, 6.39f, 6.39f, + 2.40f, 2.40f, 2.40f, 2.40f, + 8.80f, 8.80f, 8.80f, 8.80f, + }, + { + 7.59f, 7.59f, 7.59f, 7.59f, + 2.40f, 2.40f, 2.40f, 2.40f, + 1.52f, 1.52f, 1.52f, 1.52f, + 6.41f, 6.41f, 6.41f, 6.41f, + } + }, + { + { 2.04f }, + { + -110.22f, -110.22f, -110.22f, -110.22f, + -25.13f, -25.13f, -25.13f, -25.13f, + -108.18f, -108.18f, -108.18f, -108.18f, + -107.14f, -107.14f, -107.14f, -107.14f, + }, + { + 64.82f, 64.82f, 64.82f, 64.82f, + 31.65f, 31.65f, 31.65f, 31.65f, + 87.32f, 87.32f, 87.32f, 87.32f, + 58.70f, 58.70f, 58.70f, 58.70f, + }, + { + 22.01f, 22.01f, 22.01f, 22.01f, + 39.44f, 39.44f, 39.44f, 39.44f, + 69.95f, 69.95f, 69.95f, 69.95f, + 12.61f, 12.61f, 12.61f, 12.61f, + } + }, + { + { 20.35f }, + { + 881.43f, 881.43f, 881.43f, 881.43f, + 3300.17f, 3300.17f, 3300.17f, 3300.17f, + 5217.85f, 5217.85f, 5217.85f, 5217.85f, + 66.57f, 66.57f, 66.57f, 66.57f, + }, + { + 64.82f, 64.82f, 64.82f, 64.82f, + 31.65f, 31.65f, 31.65f, 31.65f, + 87.32f, 87.32f, 87.32f, 87.32f, + 58.70f, 58.70f, 58.70f, 58.70f, + }, + { + 2200.52f, 2200.52f, 2200.52f, 2200.52f, + 3944.25f, 3944.25f, 3944.25f, 3944.25f, + 6994.81f, 6994.81f, 6994.81f, 6994.81f, + 1261.12f, 1261.12f, 1261.12f, 1261.12f, + } + }, +}; + +double TEST_MULOP_DATA(double, add)[][4][N] = +{ + { + { 1.16e+12 }, + { + 1.8757e+45, 1.8757e+45, 1.8757e+45, 1.8757e+45, + 7.5140e+45, 7.5140e+45, 7.5140e+45, 7.5140e+45, + 8.2069e+45, 8.2069e+45, 8.2069e+45, 8.2069e+45, + 4.9456e+45, 4.9456e+45, 4.9456e+45, 4.9456e+45, + }, + { + 9.0242e+32, 9.0242e+32, 9.0242e+32, 9.0242e+32, + 3.6908e+32, 3.6908e+32, 3.6908e+32, 3.6908e+32, + 3.9202e+32, 3.9202e+32, 3.9202e+32, 3.9202e+32, + 5.0276e+32, 5.0276e+32, 5.0276e+32, 5.0276e+32, + }, + { + 2.9201e+45, 2.9201e+45, 2.9201e+45, 2.9201e+45, + 7.9411e+45, 7.9411e+45, 7.9411e+45, 7.9411e+45, + 8.6606e+45, 8.6606e+45, 8.6606e+45, 8.6606e+45, + 5.5275e+45, 5.5275e+45, 5.5275e+45, 5.5275e+45, + } + }, + { + { -7.29e+23 }, + { + -6.4993e+65, -6.4993e+65, -6.4993e+65, -6.4993e+65, + -4.6760e+65, -4.6760e+65, -4.6760e+65, -4.6760e+65, + -8.1564e+65, -8.1564e+65, -8.1564e+65, -8.1564e+65, + -8.2899e+65, -8.2899e+65, -8.2899e+65, -8.2899e+65, + }, + { + -7.7764e+41, -7.7764e+41, -7.7764e+41, -7.7764e+41, + -1.9756e+41, -1.9756e+41, -1.9756e+41, -1.9756e+41, + -4.8980e+41, -4.8980e+41, -4.8980e+41, -4.8980e+41, + -8.1062e+41, -8.1062e+41, -8.1062e+41, -8.1062e+41, + }, + { + -8.2928e+64, -8.2928e+64, -8.2928e+64, -8.2928e+64, + -3.2356e+65, -3.2356e+65, -3.2356e+65, -3.2356e+65, + -4.5850e+65, -4.5850e+65, -4.5850e+65, -4.5850e+65, + -2.3794e+65, -2.3794e+65, -2.3794e+65, -2.3794e+65, + } + }, + { + { 2.02e-03 }, + { + -1.2191e-35, -1.2191e-35, -1.2191e-35, -1.2191e-35, + -1.0471e-36, -1.0471e-36, -1.0471e-36, -1.0471e-36, + -9.7582e-36, -9.7582e-36, -9.7582e-36, -9.7582e-36, + -2.2097e-36, -2.2097e-36, -2.2097e-36, -2.2097e-36, + }, + { + 9.7703e-33, 9.7703e-33, 9.7703e-33, 9.7703e-33, + 4.1632e-33, 4.1632e-33, 4.1632e-33, 4.1632e-33, + 8.1964e-33, 8.1964e-33, 8.1964e-33, 8.1964e-33, + 4.7314e-33, 4.7314e-33, 4.7314e-33, 4.7314e-33, + }, + { + 7.5586e-36, 7.5586e-36, 7.5586e-36, 7.5586e-36, + 7.3684e-36, 7.3684e-36, 7.3684e-36, 7.3684e-36, + 6.8101e-36, 6.8101e-36, 6.8101e-36, 6.8101e-36, + 7.3543e-36, 7.3543e-36, 7.3543e-36, 7.3543e-36, + } + }, +}; + +_Float16 TEST_MULOP_DATA(_Float16, sub)[][4][N] = +{ + { + { 5.94f16 }, + { + -20.1f16, -20.1f16, -20.1f16, -20.1f16, + -13.1f16, -13.1f16, -13.1f16, -13.1f16, + -8.92f16, -8.92f16, -8.92f16, -8.92f16, + -43.1f16, -43.1f16, -43.1f16, -43.1f16, + }, + { + 7.44f16, 7.44f16, 7.44f16, 7.44f16, + 5.9f16, 5.9f16, 5.9f16, 5.9f16, + 6.81f16, 6.81f16, 6.81f16, 6.81f16, + 9.03f16, 9.03f16, 9.03f16, 9.03f16, + }, + { + 64.2f16, 64.2f16, 64.2f16, 64.2f16, + 48.1f16, 48.1f16, 48.1f16, 48.1f16, + 49.4f16, 49.4f16, 49.4f16, 49.4f16, + 96.7f16, 96.7f16, 96.7f16, 96.7f16, + } + }, + { + { 0.0475f16 }, + { + -0.0965f16, -0.0965f16, -0.0965f16, -0.0965f16, + -0.23f16, -0.23f16, -0.23f16, -0.23f16, + -0.267f16, -0.267f16, -0.267f16, -0.267f16, + -0.455f16, -0.455f16, -0.455f16, -0.455f16, + }, + { + 0.0748f16, 0.0748f16, 0.0748f16, 0.0748f16, + 0.0372f16, 0.0372f16, 0.0372f16, 0.0372f16, + 0.0183f16, 0.0183f16, 0.0183f16, 0.0183f16, + 0.0411f16, 0.0411f16, 0.0411f16, 0.0411f16, + }, + { + 0.1f16, 0.1f16, 0.1f16, 0.1f16, + 0.232f16, 0.232f16, 0.232f16, 0.232f16, + 0.268f16, 0.268f16, 0.268f16, 0.268f16, + 0.457f16, 0.457f16, 0.457f16, 0.457f16, + } + }, + { + { 2.46e+01f16 }, + { + -1.46e+02f16, -1.46e+02f16, -1.46e+02f16, -1.46e+02f16, + 3.66e+02f16, 3.66e+02f16, 3.66e+02f16, 3.66e+02f16, + 3.47e+02f16, 3.47e+02f16, 3.47e+02f16, 3.47e+02f16, + 6.24e+02f16, 6.24e+02f16, 6.24e+02f16, 6.24e+02f16, + }, + { + 6.17e+00f16, 6.17e+00f16, 6.17e+00f16, 6.17e+00f16, + 2.46e+01f16, 2.46e+01f16, 2.46e+01f16, 2.46e+01f16, + 1.99e+01f16, 1.99e+01f16, 1.99e+01f16, 1.99e+01f16, + 3.29e+01f16, 3.29e+01f16, 3.29e+01f16, 3.29e+01f16, + }, + { + 2.97e+02f16, 2.97e+02f16, 2.97e+02f16, 2.97e+02f16, + 2.39e+02f16, 2.39e+02f16, 2.39e+02f16, 2.39e+02f16, + 1.42e+02f16, 1.42e+02f16, 1.42e+02f16, 1.42e+02f16, + 1.85e+02f16, 1.85e+02f16, 1.85e+02f16, 1.85e+02f16, + } + }, +}; + +float TEST_MULOP_DATA(float, sub)[][4][N] = +{ + { + { 5.96f }, + { + 7.74f, 7.74f, 7.74f, 7.74f, + -57.f, -57.f, -57.f, -57.f, + 32.7f, 32.7f, 32.7f, 32.7f, + 2.44f, 2.44f, 2.44f, 2.44f, + }, + { + 7.37f, 7.37f, 7.37f, 7.37f, + 5.6f, 5.6f, 5.6f, 5.6f, + 9.07f, 9.07f, 9.07f, 9.07f, + 2.87f, 2.87f, 2.87f, 2.87f, + }, + { + 36.2f, 36.2f, 36.2f, 36.2f, + 90.4f, 90.4f, 90.4f, 90.4f, + 21.3f, 21.3f, 21.3f, 21.3f, + 14.6f, 14.6f, 14.6f, 14.6f, + } + }, + { + { 3.00e-02f }, + { + -2.83e-01f, -2.83e-01f, -2.83e-01f, -2.83e-01f, + -5.37e-01f, -5.37e-01f, -5.37e-01f, -5.37e-01f, + -7.87e-01f, -7.87e-01f, -7.87e-01f, -7.87e-01f, + -3.65e-01f, -3.65e-01f, -3.65e-01f, -3.65e-01f, + }, + { + 8.84e-02f, 8.84e-02f, 8.84e-02f, 8.84e-02f, + 9.27e-02f, 9.27e-02f, 9.27e-02f, 9.27e-02f, + 6.51e-02f, 6.51e-02f, 6.51e-02f, 6.51e-02f, + 5.67e-02f, 5.67e-02f, 5.67e-02f, 5.67e-02f, + }, + { + 2.86e-01f, 2.86e-01f, 2.86e-01f, 2.86e-01f, + 5.40e-01f, 5.40e-01f, 5.40e-01f, 5.40e-01f, + 7.89e-01f, 7.89e-01f, 7.89e-01f, 7.89e-01f, + 3.67e-01f, 3.67e-01f, 3.67e-01f, 3.67e-01f, + } + }, + { + { 9.04e+01f }, + { + 2.76e+03f, 2.76e+03f, 2.76e+03f, 2.76e+03f, + 1.05e+03f, 1.05e+03f, 1.05e+03f, 1.05e+03f, + 5.17e+03f, 5.17e+03f, 5.17e+03f, 5.17e+03f, + 3.91e+03f, 3.91e+03f, 3.91e+03f, 3.91e+03f, + }, + { + 3.99e+01f, 3.99e+01f, 3.99e+01f, 3.99e+01f, + 1.38e+01f, 1.38e+01f, 1.38e+01f, 1.38e+01f, + 6.36e+01f, 6.36e+01f, 6.36e+01f, 6.36e+01f, + 4.77e+01f, 4.77e+01f, 4.77e+01f, 4.77e+01f, + }, + { + 8.39e+02f, 8.39e+02f, 8.39e+02f, 8.39e+02f, + 1.97e+02f, 1.97e+02f, 1.97e+02f, 1.97e+02f, + 5.77e+02f, 5.77e+02f, 5.77e+02f, 5.77e+02f, + 4.02e+02f, 4.02e+02f, 4.02e+02f, 4.02e+02f, + } + }, +}; + +double TEST_MULOP_DATA(double, sub)[][4][N] = +{ + { + { 1.69e+01 }, + { + 8.58e+02, 8.58e+02, 8.58e+02, 8.58e+02, + 2.87e+02, 2.87e+02, 2.87e+02, 2.87e+02, + 4.35e+02, 4.35e+02, 4.35e+02, 4.35e+02, + -6.35e+01, -6.35e+01, -6.35e+01, -6.35e+01, + }, + { + 8.02e+01, 8.02e+01, 8.02e+01, 8.02e+01, + 7.51e+01, 7.51e+01, 7.51e+01, 7.51e+01, + 5.85e+01, 5.85e+01, 5.85e+01, 5.85e+01, + 1.65e+01, 1.65e+01, 1.65e+01, 1.65e+01, + }, + { + 4.95e+02, 4.95e+02, 4.95e+02, 4.95e+02, + 9.80e+02, 9.80e+02, 9.80e+02, 9.80e+02, + 5.51e+02, 5.51e+02, 5.51e+02, 5.51e+02, + 3.42e+02, 3.42e+02, 3.42e+02, 3.42e+02, + } + }, + { + { 8.86e-10 }, + { + -8.82e-09, -8.82e-09, -8.82e-09, -8.82e-09, + -3.09e-09, -3.09e-09, -3.09e-09, -3.09e-09, + -4.87e-09, -4.87e-09, -4.87e-09, -4.87e-09, + -5.70e-09, -5.70e-09, -5.70e-09, -5.70e-09, + }, + { + 9.72e-10, 9.72e-10, 9.72e-10, 9.72e-10, + 5.78e-10, 5.78e-10, 5.78e-10, 5.78e-10, + 1.10e-10, 1.10e-10, 1.10e-10, 1.10e-10, + 4.62e-10, 4.62e-10, 4.62e-10, 4.62e-10, + }, + { + 8.82e-09, 8.82e-09, 8.82e-09, 8.82e-09, + 3.09e-09, 3.09e-09, 3.09e-09, 3.09e-09, + 4.87e-09, 4.87e-09, 4.87e-09, 4.87e-09, + 5.70e-09, 5.70e-09, 5.70e-09, 5.70e-09, + } + }, + { + { 1.09e-20 }, + { + -5.46e-19, -5.46e-19, -5.46e-19, -5.46e-19, + -2.28e-19, -2.28e-19, -2.28e-19, -2.28e-19, + -4.77e-19, -4.77e-19, -4.77e-19, -4.77e-19, + -1.76e-19, -1.76e-19, -1.76e-19, -1.76e-19, + }, + { + 5.52e-20, 5.52e-20, 5.52e-20, 5.52e-20, + 2.20e-20, 2.20e-20, 2.20e-20, 2.20e-20, + 2.97e-20, 2.97e-20, 2.97e-20, 2.97e-20, + 3.23e-20, 3.23e-20, 3.23e-20, 3.23e-20, + }, + { + 5.46e-19, 5.46e-19, 5.46e-19, 5.46e-19, + 2.28e-19, 2.28e-19, 2.28e-19, 2.28e-19, + 4.77e-19, 4.77e-19, 4.77e-19, 4.77e-19, + 1.76e-19, 1.76e-19, 1.76e-19, 1.76e-19, + } + }, +}; + +_Float16 TEST_MULOP_DATA(_Float16, nadd)[][4][N] = +{ + { + { 1.09f16 }, + { + -60.7f16, -60.7f16, -60.7f16, -60.7f16, + -25.2f16, -25.2f16, -25.2f16, -25.2f16, + -50.9f16, -50.9f16, -50.9f16, -50.9f16, + -21.1f16, -21.1f16, -21.1f16, -21.1f16, + }, + { + 5.52f16, 5.52f16, 5.52f16, 5.52f16, + 2.2f16, 2.2f16, 2.2f16, 2.2f16, + 2.97f16, 2.97f16, 2.97f16, 2.97f16, + 3.23f16, 3.23f16, 3.23f16, 3.23f16, + }, + { + 54.6f16, 54.6f16, 54.6f16, 54.6f16, + 22.8f16, 22.8f16, 22.8f16, 22.8f16, + 47.7f16, 47.7f16, 47.7f16, 47.7f16, + 17.6f16, 17.6f16, 17.6f16, 17.6f16, + } + }, + { + { 0.794f16 }, + { + -6.8f16, -6.8f16, -6.8f16, -6.8f16, + -6.1f16, -6.1f16, -6.1f16, -6.1f16, + -3.02f16, -3.02f16, -3.02f16, -3.02f16, + -3.15f16, -3.15f16, -3.15f16, -3.15f16, + }, + { + 0.119f16, 0.119f16, 0.119f16, 0.119f16, + 0.774f16, 0.774f16, 0.774f16, 0.774f16, + 0.302f16, 0.302f16, 0.302f16, 0.302f16, + 0.784f16, 0.784f16, 0.784f16, 0.784f16, + }, + { + 6.7f16, 6.7f16, 6.7f16, 6.7f16, + 5.49f16, 5.49f16, 5.49f16, 5.49f16, + 2.78f16, 2.78f16, 2.78f16, 2.78f16, + 2.52f16, 2.52f16, 2.52f16, 2.52f16, + } + }, + { + { -2.62f16 }, + { + 48.6f16, 48.6f16, 48.6f16, 48.6f16, + 28.1f16, 28.1f16, 28.1f16, 28.1f16, + -2.93f16, -2.93f16, -2.93f16, -2.93f16, + 80.6f16, 80.6f16, 80.6f16, 80.6f16, + }, + { + -1.18f16, -1.18f16, -1.18f16, -1.18f16, + -7.52f16, -7.52f16, -7.52f16, -7.52f16, + -5.37f16, -5.37f16, -5.37f16, -5.37f16, + -5.39f16, -5.39f16, -5.39f16, -5.39f16, + }, + { + -51.7f16, -51.7f16, -51.7f16, -51.7f16, + -47.8f16, -47.8f16, -47.8f16, -47.8f16, + -11.2f16, -11.2f16, -11.2f16, -11.2f16, + -94.8f16, -94.8f16, -94.8f16, -94.8f16, + } + }, +}; + +float TEST_MULOP_DATA(float, nadd)[][4][N] = +{ + { + { 1.19f }, + { + -21.4f, -21.4f, -21.4f, -21.4f, + -9.12f, -9.12f, -9.12f, -9.12f, + -51.1f, -51.1f, -51.1f, -51.1f, + -48.8f, -48.8f, -48.8f, -48.8f, + }, + { + 3.83f, 3.83f, 3.83f, 3.83f, + 2.9f, 2.9f, 2.9f, 2.9f, + 4.63f, 4.63f, 4.63f, 4.63f, + 0.65f, 0.65f, 0.65f, 0.65f, + }, + { + 16.8f, 16.8f, 16.8f, 16.8f, + 5.66f, 5.66f, 5.66f, 5.66f, + 45.5f, 45.5f, 45.5f, 45.5f, + 48.1f, 48.1f, 48.1f, 48.1f, + } + }, + { + { 1.60e+01f }, + { + -2.69e+02f, -2.69e+02f, -2.69e+02f, -2.69e+02f, + -5.05e+02f, -5.05e+02f, -5.05e+02f, -5.05e+02f, + -2.92e+02f, -2.92e+02f, -2.92e+02f, -2.92e+02f, + -3.91e+02f, -3.91e+02f, -3.91e+02f, -3.91e+02f, + }, + { + 6.28e+00f, 6.28e+00f, 6.28e+00f, 6.28e+00f, + 1.94e+01f, 1.94e+01f, 1.94e+01f, 1.94e+01f, + 1.02e+01f, 1.02e+01f, 1.02e+01f, 1.02e+01f, + 1.60e+01f, 1.60e+01f, 1.60e+01f, 1.60e+01f, + }, + { + 1.68e+02f, 1.68e+02f, 1.68e+02f, 1.68e+02f, + 1.95e+02f, 1.95e+02f, 1.95e+02f, 1.95e+02f, + 1.30e+02f, 1.30e+02f, 1.30e+02f, 1.30e+02f, + 1.35e+02f, 1.35e+02f, 1.35e+02f, 1.35e+02f, + } + }, + { + { -5.63e+01f }, + { + -3.59e+03f, -3.59e+03f, -3.59e+03f, -3.59e+03f, + -2.25e+02f, -2.25e+02f, -2.25e+02f, -2.25e+02f, + -4.85e+03f, -4.85e+03f, -4.85e+03f, -4.85e+03f, + -1.59e+03f, -1.59e+03f, -1.59e+03f, -1.59e+03f, + }, + { + -7.96e+01f, -7.96e+01f, -7.96e+01f, -7.96e+01f, + -1.07e+01f, -1.07e+01f, -1.07e+01f, -1.07e+01f, + -9.62e+01f, -9.62e+01f, -9.62e+01f, -9.62e+01f, + -3.86e+01f, -3.86e+01f, -3.86e+01f, -3.86e+01f, + }, + { + -8.83e+02f, -8.83e+02f, -8.83e+02f, -8.83e+02f, + -3.79e+02f, -3.79e+02f, -3.79e+02f, -3.79e+02f, + -5.62e+02f, -5.62e+02f, -5.62e+02f, -5.62e+02f, + -5.85e+02f, -5.85e+02f, -5.85e+02f, -5.85e+02f, + } + }, +}; + +double TEST_MULOP_DATA(double, nadd)[][4][N] = +{ + { + { 8.64e+20 }, + { + -2.89e+41, -2.89e+41, -2.89e+41, -2.89e+41, + -6.50e+41, -6.50e+41, -6.50e+41, -6.50e+41, + -8.11e+41, -8.11e+41, -8.11e+41, -8.11e+41, + -4.44e+41, -4.44e+41, -4.44e+41, -4.44e+41, + }, + { + 2.61e+20, 2.61e+20, 2.61e+20, 2.61e+20, + 4.25e+20, 4.25e+20, 4.25e+20, 4.25e+20, + 5.77e+20, 5.77e+20, 5.77e+20, 5.77e+20, + 3.74e+20, 3.74e+20, 3.74e+20, 3.74e+20, + }, + { + 6.38e+40, 6.38e+40, 6.38e+40, 6.38e+40, + 2.83e+41, 2.83e+41, 2.83e+41, 2.83e+41, + 3.13e+41, 3.13e+41, 3.13e+41, 3.13e+41, + 1.21e+41, 1.21e+41, 1.21e+41, 1.21e+41, + } + }, + { + { -3.01e+40 }, + { + -7.27e+81, -7.27e+81, -7.27e+81, -7.27e+81, + -4.10e+81, -4.10e+81, -4.10e+81, -4.10e+81, + -7.82e+81, -7.82e+81, -7.82e+81, -7.82e+81, + -1.54e+81, -1.54e+81, -1.54e+81, -1.54e+81, + }, + { + -5.71e+40, -5.71e+40, -5.71e+40, -5.71e+40, + -1.41e+40, -1.41e+40, -1.41e+40, -1.41e+40, + -3.01e+40, -3.01e+40, -3.01e+40, -3.01e+40, + -2.47e+40, -2.47e+40, -2.47e+40, -2.47e+40, + }, + { + 5.55e+81, 5.55e+81, 5.55e+81, 5.55e+81, + 3.67e+81, 3.67e+81, 3.67e+81, 3.67e+81, + 6.92e+81, 6.92e+81, 6.92e+81, 6.92e+81, + 7.96e+80, 7.96e+80, 7.96e+80, 7.96e+80, + } + }, + { + { 3.65e-20 }, + { + -4.11e-39, -4.11e-39, -4.11e-39, -4.11e-39, + -8.48e-39, -8.48e-39, -8.48e-39, -8.48e-39, + -8.93e-39, -8.93e-39, -8.93e-39, -8.93e-39, + -2.74e-39, -2.74e-39, -2.74e-39, -2.74e-39, + }, + { + 5.78e-20, 5.78e-20, 5.78e-20, 5.78e-20, + 1.61e-20, 1.61e-20, 1.61e-20, 1.61e-20, + 6.91e-20, 6.91e-20, 6.91e-20, 6.91e-20, + 6.18e-20, 6.18e-20, 6.18e-20, 6.18e-20, + }, + { + 2.00e-39, 2.00e-39, 2.00e-39, 2.00e-39, + 7.89e-39, 7.89e-39, 7.89e-39, 7.89e-39, + 6.41e-39, 6.41e-39, 6.41e-39, 6.41e-39, + 4.87e-40, 4.87e-40, 4.87e-40, 4.87e-40, + } + }, +}; + +_Float16 TEST_MULOP_DATA(_Float16, nsub)[][4][N] = +{ + { + { 0.676f16 }, + { + 1.39f16, 1.39f16, 1.39f16, 1.39f16, + 1.68f16, 1.68f16, 1.68f16, 1.68f16, + 1.63f16, 1.63f16, 1.63f16, 1.63f16, + 2.12f16, 2.12f16, 2.12f16, 2.12f16, + }, + { + 1.04f16, 1.04f16, 1.04f16, 1.04f16, + 1.64f16, 1.64f16, 1.64f16, 1.64f16, + 1.95f16, 1.95f16, 1.95f16, 1.95f16, + 1.39f16, 1.39f16, 1.39f16, 1.39f16, + }, + { + 0.687f16, 0.687f16, 0.687f16, 0.687f16, + 0.568f16, 0.568f16, 0.568f16, 0.568f16, + 0.315f16, 0.315f16, 0.315f16, 0.315f16, + 1.18f16, 1.18f16, 1.18f16, 1.18f16, + } +}, + { + { -0.324f16 }, + { + -0.679f16, -0.679f16, -0.679f16, -0.679f16, + -0.992f16, -0.992f16, -0.992f16, -0.992f16, + -1.34f16, -1.34f16, -1.34f16, -1.34f16, + -0.297f16, -0.297f16, -0.297f16, -0.297f16, + }, + { + -1.96f16, -1.96f16, -1.96f16, -1.96f16, + -1.36f16, -1.36f16, -1.36f16, -1.36f16, + -1.05f16, -1.05f16, -1.05f16, -1.05f16, + -1.61f16, -1.61f16, -1.61f16, -1.61f16, + }, + { + -1.31f16, -1.31f16, -1.31f16, -1.31f16, + -1.43f16, -1.43f16, -1.43f16, -1.43f16, + -1.68f16, -1.68f16, -1.68f16, -1.68f16, + -0.82f16, -0.82f16, -0.82f16, -0.82f16, + } + }, + { + { 7.08e+01f16 }, + { + 4.49e+03f16, 4.49e+03f16, 4.49e+03f16, 4.49e+03f16, + 7.73e+03f16, 7.73e+03f16, 7.73e+03f16, 7.73e+03f16, + 8.42e+03f16, 8.42e+03f16, 8.42e+03f16, 8.42e+03f16, + 9.12e+03f16, 9.12e+03f16, 9.12e+03f16, 9.12e+03f16, + }, + { + 1.40e+01f16, 1.40e+01f16, 1.40e+01f16, 1.40e+01f16, + 6.80e+01f16, 6.80e+01f16, 6.80e+01f16, 6.80e+01f16, + 9.54e+01f16, 9.54e+01f16, 9.54e+01f16, 9.54e+01f16, + 4.49e+01f16, 4.49e+01f16, 4.49e+01f16, 4.49e+01f16, + }, + { + 3.50e+03f16, 3.50e+03f16, 3.50e+03f16, 3.50e+03f16, + 2.91e+03f16, 2.91e+03f16, 2.91e+03f16, 2.91e+03f16, + 1.66e+03f16, 1.66e+03f16, 1.66e+03f16, 1.66e+03f16, + 5.94e+03f16, 5.94e+03f16, 5.94e+03f16, 5.94e+03f16, + } + }, +}; + +float TEST_MULOP_DATA(float, nsub)[][4][N] = +{ + { + {8.51f }, + { + 24.21f, 24.21f, 24.21f, 24.21f, + 40.31f, 40.31f, 40.31f, 40.31f, + 59.68f, 59.68f, 59.68f, 59.68f, + 45.42f, 45.42f, 45.42f, 45.42f, + }, + { + 1.94f, 1.94f, 1.94f, 1.94f, + 4.24f, 4.24f, 4.24f, 4.24f, + 6.48f, 6.48f, 6.48f, 6.48f, + 4.68f, 4.68f, 4.68f, 4.68f, + }, + { + 7.70f, 7.70f, 7.70f, 7.70f, + 4.23f, 4.23f, 4.23f, 4.23f, + 4.54f, 4.54f, 4.54f, 4.54f, + 5.59f, 5.59f, 5.59f, 5.59f, + }, +}, + { + { 85.14f }, + { + 1731.29f, 1731.29f, 1731.29f, 1731.29f, + 3656.53f, 3656.53f, 3656.53f, 3656.53f, + 5565.07f, 5565.07f, 5565.07f, 5565.07f, + 4042.14f, 4042.14f, 4042.14f, 4042.14f, + }, + { + 19.43f, 19.43f, 19.43f, 19.43f, + 42.45f, 42.45f, 42.45f, 42.45f, + 64.83f, 64.83f, 64.83f, 64.83f, + 46.82f, 46.82f, 46.82f, 46.82f, + }, + { + 77.02f, 77.02f, 77.02f, 77.02f, + 42.34f, 42.34f, 42.34f, 42.34f, + 45.44f, 45.44f, 45.44f, 45.44f, + 55.89f, 55.89f, 55.89f, 55.89f, + } + }, + { + { 99.01f }, + { + 6240.43f, 6240.43f, 6240.43f, 6240.43f, + 2179.23f, 2179.23f, 2179.23f, 2179.23f, + 5346.65f, 5346.65f, 5346.65f, 5346.65f, + 2649.91f, 2649.91f, 2649.91f, 2649.91f, + }, + { + 59.46f, 59.46f, 59.46f, 59.46f, + 16.96f, 16.96f, 16.96f, 16.96f, + 52.55f, 52.55f, 52.55f, 52.55f, + 24.70f, 24.70f, 24.70f, 24.70f, + }, + { + 353.30f, 353.30f, 353.30f, 353.30f, + 500.02f, 500.02f, 500.02f, 500.02f, + 143.67f, 143.67f, 143.67f, 143.67f, + 204.36f, 204.36f, 204.36f, 204.36f, + } + }, +}; + +double TEST_MULOP_DATA(double, nsub)[][4][N] = +{ + { + { 80.54 }, + { + 5731.60, 5731.60, 5731.60, 5731.60, + 6682.41, 6682.41, 6682.41, 6682.41, + 7737.53, 7737.53, 7737.53, 7737.53, + 4922.68, 4922.68, 4922.68, 4922.68, + }, + { + 67.14, 67.14, 67.14, 67.14, + 78.23, 78.23, 78.23, 78.23, + 94.35, 94.35, 94.35, 94.35, + 49.68, 49.68, 49.68, 49.68, + }, + { + 324.14, 324.14, 324.14, 324.14, + 381.77, 381.77, 381.77, 381.77, + 138.58, 138.58, 138.58, 138.58, + 921.45, 921.45, 921.45, 921.45, + } + }, + { + { 8.05e+01 }, + { + 8.65e+27, 8.65e+27, 8.65e+27, 8.65e+27, + 1.01e+28, 1.01e+28, 1.01e+28, 1.01e+28, + 8.99e+27, 8.99e+27, 8.99e+27, 8.99e+27, + 1.32e+28, 1.32e+28, 1.32e+28, 1.32e+28, + }, + { + 6.71e+25, 6.71e+25, 6.71e+25, 6.71e+25, + 7.82e+25, 7.82e+25, 7.82e+25, 7.82e+25, + 9.44e+25, 9.44e+25, 9.44e+25, 9.44e+25, + 4.97e+25, 4.97e+25, 4.97e+25, 4.97e+25, + }, + { + 3.24e+27, 3.24e+27, 3.24e+27, 3.24e+27, + 3.82e+27, 3.82e+27, 3.82e+27, 3.82e+27, + 1.39e+27, 1.39e+27, 1.39e+27, 1.39e+27, + 9.21e+27, 9.21e+27, 9.21e+27, 9.21e+27, + } + }, + { + { 2.02e-03 }, + { + 2.7308e-35, 2.7308e-35, 2.7308e-35, 2.7308e-35, + 1.5784e-35, 1.5784e-35, 1.5784e-35, 1.5784e-35, + 2.3378e-35, 2.3378e-35, 2.3378e-35, 2.3378e-35, + 1.6918e-35, 1.6918e-35, 1.6918e-35, 1.6918e-35, + }, + { + 9.7703e-33, 9.7703e-33, 9.7703e-33, 9.7703e-33, + 4.1632e-33, 4.1632e-33, 4.1632e-33, 4.1632e-33, + 8.1964e-33, 8.1964e-33, 8.1964e-33, 8.1964e-33, + 4.7314e-33, 4.7314e-33, 4.7314e-33, 4.7314e-33, + }, + { + 7.5586e-36, 7.5586e-36, 7.5586e-36, 7.5586e-36, + 7.3684e-36, 7.3684e-36, 7.3684e-36, 7.3684e-36, + 6.8101e-36, 6.8101e-36, 6.8101e-36, 6.8101e-36, + 7.3543e-36, 7.3543e-36, 7.3543e-36, 7.3543e-36, + } + }, +}; + + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h new file mode 100644 index 0000000..3dadfab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h @@ -0,0 +1,39 @@ +#ifndef HAVE_DEFINED_VF_MULOP_RUN_H +#define HAVE_DEFINED_VF_MULOP_RUN_H + +#include <math.h> + +#define TYPE_FABS(x, T) \ + (__builtin_types_compatible_p (T, double) ? fabs (x) : fabsf (x)) + +#define MAX_RELATIVE_DIFF(T) \ + (__builtin_types_compatible_p (T, _Float16) ? 0.1f : \ + (__builtin_types_compatible_p (T, float) ? 0.01f : 0.01)) + +int +main () +{ + unsigned i, k; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + T f = TEST_DATA[i][0][0]; + T *b = TEST_DATA[i][1]; + T *c = TEST_DATA[i][2]; + T *expect = TEST_DATA[i][3]; + + TEST_RUN (T, NAME, c, b, f, N); + + for (k = 0; k < N; k++) + { + T diff = expect[k] - TEST_OUT[k]; + if (TYPE_FABS (diff, T) + > MAX_RELATIVE_DIFF (T) * TYPE_FABS (expect[k], T)) + __builtin_abort (); + } + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_widen_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_widen_run.h new file mode 100644 index 0000000..9f95fbb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_widen_run.h @@ -0,0 +1,32 @@ +#ifndef HAVE_DEFINED_VF_MULOP_WIDEN_RUN_H +#define HAVE_DEFINED_VF_MULOP_WIDEN_RUN_H + +#include <assert.h> + +#define N 512 + +int main () +{ + T1 f[N]; + T1 in[N]; + T2 out[N]; + T2 out2[N]; + + for (int i = 0; i < N; i++) + { + f[i] = LIMIT + i % 8723; + in[i] = LIMIT + i & 1964; + out[i] = LIMIT + i & 628; + out2[i] = LIMIT + i & 628; + asm volatile ("" ::: "memory"); + } + + TEST_RUN (T1, T2, NAME, out, in, f, N); + + for (int i = 0; i < N; i++) + assert (out[i] == NEG(((T2) *f * (T2) in[i]) OP out2[i])); + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c new file mode 100644 index 0000000..fd8aa30 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME add + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f32.c new file mode 100644 index 0000000..357c4ff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME add + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f64.c new file mode 100644 index 0000000..0da46be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME add + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c new file mode 100644 index 0000000..8fd8552 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME add + +DEF_VF_MULOP_CASE_0_WRAP (T, +, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c new file mode 100644 index 0000000..ed9bd36 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME add + +DEF_VF_MULOP_CASE_0_WRAP (T, +, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c new file mode 100644 index 0000000..b0883df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME add + +DEF_VF_MULOP_CASE_0_WRAP (T, +, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c new file mode 100644 index 0000000..e91fd15 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME sub + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f32.c new file mode 100644 index 0000000..3f03e11 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME sub + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f64.c new file mode 100644 index 0000000..0df8d3a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME sub + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c new file mode 100644 index 0000000..ca7e0db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME sub + +DEF_VF_MULOP_CASE_0_WRAP (T, -, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c new file mode 100644 index 0000000..d3cd3c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME sub + +DEF_VF_MULOP_CASE_0_WRAP (T, -, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c new file mode 100644 index 0000000..0d615da --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME sub + +DEF_VF_MULOP_CASE_0_WRAP (T, -, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c new file mode 100644 index 0000000..b38e800 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME nadd + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f32.c new file mode 100644 index 0000000..b97cdc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME nadd + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f64.c new file mode 100644 index 0000000..8da279f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME nadd + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c new file mode 100644 index 0000000..fef5d77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME nadd + +DEF_VF_MULOP_CASE_0_WRAP(T, +, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f32.c new file mode 100644 index 0000000..38d4f7d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME nadd + +DEF_VF_MULOP_CASE_0_WRAP (T, +, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f64.c new file mode 100644 index 0000000..dc9d3a05 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME nadd + +DEF_VF_MULOP_CASE_0_WRAP (T, +, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c new file mode 100644 index 0000000..7951d40 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME nsub + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f32.c new file mode 100644 index 0000000..be1084a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME nsub + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f64.c new file mode 100644 index 0000000..73b5a6e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME nsub + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c new file mode 100644 index 0000000..d0def86 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME nsub + +DEF_VF_MULOP_CASE_0_WRAP (T, -, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f32.c new file mode 100644 index 0000000..3cbeea9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME nsub + +DEF_VF_MULOP_CASE_0_WRAP (T, -, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f64.c new file mode 100644 index 0000000..00ead93 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME nsub + +DEF_VF_MULOP_CASE_0_WRAP (T, -, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c new file mode 100644 index 0000000..d4c527a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c @@ -0,0 +1,21 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME acc +#define OP + +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f32.c new file mode 100644 index 0000000..1af5240 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME acc +#define OP + +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c new file mode 100644 index 0000000..abce2f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c @@ -0,0 +1,21 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME sac +#define OP - +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f32.c new file mode 100644 index 0000000..13617a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME sac +#define OP - +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c new file mode 100644 index 0000000..ddf49d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c @@ -0,0 +1,21 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME nacc +#define OP + +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c new file mode 100644 index 0000000..851c335 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME nacc +#define OP + +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c new file mode 100644 index 0000000..a874991 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c @@ -0,0 +1,21 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME nsac +#define OP - +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c new file mode 100644 index 0000000..9eacace --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME nsac +#define OP - +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c new file mode 100644 index 0000000..4e1a575 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int16_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmax.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c new file mode 100644 index 0000000..4c4f72d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int32_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmax.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c new file mode 100644 index 0000000..abf62c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int64_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmax.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 { target { no-opts + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c new file mode 100644 index 0000000..7744bcb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int8_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmax.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c new file mode 100644 index 0000000..cb62e0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint16_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdivu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vremu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c new file mode 100644 index 0000000..e2a5dbb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint32_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdivu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vremu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c new file mode 100644 index 0000000..8e7a788 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint64_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdivu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vremu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 2 { target { no-opts { + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c new file mode 100644 index 0000000..d213c18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint8_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdivu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vremu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c new file mode 100644 index 0000000..05801a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int16_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c new file mode 100644 index 0000000..f05f091 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int32_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c new file mode 100644 index 0000000..adf9ccb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int64_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c new file mode 100644 index 0000000..8b3f5bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int8_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c new file mode 100644 index 0000000..365e650 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint16_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c new file mode 100644 index 0000000..c8fd42a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint32_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c new file mode 100644 index 0000000..bdb76b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint64_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c new file mode 100644 index 0000000..fc9c101 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint8_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c new file mode 100644 index 0000000..741f431 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int16_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c new file mode 100644 index 0000000..1741c22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int32_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c new file mode 100644 index 0000000..d326357 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int64_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c new file mode 100644 index 0000000..3137dc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int8_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c new file mode 100644 index 0000000..121daeb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T uint16_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c new file mode 100644 index 0000000..9616e7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T uint32_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c new file mode 100644 index 0000000..cf985f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T uint64_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c new file mode 100644 index 0000000..3bb382d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T uint8_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c new file mode 100644 index 0000000..2ae4804 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int16_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler {vsadd.vx} } } */ +/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=scalable -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c new file mode 100644 index 0000000..88cfc72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int32_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler {vsadd.vx} } } */ +/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c new file mode 100644 index 0000000..6b29a72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int64_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { no-opts { + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c new file mode 100644 index 0000000..f862eb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int8_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler {vsadd.vx} } } */ +/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c new file mode 100644 index 0000000..3ecfce6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint16_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c new file mode 100644 index 0000000..7ce1fe8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint32_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c new file mode 100644 index 0000000..c84a30c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint64_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} { target { no-opts { + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c new file mode 100644 index 0000000..9f3d7df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint8_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c new file mode 100644 index 0000000..df6872c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int16_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X8) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler {vsadd.vx} } } */ +/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c new file mode 100644 index 0000000..05ed639 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int32_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { no-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c new file mode 100644 index 0000000..6776b1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int64_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c new file mode 100644 index 0000000..d3e2785 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int8_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler {vsadd.vx} } } */ +/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { no-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c new file mode 100644 index 0000000..5497b5a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint16_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X8) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c new file mode 100644 index 0000000..3a8e85f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint32_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c new file mode 100644 index 0000000..060d591 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint64_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c new file mode 100644 index 0000000..86a6c45 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint8_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c new file mode 100644 index 0000000..0bfa2cb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T int16_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X8) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X8); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler {vsadd.vx} } } */ +/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c new file mode 100644 index 0000000..3e3acfc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T int32_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c new file mode 100644 index 0000000..531c119 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T int64_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c new file mode 100644 index 0000000..43246bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T int8_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1(T, -, rsub, VX_BINARY_REVERSE_BODY_X16); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler {vsadd.vx} } } */ +/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c new file mode 100644 index 0000000..f51e7a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T uint16_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X8) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X8); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c new file mode 100644 index 0000000..79b7477 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T uint32_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c new file mode 100644 index 0000000..ac5fd69 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T uint64_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c new file mode 100644 index 0000000..84aa06b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T uint8_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i16.c new file mode 100644 index 0000000..2b87321 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 8 + +#include "vx-fixed-vxrm.h" + +#define VT vint16m1_t +#define T int16_t +#define ELEM_SIZE 16 +#define SUFFIX i16 +#define FUNC __riscv_vaadd_vv_i16m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i32.c new file mode 100644 index 0000000..b95699b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 4 + +#include "vx-fixed-vxrm.h" + +#define VT vint32m1_t +#define T int32_t +#define ELEM_SIZE 32 +#define SUFFIX i32 +#define FUNC __riscv_vaadd_vv_i32m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i64.c new file mode 100644 index 0000000..48b6010 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i64.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 2 + +#include "vx-fixed-vxrm.h" + +#define VT vint64m1_t +#define T int64_t +#define ELEM_SIZE 64 +#define SUFFIX i64 +#define FUNC __riscv_vaadd_vv_i64m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i8.c new file mode 100644 index 0000000..d07a625 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 16 + +#include "vx-fixed-vxrm.h" + +#define VT vint8m1_t +#define T int8_t +#define ELEM_SIZE 8 +#define SUFFIX i8 +#define FUNC __riscv_vaadd_vv_i8m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u16.c new file mode 100644 index 0000000..bd36429 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 8 + +#include "vx-fixed-vxrm.h" + +#define VT vuint16m1_t +#define T uint16_t +#define ELEM_SIZE 16 +#define SUFFIX u16 +#define FUNC __riscv_vaaddu_vv_u16m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u32.c new file mode 100644 index 0000000..f023a76 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 4 + +#include "vx-fixed-vxrm.h" + +#define VT vuint32m1_t +#define T uint32_t +#define ELEM_SIZE 32 +#define SUFFIX u32 +#define FUNC __riscv_vaaddu_vv_u32m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u64.c new file mode 100644 index 0000000..d9a37ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u64.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 2 + +#include "vx-fixed-vxrm.h" + +#define VT vuint64m1_t +#define T uint64_t +#define ELEM_SIZE 64 +#define SUFFIX u64 +#define FUNC __riscv_vaaddu_vv_u64m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u8.c new file mode 100644 index 0000000..328e5d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 16 + +#include "vx-fixed-vxrm.h" + +#define VT vuint8m1_t +#define T uint8_t +#define ELEM_SIZE 8 +#define SUFFIX u8 +#define FUNC __riscv_vaaddu_vv_u8m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm.h new file mode 100644 index 0000000..438c7ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm.h @@ -0,0 +1,28 @@ +#ifndef HAVE_DEFINED_VX_FIXED_VXRM_H +#define HAVE_DEFINED_VX_FIXED_VXRM_H + +#include <riscv_vector.h> + +int64_t go[VL] = {}; +int64_t ga[VL] = {}; + +#define DEF_FIXED_BINARY_VX(VT, T, ES, SX, VXRM, FUNC) \ +void __attribute__((noinline)) \ +test_fixed_binary_##VT##_##VXRM##_##FUNC##_vx () { \ + VT a = __riscv_vle##ES##_v_##SX##m1((T *)ga, VL); \ + VT b; \ + T *bp = (T *)&b; \ + \ + for (int i = 0; i < VL; i++) { \ + bp[i] = 123; \ + } \ + \ + VT d = FUNC (a, b, VXRM, VL); \ + \ + __riscv_vse##ES##_v_##SX##m1((T *)&go, d, VL); \ +} + +#define DEF_FIXED_BINARY_VX_WRAP(VT, T, ES, SX, VXRM, FUNC) \ + DEF_FIXED_BINARY_VX(VT, T, ES, SX, VXRM, FUNC) + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h index db802bd..4a9daff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h @@ -3,16 +3,44 @@ #include <stdint.h> -#define DEF_VX_BINARY_CASE_0(T, OP) \ -void \ -test_vx_binary_case_0 (T * restrict out, T * restrict in, T x, unsigned n) \ -{ \ - for (unsigned i = 0; i < n; i++) \ - out[i] = in[i] OP x; \ +#undef HAS_INT128 + +#if __riscv_xlen == 64 +#define HAS_INT128 +typedef unsigned __int128 uint128_t; +typedef signed __int128 int128_t; +#endif + +#define DEF_VX_BINARY_CASE_0(T, OP, NAME) \ +void \ +test_vx_binary_##NAME##_##T##_case_0 (T * restrict out, T * restrict in, \ + T x, unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + out[i] = in[i] OP x; \ +} +#define DEF_VX_BINARY_CASE_0_WRAP(T, OP, NAME) \ + DEF_VX_BINARY_CASE_0(T, OP, NAME) +#define RUN_VX_BINARY_CASE_0(T, NAME, out, in, x, n) \ + test_vx_binary_##NAME##_##T##_case_0(out, in, x, n) +#define RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_0(T, NAME, out, in, x, n) + +#define DEF_VX_BINARY_REVERSE_CASE_0(T, OP, NAME) \ +void \ +test_vx_binary_reverse_##NAME##_##T##_case_0 (T * restrict out, \ + T * restrict in, T x, \ + unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + out[i] = x OP in[i]; \ } -#define DEF_VX_BINARY_CASE_0_WRAP(T, OP) DEF_VX_BINARY_CASE_0(T, OP) -#define RUN_VX_BINARY_CASE_0(out, in, x, n) test_vx_binary_case_0(out, in, x, n) -#define RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) RUN_VX_BINARY_CASE_0(out, in, x, n) +#define DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, OP, NAME) \ + DEF_VX_BINARY_REVERSE_CASE_0(T, OP, NAME) +#define RUN_VX_BINARY_REVERSE_CASE_0(T, NAME, out, in, x, n) \ + test_vx_binary_reverse_##NAME##_##T##_case_0(out, in, x, n) +#define RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_REVERSE_CASE_0(T, NAME, out, in, x, n) #define VX_BINARY_BODY(op) \ out[k + 0] = in[k + 0] op tmp; \ @@ -43,19 +71,362 @@ test_vx_binary_case_0 (T * restrict out, T * restrict in, T x, unsigned n) \ VX_BINARY_BODY_X64(op) \ VX_BINARY_BODY_X64(op) -#define DEF_VX_BINARY_CASE_1(T, OP, BODY) \ -void \ -test_vx_binary_case_1 (T * restrict out, T * restrict in, T x, unsigned n) \ -{ \ - unsigned k = 0; \ - T tmp = x + 3; \ - \ - while (k < n) \ - { \ - tmp = tmp ^ 0x3f; \ - BODY(OP) \ - } \ -} -#define DEF_VX_BINARY_CASE_1_WRAP(T, OP, BODY) DEF_VX_BINARY_CASE_1(T, OP, BODY) +#define DEF_VX_BINARY_CASE_1(T, OP, NAME, BODY) \ +void \ +test_vx_binary_##NAME##_##T##_case_1 (T * restrict out, T * restrict in, \ + T x, unsigned n) \ +{ \ + unsigned k = 0; \ + T tmp = x + 3; \ + \ + while (k < n) \ + { \ + tmp = tmp ^ 0x3f; \ + BODY(OP) \ + } \ +} +#define DEF_VX_BINARY_CASE_1_WRAP(T, OP, NAME, BODY) \ + DEF_VX_BINARY_CASE_1(T, OP, NAME, BODY) + +#define VX_BINARY_REVERSE_BODY(op) \ + out[k + 0] = tmp op in[k + 0]; \ + out[k + 1] = tmp op in[k + 1]; \ + k += 2; + +#define VX_BINARY_REVERSE_BODY_X4(op) \ + VX_BINARY_REVERSE_BODY(op) \ + VX_BINARY_REVERSE_BODY(op) + +#define VX_BINARY_REVERSE_BODY_X8(op) \ + VX_BINARY_REVERSE_BODY_X4(op) \ + VX_BINARY_REVERSE_BODY_X4(op) + +#define VX_BINARY_REVERSE_BODY_X16(op) \ + VX_BINARY_REVERSE_BODY_X8(op) \ + VX_BINARY_REVERSE_BODY_X8(op) + +#define VX_BINARY_REVERSE_BODY_X32(op) \ + VX_BINARY_REVERSE_BODY_X16(op) \ + VX_BINARY_REVERSE_BODY_X16(op) + +#define VX_BINARY_REVERSE_BODY_X64(op) \ + VX_BINARY_REVERSE_BODY_X32(op) \ + VX_BINARY_REVERSE_BODY_X32(op) + +#define VX_BINARY_REVERSE_BODY_X128(op) \ + VX_BINARY_REVERSE_BODY_X64(op) \ + VX_BINARY_REVERSE_BODY_X64(op) + +#define DEF_VX_BINARY_REVERSE_CASE_1(T, OP, NAME, BODY) \ +void \ +test_vx_binary_reverse_##NAME##_##T##_case_1 (T * restrict out, \ + T * restrict in, \ + T x, unsigned n) \ +{ \ + unsigned k = 0; \ + T tmp = x + 3; \ + \ + while (k < n) \ + { \ + tmp = tmp ^ 0x3f; \ + BODY(OP) \ + } \ +} +#define DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, OP, NAME, BODY) \ + DEF_VX_BINARY_REVERSE_CASE_1(T, OP, NAME, BODY) + +#define DEF_MAX_0(T) \ +static inline T \ +test_##T##_max_0 (T a, T b) \ +{ \ + return a > b ? a : b; \ +} + +#define DEF_MAX_1(T) \ +static inline T \ +test_##T##_max_1 (T a, T b) \ +{ \ + return a >= b ? a : b; \ +} + +DEF_MAX_0(int8_t) +DEF_MAX_0(int16_t) +DEF_MAX_0(int32_t) +DEF_MAX_0(int64_t) + +DEF_MAX_1(int8_t) +DEF_MAX_1(int16_t) +DEF_MAX_1(int32_t) +DEF_MAX_1(int64_t) + +DEF_MAX_0(uint8_t) +DEF_MAX_0(uint16_t) +DEF_MAX_0(uint32_t) +DEF_MAX_0(uint64_t) + +DEF_MAX_1(uint8_t) +DEF_MAX_1(uint16_t) +DEF_MAX_1(uint32_t) +DEF_MAX_1(uint64_t) + +#define MAX_FUNC_0(T) test_##T##_max_0 +#define MAX_FUNC_0_WARP(T) MAX_FUNC_0(T) + +#define MAX_FUNC_1(T) test_##T##_max_1 +#define MAX_FUNC_1_WARP(T) MAX_FUNC_1(T) + +#define DEF_MIN_0(T) \ +static inline T \ +test_##T##_min_0 (T a, T b) \ +{ \ + return a > b ? b : a; \ +} + +#define DEF_MIN_1(T) \ +static inline T \ +test_##T##_min_1 (T a, T b) \ +{ \ + return a >= b ? b : a; \ +} + +DEF_MIN_0(int8_t) +DEF_MIN_0(int16_t) +DEF_MIN_0(int32_t) +DEF_MIN_0(int64_t) + +DEF_MIN_1(int8_t) +DEF_MIN_1(int16_t) +DEF_MIN_1(int32_t) +DEF_MIN_1(int64_t) + +DEF_MIN_0(uint8_t) +DEF_MIN_0(uint16_t) +DEF_MIN_0(uint32_t) +DEF_MIN_0(uint64_t) + +DEF_MIN_1(uint8_t) +DEF_MIN_1(uint16_t) +DEF_MIN_1(uint32_t) +DEF_MIN_1(uint64_t) + +#define MIN_FUNC_0(T) test_##T##_min_0 +#define MIN_FUNC_0_WARP(T) MIN_FUNC_0(T) + +#define MIN_FUNC_1(T) test_##T##_min_1 +#define MIN_FUNC_1_WARP(T) MIN_FUNC_1(T) + +#define DEF_VX_BINARY_CASE_2(T, FUNC, NAME) \ +void \ +test_vx_binary_##NAME##_##FUNC##_##T##_case_2 (T * restrict out, \ + T * restrict in, \ + T x, unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + out[i] = FUNC (in[i], x); \ +} +#define DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) \ + DEF_VX_BINARY_CASE_2(T, FUNC, NAME) +#define RUN_VX_BINARY_CASE_2(T, NAME, FUNC, out, in, x, n) \ + test_vx_binary_##NAME##_##FUNC##_##T##_case_2(out, in, x, n) +#define RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) \ + RUN_VX_BINARY_CASE_2(T, NAME, FUNC, out, in, x, n) + +#define DEF_VX_BINARY_CASE_3(T, FUNC, NAME, BODY) \ +void \ +test_vx_binary_##NAME##_##FUNC##_##T##_case_3 (T * restrict out, \ + T * restrict in, \ + T x, unsigned n) \ +{ \ + unsigned k = 0; \ + T tmp = x + 3; \ + \ + while (k < n) \ + { \ + tmp = tmp ^ 0x82; \ + BODY(FUNC) \ + } \ +} +#define DEF_VX_BINARY_CASE_3_WRAP(T, FUNC, NAME, BODY) \ + DEF_VX_BINARY_CASE_3(T, FUNC, NAME, BODY) + +#define VX_BINARY_FUNC_BODY(func) \ + out[k + 0] = func (in[k + 0], tmp); \ + out[k + 1] = func (in[k + 1], tmp); \ + k += 2; + +#define VX_BINARY_FUNC_BODY_X4(op) \ + VX_BINARY_FUNC_BODY(op) \ + VX_BINARY_FUNC_BODY(op) + +#define VX_BINARY_FUNC_BODY_X8(op) \ + VX_BINARY_FUNC_BODY_X4(op) \ + VX_BINARY_FUNC_BODY_X4(op) + +#define VX_BINARY_FUNC_BODY_X16(op) \ + VX_BINARY_FUNC_BODY_X8(op) \ + VX_BINARY_FUNC_BODY_X8(op) + +#define VX_BINARY_FUNC_BODY_X32(op) \ + VX_BINARY_FUNC_BODY_X16(op) \ + VX_BINARY_FUNC_BODY_X16(op) + +#define VX_BINARY_FUNC_BODY_X64(op) \ + VX_BINARY_FUNC_BODY_X32(op) \ + VX_BINARY_FUNC_BODY_X32(op) + +#define VX_BINARY_FUNC_BODY_X128(op) \ + VX_BINARY_FUNC_BODY_X64(op) \ + VX_BINARY_FUNC_BODY_X64(op) + +#define DEF_SAT_U_ADD(T) \ +T \ +test_##T##_sat_add (T a, T b) \ +{ \ + return (a + b) | (-(T)((T)(a + b) < a)); \ +} + +DEF_SAT_U_ADD(uint8_t) +DEF_SAT_U_ADD(uint16_t) +DEF_SAT_U_ADD(uint32_t) +DEF_SAT_U_ADD(uint64_t) + +#define DEF_SAT_U_SUB(T) \ +T \ +test_##T##_sat_sub (T a, T b) \ +{ \ + return (a - b) & (-(T)(a >= b)); \ +} + +DEF_SAT_U_SUB(uint8_t) +DEF_SAT_U_SUB(uint16_t) +DEF_SAT_U_SUB(uint32_t) +DEF_SAT_U_SUB(uint64_t) + +#define DEF_SAT_S_ADD(T, UT, MIN, MAX) \ +T \ +test_##T##_sat_add (T x, T y) \ +{ \ + T sum = (UT)x + (UT)y; \ + return (x ^ y) < 0 \ + ? sum \ + : (sum ^ x) >= 0 \ + ? sum \ + : x < 0 ? MIN : MAX; \ +} + +DEF_SAT_S_ADD(int8_t, uint8_t, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD(int16_t, uint16_t, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD(int32_t, uint32_t, INT32_MIN, INT32_MAX) +DEF_SAT_S_ADD(int64_t, uint64_t, INT64_MIN, INT64_MAX) + +#define DEF_SAT_S_SUB(T, UT, MIN, MAX) \ +T \ +test_##T##_sat_sub (T x, T y) \ +{ \ + T minus = (UT)x - (UT)y; \ + return (x ^ y) >= 0 \ + ? minus \ + : (minus ^ x) >= 0 \ + ? minus \ + : x < 0 ? MIN : MAX; \ +} + +DEF_SAT_S_SUB(int8_t, uint8_t, INT8_MIN, INT8_MAX) +DEF_SAT_S_SUB(int16_t, uint16_t, INT16_MIN, INT16_MAX) +DEF_SAT_S_SUB(int32_t, uint32_t, INT32_MIN, INT32_MAX) +DEF_SAT_S_SUB(int64_t, uint64_t, INT64_MIN, INT64_MAX) + +#define SAT_U_ADD_FUNC(T) test_##T##_sat_add +#define SAT_U_ADD_FUNC_WRAP(T) SAT_U_ADD_FUNC(T) + +#define SAT_U_SUB_FUNC(T) test_##T##_sat_sub +#define SAT_U_SUB_FUNC_WRAP(T) SAT_U_SUB_FUNC(T) + +#define SAT_S_ADD_FUNC(T) test_##T##_sat_add +#define SAT_S_ADD_FUNC_WRAP(T) SAT_S_ADD_FUNC(T) + +#define SAT_S_SUB_FUNC(T) test_##T##_sat_sub +#define SAT_S_SUB_FUNC_WRAP(T) SAT_S_SUB_FUNC(T) + +#define DEF_AVG_FLOOR(NT, WT) \ +NT \ +test_##NT##_avg_floor(NT x, NT y) \ +{ \ + return (NT)(((WT)x + (WT)y) >> 1); \ +} + +DEF_AVG_FLOOR(uint8_t, uint16_t) +DEF_AVG_FLOOR(uint16_t, uint32_t) +DEF_AVG_FLOOR(uint32_t, uint64_t) + +DEF_AVG_FLOOR(int8_t, int16_t) +DEF_AVG_FLOOR(int16_t, int32_t) +DEF_AVG_FLOOR(int32_t, int64_t) + +#define DEF_AVG_CEIL(NT, WT) \ +NT \ +test_##NT##_avg_ceil(NT x, NT y) \ +{ \ + return (NT)(((WT)x + (WT)y + 1) >> 1); \ +} + +DEF_AVG_CEIL(uint8_t, uint16_t) +DEF_AVG_CEIL(uint16_t, uint32_t) +DEF_AVG_CEIL(uint32_t, uint64_t) + +DEF_AVG_CEIL(int8_t, int16_t) +DEF_AVG_CEIL(int16_t, int32_t) +DEF_AVG_CEIL(int32_t, int64_t) + +#ifdef HAS_INT128 + DEF_AVG_FLOOR(uint64_t, uint128_t) + DEF_AVG_FLOOR(int64_t, int128_t) + + DEF_AVG_CEIL(uint64_t, uint128_t) + DEF_AVG_CEIL(int64_t, int128_t) +#endif + +#define AVG_FLOOR_FUNC(T) test_##T##_avg_floor +#define AVG_FLOOR_FUNC_WRAP(T) AVG_FLOOR_FUNC(T) + +#define AVG_CEIL_FUNC(T) test_##T##_avg_ceil +#define AVG_CEIL_FUNC_WRAP(T) AVG_CEIL_FUNC(T) + +#define TEST_BINARY_VX_SIGNED_0(T) \ + DEF_VX_BINARY_CASE_0_WRAP(T, +, add) \ + DEF_VX_BINARY_CASE_0_WRAP(T, -, sub) \ + DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub) \ + DEF_VX_BINARY_CASE_0_WRAP(T, &, and) \ + DEF_VX_BINARY_CASE_0_WRAP(T, |, or) \ + DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) \ + DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) \ + DEF_VX_BINARY_CASE_0_WRAP(T, /, div) \ + DEF_VX_BINARY_CASE_0_WRAP(T, %, rem) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_1_WARP(T), min) \ + DEF_VX_BINARY_CASE_2_WRAP(T, SAT_S_ADD_FUNC(T), sat_add) \ + DEF_VX_BINARY_CASE_2_WRAP(T, SAT_S_SUB_FUNC(T), sat_sub) \ + DEF_VX_BINARY_CASE_2_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor) \ + DEF_VX_BINARY_CASE_2_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil) \ + +#define TEST_BINARY_VX_UNSIGNED_0(T) \ + DEF_VX_BINARY_CASE_0_WRAP(T, +, add) \ + DEF_VX_BINARY_CASE_0_WRAP(T, -, sub) \ + DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub) \ + DEF_VX_BINARY_CASE_0_WRAP(T, &, and) \ + DEF_VX_BINARY_CASE_0_WRAP(T, |, or) \ + DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) \ + DEF_VX_BINARY_CASE_0_WRAP(T, /, div) \ + DEF_VX_BINARY_CASE_0_WRAP(T, %, rem) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_1_WARP(T), min) \ + DEF_VX_BINARY_CASE_2_WRAP(T, SAT_U_ADD_FUNC(T), sat_add) \ + DEF_VX_BINARY_CASE_2_WRAP(T, SAT_U_SUB_FUNC(T), sat_sub) \ + DEF_VX_BINARY_CASE_2_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor) \ + DEF_VX_BINARY_CASE_2_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil) \ #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h index 11a32cb..626347c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -6,7 +6,7 @@ #define TEST_BINARY_DATA(T, NAME) test_##T##_##NAME##_data #define TEST_BINARY_DATA_WRAP(T, NAME) TEST_BINARY_DATA(T, NAME) -int8_t TEST_BINARY_DATA(int8_t, vadd)[][3][N] = +int8_t TEST_BINARY_DATA(int8_t, add)[][3][N] = { { { 1 }, @@ -55,7 +55,7 @@ int8_t TEST_BINARY_DATA(int8_t, vadd)[][3][N] = }, }; -int16_t TEST_BINARY_DATA(int16_t, vadd)[][3][N] = +int16_t TEST_BINARY_DATA(int16_t, add)[][3][N] = { { { 1 }, @@ -104,7 +104,7 @@ int16_t TEST_BINARY_DATA(int16_t, vadd)[][3][N] = }, }; -int32_t TEST_BINARY_DATA(int32_t, vadd)[][3][N] = +int32_t TEST_BINARY_DATA(int32_t, add)[][3][N] = { { { 1 }, @@ -153,7 +153,7 @@ int32_t TEST_BINARY_DATA(int32_t, vadd)[][3][N] = }, }; -int64_t TEST_BINARY_DATA(int64_t, vadd)[][3][N] = +int64_t TEST_BINARY_DATA(int64_t, add)[][3][N] = { { { 1 }, @@ -202,7 +202,7 @@ int64_t TEST_BINARY_DATA(int64_t, vadd)[][3][N] = }, }; -uint8_t TEST_BINARY_DATA(uint8_t, vadd)[][3][N] = +uint8_t TEST_BINARY_DATA(uint8_t, add)[][3][N] = { { { 1 }, @@ -251,7 +251,7 @@ uint8_t TEST_BINARY_DATA(uint8_t, vadd)[][3][N] = }, }; -uint16_t TEST_BINARY_DATA(uint16_t, vadd)[][3][N] = +uint16_t TEST_BINARY_DATA(uint16_t, add)[][3][N] = { { { 1 }, @@ -300,7 +300,7 @@ uint16_t TEST_BINARY_DATA(uint16_t, vadd)[][3][N] = }, }; -uint32_t TEST_BINARY_DATA(uint32_t, vadd)[][3][N] = +uint32_t TEST_BINARY_DATA(uint32_t, add)[][3][N] = { { { 1 }, @@ -349,7 +349,7 @@ uint32_t TEST_BINARY_DATA(uint32_t, vadd)[][3][N] = }, }; -uint64_t TEST_BINARY_DATA(uint64_t, vadd)[][3][N] = +uint64_t TEST_BINARY_DATA(uint64_t, add)[][3][N] = { { { 1 }, @@ -398,4 +398,5296 @@ uint64_t TEST_BINARY_DATA(uint64_t, vadd)[][3][N] = }, }; +int8_t TEST_BINARY_DATA(int8_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 126, 126, 126, 126, + -1, -1, -1, -1, + 125, 125, 125, 125, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + }, + { + { -128 }, + { + -128, -128, -128, -128, + -127, -127, -127, -127, + -1, -1, -1, -1, + -126, -126, -126, -126, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32766, 32766, 32766, 32766, + -1, -1, -1, -1, + 32765, 32765, 32765, 32765, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + }, + { + { -32768 }, + { + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + -1, -1, -1, -1, + -32766, -32766, -32766, -32766, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483646, 2147483646, 2147483646, 2147483646, + -1, -1, -1, -1, + 2147483645, 2147483645, 2147483645, 2147483645, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + }, + { + { -2147483648 }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + -1, -1, -1, -1, + -2147483646, -2147483646, -2147483646, -2147483646, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 9223372036854775807ll }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, + -1, -1, -1, -1, + 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + }, + { + { -9223372036854775808ull }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 254, 254, 254, 254, + 255, 255, 255, 255, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 128, 128, 128, 128, + }, + }, + { + { 253 }, + { + 253, 253, 253, 253, + 254, 254, 254, 254, + 255, 255, 255, 255, + 252, 252, 252, 252, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 255, 255, 255, 255, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + }, + }, + { + { 65533 }, + { + 65533, 65533, 65533, 65533, + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + 65532, 65532, 65532, 65532, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 65535, 65535, 65535, 65535, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + }, + { + { 4294967293 }, + { + 4294967293, 4294967293, 4294967293, 4294967293, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967292, 4294967292, 4294967292, 4294967292, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + }, + { + { 18446744073709551613ull }, + { + 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, rsub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 126, 126, 126, 126, + 1, 1, 1, 1, + 125, 125, 125, 125, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 126, 126, 126, 126, + 2, 2, 2, 2, + }, + }, + { + { -128 }, + { + -128, -128, -128, -128, + -127, -127, -127, -127, + -1, -1, -1, -1, + -126, -126, -126, -126, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -127, -127, -127, -127, + -2, -2, -2, -2, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, rsub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32766, 32766, 32766, 32766, + 1, 1, 1, 1, + 32765, 32765, 32765, 32765, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32766, 32766, 32766, 32766, + 2, 2, 2, 2, + }, + }, + { + { -32768 }, + { + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + -1, -1, -1, -1, + -32766, -32766, -32766, -32766, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -32767, -32767, -32767, -32767, + -2, -2, -2, -2, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, rsub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483646, 2147483646, 2147483646, 2147483646, + 1, 1, 1, 1, + 2147483645, 2147483645, 2147483645, 2147483645, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483646, 2147483646, 2147483646, 2147483646, + 2, 2, 2, 2, + }, + }, + { + { -2147483648 }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + -1, -1, -1, -1, + -2147483646, -2147483646, -2147483646, -2147483646, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -2147483647, -2147483647, -2147483647, -2147483647, + -2, -2, -2, -2, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, rsub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ll }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, + 1, 1, 1, 1, + 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + 2, 2, 2, 2, + }, + }, + { + { -9223372036854775808ull }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -2, -2, -2, -2, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, rsub)[][3][N] = +{ + { + { 12 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 11, 11, 11, 11, + 10, 10, 10, 10, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 28, 28, 28, 28, + 4, 4, 4, 4, + 5, 5, 5, 5, + }, + { + 0, 0, 0, 0, + 99, 99, 99, 99, + 123, 123, 123, 123, + 122, 122, 122, 122, + }, + }, + { + { 255 }, + { + 253, 253, 253, 253, + 254, 254, 254, 254, + 255, 255, 255, 255, + 252, 252, 252, 252, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 3, 3, 3, 3, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, rsub)[][3][N] = +{ + { + { 12 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 11, 11, 11, 11, + 10, 10, 10, 10, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32768 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 4, 4, 4, 4, + 5, 5, 5, 5, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 32764, 32764, 32764, 32764, + 32763, 32763, 32763, 32763, + }, + }, + { + { 65535 }, + { + 65533, 65533, 65533, 65533, + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + 65532, 65532, 65532, 65532, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 3, 3, 3, 3, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, rsub)[][3][N] = +{ + { + { 12 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 11, 11, 11, 11, + 10, 10, 10, 10, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483648 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4, 4, 4, 4, + 5, 5, 5, 5, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2147483644, 2147483644, 2147483644, 2147483644, + 2147483643, 2147483643, 2147483643, 2147483643, + }, + }, + { + { 4294967295 }, + { + 4294967293, 4294967293, 4294967293, 4294967293, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967292, 4294967292, 4294967292, 4294967292, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 3, 3, 3, 3, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, rsub)[][3][N] = +{ + { + { 12 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 11, 11, 11, 11, + 10, 10, 10, 10, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775808ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 4ull, 4ull, 4ull, 4ull, + 5ull, 5ull, 5ull, 5ull, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 9223372036854775804ull, 9223372036854775804ull, 9223372036854775804ull, 9223372036854775804ull, + 9223372036854775803ull, 9223372036854775803ull, 9223372036854775803ull, 9223372036854775803ull, + }, + }, + { + { 18446744073709551615ull }, + { + 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 3, 3, 3, 3, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7f }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + }, + { + { 0xff }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7fff }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + }, + { + { 0xffff }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7fffffff }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + }, + { + { 0xffffffff }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7fffffffffffffffull }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + }, + { + { 0xffffffffffffffffull }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7f }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + }, + { + { 0xff }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7fff }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + }, + { + { 0xffff }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7fffffff }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + }, + { + { 0xffffffff }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7fffffffffffffffull }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + }, + { + { 0xffffffffffffffffull }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xff, 0xff, 0xff, 0xff, + }, + }, + { + { 0x7f }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0xff, 0xff, 0xff, 0xff, + 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, + }, + }, + { + { 0xf0 }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xf0, 0xf0, 0xf0, 0xf0, + 0xf1, 0xf1, 0xf1, 0xf1, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + }, + { + { 0x7fff }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0xffff, 0xffff, 0xffff, 0xffff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + }, + }, + { + { 0xfff0 }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, + 0xfff0, 0xfff0, 0xfff0, 0xfff0, + 0xfff1, 0xfff1, 0xfff1, 0xfff1, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + { + { 0x7fffffff }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + }, + }, + { + { 0xfffffff0 }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0, + 0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + }, + { + { 0x7fffffffffffffffull }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + }, + }, + { + { 0xfffffffffffffff0ull }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, + 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xff, 0xff, 0xff, 0xff, + }, + }, + { + { 0x7f }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0xff, 0xff, 0xff, 0xff, + 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, + }, + }, + { + { 0xf0 }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xf0, 0xf0, 0xf0, 0xf0, + 0xf1, 0xf1, 0xf1, 0xf1, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + }, + { + { 0x7fff }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0xffff, 0xffff, 0xffff, 0xffff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + }, + }, + { + { 0xfff0 }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, + 0xfff0, 0xfff0, 0xfff0, 0xfff0, + 0xfff1, 0xfff1, 0xfff1, 0xfff1, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + { + { 0x7fffffff }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + }, + }, + { + { 0xfffffff0 }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0, + 0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + }, + { + { 0x7fffffffffffffffull }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + }, + }, + { + { 0xfffffffffffffff0ull }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, + 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfe, 0xfe, 0xfe, 0xfe, + }, + }, + { + { 0x7f }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + 0x70, 0x70, 0x70, 0x70, + 0xf, 0xf, 0xf, 0xf, + }, + }, + { + { 0xf0 }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xef, 0xef, 0xef, 0xef, + 0x70, 0x70, 0x70, 0x70, + 0xf1, 0xf1, 0xf1, 0xf1, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfffe, 0xfffe, 0xfffe, 0xfffe, + }, + }, + { + { 0x7fff }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + 0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0, + 0x0fff, 0x0fff, 0x0fff, 0x0fff, + }, + }, + { + { 0xfff0 }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xffef, 0xffef, 0xffef, 0xffef, + 0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0, + 0xfff1, 0xfff1, 0xfff1, 0xfff1, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfffffffe, 0xfffffffe, 0xfffffffe, 0xfffffffe, + }, + }, + { + { 0x7fffffff }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, + 0xfffffff, 0xfffffff, 0xfffffff, 0xfffffff, + }, + }, + { + { 0xfffffff0 }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xffffffef, 0xffffffef, 0xffffffef, 0xffffffef, + 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, + 0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull, + }, + }, + { + { 0x7fffffffffffffffull }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, + 0xfffffffffffffffull, 0xfffffffffffffffull, 0xfffffffffffffffull, 0xfffffffffffffffull, + }, + }, + { + { 0xfffffffffffffff0ull }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull, + 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, + 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfe, 0xfe, 0xfe, 0xfe, + }, + }, + { + { 0x7f }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + 0x70, 0x70, 0x70, 0x70, + 0xf, 0xf, 0xf, 0xf, + }, + }, + { + { 0xf0 }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xef, 0xef, 0xef, 0xef, + 0x70, 0x70, 0x70, 0x70, + 0xf1, 0xf1, 0xf1, 0xf1, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfffe, 0xfffe, 0xfffe, 0xfffe, + }, + }, + { + { 0x7fff }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + 0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0, + 0x0fff, 0x0fff, 0x0fff, 0x0fff, + }, + }, + { + { 0xfff0 }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xffef, 0xffef, 0xffef, 0xffef, + 0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0, + 0xfff1, 0xfff1, 0xfff1, 0xfff1, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfffffffe, 0xfffffffe, 0xfffffffe, 0xfffffffe, + }, + }, + { + { 0x7fffffff }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, + 0xfffffff, 0xfffffff, 0xfffffff, 0xfffffff, + }, + }, + { + { 0xfffffff0 }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xffffffef, 0xffffffef, 0xffffffef, 0xffffffef, + 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, + 0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull, + }, + }, + { + { 0x7fffffffffffffffull }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, + 0xfffffffffffffffull, 0xfffffffffffffffull, 0xfffffffffffffffull, 0xfffffffffffffffull, + }, + }, + { + { 0xfffffffffffffff0ull }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull, + 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, + 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, mul)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 127 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -127, -127, -127, -127, + -128, -128, -128, -128, + 2, 2, 2, 2, + }, + }, + { + { -128 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + -128, -128, -128, -128, + -128, -128, -128, -128, + 0, 0, 0, 0, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, mul)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 32767 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -32767, -32767, -32767, -32767, + -32768, -32768, -32768, -32768, + 2, 2, 2, 2, + }, + }, + { + { -32768 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + 0, 0, 0, 0, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, mul)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 2147483647 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -2147483647, -2147483647, -2147483647, -2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + 2, 2, 2, 2, + }, + }, + { + { -2147483648 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + 0, 0, 0, 0, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, mul)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 9223372036854775807ll }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 2, 2, 2, 2, + }, + }, + { + { -9223372036854775808ull }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 0, 0, 0, 0, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, div)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { -128 }, + { + -128, -128, -128, -128, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, div)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { -32768 }, + { + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, div)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { -2147483648 }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, div)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 9223372036854775807ll }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { -9223372036854775808ull }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, div)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 4, 4, 4, 4, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + 3, 3, 3, 3, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 1, 1, 1, 1, + 128, 128, 128, 128, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, + { + { 128 }, + { + 127, 127, 127, 127, + 255, 255, 255, 255, + 128, 128, 128, 128, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, div)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 4, 4, 4, 4, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + 3, 3, 3, 3, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 1, 1, 1, 1, + 32768, 32768, 32768, 32768, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, + { + { 32768 }, + { + 32767, 32767, 32767, 32767, + 65535, 65535, 65535, 65535, + 32768, 32768, 32768, 32768, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, div)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 4, 4, 4, 4, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + 3, 3, 3, 3, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 1, 1, 1, 1, + 2147483648, 2147483648, 2147483648, 2147483648, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, + { + { 2147483648 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483648, 2147483648, 2147483648, 2147483648, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, div)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 4, 4, 4, 4, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + 3, 3, 3, 3, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 1, 1, 1, 1, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, + { + { 9223372036854775808ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { -128 }, + { + -128, -128, -128, -128, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { -32768 }, + { + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { -2147483648 }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { 9223372036854775807ll }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { -9223372036854775808ull }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 1, 1, 1, 1, + 128, 128, 128, 128, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 128 }, + { + 128, 128, 128, 128, + 255, 255, 255, 255, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 127, 127, 127, 127, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 1, 1, 1, 1, + 32768, 32768, 32768, 32768, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 32768 }, + { + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 1, 1, 1, 1, + 2147483648, 2147483648, 2147483648, 2147483648, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 2147483648 }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 1, 1, 1, 1, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775808ull }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + 127, 127, 127, 127, + 127, 127, 127, 127, + }, + }, + { + { -128 }, + { + -128, -128, -128, -128, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + -128, -128, -128, -128, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + }, + }, + { + { -32768 }, + { + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + }, + { + { -2147483648 }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 9223372036854775807ll }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + }, + }, + { + { -9223372036854775808ull }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 127, 127, 127, 127, + }, + }, + { + { 254 }, + { + 128, 128, 128, 128, + 255, 255, 255, 255, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 254, 254, 254, 254, + 255, 255, 255, 255, + 254, 254, 254, 254, + 254, 254, 254, 254, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 32767, 32767, 32767, 32767, + }, + }, + { + { 65534 }, + { + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 65534, 65534, 65534, 65534, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + }, + { + { 4294967294 }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967294, 4294967294, 4294967294, 4294967294, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + }, + { + { 18446744073709551614ull }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + }, + { + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + }, + { + { -128 }, + { + -128, -128, -128, -128, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + -128, -128, -128, -128, + -128, -128, -128, -128, + -128, -128, -128, -128, + -128, -128, -128, -128, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + }, + { + { -32768 }, + { + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + }, + { + { -2147483648 }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 9223372036854775807ll }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + }, + { + { -9223372036854775808ull }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + 127, 127, 127, 127, + 1, 1, 1, 1, + }, + }, + { + { 254 }, + { + 128, 128, 128, 128, + 255, 255, 255, 255, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 128, 128, 128, 128, + 254, 254, 254, 254, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 1, 1, 1, 1, + }, + }, + { + { 65534 }, + { + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 32768, 32768, 32768, 32768, + 65534, 65534, 65534, 65534, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 1, 1, 1, 1, + }, + }, + { + { 4294967294 }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967294, 4294967294, 4294967294, 4294967294, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 1, 1, 1, 1, + }, + }, + { + { 18446744073709551614ull }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 254, 254, 254, 254, + 255, 255, 255, 255, + 255, 255, 255, 255, + 128, 128, 128, 128, + }, + }, + { + { 254 }, + { + 128, 128, 128, 128, + 255, 255, 255, 255, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 32768, 32768, 32768, 32768, + }, + }, + { + { 65534 }, + { + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + }, + { + { 4294967294 }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + }, + { + { 18446744073709551614ull }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + }, + { + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, sat_sub)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 128, 128, 128, 128, + 0, 0, 0, 0, + }, + }, + { + { 254 }, + { + 128, 128, 128, 128, + 255, 255, 255, 255, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, sat_sub)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32768, 32768, 32768, 32768, + 0, 0, 0, 0, + }, + }, + { + { 65534 }, + { + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, sat_sub)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483648, 2147483648, 2147483648, 2147483648, + 0, 0, 0, 0, + }, + }, + { + { 4294967294 }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, sat_sub)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 0, 0, 0, 0, + }, + }, + { + { 18446744073709551614ull }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -128, -128, -128, -128, + -127, -127, -127, -127, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + 0, 0, 0, 0, + 127, 127, 127, 127, + }, + }, + { + { -128 }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + 1, 1, 1, 1, + }, + { + -1, -1, -1, -1, + -128, -128, -128, -128, + -128, -128, -128, -128, + -127, -127, -127, -127, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + 0, 0, 0, 0, + 32767, 32767, 32767, 32767, + }, + }, + { + { -32768 }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + }, + { + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + 0, 0, 0, 0, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + }, + { + { -2147483648 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + }, + { + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -1, -1, -1, -1, + 0, 0, 0, 0, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + }, + { + { -9223372036854775808ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + }, + { + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, sat_sub)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 3, 3, 3, 3, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -128, -128, -128, -128, + -127, -127, -127, -127, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + -128, -128, -128, -128, + -128, -128, -128, -128, + -126, -126, -126, -126, + }, + }, + { + { -128 }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + 0, 0, 0, 0, + 127, 127, 127, 127, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, sat_sub)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 3, 3, 3, 3, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + -32766, -32766, -32766, -32766, + }, + }, + { + { -32768 }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 0, 0, 0, 0, + 32767, 32767, 32767, 32767, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, sat_sub)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 3, 3, 3, 3, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483646, -2147483646, -2147483646, -2147483646, + }, + }, + { + { -2147483648 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 0, 0, 0, 0, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, sat_sub)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 3, 3, 3, 3, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775806ull, -9223372036854775806ull, -9223372036854775806ull, -9223372036854775806ull, + }, + }, + { + { -9223372036854775808ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 0, 0, 0, 0, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + 191, 191, 191, 191, + 64, 64, 64, 64, + }, + }, + { + { 255 }, + { + 0, 0, 0, 0, + 255, 255, 255, 255, + 254, 254, 254, 254, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 255, 255, 255, 255, + 254, 254, 254, 254, + 128, 128, 128, 128, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 49151, 49151, 49151, 49151, + 16384, 16384, 16384, 16384, + }, + }, + { + { 65535 }, + { + 0, 0, 0, 0, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 32768, 32768, 32768, 32768, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 3221225471, 3221225471, 3221225471, 3221225471, + 1073741824, 1073741824, 1073741824, 1073741824, + }, + }, + { + { 4294967295 }, + { + 0, 0, 0, 0, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 13835058055282163711ull, 13835058055282163711ull, 13835058055282163711ull, 13835058055282163711ull, + 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, + }, + }, + { + { 18446744073709551615ull }, + { + 0, 0, 0, 0, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -128, -128, -128, -128, + -127, -127, -127, -127, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + 0, 0, 0, 0, + 64, 64, 64, 64, + }, + }, + { + {-128 }, + { + 0, 0, 0, 0, + -128, -128, -128, -128, + 126, 126, 126, 126, + 127, 127, 127, 127, + }, + { + -64, -64, -64, -64, + -128, -128, -128, -128, + -1, -1, -1, -1, + -1, -1, -1, -1, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + 0, 0, 0, 0, + 16384, 16384, 16384, 16384, + }, + }, + { + {-32768 }, + { + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + 32766, 32766, 32766, 32766, + 32767, 32767, 32767, 32767, + }, + { + -16384, -16384, -16384, -16384, + -32768, -32768, -32768, -32768, + -1, -1, -1, -1, + -1, -1, -1, -1, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + 0, 0, 0, 0, + 1073741824, 1073741824, 1073741824, 1073741824, + }, + }, + { + {-2147483648 }, + { + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + 2147483646, 2147483646, 2147483646, 2147483646, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + { + -1073741824, -1073741824, -1073741824, -1073741824, + -2147483648, -2147483648, -2147483648, -2147483648, + -1, -1, -1, -1, + -1, -1, -1, -1, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -1, -1, -1, -1, + 0, 0, 0, 0, + 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, + }, + }, + { + {-9223372036854775808ull }, + { + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + { + -4611686018427387904ull, -4611686018427387904ull, -4611686018427387904ull, -4611686018427387904ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -1, -1, -1, -1, + -1, -1, -1, -1, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 191, 191, 191, 191, + 64, 64, 64, 64, + }, + }, + { + { 255 }, + { + 0, 0, 0, 0, + 255, 255, 255, 255, + 254, 254, 254, 254, + 1, 1, 1, 1, + }, + { + 128, 128, 128, 128, + 255, 255, 255, 255, + 255, 255, 255, 255, + 128, 128, 128, 128, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 49151, 49151, 49151, 49151, + 16384, 16384, 16384, 16384, + }, + }, + { + { 65535 }, + { + 0, 0, 0, 0, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 1, 1, 1, 1, + }, + { + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 32768, 32768, 32768, 32768, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 3221225471, 3221225471, 3221225471, 3221225471, + 1073741824, 1073741824, 1073741824, 1073741824, + }, + }, + { + { 4294967295 }, + { + 0, 0, 0, 0, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 1, 1, 1, 1, + }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 13835058055282163711ull, 13835058055282163711ull, 13835058055282163711ull, 13835058055282163711ull, + 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, + }, + }, + { + { 18446744073709551615ull }, + { + 0, 0, 0, 0, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 1, 1, 1, 1, + }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -128, -128, -128, -128, + -127, -127, -127, -127, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 0, 0, 0, 0, + 0, 0, 0, 0, + 64, 64, 64, 64, + }, + }, + { + {-128 }, + { + 0, 0, 0, 0, + -128, -128, -128, -128, + 126, 126, 126, 126, + 127, 127, 127, 127, + }, + { + -64, -64, -64, -64, + -128, -128, -128, -128, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 0, 0, 0, 0, + 0, 0, 0, 0, + 16384, 16384, 16384, 16384, + }, + }, + { + {-32768 }, + { + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + 32766, 32766, 32766, 32766, + 32767, 32767, 32767, 32767, + }, + { + -16384, -16384, -16384, -16384, + -32768, -32768, -32768, -32768, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 0, 0, 0, 0, + 0, 0, 0, 0, + 1073741824, 1073741824, 1073741824, 1073741824, + }, + }, + { + {-2147483648 }, + { + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + 2147483646, 2147483646, 2147483646, 2147483646, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + { + -1073741824, -1073741824, -1073741824, -1073741824, + -2147483648, -2147483648, -2147483648, -2147483648, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 0, 0, 0, 0, + 0, 0, 0, 0, + 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, + }, + }, + { + {-9223372036854775808ull }, + { + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + { + -4611686018427387904ull, -4611686018427387904ull, -4611686018427387904ull, -4611686018427387904ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h index bb35184..3c00dbb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h @@ -13,7 +13,7 @@ main () T *in = TEST_DATA[i][1]; T *expect = TEST_DATA[i][2]; - TEST_RUN (out, in, x, N); + TEST_RUN (T, NAME, out, in, x, N); for (k = 0; k < N; k++) if (out[k] != expect[k]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i16.c new file mode 100644 index 0000000..0307b3f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i32.c new file mode 100644 index 0000000..d73325b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i64.c new file mode 100644 index 0000000..481774b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i8.c new file mode 100644 index 0000000..7de89ee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u16.c new file mode 100644 index 0000000..73d1a57 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u32.c new file mode 100644 index 0000000..60a7aa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u64.c new file mode 100644 index 0000000..803bcba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u8.c new file mode 100644 index 0000000..f28147b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i16.c new file mode 100644 index 0000000..8def643 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i32.c new file mode 100644 index 0000000..d9ca67d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i64.c new file mode 100644 index 0000000..313109a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i8.c new file mode 100644 index 0000000..47e4a5d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u16.c new file mode 100644 index 0000000..6297672 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u32.c new file mode 100644 index 0000000..30db24b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u64.c new file mode 100644 index 0000000..db3c911 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u8.c new file mode 100644 index 0000000..a7755f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c deleted file mode 100644 index 6de21a8..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(int16_t, +) - -/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c deleted file mode 100644 index f46be7a..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(int32_t, +) - -/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c deleted file mode 100644 index 2b57b28..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(int64_t, +) - -/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c deleted file mode 100644 index e139284..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(int8_t, +) - -/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c deleted file mode 100644 index 0266d44..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint16_t, +) - -/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c deleted file mode 100644 index c541733..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint32_t, +) - -/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c deleted file mode 100644 index e9e2162..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint64_t, +) - -/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c deleted file mode 100644 index da71fff..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint8_t, +) - -/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c deleted file mode 100644 index b40d0b8..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(int16_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c deleted file mode 100644 index af3a40d..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(int32_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c deleted file mode 100644 index 5f7c51c..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(int64_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c deleted file mode 100644 index 420cf0e..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(int8_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c deleted file mode 100644 index 7741d06..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint16_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c deleted file mode 100644 index 10ff20e..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint32_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c deleted file mode 100644 index fa5ab40..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint64_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c deleted file mode 100644 index 0374e1f..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint8_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c deleted file mode 100644 index f766907..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(int16_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c deleted file mode 100644 index 1b47a59..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(int32_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c deleted file mode 100644 index 92ab1e8..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(int64_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c deleted file mode 100644 index 444707e..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(int8_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c deleted file mode 100644 index e3fc112..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint16_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c deleted file mode 100644 index f76971b..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint32_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c deleted file mode 100644 index 09a4b42..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint64_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c deleted file mode 100644 index 5a0679f..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint8_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c deleted file mode 100644 index 9a26601..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X16) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c deleted file mode 100644 index 55b51fc..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(int32_t, +, VX_BINARY_BODY_X4) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c deleted file mode 100644 index 8ad6098..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c deleted file mode 100644 index 193e020..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(int8_t, +, VX_BINARY_BODY_X16) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c deleted file mode 100644 index a093fca..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint16_t, +, VX_BINARY_BODY_X16) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c deleted file mode 100644 index 9f5843b..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint32_t, +, VX_BINARY_BODY_X4) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c deleted file mode 100644 index 0f00688..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint64_t, +, VX_BINARY_BODY) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c deleted file mode 100644 index 47707e8..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint8_t, +, VX_BINARY_BODY_X16) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c deleted file mode 100644 index e5ec888..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X8) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c deleted file mode 100644 index ed6c22d..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(int32_t, +, VX_BINARY_BODY_X4) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c deleted file mode 100644 index ef44012..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c deleted file mode 100644 index d61f9df..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(int8_t, +, VX_BINARY_BODY_X16) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c deleted file mode 100644 index 3d1ba7f..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint16_t, +, VX_BINARY_BODY_X8) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c deleted file mode 100644 index 2e9862b..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint32_t, +, VX_BINARY_BODY_X4) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c deleted file mode 100644 index 72e6786..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint64_t, +, VX_BINARY_BODY) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c deleted file mode 100644 index e935be1..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint8_t, +, VX_BINARY_BODY_X16) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c deleted file mode 100644 index d80f0c0..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X8) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c deleted file mode 100644 index 99f6614..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(int32_t, +, VX_BINARY_BODY_X4) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c deleted file mode 100644 index ab06c51..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c deleted file mode 100644 index 7ead9d0..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(int8_t, +, VX_BINARY_BODY_X16) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c deleted file mode 100644 index 79b754b..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c +++ /dev/null @@ -1,9 +0,0 @@ - -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint16_t, +, VX_BINARY_BODY_X8) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c deleted file mode 100644 index 2f70dcd..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint32_t, +, VX_BINARY_BODY_X4) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c deleted file mode 100644 index 8094a2c..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint64_t, +, VX_BINARY_BODY) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c deleted file mode 100644 index 56d040b..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint8_t, +, VX_BINARY_BODY_X16) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c index 306ad76..ac7bd2e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T int16_t +#define T int16_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c index 6ccdf7a..1e8b78f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T int32_t +#define T int32_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c index 9484aa8..e2e352e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T int64_t +#define T int64_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c index aeb330e..8a197e5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T int8_t +#define T int8_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c index dafaa29..b616f39 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T uint16_t +#define T uint16_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c index 6b285c8..bf0449c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T uint32_t +#define T uint32_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c index eeee4e1..2611892 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T uint64_t +#define T uint64_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c index 22d7a0e..60cfe7b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T uint8_t +#define T uint8_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c new file mode 100644 index 0000000..a6a7db8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c new file mode 100644 index 0000000..79b7569 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c new file mode 100644 index 0000000..a80d8d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c new file mode 100644 index 0000000..d0c6f4c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c new file mode 100644 index 0000000..44bbaec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c new file mode 100644 index 0000000..d634a1a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c new file mode 100644 index 0000000..10816c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c new file mode 100644 index 0000000..f275016 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i16.c new file mode 100644 index 0000000..64cf31c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i32.c new file mode 100644 index 0000000..2fe6623 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i64.c new file mode 100644 index 0000000..03dbe03 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i8.c new file mode 100644 index 0000000..e54e5bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u16.c new file mode 100644 index 0000000..afb848d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u32.c new file mode 100644 index 0000000..4acaa5b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u64.c new file mode 100644 index 0000000..335a909 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u8.c new file mode 100644 index 0000000..160d362 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i16.c new file mode 100644 index 0000000..d36495c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i32.c new file mode 100644 index 0000000..acd8aeb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i64.c new file mode 100644 index 0000000..5ecc206 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i8.c new file mode 100644 index 0000000..5ac63e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u16.c new file mode 100644 index 0000000..ebe3f09 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u32.c new file mode 100644 index 0000000..ceec03b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u64.c new file mode 100644 index 0000000..8657253 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u8.c new file mode 100644 index 0000000..aefc72a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i16.c new file mode 100644 index 0000000..77445b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i32.c new file mode 100644 index 0000000..fc4fb55 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i64.c new file mode 100644 index 0000000..1afa12e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i8.c new file mode 100644 index 0000000..9c1222b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u16.c new file mode 100644 index 0000000..4617f07 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u32.c new file mode 100644 index 0000000..f0302e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u64.c new file mode 100644 index 0000000..a82cfc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u8.c new file mode 100644 index 0000000..8199ccd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i16.c new file mode 100644 index 0000000..180c82bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i32.c new file mode 100644 index 0000000..980b63c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i64.c new file mode 100644 index 0000000..26fae23 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i8.c new file mode 100644 index 0000000..c5c14a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u16.c new file mode 100644 index 0000000..5295bb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u32.c new file mode 100644 index 0000000..1e09610 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u64.c new file mode 100644 index 0000000..ed757e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u8.c new file mode 100644 index 0000000..dd4b93a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i16.c new file mode 100644 index 0000000..bfdabeb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i32.c new file mode 100644 index 0000000..af34049 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i64.c new file mode 100644 index 0000000..013bd83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i8.c new file mode 100644 index 0000000..0f4fd2d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u16.c new file mode 100644 index 0000000..5e450d85 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u32.c new file mode 100644 index 0000000..45bfd12 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u64.c new file mode 100644 index 0000000..46f0031 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u8.c new file mode 100644 index 0000000..971404b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i16.c new file mode 100644 index 0000000..c6be0ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME mul + +DEF_VX_BINARY_CASE_0_WRAP(T, *, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i32.c new file mode 100644 index 0000000..3c78042 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME mul + +DEF_VX_BINARY_CASE_0_WRAP(T, *, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i64.c new file mode 100644 index 0000000..63925d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME mul + +DEF_VX_BINARY_CASE_0_WRAP(T, *, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i8.c new file mode 100644 index 0000000..69962f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME mul + +DEF_VX_BINARY_CASE_0_WRAP(T, *, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c new file mode 100644 index 0000000..0a11aad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c new file mode 100644 index 0000000..759ad2b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c new file mode 100644 index 0000000..1b3007c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c new file mode 100644 index 0000000..b060744 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c new file mode 100644 index 0000000..0dc8bee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c new file mode 100644 index 0000000..8bc2528 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c new file mode 100644 index 0000000..d286bdf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c new file mode 100644 index 0000000..dba4338 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c new file mode 100644 index 0000000..4320789 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c new file mode 100644 index 0000000..43a001b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c new file mode 100644 index 0000000..2e9b43a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c new file mode 100644 index 0000000..d4185c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u16.c new file mode 100644 index 0000000..46e74f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u32.c new file mode 100644 index 0000000..94e3613 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u64.c new file mode 100644 index 0000000..566a1a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u8.c new file mode 100644 index 0000000..1532079 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i16.c new file mode 100644 index 0000000..65ce6a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i32.c new file mode 100644 index 0000000..170779c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i64.c new file mode 100644 index 0000000..796cfdf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i8.c new file mode 100644 index 0000000..0419e59 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u16.c new file mode 100644 index 0000000..bf9f6ce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u32.c new file mode 100644 index 0000000..afe037d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u64.c new file mode 100644 index 0000000..5d4c01e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u8.c new file mode 100644 index 0000000..43d785f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i16.c new file mode 100644 index 0000000..1f0fd46 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME sat_add +#define FUNC SAT_S_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i32.c new file mode 100644 index 0000000..4a8df0c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME sat_add +#define FUNC SAT_S_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i64.c new file mode 100644 index 0000000..534cd25 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME sat_add +#define FUNC SAT_S_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i8.c new file mode 100644 index 0000000..de2a9b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME sat_add +#define FUNC SAT_S_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u16.c new file mode 100644 index 0000000..e1531b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME sat_add +#define FUNC SAT_U_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u32.c new file mode 100644 index 0000000..4aa7143 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME sat_add +#define FUNC SAT_U_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u64.c new file mode 100644 index 0000000..30992c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME sat_add +#define FUNC SAT_U_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u8.c new file mode 100644 index 0000000..c6852a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME sat_add +#define FUNC SAT_U_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i16.c new file mode 100644 index 0000000..bd985c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME sat_sub +#define FUNC SAT_S_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i32.c new file mode 100644 index 0000000..c510ea0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME sat_sub +#define FUNC SAT_S_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i64.c new file mode 100644 index 0000000..b82278d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME sat_sub +#define FUNC SAT_S_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i8.c new file mode 100644 index 0000000..5fae704 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME sat_sub +#define FUNC SAT_S_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u16.c new file mode 100644 index 0000000..f0293a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME sat_sub +#define FUNC SAT_U_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u32.c new file mode 100644 index 0000000..34e1493 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME sat_sub +#define FUNC SAT_U_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u64.c new file mode 100644 index 0000000..65800b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME sat_sub +#define FUNC SAT_U_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u8.c new file mode 100644 index 0000000..f09843a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME sat_sub +#define FUNC SAT_U_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c new file mode 100644 index 0000000..e28f954 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c new file mode 100644 index 0000000..032ecad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c new file mode 100644 index 0000000..19bbe2d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c new file mode 100644 index 0000000..7063a9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c new file mode 100644 index 0000000..42a1508 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c new file mode 100644 index 0000000..2df5b14 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c new file mode 100644 index 0000000..c4f7e54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c new file mode 100644 index 0000000..869380a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c new file mode 100644 index 0000000..8441720 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c new file mode 100644 index 0000000..cdb773f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c new file mode 100644 index 0000000..8618b9e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c new file mode 100644 index 0000000..13724ce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c new file mode 100644 index 0000000..e6030f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c new file mode 100644 index 0000000..cdb773f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c new file mode 100644 index 0000000..44f0fff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c new file mode 100644 index 0000000..2e983e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c index 5880ccc..a5224e7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c @@ -3,9 +3,6 @@ #include "vec-avg-template.h" -/* { dg-final { scan-assembler-times {\tvwadd\.vv} 6 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 3 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 3 } } */ -/* { dg-final { scan-assembler-times {\tvadd\.vi} 3 } } */ -/* { dg-final { scan-assembler-times {\tvnsra.wi} 6 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 6 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c index 916f33d..32446ae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c @@ -3,9 +3,6 @@ #include "vec-avg-template.h" -/* { dg-final { scan-assembler-times {\tvwadd\.vv} 6 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 3 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 3 } } */ -/* { dg-final { scan-assembler-times {\tvadd\.vi} 3 } } */ -/* { dg-final { scan-assembler-times {\tvnsra\.wi} 6 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 6 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c index c8a5800..1528482 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c @@ -33,7 +33,7 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, } /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 3 } } */ /* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113829.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113829.c new file mode 100644 index 0000000..48c291a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113829.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gcv -mabi=lp64d" } */ + +#pragma riscv intrinsic "vector" +void +foo (void) +{ + __riscv_vfredosum_tu (X); /* { dg-error "undeclared" } */ + /* { dg-error "too many arguments" "" { target *-*-* } .-1 } */ +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c new file mode 100644 index 0000000..266e948 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c @@ -0,0 +1,22 @@ +/* Reduced from SPEC2017 blender: node_texture_util.c. + The conditional function call was tripping mode switching state machine */ + +/* { dg-do compile { target { rv64 && { ! riscv_abi_e } } } } */ +/* { dg-options " -Ofast -march=rv64gcv_zvl256b -ftree-vectorize -mrvv-vector-bits=zvl" } */ + +void *a; +float *b; +short c; +void d(); +void e() { + if (a) + d(); + if (c) { + b[0] = b[0] * 0.5f + 0.5f; + b[1] = b[1] * 0.5f + 0.5f; + } +} + +/* { dg-final { scan-assembler-not {frrm\s+[axs][0-9]+} } } */ +/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */ +/* { dg-final { scan-assembler-not {fsrm\s+[axs][0-9]+} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c new file mode 100644 index 0000000..d22091e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O0" } */ + +/* Use -O0 as otherwise the unused intrinsics get + optimized away. We used to ICE here instead of + emitting an error. */ + +#include "riscv_vector.h" + +void +clean_subreg (int32_t *in, int32_t *out, size_t m) /* { dg-error {this operation requires the RVV ISA extension} } */ +{ + vint16m8_t v24, v8, v16; + vint32m8_t result = __riscv_vle32_v_i32m8 (in, 32); /* { dg-error {built-in function '__riscv_vle32_v_i32m8\(in, 32\)' requires the 'v' ISA extension} } */ + vint32m1_t v0 = __riscv_vget_v_i32m8_i32m1 (result, 0); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c index 04dec7b..4f6785a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c @@ -6,9 +6,9 @@ /* ** foo: -** addi\t[a-x0-9]+,\s*[a-x0-9]+,100 +** ... ** vsetvli\tzero,a2,e64,m2,t[au],m[au] -** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero +** vmv.s.x\tv[0-9]+.* ** vs2r.v\tv[0-9]+,0\([a-x0-9]+\) ** ret */ @@ -23,7 +23,7 @@ void foo (void *base, void *out, size_t vl) ** foo2: ** fld\tfa[0-9]+,\s*100\(a0\) ** vsetvli\tzero,a2,e64,m2,t[au],m[au] -** vfmv\.v\.f\tv[0-9]+,\s*fa[0-9]+ +** vfmv\.s\.f\tv[0-9]+,\s*fa[0-9]+ ** vs2r.v\tv[0-9]+,0\([a-x0-9]+\) ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c index 0ebb92e..a8c9263c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c @@ -23,7 +23,7 @@ void foo (void *base, void *out, size_t vl) ** foo2: ** fld\tfa[0-9]+,\s*100\(a0\) ** vsetvli\tzero,a2,e64,m2,t[au],m[au] -** vfmv\.v\.f\tv[0-9]+,\s*fa[0-9]+ +** vfmv\.s\.f\tv[0-9]+,\s*fa[0-9]+ ** vs2r.v\tv[0-9]+,0\([a-x0-9]+\) ** ret */ @@ -52,7 +52,7 @@ void foo3 (void *base, void *out, size_t vl) /* ** foo4: ** ... -** vfmv\.v\.f\tv[0-9]+,\s*fa[0-9]+ +** vfmv\.s\.f\tv[0-9]+,\s*fa[0-9]+ ** ... ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c index 512fa62..cf53aca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c @@ -6,9 +6,9 @@ /* ** foo: -** addi\t[a-x0-9]+,\s*[a-x0-9]+,100 +** ... ** vsetvli\tzero,a2,e64,m2,t[au],m[au] -** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero +** vmv\.v\.x\tv[0-9]+,\s*a[0-9]+ ** vs2r.v\tv[0-9]+,0\([a-x0-9]+\) ** ret */ @@ -37,7 +37,7 @@ void foo2 (void *base, void *out, size_t vl) /* ** foo3: ** ... -** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero +** vmv\.v\.x\tv[0-9]+,\s*a[0-9]+ ** ... ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-8.c index d9d10f3..fd3b7c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-8.c @@ -175,9 +175,8 @@ void foo12 (void *base, void *out, size_t vl) /* ** foo13: ** ... -** vmv.v.x\tv[0-9]+,\s*[a-x0-9]+ +** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero ** ... -** ret */ void foo13 (void *base, void *out, size_t vl) { @@ -189,7 +188,7 @@ void foo13 (void *base, void *out, size_t vl) /* ** foo14: ** ... -** vmv.v.x\tv[0-9]+,\s*[a-x0-9]+ +** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero ** ... */ void foo14 (void *base, void *out, size_t vl) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c index 80ee1b5..64c22dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c @@ -23,4 +23,3 @@ vuint64m2_t f3(vuint64m2_t var_17, uint64_t var_60, size_t vl) /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*0,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 } } */ /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 } } */ -/* { dg-final { scan-assembler-times {sgtu} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/pr120297.c b/gcc/testsuite/gcc.target/riscv/rvv/pr120297.c new file mode 100644 index 0000000..3d1845d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/pr120297.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fwhole-program" } */ + +unsigned a; +short c; +char d; +unsigned long e; +_Bool f[10][10]; +unsigned g[10]; +long long ak; +char i = 7; +long long t[10]; +short x[10][10][10][10]; +short y[10][10][10][10]; + +void +h (char i, long long t[], short x[][10][10][10], short y[][10][10][10], + _Bool aa) +{ + for (int j = 2; j < 8; j += 2) + { + for (short k = 0; k < 10; k++) + { + for (int l = 3; l < 8; l += 2) + a = x[1][j][k][l]; + c = x[c][1][1][c]; + } + for (int k = 0; k < 10; k++) + { + f[2][k] |= (_Bool) t[c]; + g[c] = t[c + 1]; + d += y[j][1][k][k]; + e = e > i ? e : i; + } + } +} + +int +main () +{ + t[c] = 1; + h (i, t, x, y, a); + for (int j = 0; j < 10; ++j) + for (int k = 0; k < 10; ++k) + ak ^= f[j][k] + 238516665 + (ak >> 2); + ak ^= g[c] + 238516665 + (ak >> 2); + if (ak != 234635118ull) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/pr121073.c b/gcc/testsuite/gcc.target/riscv/rvv/pr121073.c new file mode 100644 index 0000000..2789d0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/pr121073.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fsigned-char -fno-strict-aliasing -fwrapv -Wno-stringop-overflow -Wno-aggressive-loop-optimizations" } */ + +int a; +unsigned char p[1][21]; +void init() { + for (int s = 0; s < 21; ++s) + for (int t = 0; t < 21; ++t) + p[s][t] = 39; + for (short t = 0; t < 9; t += -5077966496202321318LL + 28071) + a = p[3][t] && p[2][t]; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c index 3a64b3b..e0bd0fe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c @@ -29,4 +29,4 @@ void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" no-opts "-Oz" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c index cd9a5c8..0ff7f3b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c @@ -32,4 +32,4 @@ void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" no-opts "-Oz" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c index 35cad2d..bd1585c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c @@ -22,4 +22,4 @@ void f (int8_t * restrict in, int8_t * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" no-opts "-Oz" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c index cd3e961..9bade06 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -mtune=rocket" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c index fa5f3c6..55740ba 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c @@ -16,4 +16,4 @@ void f (int8_t *base, int8_t *out, size_t m, size_t n) { } /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" no-opts "-Oz" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c index 99c1722..91102ac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c @@ -16,4 +16,4 @@ void f (int8_t *base, int8_t *out, size_t m, size_t n) { } /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" no-opts "-Oz" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr117974.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr117974.c new file mode 100644 index 0000000..bf99240 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr117974.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -Ofast" } */ + +float g(float q[], int N){ + float dqnorm = 0.0; + + #pragma GCC unroll 4 + + for (int i=0; i < N; i++) { + dqnorm = dqnorm + q[i] * q[i]; + } + return dqnorm; +} + +/* need slightly different test for when -funroll-loops is enabled to keep + test output stable. Otherwise test may be flakey. */ +/* { dg-final { scan-assembler-times {beq\s+[a-x0-9]+,zero,.L12\s+vsetvli} 3 { target { no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {beq\s+[a-x0-9]+,[a-x0-9]+,.L12\s+vsetvli} 3 { target { any-opts "-funroll-loops" } } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c index d7f6d18..321eb3b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -mtune=rocket" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c index 1354c5e..29dcfef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -mtune=rocket" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c index 6366dd9..8b6299e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -mtune=rocket" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c index bbff028..3b836f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -mtune=rocket" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c index be14365..47eb43e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c @@ -18,4 +18,4 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t k) { /* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*4} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c index 2304246..45c8a4d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c @@ -18,6 +18,6 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int c } } -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*5} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c index 3df00d6..9bef7dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c @@ -17,5 +17,5 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n) { } } -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c index 3228a75..28c3dd0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c @@ -17,5 +17,5 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n) { } } -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vtype-call-clobbered.c b/gcc/testsuite/gcc.target/riscv/rvv/vtype-call-clobbered.c index be9f312..78c8a4a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vtype-call-clobbered.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vtype-call-clobbered.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64 -O2" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ /* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c new file mode 100644 index 0000000..6939157 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=xt-c920 -mrvv-vector-bits=zvl -fzero-call-used-regs=all" */ + +void +foo () +{} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120642.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120642.c new file mode 100644 index 0000000..1a72580 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120642.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mcpu=xt-c920 -mrvv-vector-bits=zvl" } */ +int __attribute__((__vector_size__(4 * sizeof(int)))) v; +void foo() { v /= 3; } diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h index 2225d30..e40902a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h @@ -4,6 +4,10 @@ #include <stdint-gcc.h> #include <stdbool.h> +#if __riscv_xlen == 64 +typedef unsigned __int128 uint128_t; +#endif + /******************************************************************************/ /* Saturation Add (unsigned and signed) */ /******************************************************************************/ @@ -13,6 +17,7 @@ sat_u_add_##T##_fmt_1 (T x, T y) \ { \ return (x + y) | (-(T)((T)(x + y) < x)); \ } +#define DEF_SAT_U_ADD_FMT_1_WRAP(T) DEF_SAT_U_ADD_FMT_1(T) #define DEF_SAT_U_ADD_FMT_2(T) \ T __attribute__((noinline)) \ @@ -20,6 +25,7 @@ sat_u_add_##T##_fmt_2 (T x, T y) \ { \ return (T)(x + y) >= x ? (x + y) : -1; \ } +#define DEF_SAT_U_ADD_FMT_2_WRAP(T) DEF_SAT_U_ADD_FMT_2(T) #define DEF_SAT_U_ADD_FMT_3(T) \ T __attribute__((noinline)) \ @@ -29,6 +35,7 @@ sat_u_add_##T##_fmt_3 (T x, T y) \ T overflow = __builtin_add_overflow (x, y, &ret); \ return (T)(-overflow) | ret; \ } +#define DEF_SAT_U_ADD_FMT_3_WRAP(T) DEF_SAT_U_ADD_FMT_3(T) #define DEF_SAT_U_ADD_FMT_4(T) \ T __attribute__((noinline)) \ @@ -37,6 +44,7 @@ sat_u_add_##T##_fmt_4 (T x, T y) \ T ret; \ return __builtin_add_overflow (x, y, &ret) ? -1 : ret; \ } +#define DEF_SAT_U_ADD_FMT_4_WRAP(T) DEF_SAT_U_ADD_FMT_4(T) #define DEF_SAT_U_ADD_FMT_5(T) \ T __attribute__((noinline)) \ @@ -45,6 +53,7 @@ sat_u_add_##T##_fmt_5 (T x, T y) \ T ret; \ return __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1; \ } +#define DEF_SAT_U_ADD_FMT_5_WRAP(T) DEF_SAT_U_ADD_FMT_5(T) #define DEF_SAT_U_ADD_FMT_6(T) \ T __attribute__((noinline)) \ @@ -52,6 +61,7 @@ sat_u_add_##T##_fmt_6 (T x, T y) \ { \ return (T)(x + y) < x ? -1 : (x + y); \ } +#define DEF_SAT_U_ADD_FMT_6_WRAP(T) DEF_SAT_U_ADD_FMT_6(T) #define DEF_SAT_U_ADD_FMT_7(WT, T) \ T __attribute__((noinline)) \ @@ -63,12 +73,34 @@ sat_u_add_##WT##_##T##_fmt_7(T x, T y) \ } #define DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) DEF_SAT_U_ADD_FMT_7(WT, T) +#define DEF_SAT_U_ADD_FMT_8(T) \ +T __attribute__((noinline)) \ +sat_u_add_##T##_fmt_8(T x, T y) \ +{ \ + return x <= (T)(x + y) ? (x + y) : -1; \ +} +#define DEF_SAT_U_ADD_FMT_8_WRAP(T) DEF_SAT_U_ADD_FMT_8(T) + +#define DEF_SAT_U_ADD_FMT_9(T) \ +T __attribute__((noinline)) \ +sat_u_add_##T##_fmt_9(T x, T y) \ +{ \ + return x > (T)(x + y) ? -1 : (x + y); \ +} +#define DEF_SAT_U_ADD_FMT_9_WRAP(T) DEF_SAT_U_ADD_FMT_9(T) + #define RUN_SAT_U_ADD_FMT_1(T, x, y) sat_u_add_##T##_fmt_1(x, y) +#define RUN_SAT_U_ADD_FMT_1_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_1(T, x, y) #define RUN_SAT_U_ADD_FMT_2(T, x, y) sat_u_add_##T##_fmt_2(x, y) +#define RUN_SAT_U_ADD_FMT_2_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_2(T, x, y) #define RUN_SAT_U_ADD_FMT_3(T, x, y) sat_u_add_##T##_fmt_3(x, y) +#define RUN_SAT_U_ADD_FMT_3_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_3(T, x, y) #define RUN_SAT_U_ADD_FMT_4(T, x, y) sat_u_add_##T##_fmt_4(x, y) +#define RUN_SAT_U_ADD_FMT_4_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_4(T, x, y) #define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y) +#define RUN_SAT_U_ADD_FMT_5_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_5(T, x, y) #define RUN_SAT_U_ADD_FMT_6(T, x, y) sat_u_add_##T##_fmt_6(x, y) +#define RUN_SAT_U_ADD_FMT_6_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_6(T, x, y) #define RUN_SAT_U_ADD_FMT_7_FROM_U16(T, x, y) \ sat_u_add_uint16_t_##T##_fmt_7(x, y) #define RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP(T, x, y) \ @@ -81,6 +113,10 @@ sat_u_add_##WT##_##T##_fmt_7(T x, T y) \ sat_u_add_uint64_t_##T##_fmt_7(x, y) #define RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T, x, y) \ RUN_SAT_U_ADD_FMT_7_FROM_U64(T, x, y) +#define RUN_SAT_U_ADD_FMT_8(T, x, y) sat_u_add_##T##_fmt_8(x, y) +#define RUN_SAT_U_ADD_FMT_8_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_8(T, x, y) +#define RUN_SAT_U_ADD_FMT_9(T, x, y) sat_u_add_##T##_fmt_9(x, y) +#define RUN_SAT_U_ADD_FMT_9_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_9(T, x, y) #define DEF_SAT_U_ADD_IMM_FMT_1(T, IMM) \ T __attribute__((noinline)) \ @@ -215,6 +251,18 @@ sat_s_add_imm_##T##_fmt_1##_##INDEX (T x) \ #define RUN_SAT_S_ADD_IMM_FMT_1(INDEX, T, x, expect) \ if (sat_s_add_imm##_##T##_fmt_1##_##INDEX(x) != expect) __builtin_abort () +#define DEF_SAT_S_ADD_IMM_FMT_2(INDEX, T, UT, IMM, MIN, MAX) \ +T __attribute__((noinline)) \ +sat_s_add_imm_##T##_fmt_2##_##INDEX (T x) \ +{ \ + T sum = (T)((UT)x + (UT)IMM); \ + return ((x ^ sum) < 0 && (x ^ IMM) >= 0) ? \ + (-(T)(x < 0) ^ MAX) : sum; \ +} + +#define RUN_SAT_S_ADD_IMM_FMT_2(INDEX, T, x, expect) \ + if (sat_s_add_imm##_##T##_fmt_2##_##INDEX(x) != expect) __builtin_abort () + /******************************************************************************/ /* Saturation Sub (Unsigned and Signed) */ /******************************************************************************/ @@ -624,4 +672,25 @@ sat_s_trunc_##WT##_to_##NT##_fmt_8 (WT x) \ #define RUN_SAT_S_TRUNC_FMT_8(NT, WT, x) sat_s_trunc_##WT##_to_##NT##_fmt_8 (x) #define RUN_SAT_S_TRUNC_FMT_8_WRAP(NT, WT, x) RUN_SAT_S_TRUNC_FMT_8(NT, WT, x) +/******************************************************************************/ +/* Saturation Mult (unsigned and signed) */ +/******************************************************************************/ + +#define DEF_SAT_U_MUL_FMT_1(NT, WT) \ +NT __attribute__((noinline)) \ +sat_u_mul_##NT##_from_##WT##_fmt_1 (NT a, NT b) \ +{ \ + WT x = (WT)a * (WT)b; \ + NT max = -1; \ + if (x > (WT)(max)) \ + return max; \ + else \ + return (NT)x; \ +} + +#define DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) DEF_SAT_U_MUL_FMT_1(NT, WT) +#define RUN_SAT_U_MUL_FMT_1(NT, WT, a, b) \ + sat_u_mul_##NT##_from_##WT##_fmt_1 (a, b) +#define RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, a, b) RUN_SAT_U_MUL_FMT_1(NT, WT, a, b) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith_data.h b/gcc/testsuite/gcc.target/riscv/sat/sat_arith_data.h index 9f9f7d0..bd33ff1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith_data.h +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith_data.h @@ -12,6 +12,7 @@ #define TEST_BINARY_STRUCT_NAME(T, NAME) test_##T##_##NAME##_s #define TEST_BINARY_STRUCT_DECL(T, NAME) struct TEST_BINARY_STRUCT_NAME(T, NAME) +#define TEST_BINARY_STRUCT_DECL_WRAP(T, NAME) TEST_BINARY_STRUCT_DECL(T, NAME) #define TEST_BINARY_STRUCT(T, NAME) \ struct TEST_BINARY_STRUCT_NAME(T, NAME) \ { \ @@ -32,6 +33,16 @@ TEST_UNARY_STRUCT (uint16_t, uint32_t) TEST_UNARY_STRUCT (uint16_t, uint64_t) TEST_UNARY_STRUCT (uint32_t, uint64_t) +TEST_BINARY_STRUCT (uint8_t, usadd) +TEST_BINARY_STRUCT (uint16_t, usadd) +TEST_BINARY_STRUCT (uint32_t, usadd) +TEST_BINARY_STRUCT (uint64_t, usadd) + +TEST_BINARY_STRUCT (uint8_t, usmul) +TEST_BINARY_STRUCT (uint16_t, usmul) +TEST_BINARY_STRUCT (uint32_t, usmul) +TEST_BINARY_STRUCT (uint64_t, usmul) + TEST_BINARY_STRUCT (int8_t, ssadd) TEST_BINARY_STRUCT (int16_t, ssadd) TEST_BINARY_STRUCT (int32_t, ssadd) @@ -236,6 +247,62 @@ TEST_UNARY_STRUCT_DECL(int32_t, int64_t) \ {-2147483648, -9223372036854775808ull}, }; +TEST_BINARY_STRUCT_DECL(uint8_t, usadd) TEST_BINARY_DATA(uint8_t, usadd)[] = +{ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 254, 254, }, + { 1, 254, 255, }, + { 2, 254, 255, }, + { 0, 255, 255, }, + { 1, 255, 255, }, + { 2, 255, 255, }, + { 255, 255, 255, }, +}; + +TEST_BINARY_STRUCT_DECL(uint16_t, usadd) TEST_BINARY_DATA(uint16_t, usadd)[] = +{ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 65534, 65534, }, + { 1, 65534, 65535, }, + { 2, 65534, 65535, }, + { 0, 65535, 65535, }, + { 1, 65535, 65535, }, + { 2, 65535, 65535, }, + { 65535, 65535, 65535, }, +}; + +TEST_BINARY_STRUCT_DECL(uint32_t, usadd) TEST_BINARY_DATA(uint32_t, usadd)[] = +{ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 4294967294, 4294967294, }, + { 1, 4294967294, 4294967295, }, + { 2, 4294967294, 4294967295, }, + { 0, 4294967295, 4294967295, }, + { 1, 4294967295, 4294967295, }, + { 2, 4294967295, 4294967295, }, + { 4294967295, 4294967295, 4294967295, }, +}; + +TEST_BINARY_STRUCT_DECL(uint64_t, usadd) TEST_BINARY_DATA(uint64_t, usadd)[] = +{ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 18446744073709551614u, 18446744073709551614u, }, + { 1, 18446744073709551614u, 18446744073709551615u, }, + { 2, 18446744073709551614u, 18446744073709551615u, }, + { 0, 18446744073709551615u, 18446744073709551615u, }, + { 1, 18446744073709551615u, 18446744073709551615u, }, + { 2, 18446744073709551615u, 18446744073709551615u, }, + { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, +}; + TEST_BINARY_STRUCT_DECL(int8_t, ssadd) TEST_BINARY_DATA(int8_t, ssadd)[] = { { 0, 0, 0}, @@ -372,4 +439,60 @@ TEST_BINARY_STRUCT_DECL(int64_t, sssub) TEST_BINARY_DATA(int64_t, sssub)[] = { 9223372036854775806ll, 9223372036854775800ll, 6}, }; +TEST_BINARY_STRUCT_DECL(uint8_t, usmul) TEST_BINARY_DATA(uint8_t, usmul)[] = +{ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 1, }, + { 1, 127, 127, }, + { 2, 127, 254, }, + { 3, 127, 255, }, + { 127, 127, 255, }, + { 1, 255, 255, }, + { 127, 255, 255, }, + { 255, 255, 255, }, +}; + +TEST_BINARY_STRUCT_DECL(uint16_t, usmul) TEST_BINARY_DATA(uint16_t, usmul)[] = +{ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 1, }, + { 1, 32767, 32767, }, + { 2, 32767, 65534, }, + { 3, 32767, 65535, }, + { 32767, 32767, 65535, }, + { 1, 65535, 65535, }, + { 32767, 65535, 65535, }, + { 65535, 65535, 65535, }, +}; + +TEST_BINARY_STRUCT_DECL(uint32_t, usmul) TEST_BINARY_DATA(uint32_t, usmul)[] = +{ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 1, }, + { 1, 2147483647, 2147483647, }, + { 2, 2147483647, 4294967294, }, + { 3, 2147483647, 4294967295, }, + { 2147483647, 2147483647, 4294967295, }, + { 1, 4294967295, 4294967295, }, + { 2147483647, 4294967295, 4294967295, }, + { 4294967295, 4294967295, 4294967295, }, +}; + +TEST_BINARY_STRUCT_DECL(uint64_t, usmul) TEST_BINARY_DATA(uint64_t, usmul)[] = +{ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 1, }, + { 1, 9223372036854775807ull, 9223372036854775807ull, }, + { 2, 9223372036854775807ull, 18446744073709551614ull, }, + { 3, 9223372036854775807ull, 18446744073709551615ull, }, + { 9223372036854775807ull, 9223372036854775807ull, 18446744073709551615ull, }, + { 1, 18446744073709551615ull, 18446744073709551615ull, }, + { 9223372036854775807ull, 18446744073709551615ull, 18446744073709551615ull, }, + { 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i16.c index 55890d8..50f0f1f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i16.c @@ -1,32 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int16_t_fmt_1: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_ADD_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i32.c index 29e843f..dc65817 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i32.c @@ -1,31 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int32_t_fmt_1: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_ADD_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i64.c index 7f29d21..9995bc7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i64.c @@ -1,29 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int64_t_fmt_1: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_ADD_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i8.c index 3ad7bdd..caf745a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i8.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int8_t_fmt_1: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_ADD_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i16.c index 07d3101..f19187d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i16.c @@ -1,32 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int16_t_fmt_2: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_ADD_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i32.c index 81b85b4..88dc37d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i32.c @@ -1,31 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int32_t_fmt_2: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_ADD_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i64.c index 9a3d83e..891d6cf 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i64.c @@ -1,29 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int64_t_fmt_2: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_ADD_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i8.c index ecc9a0f..a07172b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i8.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int8_t_fmt_2: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_ADD_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i16.c index 7e93385..5077198 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i16.c @@ -1,32 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int16_t_fmt_3: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_ADD_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i32.c index 09bf497..07af4e1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i32.c @@ -1,31 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int32_t_fmt_3: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_ADD_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i64.c index 5652cdb..7c4be5b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i64.c @@ -1,29 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int64_t_fmt_3: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_ADD_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i8.c index 0eb0c84..fc0e1b7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i8.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int8_t_fmt_3: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_ADD_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i16.c index 9dfdb9e..4c0b38a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i16.c @@ -1,32 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int16_t_fmt_4: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_ADD_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i32.c index 74df576..45b4638 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i32.c @@ -1,31 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int32_t_fmt_4: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_ADD_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i64.c index 5937699..294eb52 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i64.c @@ -1,29 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int64_t_fmt_4: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_ADD_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i8.c index af850d0..143fa3c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i8.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int8_t_fmt_4: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_ADD_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i16.c index 34459b8..1023934 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i32.c index 4d4841f..bccb768 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i64.c index df81887..34de520 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i8.c index 9a4ce33..6d136ec 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i16.c index cdac5bd..ee8e439 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i32.c index 4ac952e..8996dd2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i64.c index 4d25e7f..155c8e9 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i8.c index d57e0a0..4502ed3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i16.c index 08b961a..21289c9 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i32.c index 3611b6e..3d4a6fa 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i64.c index 3eaa6c2..b55d221 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i8.c index 6d38e5f..9fef8b0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i16.c index 2e73450..fd135e5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i32.c index ec3022d..38ade40 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i64.c index 911856e..04ba746 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i8.c index 94d48ef..32aea5c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i16.c new file mode 100644 index 0000000..414cb61 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, -7, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD_IMM_FMT_1(1, int16_t, uint16_t, -1, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i32.c new file mode 100644 index 0000000..adf5b39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, 10, INT32_MIN, INT32_MAX) + +DEF_SAT_S_ADD_IMM_FMT_1(1, int32_t, uint32_t, -1, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i64.c new file mode 100644 index 0000000..b88e064 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_1(0, int64_t, uint64_t, 10, INT64_MIN, INT64_MAX) + +DEF_SAT_S_ADD_IMM_FMT_1(1, int64_t, uint64_t, -1, INT64_MIN, INT64_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i8.c new file mode 100644 index 0000000..0e337ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i8.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, 9, INT8_MIN, INT8_MAX) + +DEF_SAT_S_ADD_IMM_FMT_1(1, int8_t, uint8_t, -1, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1.c deleted file mode 100644 index b6f1731..0000000 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1.c +++ /dev/null @@ -1,29 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ - -#include "sat_arith.h" - -/* -** sat_s_add_imm_int8_t_fmt_1_0: -** addi\s+[atx][0-9]+,\s*a0,\s*9 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** srli\s+[atx][0-9]+,\s*a0,\s*7 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+a0,\s*a0,\s*63 -** xori\s+[atx][0-9]+,\s*a0,\s*127 -** neg\s+a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*a0,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ -DEF_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, 9, INT8_MIN, INT8_MAX) - -/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i16.c new file mode 100644 index 0000000..f217fe1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i16.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int16_t, uint16_t, -7, INT16_MIN, INT16_MAX) + +DEF_SAT_S_ADD_IMM_FMT_2(1, int16_t, uint16_t, -1, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i32.c new file mode 100644 index 0000000..4025b5a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int32_t, uint32_t, 10, INT32_MIN, INT32_MAX) + +DEF_SAT_S_ADD_IMM_FMT_2(1, int32_t, uint32_t, -1, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i64.c new file mode 100644 index 0000000..3fc2514 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int64_t, uint64_t, 10, INT64_MIN, INT64_MAX) + +DEF_SAT_S_ADD_IMM_FMT_2(1, int64_t, uint64_t, -1, INT64_MIN, INT64_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i8.c new file mode 100644 index 0000000..a0e15cf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i8.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int8_t, uint8_t, 9, INT8_MIN, INT8_MAX) + +DEF_SAT_S_ADD_IMM_FMT_2(1, int8_t, uint8_t, -1, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2.c deleted file mode 100644 index 3878286..0000000 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2.c +++ /dev/null @@ -1,32 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ - -#include "sat_arith.h" - -/* -** sat_s_add_imm_int16_t_fmt_1_0: -** addi\s+[atx][0-9]+,\s*a0,\s*-7 -** xori\s+[atx][0-9]+,\s*a0,\s*-7 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+a0,\s*a0,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** neg\s+a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*a0,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ -DEF_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, -7, INT16_MIN, INT16_MAX) - -/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3.c deleted file mode 100644 index c9fbc66..0000000 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ - -#include "sat_arith.h" - -/* -** sat_s_add_imm_int32_t_fmt_1_0: -** addi\s+[atx][0-9]+,\s*a0,\s*10 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srli\s+[atx][0-9]+,\s*a0,\s*31 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+a0,\s*a0,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** neg\s+a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,a0,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ -DEF_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, 10, INT32_MIN, INT32_MAX) - -/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-4.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-4.c deleted file mode 100644 index 2aa9545..0000000 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-4.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ - -#include "sat_arith.h" - -/* -** sat_s_add_imm_int64_t_fmt_1_0: -** addi\s+[atx][0-9]+,\s*a0,\s*10 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srli\s+[atx][0-9]+,\s*a0,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*a0,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ -DEF_SAT_S_ADD_IMM_FMT_1(0, int64_t, uint64_t, 10, INT64_MIN, INT64_MAX) - -/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i16.c index 187a098..ae2c306 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i16.c @@ -7,6 +7,7 @@ DEF_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, -32768, INT16_MIN, INT16_MAX) DEF_SAT_S_ADD_IMM_FMT_1(1, int16_t, uint16_t, 32767, INT16_MIN, INT16_MAX) DEF_SAT_S_ADD_IMM_FMT_1(2, int16_t, uint16_t, 100, INT16_MIN, INT16_MAX) DEF_SAT_S_ADD_IMM_FMT_1(3, int16_t, uint16_t, -100, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD_IMM_FMT_1(4, int16_t, uint16_t, -1, INT16_MIN, INT16_MAX) #define T int16_t #define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_1(INDEX, T, x, expect) @@ -21,6 +22,8 @@ T d[][2] = { { -32768, -32668, }, { -32768, -32768, }, { 0, -100, }, + { -32768, -32768, }, + { 0, -1, }, }; int @@ -38,5 +41,8 @@ main () RUN (3, T, d[6][0], d[6][1]); RUN (3, T, d[7][0], d[7][1]); + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + return 0; } diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i32.c index 899fda8..02a947f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i32.c @@ -7,6 +7,7 @@ DEF_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, -2147483648, INT32_MIN, INT32_MAX) DEF_SAT_S_ADD_IMM_FMT_1(1, int32_t, uint32_t, 2147483647, INT32_MIN, INT32_MAX) DEF_SAT_S_ADD_IMM_FMT_1(2, int32_t, uint32_t, 100, INT32_MIN, INT32_MAX) DEF_SAT_S_ADD_IMM_FMT_1(3, int32_t, uint32_t, -100, INT32_MIN, INT32_MAX) +DEF_SAT_S_ADD_IMM_FMT_1(4, int32_t, uint32_t, -1, INT32_MIN, INT32_MAX) #define T int32_t #define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_1(INDEX, T, x, expect) @@ -21,6 +22,8 @@ T d[][2] = { { -300, -200, }, { 100, 0, }, { 0, -100, }, + { 100, 99, }, + { 0, -1, }, }; int @@ -38,5 +41,8 @@ main () RUN (3, T, d[6][0], d[6][1]); RUN (3, T, d[7][0], d[7][1]); + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + return 0; } diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-4.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i64.c index 3dc4f72..40270ec 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-4.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i64.c @@ -7,6 +7,7 @@ DEF_SAT_S_ADD_IMM_FMT_1(0, int64_t, uint64_t, (-9223372036854775807ll - 1), INT6 DEF_SAT_S_ADD_IMM_FMT_1(1, int64_t, uint64_t, 9223372036854775807ll, INT64_MIN, INT64_MAX) DEF_SAT_S_ADD_IMM_FMT_1(2, int64_t, uint64_t, 100, INT64_MIN, INT64_MAX) DEF_SAT_S_ADD_IMM_FMT_1(3, int64_t, uint64_t, -100, INT64_MIN, INT64_MAX) +DEF_SAT_S_ADD_IMM_FMT_1(4, int64_t, uint64_t, -1, INT64_MIN, INT64_MAX) #define T int64_t #define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_1(INDEX, T, x, expect) @@ -21,6 +22,8 @@ T d[][2] = { { -1, 99, }, { 0, -100, }, { 100, 0, }, + { 0, -1, }, + { 100, 99, }, }; int @@ -38,5 +41,8 @@ main () RUN (3, T, d[6][0], d[6][1]); RUN (3, T, d[7][0], d[7][1]); + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + return 0; } diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i8.c index c71b717..9efb743 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i8.c @@ -7,6 +7,7 @@ DEF_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, -128, INT8_MIN, INT8_MAX) DEF_SAT_S_ADD_IMM_FMT_1(1, int8_t, uint8_t, 127, INT8_MIN, INT8_MAX) DEF_SAT_S_ADD_IMM_FMT_1(2, int8_t, uint8_t, 6, INT8_MIN, INT8_MAX) DEF_SAT_S_ADD_IMM_FMT_1(3, int8_t, uint8_t, -6, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD_IMM_FMT_1(4, int8_t, uint8_t, -1, INT8_MIN, INT8_MAX) #define T int8_t #define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_1(INDEX, T, x, expect) @@ -21,6 +22,8 @@ T d[][2] = { { -10, -4, }, { -128, -128, }, { 127, 121, }, + { -128, -128, }, + { 1, 0, }, }; int @@ -38,5 +41,8 @@ main () RUN (3, T, d[6][0], d[6][1]); RUN (3, T, d[7][0], d[7][1]); + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + return 0; } diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i16.c new file mode 100644 index 0000000..4f24624 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i16.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int16_t, uint16_t, -32768, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(1, int16_t, uint16_t, 32767, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(2, int16_t, uint16_t, 100, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(3, int16_t, uint16_t, -100, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(4, int16_t, uint16_t, -1, INT16_MIN, INT16_MAX) + +#define T int16_t +#define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_2(INDEX, T, x, expect) + +T d[][2] = { + /* arg_0, expect */ + { -1, -32768, }, + { 2, -32766, }, + { 1, 32767, }, + { -10, 32757, }, + { 32669, 32767, }, + { -32768, -32668, }, + { -32768, -32768, }, + { 0, -100, }, + { -32768, -32768, }, + { 0, -1, }, +}; + +int +main () +{ + RUN (0, T, d[0][0], d[0][1]); + RUN (0, T, d[1][0], d[1][1]); + + RUN (1, T, d[2][0], d[2][1]); + RUN (1, T, d[3][0], d[3][1]); + + RUN (2, T, d[4][0], d[4][1]); + RUN (2, T, d[5][0], d[5][1]); + + RUN (3, T, d[6][0], d[6][1]); + RUN (3, T, d[7][0], d[7][1]); + + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i32.c new file mode 100644 index 0000000..8d9ddeb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i32.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int32_t, uint32_t, -2147483648, INT32_MIN, INT32_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(1, int32_t, uint32_t, 2147483647, INT32_MIN, INT32_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(2, int32_t, uint32_t, 100, INT32_MIN, INT32_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(3, int32_t, uint32_t, -100, INT32_MIN, INT32_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(4, int32_t, uint32_t, -1, INT32_MIN, INT32_MAX) + +#define T int32_t +#define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_2(INDEX, T, x, expect) + +T d[][2] = { + /* arg_0, expect */ + { -1, -2147483648, }, + { 2, -2147483646, }, + { 1, 2147483647, }, + { -10, 2147483637, }, + { 300, 400, }, + { -300, -200, }, + { 100, 0, }, + { 0, -100, }, + { 100, 99, }, + { 0, -1, }, +}; + +int +main () +{ + RUN (0, T, d[0][0], d[0][1]); + RUN (0, T, d[1][0], d[1][1]); + + RUN (1, T, d[2][0], d[2][1]); + RUN (1, T, d[3][0], d[3][1]); + + RUN (2, T, d[4][0], d[4][1]); + RUN (2, T, d[5][0], d[5][1]); + + RUN (3, T, d[6][0], d[6][1]); + RUN (3, T, d[7][0], d[7][1]); + + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i64.c new file mode 100644 index 0000000..4523f9a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i64.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int64_t, uint64_t, (-9223372036854775807ll - 1), INT64_MIN, INT64_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(1, int64_t, uint64_t, 9223372036854775807ll, INT64_MIN, INT64_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(2, int64_t, uint64_t, 100, INT64_MIN, INT64_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(3, int64_t, uint64_t, -100, INT64_MIN, INT64_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(4, int64_t, uint64_t, -1, INT64_MIN, INT64_MAX) + +#define T int64_t +#define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_2(INDEX, T, x, expect) + +T d[][2] = { + /* arg_0, expect */ + { -1, (-9223372036854775807ll - 1), }, + { 2, -9223372036854775806ll, }, + { 1, 9223372036854775807ll, }, + { -7, 9223372036854775800ll, }, + { 0, 100, }, + { -1, 99, }, + { 0, -100, }, + { 100, 0, }, + { 0, -1, }, + { 100, 99, }, +}; + +int +main () +{ + RUN (0, T, d[0][0], d[0][1]); + RUN (0, T, d[1][0], d[1][1]); + + RUN (1, T, d[2][0], d[2][1]); + RUN (1, T, d[3][0], d[3][1]); + + RUN (2, T, d[4][0], d[4][1]); + RUN (2, T, d[5][0], d[5][1]); + + RUN (3, T, d[6][0], d[6][1]); + RUN (3, T, d[7][0], d[7][1]); + + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i8.c new file mode 100644 index 0000000..96445ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i8.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int8_t, uint8_t, -128, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(1, int8_t, uint8_t, 127, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(2, int8_t, uint8_t, 6, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(3, int8_t, uint8_t, -6, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(4, int8_t, uint8_t, -1, INT8_MIN, INT8_MAX) + +#define T int8_t +#define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_2(INDEX, T, x, expect) + +T d[][2] = { + /* arg_0, expect */ + { -1, -128, }, + { 2, -126, }, + { 1, 127, }, + { -10, 117, }, + { 122, 127, }, + { -10, -4, }, + { -128, -128, }, + { 127, 121, }, + { -128, -128, }, + { 1, 0, }, +}; + +int +main () +{ + RUN (0, T, d[0][0], d[0][1]); + RUN (0, T, d[1][0], d[1][1]); + + RUN (1, T, d[2][0], d[2][1]); + RUN (1, T, d[3][0], d[3][1]); + + RUN (2, T, d[4][0], d[4][1]); + RUN (2, T, d[5][0], d[5][1]); + + RUN (3, T, d[6][0], d[6][1]); + RUN (3, T, d[7][0], d[7][1]); + + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i16.c index e9f7080..e9f7080 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i16.c diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i32.c index 9dae425..9dae425 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i32.c diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i8.c index 84c6bc7..84c6bc7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i8.c diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i16.c new file mode 100644 index 0000000..a73a77f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int16_t, uint16_t, -32769, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(1, int16_t, uint16_t, 32768, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i32.c new file mode 100644 index 0000000..9dae425 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, -2147483649, INT32_MIN, INT32_MAX) +DEF_SAT_S_ADD_IMM_FMT_1(1, int32_t, uint32_t, 2147483648, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i8.c new file mode 100644 index 0000000..a9cd4b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int8_t, uint8_t, -129, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(1, int8_t, uint8_t, 128, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i16.c index c244eb4..734e8be 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i16.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int16_t_fmt_1: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_SUB_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i32.c index 9d8245d..3aa4c58 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i32.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int32_t_fmt_1: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srliw\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-7] -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c index 929de16..4c0caa1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c @@ -1,27 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int64_t_fmt_1: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i8.c index a918d5c..6c1441b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i8.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int8_t_fmt_1: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_SUB_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i16.c index 2da1c0d..57a4327 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i16.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int16_t_fmt_2: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_SUB_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i32.c index 20b28e7..28582fb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i32.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int32_t_fmt_2: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srliw\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-7] -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c index a540198..130ca46 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c @@ -1,27 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int64_t_fmt_2: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i8.c index c54057d..cd407b2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i8.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int8_t_fmt_2: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_SUB_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i16.c index 469a113..748d61a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i16.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int16_t_fmt_3: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_SUB_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i32.c index b2c03f6..be7869a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i32.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int32_t_fmt_3: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srliw\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-7] -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c index e3fe6c7..d16a7fb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c @@ -1,27 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int64_t_fmt_3: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i8.c index 150cde1..14a2454 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i8.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int8_t_fmt_3: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_SUB_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i16.c index 26d159c..614d1ec 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i16.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int16_t_fmt_4: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_SUB_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i32.c index d576c38..2f52bd7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i32.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int32_t_fmt_4: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srliw\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-7] -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c index f42ffea..cef478b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c @@ -1,27 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int64_t_fmt_4: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i8.c index ee510a6..3ed7790 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i8.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int8_t_fmt_4: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_SUB_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i16.c index e248b73..b2c5735 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i32.c index bebb4be..6d1518e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i64.c index f31eb29..adcd1bb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i8.c index e165e39..31fa0a6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i16.c index 08a9b5c..0c5ad8c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i32.c index fc79969..5e89539 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i64.c index 8d5f745..199e204 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i8.c index 9f6ef30..4cfe787 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i16.c index 0523d13..3cf4ecd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i32.c index e720964..ce2151c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i64.c index 49ed051..158eeaa 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i8.c index 99b413f..8eb7ab5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i16.c index c7056ed..339a403 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i32.c index 7168f94..285733a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i64.c index 29b2b54..546bac1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i8.c index 65027b7..dafc86f1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c index 451a375..6d1fbc4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_1: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_1(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c index 2aafb94..56a6699 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_1: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_1(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c index 6e21ee3..10c3320 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_1: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_1(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c index 5e971e4..558d704 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_1: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_1(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c index 87e5a52..02bef46 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_1: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_1(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c index 22a0dd4..da04904 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_1: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_1(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c index cb307ac..41391e2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_2: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_2(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c index b4bee21..3e5f9e1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_2: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_2(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c index c467c8d..228eeab 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_2: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_2(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c index 883b77b..78542ca 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_2: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_2(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c index bb9ffce..556e8ea 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_2: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_2(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c index a54db48..918a8c3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_2: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_2(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c index 219156c..13c0291 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_3: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_3(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c index 87b8a70..03077b7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_3: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_3(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c index 7acd515..e09a88d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_3: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_3(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c index 9141f08..ca071d1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_3: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_3(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c index 839a6f7..4acd93c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_3: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_3(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c index 5d13f09..362970c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_3: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_3(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c index 34dc804..94d9cc4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_4: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_4(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c index 89c476e..51a6e7b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_4: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_4(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c index 03ca7b7..9101b40 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_4: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_4(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c index aafe167..48452e3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_4: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_4(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c index 08e5eb3..6757913 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_4: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_4(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c index b0e71fe..9c65582 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_4: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_4(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c index b42c759..f02f866 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_5: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_5(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c index 625372e..6753c03 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_5: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_5(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c index 250e174..3fd17fa 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_5: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_5(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c index 4a6ac6d..fba761a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_5: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_5(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c index 02aa6db..8872f7f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_5: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_5(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c index ae1bcb9..13539aa 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_5: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_5(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c index 9a740d7..4aa9a8f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_6: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_6(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c index 1e42bfd..a772ee8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_6: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_6(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c index c3bd46d..9c5d88b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_6: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_6(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c index a6575f5..f9f18e9 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_6: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_6(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c index fd7b72e..3658fbb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_6: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_6(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c index 242d2d0..f1a7eb8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_6: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_6(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c index 3f258b8..50b06d5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_7: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_7(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c index f37a57e..12be220 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_7: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_7(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c index 4e4a7eb..cb73531 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_7: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_7(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c index 29b64b4..d52394c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_7: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_7(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c index 2bfe898..cf79778 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_7: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_7(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c index 494a314..67485a3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_7: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_7(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c index 678dec6..a34bf4a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_8: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_8(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c index 4acc789..9c25ff0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_8: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_8(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c index 34a992b..9ee75e2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_8: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_8(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c index 1919ba5..8cd361e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_8: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_8(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c index 541e55c..ace064b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_8: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_8(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c index 36a0085..e9a4d3b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_8: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_8(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i16-to-i8.c index 1f230c5..7ed6809 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i16.c index 563760b..82e4201 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i8.c index af50d3e..78be831 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i16.c index 4ac7025..e8a497f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i32.c index ca6d31c..1420541 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i8.c index 697e1bc..31fecc7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i16-to-i8.c index 0d9da40..333bb92 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i16.c index 2e183ef..f494909 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i8.c index 1950092..d8a619b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i16.c index b11b097..348832d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i32.c index 419e909..fc183cf 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i8.c index de3d9f1..dec54d3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i16-to-i8.c index 032c83b..2b8700a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i16.c index 51f4946..cf3f763 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i8.c index b959bce..20a68bb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i16.c index ddfb522..5159ab1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i32.c index 22965e2..edeff90 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i8.c index 7cba408..7a22637 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i16-to-i8.c index 6dfdd4b..65f9aea 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i16.c index fcf8e47..ab32e5d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i8.c index 9d911a4..eecfc49 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i16.c index 3cc2498..410d202 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i32.c index b9abf50..17518ba 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i8.c index d90682f..bf0c43e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i16-to-i8.c index 1911166..bac1fda 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i16.c index 28116eb..3a82ea0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i8.c index 54b1ffb..26a89e7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i16.c index 633417b..a8bfeef 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i32.c index c5e4e4a..f79a049 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i8.c index 9acbee0..eea31af 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i16-to-i8.c index db1a698..0ea32f0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i16.c index e6b52d4..39e44d8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i8.c index d83836d..cb42b7e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i16.c index e910edf..f64a46b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i32.c index 98dd0c2..18e9029 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i8.c index b843300..d8cda79 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i16-to-i8.c index ab51ad5..894d5f5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i16.c index 9b2c525..1ced757 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i8.c index ab409f2..ab41a84 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i16.c index 9013952..c078136 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i32.c index 67e19e7..af86e69 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i8.c index a573706..4a2532d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i16-to-i8.c index dbd70de..65c82ad 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i16.c index 25bb42f..a8cb8e1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i8.c index 7c71b3d..5b5f8f4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i16.c index 61392b5..f489846 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i32.c index b47e5da..a3f3ae5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i8.c index 1cd7f80..aafe96b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u16.c index 3c916bc..8f1b5c0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint16_t_fmt_1: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_FMT_1(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u32.c index edded3e..2c66eee 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint32_t_fmt_1: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a[01],\s*a[01] -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_FMT_1(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u64.c index 821e4bc..28d7b7c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_fmt_1: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_FMT_1(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u8.c index fd73c3a..ab18336 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint8_t_fmt_1: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_1(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u16.c index a166d28..c03b15d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint16_t_fmt_2: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_FMT_2(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u32.c index c06731b..f753c01 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint32_t_fmt_2: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a[01],\s*a[01] -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_FMT_2(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u64.c index ae10dff..cad539c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_fmt_2: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_FMT_2(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u8.c index f3977be..b595241 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint8_t_fmt_2: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_2(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u16.c index 5898c3b..08cd820 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint16_t_fmt_3: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_FMT_3(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u32.c index a1017c9..e0b73748 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint32_t_fmt_3: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a[01],\s*a[01] -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_FMT_3(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u64.c index 83fcb60..7ce0121 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_fmt_3: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_FMT_3(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u8.c index 2c398e0c..48f61c1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint8_t_fmt_3: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_3(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u16.c index c18a5d59..49d5af1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint16_t_fmt_4: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_FMT_4(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u32.c index fa2e55d..20ad476 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint32_t_fmt_4: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a[01],\s*a[01] -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_FMT_4(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u64.c index 6818c0c..6d2c9a7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_fmt_4: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_FMT_4(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u8.c index 1096de8..15e613b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint8_t_fmt_4: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_4(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u16.c index fd4be5c..225ba0c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint16_t_fmt_5: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_FMT_5(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u32.c index 4fbc807..106baf7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint32_t_fmt_5: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a[01],\s*a[01] -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_FMT_5(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u64.c index 5bc2948..48e84f6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_fmt_5: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_FMT_5(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u8.c index 74109c3..9c0d42a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint8_t_fmt_5: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_5(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u16.c index 3cb9cbe..0b541e0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint16_t_fmt_6: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_FMT_6(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u32.c index fd1cb1a..ee79156 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint32_t_fmt_6: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a[01],\s*a[01] -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_FMT_6(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u64.c index c968f33..fd79139 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_fmt_6: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_FMT_6(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u8.c index 9cd95ad..f826aa4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint8_t_fmt_6: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_6(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c index 527f8de..446a951 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint32_t_uint16_t_fmt_7: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_FMT_7(uint32_t, uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c index e9031de..626effc 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_uint16_t_fmt_7: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_FMT_7(uint64_t, uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c index a71bd2f..3014634 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_uint32_t_fmt_7: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a[01],\s*a[01] -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_FMT_7(uint64_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c index 5892986..541a1d8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint16_t_uint8_t_fmt_7: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_7(uint16_t, uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c index a42a712..26749a8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint32_t_uint8_t_fmt_7: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_7(uint32_t, uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c index f37ef1c..321f662 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_uint8_t_fmt_7: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_7(uint64_t, uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u16.c new file mode 100644 index 0000000..a7062b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_8(uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u32.c new file mode 100644 index 0000000..2e43c7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_8(uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u64.c new file mode 100644 index 0000000..4ad18c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_8(uint64_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u8.c new file mode 100644 index 0000000..608d31b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_8(uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u16.c new file mode 100644 index 0000000..b9766d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_9(uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u32.c new file mode 100644 index 0000000..2456d39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_9(uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u64.c new file mode 100644 index 0000000..0a0ff24 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_9(uint64_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u8.c new file mode 100644 index 0000000..53879dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_9(uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u16.c index cb3879d..548fae3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u16.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_1 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_1(T) +DEF_SAT_U_ADD_FMT_1_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_1_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u32.c index c9a6080..e76b636 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u32.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_1 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_1(T) +DEF_SAT_U_ADD_FMT_1_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_1_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u64.c index c19b7e2..0ea6509 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u64.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_1 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_1(T) +DEF_SAT_U_ADD_FMT_1_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_1_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u8.c index f197249..3aa7441 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u8.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_1 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_1(T) +DEF_SAT_U_ADD_FMT_1_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_1_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u16.c index 99b5c3a..f6f8b9d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u16.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_2(T) +DEF_SAT_U_ADD_FMT_2_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_2_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u32.c index 13f5954..da8c3eb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u32.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_2(T) +DEF_SAT_U_ADD_FMT_2_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_2_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u64.c index cdbea7b..03f5960 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u64.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_2(T) +DEF_SAT_U_ADD_FMT_2_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_2_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u8.c index 508531c..af898e55 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u8.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_2(T) +DEF_SAT_U_ADD_FMT_2_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_2_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u16.c index bd935dc..7862a48 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u16.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_3 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_3(T) +DEF_SAT_U_ADD_FMT_3_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_3_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u32.c index deccf9a..d2fbcf2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u32.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_3 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_3(T) +DEF_SAT_U_ADD_FMT_3_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_3_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u64.c index 4f99367..23b5488 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u64.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_3 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_3(T) +DEF_SAT_U_ADD_FMT_3_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_3_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u8.c index 670932f..b5931d4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u8.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_3 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_3(T) +DEF_SAT_U_ADD_FMT_3_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_3_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u16.c index 33a595d..a9937a7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u16.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_4 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_4(T) +DEF_SAT_U_ADD_FMT_4_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_4_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u32.c index 8a5b7c1..966831a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u32.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_4 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_4(T) +DEF_SAT_U_ADD_FMT_4_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_4_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u64.c index fa20aae..08db7a1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u64.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_4 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_4(T) +DEF_SAT_U_ADD_FMT_4_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_4_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u8.c index 083d6e5..f7bbb5a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u8.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_4 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_4(T) +DEF_SAT_U_ADD_FMT_4_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_4_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u16.c index a1d5d70..da1782d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u16.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_5(T) +DEF_SAT_U_ADD_FMT_5_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_5_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u32.c index 7608e71..524106a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u32.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_5(T) +DEF_SAT_U_ADD_FMT_5_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_5_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u64.c index 496ab58..62fdd25 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u64.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_5(T) +DEF_SAT_U_ADD_FMT_5_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_5_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u8.c index 936028c..334eb04 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u8.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_5(T) +DEF_SAT_U_ADD_FMT_5_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_5_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u16.c index d304288..28a2fb8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u16.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_6(T) +DEF_SAT_U_ADD_FMT_6_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_6_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u32.c index 1a1ea59..3b19af3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u32.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_6(T) +DEF_SAT_U_ADD_FMT_6_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_6_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u64.c index dc977d5..f35334a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u64.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_6(T) +DEF_SAT_U_ADD_FMT_6_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_6_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u8.c index 8bc204e..e04fbf0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u8.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_6(T) +DEF_SAT_U_ADD_FMT_6_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_6_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c index 25dc1d1..3363220 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c @@ -1,26 +1,16 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define WT uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP +#define T1 uint16_t +#define T2 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c index 565b108..bc4ca2f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c @@ -1,26 +1,16 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define WT uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP +#define T1 uint16_t +#define T2 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c index 6ff34fd..04abd95 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c @@ -1,26 +1,16 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define WT uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP +#define T1 uint32_t +#define T2 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c index 9e6e70a..c514a86 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c @@ -1,26 +1,16 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define WT uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP +#define T1 uint8_t +#define T2 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c index a1134ed..b1a644b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c @@ -1,26 +1,16 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define WT uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP +#define T1 uint8_t +#define T2 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c index ef9f7aa..8664ffa 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c @@ -1,26 +1,16 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define WT uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP +#define T1 uint8_t +#define T2 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u16.c new file mode 100644 index 0000000..aaf13be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_8_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_8_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u32.c new file mode 100644 index 0000000..0ec8d90 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_8_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_8_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u64.c new file mode 100644 index 0000000..f367f67 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_8_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_8_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u8.c new file mode 100644 index 0000000..0fd4036 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_8_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_8_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u16.c new file mode 100644 index 0000000..4289e2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_9_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_9_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u32.c new file mode 100644 index 0000000..d3dd52e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_9_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_9_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u64.c new file mode 100644 index 0000000..a9f0964 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_9_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_9_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u8.c new file mode 100644 index 0000000..91cdb7e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_9_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_9_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u16.c index 3c31ac3..b6388dc 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm3_uint16_t_fmt_1: -** addi\s+[atx][0-9]+,\s*a0,\s*3 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 3) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u32.c index c6b352c..cae6796 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm7_uint32_t_fmt_1: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*a0,\s*7 -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 7) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u64.c index 1d9df3c..f9d6939 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm8_uint64_t_fmt_1: -** addi\s+[atx][0-9]+,\s*a0,\s*8 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 8) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u8.c index 101acd8..d90209a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm9_uint8_t_fmt_1: -** addi\s+[atx][0-9]+,\s*a0,\s*9 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 9) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u16.c index ac57cc9..a34194d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm3_uint16_t_fmt_2: -** addi\s+[atx][0-9]+,\s*a0,\s*3 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 3) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u32.c index 6aca60c..9a801d2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm7_uint32_t_fmt_2: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*a0,\s*7 -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 7) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u64.c index d041724..2eb57a3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm8_uint64_t_fmt_2: -** addi\s+[atx][0-9]+,\s*a0,\s*8 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 8) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u8.c index 7baeb8d..363b2df 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm9_uint8_t_fmt_2: -** addi\s+[atx][0-9]+,\s*a0,\s*9 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 9) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u16.c index 6dbabf6..aaf1209 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm3_uint16_t_fmt_3: -** addi\s+[atx][0-9]+,\s*a0,\s*3 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 3) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u32.c index 1c52b21..e430b37 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm7u_uint32_t_fmt_3: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*a0,\s*7 -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 7u) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u64.c index ef60ce2..aef5c58 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm8ull_uint64_t_fmt_3: -** addi\s+[atx][0-9]+,\s*a0,\s*8 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 8ull) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u8.c index 81a4b21..039d982 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm9_uint8_t_fmt_3: -** addi\s+[atx][0-9]+,\s*a0,\s*9 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 9) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u16.c index 2f6c0460..baf70c3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm3_uint16_t_fmt_4: -** addi\s+[atx][0-9]+,\s*a0,\s*3 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 3) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u32.c index 1fc9a50..a4bfe50 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm7u_uint32_t_fmt_4: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*a0,\s*7 -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 7u) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u64.c index 0ca423c..f355de6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm8ull_uint64_t_fmt_4: -** addi\s+[atx][0-9]+,\s*a0,\s*8 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 8ull) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u8.c index c8a43fa..54880d7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm9_uint8_t_fmt_4: -** addi\s+[atx][0-9]+,\s*a0,\s*9 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 9) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u16.c index 090c765..e715bb0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u32.c index 8dade74..8b8b475 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u64.c index ace2df8..f6f6408 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u8.c index 0ce546f..f2154fc 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u16.c index 7b6bd73..8e3aa83 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u32.c index 8024152..403cf14 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u64.c index 4a76dbb..17eca5e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u8.c index 8e8759c..9a277a1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u16.c index 64924a6..2068037 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u32.c index 04f3217..5f8f1e6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u64.c index 8ef6c14..c574521 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u8.c index 8867361..6b9439a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u16.c index 0b75206..224c3ae 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u32.c index e548d0c..5c03e1b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u64.c index 4335d82..1ceacd2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u8.c index 872923e..aef253c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u128.c new file mode 100644 index 0000000..cd6f2f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u32.c new file mode 100644 index 0000000..7409232 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u64.c new file mode 100644 index 0000000..43ab563 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u128.c new file mode 100644 index 0000000..dea9f6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c new file mode 100644 index 0000000..8d5449b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c new file mode 100644 index 0000000..d8a01d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint64_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u128.c new file mode 100644 index 0000000..dfc9d2e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u16.c new file mode 100644 index 0000000..ec79e5d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u16.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint16_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u32.c new file mode 100644 index 0000000..eb95184 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u64.c new file mode 100644 index 0000000..ee41593 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u16-from-u64.c new file mode 100644 index 0000000..b1d33a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u16-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u32-from-u64.c new file mode 100644 index 0000000..af5ffecf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u32-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u8-from-u64.c new file mode 100644 index 0000000..d65cab0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u8-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c new file mode 100644 index 0000000..79f6297 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u32.c new file mode 100644 index 0000000..e212391 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c new file mode 100644 index 0000000..79d3fb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c new file mode 100644 index 0000000..e5a9462 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint32_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c new file mode 100644 index 0000000..ad63db3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint32_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c new file mode 100644 index 0000000..cbe2a22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint64_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c new file mode 100644 index 0000000..1f54c30 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u16.c new file mode 100644 index 0000000..f5a0ab5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint16_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u32.c new file mode 100644 index 0000000..32074a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c new file mode 100644 index 0000000..16ca905 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u16.c index eb140ae..66a439e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_1: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_1(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u32.c index 59ad242..6f40907 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_1: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_1(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u64.c index 47a8382..647fc6d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_1: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_1(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u8.c index f01317b..a344c58 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_1: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_1(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u16.c index 4b7bd3a..87fb1fc 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_10: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_10(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u32.c index a28213f..280236a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_10: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_10(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u64.c index 432da0c..4b7d339 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_10: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_10(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u8.c index 0658d38..191c3a5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_10: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_10(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u16.c index 2e4b875..9dc41e1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_11: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_11(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u32.c index 61fb80f..475f944 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_11: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_11(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u64.c index 2a28b1f..61e3584 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_11: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_11(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u8.c index 3033844..7a61055 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_11: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_11(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u16.c index 9cb86df..c4d21cb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_12: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_12(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u32.c index babe768..56beb83 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_12: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_12(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u64.c index 294ef5a..1bef3fe 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_12: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_12(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u8.c index 8b8f924..9004281 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_12: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_12(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u16.c index e724752..7b85582 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_2: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_2(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u32.c index 9240406..cfdf66c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_2: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_2(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u64.c index 3e1efba..3898817 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_2: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_2(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u8.c index 600688a..3318211 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_2: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_2(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u16.c index bb2d0b7..61bb5e5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_3: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_3(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u32.c index 06635df..73bfa99 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_3: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_3(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u64.c index ac485da..24d1e69 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_3: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_3(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u8.c index cdc8776..5523112 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_3: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_3(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u16.c index 407ff8f..fb6a604 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_4: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_4(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u32.c index cb2cd05..0f7e2d3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_4: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_4(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u64.c index 0ce6269..c762647 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_4: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_4(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u8.c index 302206a..3e5d2e6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_4: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_4(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u16.c index ce2758f..ab1b375 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_5: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_5(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u32.c index d33cef3..1b8ce84 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_5: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_5(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u64.c index 1bf1e97..3fc4e7a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_5: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_5(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u8.c index b2ed732..5c34ead 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_5: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_5(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u16.c index 20614ec..70dc6ec 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_6: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_6(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u32.c index 5d7adfd..cc36036 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_6: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_6(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u64.c index b3c6f8d..ea633ff 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_6: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_6(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u8.c index a4f92a8..7c4747a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_6: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_6(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u16.c index ebfe673..cac8471 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_7: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_7(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u32.c index 9884123..18b8e5f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_7: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_7(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u64.c index 67236d5..f5ade61 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_7: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_7(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u8.c index 549d9d2..9b528a4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_7: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_7(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u16.c index aa5aec7..0d093c3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_8: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_8(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u32.c index 89a8cc9..f04ea1d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_8: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_8(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u64.c index a52948d..17dd8f3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_8: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_8(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u8.c index 5606733..b043207 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_8: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_8(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u16.c index 984867a..19b1a5b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_9: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_9(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u32.c index d1109a4..a0026a1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_9: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_9(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u64.c index a9acf15..01c155e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_9: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_9(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u8.c index 47551fa..7b94d40 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_9: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_9(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u16.c index 1534cf9..20e14d6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u32.c index 5c60d28..1a0c394 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u64.c index 403764c..ee348b3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u8.c index 931420a..216af86 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u16.c index ae87544..109539d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u32.c index 43414ae..9e35fa2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u64.c index 3ef70a1..3c7c8db 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u8.c index 2a157f0..df291e2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u16.c index 534795c..88dded4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u32.c index 4d0a34f..239b422 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u64.c index d74d10d..9a524fd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u8.c index 949bd0d..b9b84ea 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u16.c index 80cce95..91bd9de 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u32.c index 3ecd19c..eaaa256 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u64.c index 2d7bfc4..04d2a20 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u8.c index 209965c..caedfe7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u16.c index 7deaae9a5..06a44f1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u32.c index d9b1d5c..9d38c9c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u64.c index 2774c23..5c10409 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u8.c index 6fa44ca..0ff9827 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u16.c index ea52ff4..aab99ca 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u32.c index fdea891..5231d6f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u64.c index 164ee77..d7462a8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u8.c index 724adf9..5da7838 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u16.c index 9b57861..8e69888 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u32.c index df2eece..9b22dda 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u64.c index 09e9ac3..abd0a95 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u8.c index c8ae7a6..d92c0e1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u16.c index 9f575a47..b404bfd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u32.c index c370455..b746712 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u64.c index 22d82f9..da90b7a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u8.c index b282311..38dcabe 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u16.c index e0dda45..fd55bec 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u32.c index dfd95ef..2e810dd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u64.c index 7cac446..e86eebc 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u8.c index 0b4cbdb..e749bb5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u16.c index 10c65fe..eb57d55 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u32.c index e3b4dde..c1a5bcf 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u64.c index 6e93fcf..27d4b82 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u8.c index d101d28..feb56e1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u16.c index 4e50e3f..a22f1df 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u32.c index 3c8f78d..b98931d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u64.c index 932596a..dff3c0a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u8.c index 1f74562..d2f3126 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u16.c index 66a82f2..3740099 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u32.c index a54b5c3..b6ae459 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u64.c index 97943b3e..55198d6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u8.c index ab8b475..ce73d26 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-1.c index 573ef11..475b31e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-1.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm32768_uint16_t_fmt_1: -** li\s+[atx][0-9]+,\s*32768 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint16_t, 32768) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-2.c index 0fefbe7..a984f84b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-2.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm65533_uint16_t_fmt_1: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-3 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint16_t, 65533) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-3.c index ad6d4f9..b2930d4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-3.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm65534_uint16_t_fmt_1: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-2 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint16_t, 65534) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-4.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-4.c index 02dcbc5..362cf48 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-4.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-4.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint16_t_fmt_1: -** li\s+[atx][0-9]+,\s*1 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint16_t, 1) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16.c index 7346fbb..9f17082 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm6_uint16_t_fmt_1: -** li\s+[atx][0-9]+,\s*6 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint16_t, 6) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-1.c index c7dac8a..801a86e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-1.c @@ -1,23 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm2147483648_uint32_t_fmt_1: -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint32_t, 2147483648) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-2.c index 4320db3..e044768 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-2.c @@ -1,24 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm68719476732_uint32_t_fmt_1: -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-4 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint32_t, 68719476732) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-3.c index 765d13c..5518064 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-3.c @@ -1,24 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm4294967294_uint32_t_fmt_1: -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-2 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint32_t, 4294967294) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-4.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-4.c index ca11cf1..a4cb49b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-4.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-4.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint32_t_fmt_1: -** li\s+[atx][0-9]+,\s*1 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint32_t, 1) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32.c index 3711930..64808bf 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm255_uint32_t_fmt_1: -** li\s+[atx][0-9]+,\s*255 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint32_t, 255) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-1.c index 2e490f0..493a14d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-1.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm18446744073709551614u_uint64_t_fmt_1: -** li\s+[atx][0-9]+,\s*-2 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint64_t, 18446744073709551614u) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-2.c index 45baa8f..4faae52 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-2.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint64_t_fmt_1: -** li\s+[atx][0-9]+,\s*1 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint64_t, 1) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64.c index a29a6e9..3f993fd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm82_uint64_t_fmt_1: -** li\s+[atx][0-9]+,\s*82 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint64_t, 82) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-1.c index d1c6e94..a0d9235 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-1.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm128_uint8_t_fmt_1: -** li\s+[atx][0-9]+,\s*128 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint8_t, 128) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-2.c index 4c8cf90..67dae03 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-2.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm253_uint8_t_fmt_1: -** li\s+[atx][0-9]+,\s*253 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint8_t, 253) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-3.c index b958f5e..0054532 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-3.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm254_uint8_t_fmt_1: -** li\s+[atx][0-9]+,\s*254 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint8_t, 254) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-4.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-4.c index 1951ec5..c12b560 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-4.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-4.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint8_t_fmt_1: -** li\s+[atx][0-9]+,\s*1 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint8_t, 1) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8.c index 86d0b39..ce9f495 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm11_uint8_t_fmt_1: -** li\s+[atx][0-9]+,\s*11 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint8_t, 11) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-1.c index 31c1bb8..93d7169 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-1.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm32768_uint16_t_fmt_2: -** li\s+[atx][0-9]+,\s*32768 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 32768) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-2.c index 68807b9..8ac2ce8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-2.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm65533_uint16_t_fmt_2: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-3 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 65533) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-3.c index 62deec1..740d6ac 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-3.c @@ -1,18 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint16_t_fmt_2: -** snez\s+[atx][0-9]+,\s*a0 -** subw\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 1) /* { dg-final { scan-tree-dump-not ".SAT_SUB" "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16.c index f789fee..c82c478 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm6_uint16_t_fmt_2: -** addi\s+[atx][0-9]+,\s*a0,\s*-6 -** sltiu\s+a0,\s*[atx][0-9]+,\s*6 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 6) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-1.c index 2f4a439..b2f690a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-1.c @@ -1,23 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm2147483648_uint32_t_fmt_2: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 2147483648) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-2.c index dcfba62..e62010b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-2.c @@ -1,24 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm68719476732_uint32_t_fmt_2: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-4 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 68719476732) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-3.c index a3f48f7..dd063d8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-3.c @@ -1,16 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint32_t_fmt_2: -** snez\s+[atx][0-9]+,\s*a0 -** subw\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ - DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 1) /* { dg-final { scan-tree-dump-not ".SAT_SUB" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32.c index 0bd8ddc..c0eb8a7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm255_uint32_t_fmt_2: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** addi\s+[atx][0-9]+,\s*a0,\s*-255 -** sltiu\s+a0,\s*[atx][0-9]+,\s*255 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 255) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64-1.c index 7b6d857..ed69313 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64-1.c @@ -1,16 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint64_t_fmt_2: -** snez\s+[atx][0-9]+,\s*a0 -** sub\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ - DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 1) /* { dg-final { scan-tree-dump-not ".SAT_SUB" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64.c index c334665..fb7db13 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64.c @@ -1,18 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm82_uint64_t_fmt_2: -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-82 -** sltiu\s+a0,\s*[atx][0-9]+,\s*82 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 82) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-1.c index 26e77f0..efe6c00 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-1.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm128_uint8_t_fmt_2: -** addi\s+[atx][0-9]+,\s*a0,\s*-128 -** sltiu\s+a0,\s*[atx][0-9]+,\s*128 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 128) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-2.c index c5ac1b0..1262648 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-2.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm253_uint8_t_fmt_2: -** addi\s+[atx][0-9]+,\s*a0,\s*-253 -** sltiu\s+a0,\s*[atx][0-9]+,\s*253 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 253) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-3.c index ee59b5a..108daf2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-3.c @@ -1,17 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint8_t_fmt_2: -** snez\s+[atx][0-9]+,\s*a0 -** subw\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ - DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 1) /* { dg-final { scan-tree-dump-not ".SAT_SUB" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8.c index 69dcc2a..784a97b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm11_uint8_t_fmt_2: -** addi\s+[atx][0-9]+,\s*a0,\s*-11 -** sltiu\s+a0,\s*[atx][0-9]+,\s*11 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 11) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-1.c index f312362..0f16f9c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-1.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm32769_uint16_t_fmt_3: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 32769) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-2.c index fa9a9ef..49daab5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-2.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm65533_uint16_t_fmt_3: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-3 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 65533) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16.c index b98de41..30fc2bf 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm6_uint16_t_fmt_3: -** li\s+[atx][0-9]+,\s*6 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 6) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-1.c index 79457a3..2d3c63d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-1.c @@ -1,24 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm2147483649_uint32_t_fmt_3: -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 2147483649) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-2.c index 2e8426e..8d96c00 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-2.c @@ -1,24 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm68719476732_uint32_t_fmt_3: -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-4 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 68719476732) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32.c index 845218c..c06c441 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm255_uint32_t_fmt_3: -** li\s+[atx][0-9]+,\s*255 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 255) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u64.c index ee2fbf8..4d2b96d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u64.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm82_uint64_t_fmt_3: -** li\s+[atx][0-9]+,\s*82 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint64_t, 82) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-1.c index 8cc81e2..8c3eb14 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-1.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm134_uint8_t_fmt_3: -** li\s+[atx][0-9]+,\s*134 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 134) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-2.c index 8d8c70b..b02d832 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-2.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm253_uint8_t_fmt_3: -** li\s+[atx][0-9]+,\s*253 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 253) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8.c index 348d75b..d8e0a69 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm11_uint8_t_fmt_3: -** li\s+[atx][0-9]+,\s*11 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 11) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-1.c index 089c168..8f3726f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-1.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm32768_uint16_t_fmt_4: -** li\s+[atx][0-9]+,\s*32768 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 32768) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-2.c index b96e3f3..56c377e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-2.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm65533_uint16_t_fmt_4: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-3 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 65533) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16.c index 5c209bc..29c6b86 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm6_uint16_t_fmt_4: -** addi\s+[atx][0-9]+,\s*a0,\s*-6 -** sltiu\s+a0,\s*[atx][0-9]+,\s*6 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 6) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-1.c index 2f4a439..b2f690a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-1.c @@ -1,23 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm2147483648_uint32_t_fmt_2: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 2147483648) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-2.c index dcfba62..e62010b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-2.c @@ -1,24 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm68719476732_uint32_t_fmt_2: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-4 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 68719476732) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32.c index ee1ad9a..6cfb1e4c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm255_uint32_t_fmt_4: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** addi\s+[atx][0-9]+,\s*a0,\s*-255 -** sltiu\s+a0,\s*[atx][0-9]+,\s*255 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_4(uint32_t, 255) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u64.c index c334665..fb7db13 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u64.c @@ -1,18 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm82_uint64_t_fmt_2: -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-82 -** sltiu\s+a0,\s*[atx][0-9]+,\s*82 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 82) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-1.c index 3fe4103..49a4150 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-1.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm128_uint8_t_fmt_4: -** addi\s+[atx][0-9]+,\s*a0,\s*-128 -** sltiu\s+a0,\s*[atx][0-9]+,\s*128 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 128) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-2.c index 18dc505..1022de2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-2.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm253_uint8_t_fmt_4: -** addi\s+[atx][0-9]+,\s*a0,\s*-253 -** sltiu\s+a0,\s*[atx][0-9]+,\s*253 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 253) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8.c index 5c40f32..48aaeb2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm11_uint8_t_fmt_4: -** addi\s+[atx][0-9]+,\s*a0,\s*-11 -** sltiu\s+a0,\s*[atx][0-9]+,\s*11 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 11) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u16.c index 2bc3be3..a193d88 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u32.c index b1d1ee3..e1dd81c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u64.c index 2539d75..a71526c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u8.c index 5091872..4fedf96 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u16.c index 0f4f9e4..f990c43 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u32.c index ea15d85..44d5e88 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u64.c index 612da92..91ea986 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u8.c index fc38095..7da49eb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u16.c index 150ab2a..8c44ee0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u32.c index c7d2850..f5c4e5a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u64.c index 6bf5cd2..393f7f6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u8.c index dfef1f2..e46463b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u16.c index 610e021..3062e0f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u32.c index 1d9e0cb..e621cd2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u64.c index f864a67..cfc96bf 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u8.c index 603f2ee..771ec4a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u16.c index b73290a..d368621 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u16.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint16_t_fmt_1: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_1(uint16_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u32.c index 8af803f..02ca992 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u32.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint32_t_fmt_1: -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_TRUNC_FMT_1(uint32_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u64.c index 1c887d4..cc01abd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint8_t_fmt_1: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_1(uint8_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u8.c index 6bcf64b..e28ee5c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u8.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint16_t_to_uint8_t_fmt_1: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_1(uint8_t, uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u16.c index 8a35e72..59302cb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u16.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint16_t_fmt_1: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_1(uint16_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u32.c index a3b52de..735ea7e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u32.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint16_t_to_uint8_t_fmt_2: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_2(uint8_t, uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u64.c index b9b43f1..8fd3f43 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u64.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint16_t_fmt_2: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_2(uint16_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u8.c index 7ed3623..bb4ecc5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u8.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint8_t_fmt_1: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_1(uint8_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u16.c index 7572c9e..e476897 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u16.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint8_t_fmt_2: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_2(uint8_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u32.c index d83b5dd..524d625 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u32.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint8_t_fmt_2: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_2(uint8_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u64.c index b7202f9..ba8b238 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u64.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint16_t_fmt_2: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_2(uint16_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u8.c index e90b853..cba8573 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint32_t_fmt_2: -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_TRUNC_FMT_2(uint32_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u16.c index e8655b9..5852028 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u16.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint16_t_fmt_3: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_3(uint16_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u32.c index 41e676a..5d5cf97 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u32.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint32_t_fmt_3: -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_TRUNC_FMT_3(uint32_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u64.c index 32eeb88..866e240 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint8_t_fmt_3: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_3(uint8_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u8.c index 5d043ce..f3adfb6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u8.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint16_t_to_uint8_t_fmt_3: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_3(uint8_t, uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u16.c index 7e5906b..4e132a9 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u16.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint16_t_fmt_3: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_3(uint16_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u32.c index e1b0acd..893f43e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u32.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint16_t_to_uint8_t_fmt_4: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_4(uint8_t, uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u64.c index 618d50bd..5c0c7a7e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u64.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint16_t_fmt_4: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_4(uint16_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u8.c index c9a9a4c..395bb1b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u8.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint8_t_fmt_3: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_3(uint8_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u16.c index 418cdc8..8f20c8f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u16.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint8_t_fmt_4: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_4(uint8_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u32.c index 4903a04..f7e7ff2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u32.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint8_t_fmt_4: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_4(uint8_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u64.c index 6f8191c..2d9b6a6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u64.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint16_t_fmt_4: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_4(uint16_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u8.c index 24bb846..4fa81fe 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint32_t_fmt_4: -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_TRUNC_FMT_4(uint32_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u16.c index a5f43e9..72c175c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u32.c index a76ae08..aef195a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u64.c index d05ea79..4517418 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u8.c index adaa421..2e51023 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u16.c index 38fcba3..8ea83d6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u32.c index 93705f9..1d0dd5b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u64.c index c116484..f69968c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u8.c index 4fbdc91..dcff0b4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u16.c index 2281610..33f46ec 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u32.c index 126c97c..b9c4617 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u64.c index 61ad79d..21755a7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u8.c index 4142e87..bcf2081 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u16.c index 8952c06..69f5352 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u32.c index 8952c06..69f5352 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u64.c index 20ceda6..f001c39 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u8.c index 7011e50..1394d9f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u16.c index e868da1..de5d723 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u32.c index 7f52283..c345bfa 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u64.c index ee13f0a..8ca8cc7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u8.c index 8471c76..54e00e8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u16.c index f056bd4..a957cc3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u32.c index 96c06eb..9691b4d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u64.c index 1623e52..ff2c2a5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u8.c index a1b8a5f..918eabb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/ventana-16122.c b/gcc/testsuite/gcc.target/riscv/ventana-16122.c new file mode 100644 index 0000000..59e6467 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/ventana-16122.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { rv64 } } } */ + +extern void NG (void); +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed int int32_t; +void f74(void) { + int16_t x309 = 0x7fff; + volatile int32_t x310 = 0x7fffffff; + int8_t x311 = 59; + int16_t x312 = -0x8000; + static volatile int32_t t74 = 614992577; + + t74 = (x309==((x310^x311)%x312)); + + if (t74 != 0) { NG(); } else { ; } + +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadint-push-pop.c b/gcc/testsuite/gcc.target/riscv/xtheadint-push-pop.c index dc5609c..167fa15 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadint-push-pop.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadint-push-pop.c @@ -20,12 +20,6 @@ void func_machine (void) /* { dg-final { scan-assembler-times {\mth\.ipop\M} 2 { target { rv32 } } } } */ -__attribute__ ((interrupt ("user"))) -void func_usr (void) -{ - f (); -} - __attribute__ ((interrupt ("supervisor"))) void func_supervisor (void) { diff --git a/gcc/testsuite/gcc.target/riscv/zalrsc.c b/gcc/testsuite/gcc.target/riscv/zalrsc.c new file mode 100644 index 0000000..19a26bf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zalrsc.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64imfd_zalrsc -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } {"-O0"} } */ + +/* lr.w/sc.w */ +int *i; +int lr_sc(int v) +{ + return __atomic_exchange_4(i, v, __ATOMIC_RELAXED); +} + +/* { dg-final { scan-assembler-times {\mlr.w} 1 } } */ +/* { dg-final { scan-assembler-times {\msc.w} 1 } } */ +/* { dg-final { scan-assembler-not {"mv\t"} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c index c123bb5..69914db 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c +++ b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ long foo (long i) diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c new file mode 100644 index 0000000..1ad1b77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mtune=generic" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mtune=generic" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-O3" } } */ + +#define N 10000 + +int primitiveSemantics_compare_reg_reg_return_reg_reg_00(int *a, int min_v) +{ + int last = 0; + + for (int i = 0; i < N; i++) + { + if (a[i] < min_v) + last = a[i]; + } + return last; +} + +/* { dg-final { scan-assembler-times {\mczero\.nez\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mczero\.eqz\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-1.c b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-1.c new file mode 100644 index 0000000..3602626 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i_zilsd -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +long long y; +long long foo(long long x) +{ + return y + x; +} + +/* { dg-final { scan-assembler-times "ld\t" 1 } } */ +/* { dg-final { scan-assembler-not "lw\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-2.c b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-2.c new file mode 100644 index 0000000..3adcd21 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i_zilsd -mabi=ilp32" } */ + +long long y; +long long foo(long long x) +{ + return y >> x; +} +/* TODO: We should not split that 64 bit load into two 32 bit load if we have + zilsd, but we split that during the expand time, so it's hard to fix via cost + model turning, we could either fix that for expander, or...combine those two + 32 bit load back later. */ +/* { dg-final { scan-assembler-times "ld\t" 1 { xfail riscv*-*-* } } } */ + +/* Os and Oz will use libcall, so the 64 bit load won't be split. */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zilsd-code-gen.c b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen.c new file mode 100644 index 0000000..9155622 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i_zilsd -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +long long foo1(long long *a) +{ + return *a; +} + +long long g; + +void foo2(long long a) +{ + g = a; +} + +/* { dg-final { scan-assembler-times "ld\t" 1 } } */ +/* { dg-final { scan-assembler-times "sd\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-1.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-1.c new file mode 100644 index 0000000..671c0ed --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-1.c @@ -0,0 +1,103 @@ +/* { dg-do compile { target { lp64 } } } */ +/* { dg-options "-O2 -march=z13 -mzarch" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* +** test_in_1: +** foo %r2 +** br %r14 +*/ + +int +test_in_1 (int x) +{ + asm ("foo %0" :: "{r2}" (x)); + return x; +} + +/* +** test_in_2: +** lgr (%r[0-9]+),%r2 +** lr %r2,%r3 +** foo %r2 +** lgr %r2,\1 +** br %r14 +*/ + +int +test_in_2 (int x, int y) +{ + asm ("foo %0" :: "{r2}" (y)); + return x; +} + +/* +** test_in_3: +** stmg %r12,%r15,96\(%r15\) +** lay %r15,-160\(%r15\) +** lgr (%r[0-9]+),%r2 +** ahi %r2,1 +** lgfr %r2,%r2 +** brasl %r14,foo@PLT +** lr %r3,%r2 +** lr %r2,\1 +** foo %r3,%r2 +** lgr %r2,\1 +** lmg %r12,%r15,256\(%r15\) +** br %r14 +*/ + +extern int foo (int); + +int +test_in_3 (int x) +{ + asm ("foo %0,%1\n" :: "{r3}" (foo (x + 1)), "{r2}" (x)); + return x; +} + +/* +** test_out_1: +** foo %r3 +** lgfr %r2,%r3 +** br %r14 +*/ + +int +test_out_1 (void) +{ + int x; + asm ("foo %0" : "={r3}" (x)); + return x; +} + +/* +** test_out_2: +** lgr (%r[0-9]+),%r2 +** foo %r2 +** ark (%r[0-9]+),\1,%r2 +** lgfr %r2,\2 +** br %r14 +*/ + +int +test_out_2 (int x) +{ + int y; + asm ("foo %0" : "={r2}" (y)); + return x + y; +} + +/* +** test_inout_1: +** foo %r2 +** lgfr %r2,%r2 +** br %r14 +*/ + +int +test_inout_1 (int x) +{ + asm ("foo %0" : "+{r2}" (x)); + return x; +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-2.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-2.c new file mode 100644 index 0000000..a892fe8 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-2.c @@ -0,0 +1,43 @@ +/* { dg-do compile { target { lp64 } } } */ +/* { dg-options "-O2 -march=z13 -mzarch" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ +/* { dg-final { scan-assembler {\.LC0:\n\t\.long\t1078523331\n} } } */ + + +/* +** test_float_into_gpr: +** lrl %r4,.LC0 +** foo %r4 +** br %r14 +*/ + +void +test_float_into_gpr (void) +{ + // This is the counterpart to + // register float x asm ("r4") = 3.14f; + // asm ("foo %0" :: "r" (x)); + // where the bit-pattern of 3.14f is loaded into GPR. + asm ("foo %0" :: "{r4}" (3.14f)); +} + +/* +** test_float: +** ( +** ldr %f4,%f0 +** ldr %f5,%f2 +** | +** ldr %f5,%f2 +** ldr %f4,%f0 +** ) +** aebr %f5,%f4 +** ldr %f0,%f5 +** br %r14 +*/ + +float +test_float (float x, float y) +{ + asm ("aebr %0,%1" : "+{f5}" (y) : "{f4}" (x)); + return y; +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-3.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-3.c new file mode 100644 index 0000000..5df37b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-3.c @@ -0,0 +1,42 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -march=z13 -mzarch" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ +/* { dg-final { scan-assembler {\.LC0:\n\t\.long\t1074339512\n\t\.long\t1374389535\n} } } */ + +/* +** test_double_into_gpr: +** lgrl %r4,.LC0 +** foo %r4 +** br %r14 +*/ + +void +test_double_into_gpr (void) +{ + // This is the counterpart to + // register double x asm ("r4") = 3.14; + // asm ("foo %0" :: "r" (x)); + // where the bit-pattern of 3.14 is loaded into GPR. + asm ("foo %0" :: "{r4}" (3.14)); +} + +/* +** test_double: +** ( +** ldr %f4,%f0 +** ldr %f5,%f2 +** | +** ldr %f5,%f2 +** ldr %f4,%f0 +** ) +** adbr %f5,%f4 +** ldr %f0,%f5 +** br %r14 +*/ + +double +test_double (double x, double y) +{ + asm ("adbr %0,%1" : "+{f5}" (y) : "{f4}" (x)); + return y; +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-4.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-4.c new file mode 100644 index 0000000..29927ce --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-4.c @@ -0,0 +1,6 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O2 -march=z13 -mzarch" } */ + +/* Test TARGET_MD_ASM_ADJUST for z13 and long double. */ + +#include "asm-hard-reg-longdouble.h" diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-5.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-5.c new file mode 100644 index 0000000..eaf34d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-5.c @@ -0,0 +1,6 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O2 -march=z14 -mzarch" } */ + +/* Test TARGET_MD_ASM_ADJUST for z14 and long double. */ + +#include "asm-hard-reg-longdouble.h" diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-6.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-6.c new file mode 100644 index 0000000..d012966 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-6.c @@ -0,0 +1,152 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +test (void) +{ + // GPRs + { + int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p; + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14" + : "=r" (a), + "=r" (b), + "=r" (c), + "=r" (d), + "=r" (e), + "=r" (f), + "=r" (g), + "=r" (h), + "=r" (i), + "=r" (j), + "=r" (k), + "=r" (l), + "=r" (m), + "=r" (n), + "=r" (o)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14" + : "={r0}" (a), + "={r1}" (b), + "={r2}" (c), + "={r3}" (d), + "={r4}" (e), + "={r5}" (f), + "={r6}" (g), + "={r7}" (h), + "={r8}" (i), + "={r9}" (j), + "={r10}" (k), + "={r11}" (l), + "={r12}" (m), + "={r13}" (n), + "={r14}" (o)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15" /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + : "=r" (a), + "=r" (b), + "=r" (c), + "=r" (d), + "=r" (e), + "=r" (f), + "=r" (g), + "=r" (h), + "=r" (i), + "=r" (j), + "=r" (k), + "=r" (l), + "=r" (m), + "=r" (n), + "=r" (o), + "=r" (p)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15" /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + : "=r" (a), + "=r" (b), + "=r" (c), + "=r" (d), + "=r" (e), + "=r" (f), + "=r" (g), + "=r" (h), + "=r" (i), + "=r" (j), + "=r" (k), + "=r" (l), + "=r" (m), + "=r" (n), + "=r" (o), + "={r4}" (p)); + } + + // FPRs + { + float a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q; + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15" + : "=f" (a), + "=f" (b), + "=f" (c), + "=f" (d), + "=f" (e), + "=f" (f), + "=f" (g), + "=f" (h), + "=f" (i), + "=f" (j), + "=f" (k), + "=f" (l), + "=f" (m), + "=f" (n), + "=f" (o), + "=f" (p)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15" + : "={f0}" (a), + "={f1}" (b), + "={f2}" (c), + "={f3}" (d), + "={f4}" (e), + "={f5}" (f), + "={f6}" (g), + "={f7}" (h), + "={f8}" (i), + "={f9}" (j), + "={f10}" (k), + "={f11}" (l), + "={f12}" (m), + "={f13}" (n), + "={f14}" (o), + "={f15}" (p)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16" /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + : "=f" (a), + "=f" (b), + "=f" (c), + "=f" (d), + "=f" (e), + "=f" (f), + "=f" (g), + "=f" (h), + "=f" (i), + "=f" (j), + "=f" (k), + "=f" (l), + "=f" (m), + "=f" (n), + "=f" (o), + "=f" (p), + "=f" (q)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16" /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + : "=f" (a), + "=f" (b), + "=f" (c), + "=f" (d), + "=f" (e), + "=f" (f), + "=f" (g), + "=f" (h), + "=f" (i), + "=f" (j), + "=f" (k), + "=f" (l), + "=f" (m), + "=f" (n), + "=f" (o), + "=f" (p), + "={f4}" (q)); + } +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-7.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-7.c new file mode 100644 index 0000000..923c9d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-7.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=z13" } */ + +/* Test register pairs. */ + +void +test (void) +{ + register double f0 __asm__ ("f0"); + register double f2 __asm__ ("f2"); + register long double f0f2 __asm__ ("f0"); + double x; + long double y; + + /* Outputs */ + __asm__ __volatile__ ("" : "=r" (f0), "=r" (f0f2)); + __asm__ __volatile__ ("" : "=r" (f0f2), "={f0}" (y)); /* { dg-error "multiple outputs to hard register: %f0" } */ + __asm__ __volatile__ ("" : "={f0}" (x), "=r" (f0f2)); /* { dg-error "multiple outputs to hard register: %f0" } */ + + __asm__ __volatile__ ("" : "=r" (f2), "=r" (f0f2)); + __asm__ __volatile__ ("" : "={f2}" (x), "={f0}" (y)); /* { dg-error "multiple outputs to hard register: %f2" } */ + __asm__ __volatile__ ("" : "=r" (f2), "={f0}" (y)); /* { dg-error "multiple outputs to hard register: %f2" } */ + __asm__ __volatile__ ("" : "={f2}" (x), "=r" (f0f2)); /* { dg-error "multiple outputs to hard register: %f2" } */ + + /* Inputs */ + __asm__ __volatile__ ("" :: "r" (f0), "r" (f0f2)); + __asm__ __volatile__ ("" :: "r" (f0f2), "{f0}" (y)); /* { dg-error "multiple inputs to hard register: %f0" } */ + __asm__ __volatile__ ("" :: "{f0}" (x), "r" (f0f2)); /* { dg-error "multiple inputs to hard register: %f0" } */ + + __asm__ __volatile__ ("" :: "r" (f2), "r" (f0f2)); + __asm__ __volatile__ ("" :: "{f2}" (x), "{f0}" (y)); /* { dg-error "multiple inputs to hard register: %f2" } */ + __asm__ __volatile__ ("" :: "r" (f2), "{f0}" (y)); /* { dg-error "multiple inputs to hard register: %f2" } */ + __asm__ __volatile__ ("" :: "{f2}" (x), "r" (f0f2)); /* { dg-error "multiple inputs to hard register: %f2" } */ +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-longdouble.h b/gcc/testsuite/gcc.target/s390/asm-hard-reg-longdouble.h new file mode 100644 index 0000000..9f4adad --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-longdouble.h @@ -0,0 +1,18 @@ +__attribute__ ((noipa)) +long double +test_longdouble (long double x) +{ + long double y; + asm ("sqxbr\t%0,%1" : "={f4}" (y) : "{f5}" (x)); + return y; +} + +int +main (void) +{ + long double x = test_longdouble (42.L); + long double y = 6.48074069840786023096596743608799656681773277430814773408787249757445105002862106857719481922686100006103515625L; + if (x != y) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/s390/fminmax-1.c b/gcc/testsuite/gcc.target/s390/fminmax-1.c new file mode 100644 index 0000000..df10905 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/fminmax-1.c @@ -0,0 +1,77 @@ +/* Check fmin/fmax expanders for scalars on VXE targets. */ + +/* { dg-do compile } */ +/* { dg-options "-O2 -march=z14 -mzarch" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** dofmaxl: +** vl (%v.),0\(%r3\),3 +** vl (%v.),0\(%r4\),3 +** wfmaxxb (%v.),\1,\2,4 +** vst \3,0\(%r2\),3 +** br %r14 +*/ +long double +dofmaxl (long double d1, long double d2) +{ + return __builtin_fmaxl (d1, d2); +} + +/* +** dofminl: +** vl (%v.),0\(%r3\),3 +** vl (%v.),0\(%r4\),3 +** wfminxb (%v.),\1,\2,4 +** vst \3,0\(%r2\),3 +** br %r14 +*/ +long double +dofminl (long double d1, long double d2) +{ + return __builtin_fminl (d1, d2); +} + +/* +** dofmax: +** wfmaxdb %v0,%v0,%v2,4 +** br %r14 +*/ +double +dofmax (double d1, double d2) +{ + return __builtin_fmax (d1, d2); +} + +/* +** dofmin: +** wfmindb %v0,%v0,%v2,4 +** br %r14 +*/ +double +dofmin (double d1, double d2) +{ + return __builtin_fmin (d1, d2); +} + +/* +** dofmaxf: +** wfmaxsb %v0,%v0,%v2,4 +** br %r14 +*/ +float +dofmaxf (float f1, float f2) +{ + return __builtin_fmaxf (f1, f2); +} + +/* +** dofminf: +** wfminsb %v0,%v0,%v2,4 +** br %r14 +*/ +float +dofminf (float f1, float f2) +{ + return __builtin_fminf (f1, f2); +} diff --git a/gcc/testsuite/gcc.target/s390/fminmax-2.c b/gcc/testsuite/gcc.target/s390/fminmax-2.c new file mode 100644 index 0000000..ea37a0a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/fminmax-2.c @@ -0,0 +1,29 @@ +/* Check fmin/fmax expanders for scalars on non-VXE targets. */ + +/* { dg-do compile } */ +/* { dg-options "-O2 -march=z13 -mzarch" } */ +/* { dg-final { scan-assembler-times "jg" 4 } } */ + +double +dofmax (double d1, double d2) +{ + return __builtin_fmax (d1, d2); +} + +double +dofmin (double d1, double d2) +{ + return __builtin_fmin (d1, d2); +} + +float +dofmaxf (float f1, float f2) +{ + return __builtin_fmaxf (f1, f2); +} + +float +dofminf (float f1, float f2) +{ + return __builtin_fminf (f1, f2); +} diff --git a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c index 2ff5a37..e1c7806 100644 --- a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c +++ b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c @@ -3,8 +3,10 @@ #include "isfinite-isinf-isnormal-signbit.h" -/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 1 } } SIGNBIT long double */ -/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 } } SIGNBIT _Decimal128 */ +/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 0 { target lp64 } } } SIGNBIT long double */ +/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 0 { target lp64 } } } SIGNBIT _Decimal128 */ +/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } SIGNBIT long double */ +/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } SIGNBIT _Decimal128 */ /* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,4032} 1 } } ISFINITE long double */ /* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,4032} 1 } } ISFINITE _Decimal128 */ /* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,48} 1 } } ISINF long double */ diff --git a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c index 8f67553..5c9986d 100644 --- a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c +++ b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c @@ -3,8 +3,10 @@ #include "isfinite-isinf-isnormal-signbit.h" -/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 1 } } */ -/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 } } */ +/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 0 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 0 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } */ /* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,4032} 1 } } */ /* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,4032} 1 } } */ /* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,48} 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/signbit-1.c b/gcc/testsuite/gcc.target/s390/signbit-1.c new file mode 100644 index 0000000..45f608a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -march=z900 -save-temps" } */ +/* { dg-final { scan-assembler-times {\ttceb\t} 2 } } */ +/* { dg-final { scan-assembler-times {\ttcdb\t} 2 } } */ +/* { dg-final { scan-assembler-times {\ttcxb\t} 2 } } */ + +/* Binary Floating-Point */ + +__attribute__ ((noipa)) +int signbit_float_reg (float x) { return __builtin_signbit (x); } +__attribute__ ((noipa)) +int signbit_float_mem (float *x) { return __builtin_signbit (*x); } +__attribute__ ((noipa)) +int signbit_double_reg (double x) { return __builtin_signbit (x); } +__attribute__ ((noipa)) +int signbit_double_mem (double *x) { return __builtin_signbit (*x); } + +__attribute__ ((noipa)) +int +signbit_longdouble_reg (long double x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +__attribute__ ((noipa)) +int signbit_longdouble_mem (long double *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (float, float, __builtin_inff(), __builtin_nanf("42"), 0.f, 42.f) +TEST (double, double, __builtin_inf(), __builtin_nan("42"), 0., 42.) +TEST (longdouble, long double, __builtin_infl(), __builtin_nanl("42"), 0.L, 42.L) + +int +main (void) +{ + test_float (); + test_double (); + test_longdouble (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit-2.c b/gcc/testsuite/gcc.target/s390/signbit-2.c new file mode 100644 index 0000000..488c477 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-2.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -march=z9-ec -mzarch -save-temps" } */ +/* { dg-final { scan-assembler-times {\ttdcet\t} 2 } } */ +/* { dg-final { scan-assembler-times {\ttdcdt\t} 2 } } */ +/* { dg-final { scan-assembler-times {\ttdcxt\t} 2 } } */ + +/* Decimal Floating-Point */ + +__attribute__ ((noipa)) +int signbit_dec32_reg (_Decimal32 x) { return __builtin_signbit (x); } +__attribute__ ((noipa)) +int signbit_dec32_mem (_Decimal32 *x) { return __builtin_signbit (*x); } +__attribute__ ((noipa)) +int signbit_dec64_reg (_Decimal64 x) { return __builtin_signbit (x); } +__attribute__ ((noipa)) +int signbit_dec64_mem (_Decimal64 *x) { return __builtin_signbit (*x); } + +__attribute__ ((noipa)) +int +signbit_dec128_reg (_Decimal128 x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +__attribute__ ((noipa)) +int signbit_dec128_mem (_Decimal128 *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (dec32, _Decimal32, __builtin_infd32(), __builtin_nand32("42"), 0.df, 42.df) +TEST (dec64, _Decimal64, __builtin_infd64(), __builtin_nand64("42"), 0.dd, 42.dd) +TEST (dec128, _Decimal128, __builtin_infd128(), __builtin_nand128("42"), 0.dl, 42.dl) + +int +main (void) +{ + test_dec32 (); + test_dec64 (); + test_dec128 (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit-3.c b/gcc/testsuite/gcc.target/s390/signbit-3.c new file mode 100644 index 0000000..2fad58b --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-3.c @@ -0,0 +1,152 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O2 -march=z10 -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* Binary Floating-Point */ + +/* +** signbit_float_reg: +** lgdr (%r[0-9]+),%f0 +** srlg (%r[0-9]+),\1,63 +** lgfr %r2,\2 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_float_reg (float x) { return __builtin_signbit (x); } + +/* +** signbit_float_mem: +** l (%r[0-9]+),0\(%r2\) +** srl \1,31 +** lgfr %r2,\1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_float_mem (float *x) { return __builtin_signbit (*x); } + +/* +** signbit_double_reg: +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_double_reg (double x) { return __builtin_signbit (x); } + +/* +** signbit_double_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_double_mem (double *x) { return __builtin_signbit (*x); } + +/* +** signbit_longdouble_reg: +** ld %f0,0\(%r2\) +** ld %f2,8\(%r2\) +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int +signbit_longdouble_reg (long double x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +/* +** signbit_longdouble_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_longdouble_mem (long double *x) { return __builtin_signbit (*x); } + +/* Decimal Floating-Point */ + +/* +** signbit_dec32_reg: +** lgdr (%r[0-9]+),%f0 +** srlg (%r[0-9]+),\1,63 +** lgfr %r2,\2 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec32_reg (_Decimal32 x) { return __builtin_signbit (x); } + +/* +** signbit_dec32_mem: +** l (%r[0-9]+),0\(%r2\) +** srl \1,31 +** lgfr %r2,\1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec32_mem (_Decimal32 *x) { return __builtin_signbit (*x); } + +/* +** signbit_dec64_reg: +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec64_reg (_Decimal64 x) { return __builtin_signbit (x); } + +/* +** signbit_dec64_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec64_mem (_Decimal64 *x) { return __builtin_signbit (*x); } + +/* +** signbit_dec128_reg: +** ld %f0,0\(%r2\) +** ld %f2,8\(%r2\) +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int +signbit_dec128_reg (_Decimal128 x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +/* +** signbit_dec128_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec128_mem (_Decimal128 *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (float, float, __builtin_inff(), __builtin_nanf("42"), 0.f, 42.f) +TEST (double, double, __builtin_inf(), __builtin_nan("42"), 0., 42.) +TEST (longdouble, long double, __builtin_infl(), __builtin_nanl("42"), 0.L, 42.L) +TEST (dec32, _Decimal32, __builtin_infd32(), __builtin_nand32("42"), 0.df, 42.df) +TEST (dec64, _Decimal64, __builtin_infd64(), __builtin_nand64("42"), 0.dd, 42.dd) +TEST (dec128, _Decimal128, __builtin_infd128(), __builtin_nand128("42"), 0.dl, 42.dl) + +int +main (void) +{ + test_float (); + test_double (); + test_longdouble (); + test_dec32 (); + test_dec64 (); + test_dec128 (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit-4.c b/gcc/testsuite/gcc.target/s390/signbit-4.c new file mode 100644 index 0000000..2cb743e --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-4.c @@ -0,0 +1,55 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-require-effective-target s390_vx } */ +/* { dg-options "-O2 -march=z13 -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* Binary Floating-Point */ + +/* +** signbit_float_reg: +** vlgvf (%r[0-9]+),%v0,0 +** risbgn %r2,\1,64-1,128\+63,32\+1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_float_reg (float x) { return __builtin_signbit (x); } + +/* +** signbit_float_mem: +** l (%r[0-9]+),0\(%r2\) +** risbgn %r2,\1,64-1,128\+63,32\+1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_float_mem (float *x) { return __builtin_signbit (*x); } + +/* Decimal Floating-Point */ + +/* +** signbit_dec32_reg: +** vlgvf (%r[0-9]+),%v0,0 +** risbgn %r2,\1,64-1,128\+63,32\+1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec32_reg (_Decimal32 x) { return __builtin_signbit (x); } + +/* +** signbit_dec32_mem: +** l (%r[0-9]+),0\(%r2\) +** risbgn %r2,\1,64-1,128\+63,32\+1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec32_mem (_Decimal32 *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (float, float, __builtin_inff(), __builtin_nanf("42"), 0.f, 42.f) +TEST (dec32, _Decimal32, __builtin_infd32(), __builtin_nand32("42"), 0.df, 42.df) + +int +main (void) +{ + test_float (); + test_dec32 (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit-5.c b/gcc/testsuite/gcc.target/s390/signbit-5.c new file mode 100644 index 0000000..6840327 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-5.c @@ -0,0 +1,35 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O2 -march=z14 -save-temps" } */ + +/* +** signbit_longdouble_reg: +** ld %f0,0(%r2);ld %f2,8+0(%r2) +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int +signbit_longdouble_reg (long double x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +/* +** signbit_longdouble_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_longdouble_mem (long double *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (longdouble, long double, __builtin_infl(), __builtin_nanl("42"), 0.L, 42.L) + +int +main (void) +{ + test_longdouble (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit.h b/gcc/testsuite/gcc.target/s390/signbit.h new file mode 100644 index 0000000..730e387 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit.h @@ -0,0 +1,36 @@ +#define TEST(T, U, I, N, C0, C42) \ + void test_##T (void) \ + { \ + U tmp; \ + int x; \ + \ + x = signbit_##T##_reg(C42); \ + x += signbit_##T##_reg(C0); \ + x += signbit_##T##_reg(I); \ + x += signbit_##T##_reg(N); \ + tmp = C42; \ + x += signbit_##T##_mem(&tmp); \ + tmp = C0; \ + x += signbit_##T##_mem(&tmp); \ + tmp = I; \ + x += signbit_##T##_mem(&tmp); \ + tmp = N; \ + x += signbit_##T##_mem(&tmp); \ + if (x != 0) \ + __builtin_abort(); \ + \ + x = signbit_##T##_reg(-C42); \ + x += signbit_##T##_reg(-C0); \ + x += signbit_##T##_reg(-I); \ + x += signbit_##T##_reg(-N); \ + tmp = -C42; \ + x += signbit_##T##_mem(&tmp); \ + tmp = -C0; \ + x += signbit_##T##_mem(&tmp); \ + tmp = -I; \ + x += signbit_##T##_mem(&tmp); \ + tmp = -N; \ + x += signbit_##T##_mem(&tmp); \ + if (x != 8) \ + __builtin_abort(); \ + } diff --git a/gcc/testsuite/gcc.target/s390/spaceship-fp-1.c b/gcc/testsuite/gcc.target/s390/spaceship-fp-1.c new file mode 100644 index 0000000..56c3d77 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-fp-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 2\)} 3 optimized } } */ +/* { dg-final { scan-assembler-times {\tk[edx]br\t} 3 } } */ +/* { dg-final { scan-assembler-not {\tbrc} } } */ +/* { dg-final { scan-assembler-not {\tc[edx]br\t} } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else if (x > y) \ + return 1; \ + else \ + return 2; \ + } + +TEST (float, float) +TEST (double, double) +TEST (long double, longdouble) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-fp-2.c b/gcc/testsuite/gcc.target/s390/spaceship-fp-2.c new file mode 100644 index 0000000..0c6e6b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-fp-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -ffinite-math-only -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 2\)} 3 optimized } } */ +/* { dg-final { scan-assembler-times {\tc[edx]br\t} 3 } } */ +/* { dg-final { scan-assembler-not {\tbrc} } } */ +/* { dg-final { scan-assembler-not {\tk[edx]br\t} } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else if (x > y) \ + return 1; \ + else \ + return 2; \ + } + +TEST (float, float) +TEST (double, double) +TEST (long double, longdouble) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-fp-3.c b/gcc/testsuite/gcc.target/s390/spaceship-fp-3.c new file mode 100644 index 0000000..2f567d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-fp-3.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 42\)} 3 optimized } } */ +/* { dg-final { scan-assembler-times {\tk[edx]br\t} 3 } } */ +/* { dg-final { scan-assembler-not {\tbrc} } } */ +/* { dg-final { scan-assembler-not {\tc[edx]br\t} } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else if (x > y) \ + return 1; \ + else \ + return 42; \ + } + +TEST (float, float) +TEST (double, double) +TEST (long double, longdouble) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-fp-4.c b/gcc/testsuite/gcc.target/s390/spaceship-fp-4.c new file mode 100644 index 0000000..4531ecb --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-fp-4.c @@ -0,0 +1,53 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 0\)} 3 optimized } } */ +/* { dg-final { scan-assembler-times {\tk[edx]br\t} 3 } } */ +/* { dg-final { scan-assembler-not {\tloc} } } */ +/* { dg-final { scan-assembler-not {\tbrc} } } */ +/* { dg-final { scan-assembler-not {\tc[edx]br\t} } } */ + +/* By time of writing this we emit + + kebr %f0,%f2 + jo .L2 + je .L3 + jnh .L10 + jg f3@PLT +.L10: + jg f2@PLT +.L3: + jg f1@PLT +.L2: + jg f4@PLT + + which is not optimal. Instead we could fold the conditional branch with the + unconditional into something along the lines + + kebr %f0,%f2 + jo f4@PLT + je f1@PLT + jnh f2@PLT + jg f3@PLT +*/ + +void f1 (void); +void f2 (void); +void f3 (void); +void f4 (void); + +#define TEST(T, U) \ + void test_##U (T x, T y) \ + { \ + if (x == y) \ + f1 (); \ + else if (x < y) \ + f2 (); \ + else if (x > y) \ + f3 (); \ + else \ + f4 (); \ + } + +TEST (float, float) +TEST (double, double) +TEST (long double, longdouble) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-int-1.c b/gcc/testsuite/gcc.target/s390/spaceship-int-1.c new file mode 100644 index 0000000..8ca2677 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-int-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, -1\)} 4 optimized } } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 1\)} 5 optimized } } */ +/* { dg-final { scan-assembler-times {\tlhi} 9 } } */ +/* { dg-final { scan-assembler-times {\tloc} 18 } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else \ + return 1; \ + } + +TEST(signed char, schar) +TEST(unsigned char, uchar) +TEST(char, char) + +TEST(short, sshort) +TEST(unsigned short, ushort) + +TEST(int, sint) +TEST(unsigned int, uint) + +TEST(long, slong) +TEST(unsigned long, ulong) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-int-2.c b/gcc/testsuite/gcc.target/s390/spaceship-int-2.c new file mode 100644 index 0000000..5f7975c --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-int-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, -1\)} 1 optimized } } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 1\)} 1 optimized } } */ +/* { dg-final { scan-assembler-times {\tvecg} 1 } } */ +/* { dg-final { scan-assembler-times {\tveclg} 1 } } */ +/* { dg-final { scan-assembler-times {\tvchlgs} 2 } } */ +/* { dg-final { scan-assembler-times {\tvceqgs} 2 } } */ +/* { dg-final { scan-assembler-times {\tlhi} 2 } } */ +/* { dg-final { scan-assembler-times {\tloc} 4 } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else \ + return 1; \ + } + +TEST(__int128, sint128) +TEST(unsigned __int128, uint128) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-int-3.c b/gcc/testsuite/gcc.target/s390/spaceship-int-3.c new file mode 100644 index 0000000..46b0e4a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-int-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -march=z17 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, -1\)} 1 optimized } } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 1\)} 1 optimized } } */ +/* { dg-final { scan-assembler-times {\tvecq\t} 1 } } */ +/* { dg-final { scan-assembler-times {\tveclq\t} 1 } } */ +/* { dg-final { scan-assembler-times {\tloc} 4 } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else \ + return 1; \ + } + +TEST(__int128, sint128) +TEST(unsigned __int128, uint128) diff --git a/gcc/testsuite/gcc.target/s390/stack-protector-guard-tls-1.c b/gcc/testsuite/gcc.target/s390/stack-protector-guard-tls-1.c new file mode 100644 index 0000000..1efd245 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/stack-protector-guard-tls-1.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fstack-protector-all" } */ +/* { dg-final { scan-assembler-times {\tear\t%r[0-9]+,%a[01]} 8 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\tsllg\t%r[0-9]+,%r[0-9]+,32} 4 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\tear\t%r[0-9]+,%a[01]} 3 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times {\tmvc\t160\(8,%r15\),40\(%r[0-9]+\)} 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\tmvc\t100\(4,%r15\),20\(%r[0-9]+\)} 2 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times {\tclc\t160\(8,%r15\),40\(%r[0-9]+\)} 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\tclc\t100\(4,%r15\),20\(%r[0-9]+\)} 2 { target { ! lp64 } } } } */ + +/* Computing the address of the thread pointer on s390 involves multiple + instructions and therefore bears the risk that the address of the canary or + intermediate values of it are spilled and reloaded. Therefore, as a + precaution compute the address always twice, i.e., one time for the prologue + and one time for the epilogue. */ + +void test_0 (void) { } + +void test_1 (void) +{ + __asm__ __volatile ("" ::: + "r0", + "r1", + "r2", + "r3", + "r4", + "r5", + "r6", + "r7", + "r8", + "r9", + "r10", + "r11", +#ifndef __PIC__ + "r12", +#endif + "r13", + "r14"); +} diff --git a/gcc/testsuite/gcc.target/s390/vector/pattern-avg-1.c b/gcc/testsuite/gcc.target/s390/vector/pattern-avg-1.c new file mode 100644 index 0000000..285ebc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/pattern-avg-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=z16 -ftree-vectorize -fdump-tree-optimized" } */ + +#define TEST(T1,T2,N) \ + void \ + avg##T1 (signed T1 *__restrict res, signed T1 *__restrict a, \ + signed T1 *__restrict b) \ + { \ + for (int i = 0; i < N; ++i) \ + res[i] = ((signed T2)a[i] + b[i] + 1) >> 1; \ + } \ + \ + void \ + uavg##T1 (unsigned T1 *__restrict res, unsigned T1 *__restrict a, \ + unsigned T1 *__restrict b) \ + { \ + for (int i = 0; i < N; ++i) \ + res[i] = ((unsigned T2)a[i] + b[i] + 1) >> 1; \ + } + +TEST(char,short,16) +TEST(short,int,8) +TEST(int,long,4) + +/* { dg-final { scan-tree-dump-times "\.AVG_CEIL" 6 "optimized" { target lp64 } } } */ +/* { dg-final { scan-tree-dump-times "\.AVG_CEIL" 4 "optimized" { target { ! lp64 } } } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/pattern-avg-2.c b/gcc/testsuite/gcc.target/s390/vector/pattern-avg-2.c new file mode 100644 index 0000000..1cc614e --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/pattern-avg-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O3 -mzarch -march=z16 -ftree-vectorize -fdump-tree-optimized" } */ + +#define TEST(T1,T2,N) \ + void \ + avg##T1 (signed T1 *__restrict res, signed T1 *__restrict a, \ + signed T1 *__restrict b) \ + { \ + for (int i = 0; i < N; ++i) \ + res[i] = ((signed T2)a[i] + b[i] + 1) >> 1; \ + } \ + \ + void \ + uavg##T1 (unsigned T1 *__restrict res, unsigned T1 *__restrict a, \ + unsigned T1 *__restrict b) \ + { \ + for (int i = 0; i < N; ++i) \ + res[i] = ((unsigned T2)a[i] + b[i] + 1) >> 1; \ + } + +TEST(long,__int128,2) + +/* { dg-final { scan-tree-dump-times "\.AVG_CEIL" 2 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/pattern-mulh-1.c b/gcc/testsuite/gcc.target/s390/vector/pattern-mulh-1.c new file mode 100644 index 0000000..f0b37d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/pattern-mulh-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=arch15 -ftree-vectorize -fdump-tree-optimized" } */ + +#define TEST(T1,T2,N,S) \ + void \ + mulh##T1 (signed T1 *__restrict res, \ + signed T1 *__restrict l, \ + signed T1 *__restrict r) \ + { \ + for (int i = 0; i < N; ++i) \ + res[i] = (signed T1) (((signed T2)l[i] * (signed T2)r[i]) >> S); \ + } \ + \ + void \ + umulh##T1 (unsigned T1 *__restrict res, \ + unsigned T1 *__restrict l, \ + unsigned T1 *__restrict r) \ + { \ + for (int i = 0; i < N; ++i) \ + res[i] = (unsigned T1) \ + (((unsigned T2)l[i] * (unsigned T2)r[i]) >> S); \ + } + +TEST(char,short,16,8) +TEST(short,int,8,16) + +/* { dg-final { scan-tree-dump-times "\.MULH" 4 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/pattern-mulh-2.c b/gcc/testsuite/gcc.target/s390/vector/pattern-mulh-2.c new file mode 100644 index 0000000..2ff66b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/pattern-mulh-2.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O3 -mzarch -march=arch15 -ftree-vectorize -fdump-tree-optimized" } */ + +#define TEST(T1,T2,N,S) \ + void \ + mulh##T1 (signed T1 *__restrict res, \ + signed T1 *__restrict l, \ + signed T1 *__restrict r) \ + { \ + for (int i = 0; i < N; ++i) \ + res[i] = (signed T1) (((signed T2)l[i] * (signed T2)r[i]) >> S); \ + } \ + \ + void \ + umulh##T1 (unsigned T1 *__restrict res, \ + unsigned T1 *__restrict l, \ + unsigned T1 *__restrict r) \ + { \ + for (int i = 0; i < N; ++i) \ + res[i] = (unsigned T1) \ + (((unsigned T2)l[i] * (unsigned T2)r[i]) >> S); \ + } + +TEST(int,long,4,32) +TEST(long,__int128,2,64) + +/* { dg-final { scan-tree-dump-times "\.MULH" 4 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/reduc-binops-1.c b/gcc/testsuite/gcc.target/s390/vector/reduc-binops-1.c new file mode 100644 index 0000000..efd3294 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/reduc-binops-1.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=z13 -ftree-vectorize -fdump-tree-optimized" } */ + +#define T(X,N) \ + unsigned X \ + reduce_and_##X (unsigned X *in) \ + { \ + unsigned X acc = (unsigned X)-1; \ + for (int i = 0; i < N; i++) \ + acc &= in[i]; \ + return acc; \ + } \ + unsigned X \ + reduce_ior_##X (unsigned X *in) \ + { \ + unsigned X acc = 0; \ + for (int i = 0; i < N; i++) \ + acc |= in[i]; \ + return acc; \ + } \ + unsigned X \ + redue_xor_##X (unsigned X *in) \ + { \ + unsigned X acc = 0; \ + for (int i = 0; i < N; i++) \ + acc ^= in[i]; \ + return acc; \ + } + +T(char,16) + +T(short, 8) + +T(int,4) + +T(long,4) + +/* { dg-final { scan-tree-dump-times "\.REDUC_AND" 4 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.REDUC_IOR" 4 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.REDUC_XOR" 4 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/reduc-minmax-1.c b/gcc/testsuite/gcc.target/s390/vector/reduc-minmax-1.c new file mode 100644 index 0000000..5295250 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/reduc-minmax-1.c @@ -0,0 +1,234 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=z14 -ftree-vectorize -fdump-tree-optimized" } */ + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) > (b) ? (b) : (a)) + +/* unsigned integers */ + +unsigned char +reduce_umax_char (unsigned char *p) +{ + unsigned char res = p[0]; + for (int i = 0; i < 16; i++) + res = MAX (res, p[i]); + return res; +} + +unsigned char +reduce_umin_char (unsigned char *p) +{ + unsigned char res = p[0]; + for (int i = 0; i < 16; i++) + res = MIN (res, p[i]); + return res; +} + +unsigned short +reduce_umax_short (unsigned short *p) +{ + unsigned short res = p[0]; + for (int i = 0; i < 8; i++) + res = MAX (res, p[i]); + return res; +} + +unsigned short +reduce_umin_short (unsigned short *p) +{ + unsigned short res = p[0]; + for (int i = 0; i < 8; i++) + res = MIN (res, p[i]); + return res; +} + +unsigned int +reduce_umax_int (unsigned int* p) +{ + unsigned int res = p[0]; + for (int i = 0; i != 4; i++) + res = MAX (res, p[i]); + return res; +} + +unsigned int +reduce_umin_int (unsigned int* p) +{ + unsigned int res = p[0]; + for (int i = 0; i != 4; i++) + res = MIN(res, p[i]); + return res; +} + +unsigned long +reduce_umax_long (unsigned long* p) +{ + unsigned long res = p[0]; + for (int i = 0; i != 4; i++) + res = MAX (res, p[i]); + return res; +} + +unsigned long +reduce_umin_long (unsigned long* p) +{ + unsigned long res = p[0]; + for (int i = 0; i != 4; i++) + res = MIN(res, p[i]); + return res; +} + +/* signed integers */ + +signed char +reduce_smax_char (signed char *p) +{ + signed char res = p[0]; + for (int i = 0; i < 16; i++) + res = MAX (res, p[i]); + return res; +} + +signed char +reduce_smin_char (signed char *p) +{ + signed char res = p[0]; + for (int i = 0; i < 16; i++) + res = MIN (res, p[i]); + return res; +} + +signed short +reduce_smax_short (signed short *p) +{ + signed short res = p[0]; + for (int i = 0; i < 8; i++) + res = MAX (res, p[i]); + return res; +} + +signed short +reduce_smin_short (signed short *p) +{ + signed short res = p[0]; + for (int i = 0; i < 8; i++) + res = MIN (res, p[i]); + return res; +} + +signed int +reduce_smax_int (signed int* p) +{ + signed int res = p[0]; + for (int i = 0; i != 4; i++) + res = MAX (res, p[i]); + return res; +} + +signed int +reduce_smin_int (signed int* p) +{ + signed int res = p[0]; + for (int i = 0; i != 4; i++) + res = MIN(res, p[i]); + return res; +} + +signed long +reduce_smax_long (signed long* p) +{ + signed long res = p[0]; + for (int i = 0; i != 4; i++) + res = MAX (res, p[i]); + return res; +} + +signed long +reduce_smin_long (signed long* p) +{ + signed long res = p[0]; + for (int i = 0; i != 4; i++) + res = MIN(res, p[i]); + return res; +} + +float +__attribute__((optimize("Ofast"))) +reduce_smax_float (float* p) +{ + float res = p[0]; + for (int i = 0; i != 4; i++) + res = MAX (res, p[i]); + return res; +} + +float +__attribute__((optimize("Ofast"))) +reduce_smin_float (float* p) +{ + float res = p[0]; + for (int i = 0; i != 4; i++) + res = MIN (res, p[i]); + return res; +} + +double +__attribute__((optimize("Ofast"))) +reduce_smax_double (double* p) +{ + double res = p[0]; + for (int i = 0; i != 4; i++) + res = MAX (res, p[i]); + return res; +} + +double +__attribute__((optimize("Ofast"))) +reduce_smin_double (double* p) +{ + double res = p[0]; + for (int i = 0; i != 4; i++) + res = MIN (res, p[i]); + return res; +} + +float +reduce_fmax_float (float* p) +{ + float res = p[0]; + for (int i = 0; i != 4; i++) + res = __builtin_fmaxf (res, p[i]); + return res; +} + +float +reduce_fmin_float (float* p) +{ + float res = p[0]; + for (int i = 0; i != 4; i++) + res = __builtin_fminf (res, p[i]); + return res; +} + +double +reduce_fmax_double (double* p) +{ + double res = p[0]; + for (int i = 0; i != 4; i++) + res = __builtin_fmax (res, p[i]); + return res; +} + +double +reduce_fmin_double (double* p) +{ + double res = p[0]; + for (int i = 0; i != 4; i++) + res = __builtin_fmin (res, p[i]); + return res; +} + +/* { dg-final { scan-tree-dump-times "\.REDUC_MAX" 10 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.REDUC_MIN" 10 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.REDUC_FMAX" 2 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.REDUC_FMIN" 2 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/reduc-plus-1.c b/gcc/testsuite/gcc.target/s390/vector/reduc-plus-1.c new file mode 100644 index 0000000..12cdd5f --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/reduc-plus-1.c @@ -0,0 +1,152 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=z14 -ftree-vectorize -fdump-tree-optimized" } */ +/* { dg-do run { target { s390_z14_hw } } } */ + +/* signed integers */ + +signed char +__attribute__((noipa, optimize("Ofast"))) +reduce_add_char (signed char* p) +{ + signed char sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +short +__attribute__((noipa, optimize("Ofast"))) +reduce_add_short (short* p) +{ + short sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +int +__attribute__((noipa, optimize("Ofast"))) +reduce_add_int (int* p) +{ + int sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +long +__attribute__((noipa, optimize("Ofast"))) +reduce_add_long (long* p) +{ + long sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +/* unsigned integers */ + +unsigned char +__attribute__((noipa, optimize("Ofast"))) +reduce_add_uchar (unsigned char* p) +{ + unsigned char sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +unsigned short +__attribute__((noipa, optimize("Ofast"))) +reduce_add_ushort (unsigned short* p) +{ + unsigned short sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +unsigned int +__attribute__((noipa, optimize("Ofast"))) +reduce_add_uint (unsigned int* p) +{ + unsigned int sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +unsigned long +__attribute__((noipa, optimize("Ofast"))) +reduce_add_ulong (unsigned long* p) +{ + unsigned long sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +/* floating point */ + +float +__attribute__((noipa, optimize("Ofast"))) +reduce_add_float (float* p) +{ + float sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +double +__attribute__((noipa, optimize("Ofast"))) +reduce_add_double (double* p) +{ + double sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +int +main() +{ + signed char chararr[] = {-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,-16}; + signed short shortarr[] = {-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,-16}; + signed int intarr[] = {-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,-16}; + signed long longarr[] = {-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,-16}; + + unsigned char uchararr[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}; + unsigned short ushortarr[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}; + unsigned int uintarr[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}; + unsigned long ulongarr[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}; + + float floatarr[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}; + double doublearr[] = {-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,-16}; + + if (reduce_add_char (chararr) != (-136 & 0xff)) + __builtin_abort(); + if (reduce_add_short (shortarr) != -136) + __builtin_abort(); + if (reduce_add_int (intarr) != -136) + __builtin_abort(); + if (reduce_add_long (longarr) != -136) + __builtin_abort(); + + if (reduce_add_uchar (uchararr) != 136) + __builtin_abort(); + if (reduce_add_ushort (ushortarr) != 136) + __builtin_abort(); + if (reduce_add_uint (uintarr) != 136) + __builtin_abort(); + if (reduce_add_ulong (ulongarr) != 136) + __builtin_abort(); + + if (reduce_add_float (floatarr) != 136) + __builtin_abort(); + if (reduce_add_double (doublearr) != -136) + __builtin_abort(); + return 0; +} + +/* { dg-final { scan-tree-dump-times "\.REDUC_PLUS" 10 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-abs-emu.c b/gcc/testsuite/gcc.target/s390/vector/vec-abs-emu.c index e0dd222..2fcaa95 100644 --- a/gcc/testsuite/gcc.target/s390/vector/vec-abs-emu.c +++ b/gcc/testsuite/gcc.target/s390/vector/vec-abs-emu.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mzarch -march=z13 -save-temps" } */ +/* { dg-options "-O3 -mzarch -march=z13 -save-temps -fno-stack-protector" } */ /* { dg-require-effective-target int128 } */ /* { dg-final { check-function-bodies "**" "" "" } } */ /* { dg-final { scan-assembler-not {\tvlpq\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-extract-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-extract-1.c new file mode 100644 index 0000000..83af839 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-extract-1.c @@ -0,0 +1,178 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=arch11 -mzarch" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +typedef double V2DF __attribute__((vector_size(16))); +typedef float V4SF __attribute__((vector_size(16))); +typedef float V2SF __attribute__((vector_size(8))); +typedef double V1DF __attribute__((vector_size(8))); +typedef float V1SF __attribute__((vector_size(4))); +typedef long double V1TF __attribute__((vector_size(16))); + +/* +** extractfirstdouble: +** vlr %v0,%v24 +** br %r14 +*/ +double +extractfirstdouble (V2DF x) +{ + return x[0]; +} + +/* +** extractseconddouble: +** vrepg %v0,%v24,1 +** br %r14 +*/ +double +extractseconddouble (V2DF x) +{ + return x[1]; +} + +/* +** extractnthdouble: +** vlgvg (%r.),%v24,0\(%r2\) +** ldgr %f0,\1 +** br %r14 +*/ +double +extractnthdouble (V2DF x, int n) +{ + return x[n]; +} + +/* +** sumfirstdouble: +** vfadb %v0,%v24,%v26 +** br %r14 +*/ +double +sumfirstdouble (V2DF x, V2DF y) +{ + return (x + y)[0]; +} + +/* +** extractfirstfloat: +** vlr %v0,%v24 +** br %r14 +*/ +float +extractfirstfloat (V4SF x) +{ + return x[0]; +} + +/* +** extractsecondfloat: +** vrepf %v0,%v24,1 +** br %r14 +*/ +float +extractsecondfloat (V4SF x) +{ + return x[1]; +} + +/* +** extractthirdfloat: +** vrepf %v0,%v24,2 +** br %r14 +*/ +float +extractthirdfloat (V4SF x) +{ + return x[2]; +} + +/* +** extractfourthfloat: +** vrepf %v0,%v24,3 +** br %r14 +*/ +float +extractfourthfloat (V4SF x) +{ + return x[3]; +} + +/* +** extractnthfloat: +** vlgvf (%r.),%v24,0\(%r2\) +** vlvgf %v0,\1,0 +** br %r14 +*/ +float +extractnthfloat (V4SF x, int n) +{ + return x[n]; +} + +/* +** extractfirst2: +** vlr %v0,%v24 +** br %r14 +*/ +float +extractfirst2 (V2SF x) +{ + return x[0]; +} + +/* +** extractsecond2: +** vrepf %v0,%v24,1 +** br %r14 +*/ +float +extractsecond2 (V2SF x) +{ + return x[1]; +} + +/* +** extractnth2: +** vlgvf (%r.),%v24,0\(%r2\) +** vlvgf %v0,\1,0 +** br %r14 +*/ +float +extractnth2 (V2SF x, int n) +{ + return x[n]; +} + +/* +** extractsinglef: +** vlr %v0,%v24 +** br %r14 +*/ +float +extractsinglef (V1SF x) +{ + return x[0]; +} + +/* +** extractsingled: +** vlr %v0,%v24 +** br %r14 +*/ +double +extractsingled (V1DF x) +{ + return x[0]; +} + +/* +** extractsingleld: +** vst %v24,0\(%r2\),3 +** br %r14 +*/ +long double +extractsingleld (V1TF x) +{ + return x[0]; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-extract-2.c b/gcc/testsuite/gcc.target/s390/vector/vec-extract-2.c new file mode 100644 index 0000000..640ac0c --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-extract-2.c @@ -0,0 +1,168 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=arch11 -mzarch" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +typedef double V2DF __attribute__((vector_size(16))); +typedef float V4SF __attribute__((vector_size(16))); +typedef float V2SF __attribute__((vector_size(8))); +typedef double V1DF __attribute__((vector_size(8))); +typedef float V1SF __attribute__((vector_size(4))); +typedef long double V1TF __attribute__((vector_size(16))); + +/* +** extractfirstdouble: +** vsteg %v24,0\(%r2\),0 +** br %r14 +*/ +void +extractfirstdouble (double *res, V2DF x) +{ + *res = x[0]; +} + +/* +** extractseconddouble: +** vsteg %v24,0\(%r2\),1 +** br %r14 +*/ +void +extractseconddouble (double *res, V2DF x) +{ + *res = x[1]; +} + +/* +** extractnthdouble: +** vlgvg (%r.),%v24,0\(%r3\) +** stg \1,0\(%r2\) +** br %r14 +*/ +void +extractnthdouble (double *res, V2DF x, int n) +{ + *res = x[n]; +} + +/* +** extractfirstfloat: +** vstef %v24,0\(%r2\),0 +** br %r14 +*/ +void +extractfirstfloat (float *res, V4SF x) +{ + *res = x[0]; +} + +/* +** extractsecondfloat: +** vstef %v24,0\(%r2\),1 +** br %r14 +*/ +void +extractsecondfloat (float *res, V4SF x) +{ + *res = x[1]; +} + +/* +** extractthirdfloat: +** vstef %v24,0\(%r2\),2 +** br %r14 +*/ +void +extractthirdfloat (float *res, V4SF x) +{ + *res = x[2]; +} + +/* +** extractfourthfloat: +** vstef %v24,0\(%r2\),3 +** br %r14 +*/ +void +extractfourthfloat (float *res, V4SF x) +{ + *res = x[3]; +} + +/* +** extractnthfloat: +** vlgvf (%r.),%v24,0\(%r3\) +** st \1,0\(%r2\) +** br %r14 +*/ +void +extractnthfloat (float *res, V4SF x, int n) +{ + *res = x[n]; +} + +/* +** extractfirst2: +** vstef %v24,0\(%r2\),0 +** br %r14 +*/ +void +extractfirst2 (float *res, V2SF x) +{ + *res = x[0]; +} + +/* +** extractsecond2: +** vstef %v24,0\(%r2\),1 +** br %r14 +*/ +void +extractsecond2 (float *res, V2SF x) +{ + *res = x[1]; +} + +/* +** extractnth2: +** vlgvf (%r.),%v24,0\(%r3\) +** st \1,0\(%r2\) +** br %r14 +*/ +void +extractnth2 (float *res, V2SF x, int n) +{ + *res = x[n]; +} + +/* +** extractsinglef: +** vlr %v(.),%v24 +** ste %f\1,0\(%r2\) +** br %r14 +*/ +void +extractsinglef (float *res, V1SF x) +{ + *res = x[0]; +} + +/* +** extractsingled: +** vsteg %v24,0\(%r2\),0 +** br %r14 +*/ +void +extractsingled (double *res, V1DF x) +{ + *res = x[0]; +} + +/* +** extractsingleld: +** vst %v24,0\(%r2\),3 +** br %r14 +*/ +void +extractsingleld (long double *res, V1TF x) +{ + *res = x[0]; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-max-emu.c b/gcc/testsuite/gcc.target/s390/vector/vec-max-emu.c index 12c7e76..16afd1d 100644 --- a/gcc/testsuite/gcc.target/s390/vector/vec-max-emu.c +++ b/gcc/testsuite/gcc.target/s390/vector/vec-max-emu.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mzarch -march=z13 -save-temps" } */ +/* { dg-options "-O3 -mzarch -march=z13 -save-temps -fno-stack-protector" } */ /* { dg-require-effective-target int128 } */ /* { dg-final { check-function-bodies "**" "" "" } } */ /* { dg-final { scan-assembler-not {\tvmxq\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-min-emu.c b/gcc/testsuite/gcc.target/s390/vector/vec-min-emu.c index a9bcba3..0eb0916 100644 --- a/gcc/testsuite/gcc.target/s390/vector/vec-min-emu.c +++ b/gcc/testsuite/gcc.target/s390/vector/vec-min-emu.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mzarch -march=z13 -save-temps" } */ +/* { dg-options "-O3 -mzarch -march=z13 -save-temps -fno-stack-protector" } */ /* { dg-require-effective-target int128 } */ /* { dg-final { check-function-bodies "**" "" "" } } */ /* { dg-final { scan-assembler-not {\tvmnq\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-perm-merge-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-perm-merge-1.c new file mode 100644 index 0000000..79f8a88 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-perm-merge-1.c @@ -0,0 +1,242 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=z14 -mzvector --save-temps -fno-stack-protector" } */ +/* { dg-do run { target { s390_z14_hw } } } */ +/* { dg-final {check-function-bodies "**" "" } } */ + +#include "vec-types.h" + +/* +** qi_via_hi_hi: +** vmrhh %v24,%v24,%v26 +** br %r14 +*/ +v16qi __attribute__((noinline,noipa)) +qi_via_hi_hi (v16qi a, v16qi b) +{ + return (v16qi){a[0], a[1], b[0], b[1], a[2], a[3], b[2], b[3], + a[4], a[5], b[4], b[5], a[6], a[7], b[6], b[7]}; +} + +/* +** qi_via_hi_lo: +** vmrlh %v24,%v24,%v26 +** br %r14 +*/ +v16qi __attribute__((noinline,noipa)) +qi_via_hi_lo (v16qi a, v16qi b) +{ + return (v16qi){a[8], a[9], b[8], b[9], a[10], a[11], b[10], b[11], + a[12], a[13], b[12], b[13], a[14], a[15], b[14], b[15]}; +} + +/* +** qi_via_si_hi: +** vmrhf %v24,%v24,%v26 +** br %r14 +*/ +v16qi __attribute__((noinline,noipa)) +qi_via_si_hi (v16qi a, v16qi b) +{ + return (v16qi){a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], + a[4], a[5], a[6], a[7], b[4], b[5], b[6], b[7]}; +} + +/* +** qi_via_si_lo: +** vmrlf %v24,%v24,%v26 +** br %r14 +*/ +v16qi __attribute__((noinline,noipa)) +qi_via_si_lo (v16qi a, v16qi b) +{ + return (v16qi){a[8], a[9], a[10], a[11], b[8], b[9], b[10], b[11], + a[12], a[13], a[14], a[15], b[12], b[13], b[14], b[15]}; +} + +/* +** qi_via_di_hi: +** vmrhg %v24,%v24,%v26 +** br %r14 +*/ +v16qi __attribute__((noinline,noipa)) +qi_via_di_hi (v16qi a, v16qi b) +{ + return (v16qi){a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], + b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]}; +} + +/* +** qi_via_di_lo: +** vmrlg %v24,%v24,%v26 +** br %r14 +*/ +v16qi __attribute__((noinline,noipa)) +qi_via_di_lo (v16qi a, v16qi b) +{ + return (v16qi){a[8], a[9], a[10], a[11], a[12], a[13], a[14], a[15], + b[8], b[9], b[10], b[11], b[12], b[13], b[14], b[15]}; +} + +/* +** hi_via_si_hi: +** vmrhf %v24,%v24,%v26 +** br %r14 +*/ +v8hi __attribute__((noinline,noipa)) +hi_via_si_hi (v8hi a, v8hi b) +{ + return (v8hi){a[0], a[1], b[0], b[1], a[2], a[3], b[2], b[3]}; +} + +/* +** hi_via_si_lo: +** vmrlf %v24,%v24,%v26 +** br %r14 +*/ +v8hi __attribute__((noinline,noipa)) +hi_via_si_lo (v8hi a, v8hi b) +{ + return (v8hi){a[4], a[5], b[4], b[5], a[6], a[7], b[6], b[7]}; +} + +/* +** hi_via_di_hi: +** vmrhg %v24,%v24,%v26 +** br %r14 +*/ +v8hi __attribute__((noinline,noipa)) +hi_via_di_hi (v8hi a, v8hi b) +{ + return (v8hi){a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3]}; +} + +/* +** hi_via_di_lo: +** vmrlg %v24,%v24,%v26 +** br %r14 +*/ +v8hi __attribute__((noinline,noipa)) +hi_via_di_lo (v8hi a, v8hi b) +{ + return (v8hi){a[4], a[5], a[6], a[7], b[4], b[5], b[6], b[7]}; +} + +/* +** si_via_di_hi: +** vmrhg %v24,%v24,%v26 +** br %r14 +*/ +v4si __attribute__((noinline,noipa)) +si_via_di_hi (v4si a, v4si b) +{ + return (v4si){a[0], a[1], b[0], b[1]}; +} + +/* +** si_via_di_lo: +** vmrlg %v24,%v24,%v26 +** br %r14 +*/ +v4si __attribute__((noinline,noipa)) +si_via_di_lo (v4si a, v4si b) +{ + return (v4si){a[2], a[3], b[2], b[3]}; +} + +int +main () +{ + static const signed char e_qi_via_hi_hi[16] + = {0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23}; + static const signed char e_qi_via_hi_lo[16] + = {8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31}; + static const signed char e_qi_via_si_hi[16] + = {0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23}; + static const signed char e_qi_via_si_lo[16] + = {8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31}; + static const signed char e_qi_via_di_hi[16] + = {0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23}; + static const signed char e_qi_via_di_lo[16] + = {8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31}; + + static const short e_hi_via_si_hi[8] = {0, 1, 8, 9, 2, 3, 10, 11}; + static const short e_hi_via_si_lo[8] = {4, 5, 12, 13, 6, 7, 14, 15}; + static const short e_hi_via_di_hi[8] = {0, 1, 2, 3, 8, 9, 10, 11}; + static const short e_hi_via_di_lo[8] = {4, 5, 6, 7, 12, 13, 14, 15}; + + static const int e_si_via_di_hi[4] = {0, 1, 4, 5}; + static const int e_si_via_di_lo[4] = {2, 3, 6, 7}; + + v16qi a_qi = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; + v16qi b_qi = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}; + v8hi a_hi = {0, 1, 2, 3, 4, 5, 6, 7}; + v8hi b_hi = {8, 9, 10, 11, 12, 13, 14, 15}; + v4si a_si = {0, 1, 2, 3}; + v4si b_si = {4, 5, 6, 7}; + v16qi r_qi; + v8hi r_hi; + v4si r_si; + int i; + + r_qi = qi_via_hi_hi (a_qi, b_qi); + for (i = 0; i < 16; ++i) + if (r_qi[i] != e_qi_via_hi_hi[i]) + __builtin_abort (); + + r_qi = qi_via_hi_lo (a_qi, b_qi); + for (i = 0; i < 16; ++i) + if (r_qi[i] != e_qi_via_hi_lo[i]) + __builtin_abort (); + + r_qi = qi_via_si_hi (a_qi, b_qi); + for (i = 0; i < 16; ++i) + if (r_qi[i] != e_qi_via_si_hi[i]) + __builtin_abort (); + + r_qi = qi_via_si_lo (a_qi, b_qi); + for (i = 0; i < 16; ++i) + if (r_qi[i] != e_qi_via_si_lo[i]) + __builtin_abort (); + + r_qi = qi_via_di_hi (a_qi, b_qi); + for (i = 0; i < 16; ++i) + if (r_qi[i] != e_qi_via_di_hi[i]) + __builtin_abort (); + + r_qi = qi_via_di_lo (a_qi, b_qi); + for (i = 0; i < 16; ++i) + if (r_qi[i] != e_qi_via_di_lo[i]) + __builtin_abort (); + + r_hi = hi_via_si_hi (a_hi, b_hi); + for (i = 0; i < 8; ++i) + if (r_hi[i] != e_hi_via_si_hi[i]) + __builtin_abort (); + + r_hi = hi_via_si_lo (a_hi, b_hi); + for (i = 0; i < 8; ++i) + if (r_hi[i] != e_hi_via_si_lo[i]) + __builtin_abort (); + + r_hi = hi_via_di_hi (a_hi, b_hi); + for (i = 0; i < 8; ++i) + if (r_hi[i] != e_hi_via_di_hi[i]) + __builtin_abort (); + + r_hi = hi_via_di_lo (a_hi, b_hi); + for (i = 0; i < 8; ++i) + if (r_hi[i] != e_hi_via_di_lo[i]) + __builtin_abort (); + + r_si = si_via_di_hi (a_si, b_si); + for (i = 0; i < 4; ++i) + if (r_si[i] != e_si_via_di_hi[i]) + __builtin_abort (); + + r_si = si_via_di_lo (a_si, b_si); + for (i = 0; i < 4; ++i) + if (r_si[i] != e_si_via_di_lo[i]) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-perm-pack-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-perm-pack-1.c new file mode 100644 index 0000000..6590c92 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-perm-pack-1.c @@ -0,0 +1,133 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=z14 -mzvector --save-temps -fno-stack-protector" } */ +/* { dg-do run { target { s390_z14_hw } } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec-types.h" + +/* +** qi_via_hi: +** vpkh %v24,%v24,%v26 +** br %r14 +*/ +v16qi __attribute__((noinline,noipa)) +qi_via_hi (v16qi a, v16qi b) +{ + return (v16qi){a[1], a[3], a[5], a[7], a[9], a[11], a[13], a[15], + b[1], b[3], b[5], b[7], b[9], b[11], b[13], b[15]}; +} + +/* +** qi_via_si: +** vpkf %v24,%v24,%v26 +** br %r14 +*/ +v16qi __attribute__((noinline,noipa)) +qi_via_si (v16qi a, v16qi b) +{ + return (v16qi){a[2], a[3], a[6], a[7], a[10], a[11], a[14], a[15], + b[2], b[3], b[6], b[7], b[10], b[11], b[14], b[15]}; +} + +/* +** qi_via_di: +** vpkg %v24,%v24,%v26 +** br %r14 +*/ +v16qi __attribute__((noinline,noipa)) +qi_via_di (v16qi a, v16qi b) +{ + return (v16qi){a[4], a[5], a[6], a[7], a[12], a[13], a[14], a[15], + b[4], b[5], b[6], b[7], b[12], b[13], b[14], b[15]}; +} + +/* +** hi_via_si: +** vpkf %v24,%v24,%v26 +** br %r14 +*/ +v8hi __attribute__((noinline,noipa)) +hi_via_si (v8hi a, v8hi b) +{ + return (v8hi){a[1], a[3], a[5], a[7], b[1], b[3], b[5], b[7]}; +} + +/* +** hi_via_di: +** vpkg %v24,%v24,%v26 +** br %r14 +*/ +v8hi __attribute__((noinline,noipa)) +hi_via_di (v8hi a, v8hi b) +{ + return (v8hi){a[2], a[3], a[6], a[7], b[2], b[3], b[6], b[7]}; +} + +/* +** si_via_di: +** vpkg %v24,%v24,%v26 +** br %r14 +*/ +v4si __attribute__((noinline,noipa)) +si_via_di (v4si a, v4si b) +{ + return (v4si){a[1], a[3], b[1], b[3]}; +} + +int +main () +{ + static const signed char e_qi_via_hi[16] + = {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31}; + static const signed char e_qi_via_si[16] + = {2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31}; + static const signed char e_qi_via_di[16] + = {4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31}; + + static const short e_hi_via_si[8] = {1, 3, 5, 7, 9, 11, 13, 15}; + static const short e_hi_via_di[8] = {2, 3, 6, 7, 10, 11, 14, 15}; + + static const int e_si_via_di[4] = {1, 3, 5, 7}; + + v16qi a_qi = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; + v16qi b_qi = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}; + v8hi a_hi = {0, 1, 2, 3, 4, 5, 6, 7}; + v8hi b_hi = {8, 9, 10, 11, 12, 13, 14, 15}; + v4si a_si = {0, 1, 2, 3}; + v4si b_si = {4, 5, 6, 7}; + v16qi r_qi; + v8hi r_hi; + v4si r_si; + int i; + + r_qi = qi_via_hi (a_qi, b_qi); + for (i = 0; i < 16; ++i) + if (r_qi[i] != e_qi_via_hi[i]) + __builtin_abort (); + + r_qi = qi_via_si (a_qi, b_qi); + for (i = 0; i < 16; ++i) + if (r_qi[i] != e_qi_via_si[i]) + __builtin_abort (); + + r_qi = qi_via_di (a_qi, b_qi); + for (i = 0; i < 16; ++i) + if (r_qi[i] != e_qi_via_di[i]) + __builtin_abort (); + + r_hi = hi_via_si (a_hi, b_hi); + for (i = 0; i < 8; ++i) + if (r_hi[i] != e_hi_via_si[i]) + __builtin_abort (); + + r_hi = hi_via_di (a_hi, b_hi); + for (i = 0; i < 8; ++i) + if (r_hi[i] != e_hi_via_di[i]) + __builtin_abort (); + + r_si = si_via_di (a_si, b_si); + for (i = 0; i < 4; ++i) + if (r_si[i] != e_si_via_di[i]) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-set-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-set-1.c new file mode 100644 index 0000000..c03963e --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vec-set-1.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=arch11 -mzarch" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +typedef double V2DF __attribute__((vector_size(16))); +typedef double V1DF __attribute__((vector_size(8))); +typedef float V4SF __attribute__((vector_size(16))); + +/* +** setdf0: +** vpdi %v24,%v0,%v24,1 +** br %r14 +*/ +V2DF +setdf0 (V2DF x, double y) +{ + x[0] = y; + return x; +} + +/* +** setdf1: +** vmrhg %v24,%v24,%v0 +** br %r14 +*/ +V2DF +setdf1 (V2DF x, double y) +{ + x[1] = y; + return x; +} + +/* +** setdfn: +** lgdr (%r.),%f0 +** vlvgg %v24,\1,0\(%r2\) +** br %r14 +*/ +V2DF +setdfn (V2DF x, double y, int n) +{ + x[n] = y; + return x; +} + +/* +** set1df: +** vlr %v24,%v0 +** br %r14 +*/ +V1DF +set1df (V1DF x, double y) +{ + x[0] = y; + return x; +} + +/* +** set1dfn: +** vlr %v24,%v0 +** br %r14 +*/ +V1DF +set1dfn (V1DF x, double y, int n) +{ + x[n] = y; + return x; +} + +/* +** setsf0: +** vlgvf (%r.),%v0,0 +** vlvgf %v24,\1,0 +** br %r14 +*/ +V4SF +setsf0 (V4SF x, float y) +{ + x[0] = y; + return x; +} + +/* +** setsf1: +** vlgvf (%r.),%v0,0 +** vlvgf %v24,\1,1 +** br %r14 +*/ +V4SF +setsf1 (V4SF x, float y) +{ + x[1] = y; + return x; +} + +/* +** setsf2: +** vlgvf (%r.),%v0,0 +** vlvgf %v24,\1,2 +** br %r14 +*/ +V4SF +setsf2 (V4SF x, float y) +{ + x[2] = y; + return x; +} + +/* +** setsf3: +** vlgvf (%r.),%v0,0 +** vlvgf %v24,\1,3 +** br %r14 +*/ +V4SF +setsf3 (V4SF x, float y) +{ + x[3] = y; + return x; +} + +/* +** setsfn: +** vlgvf (%r.),%v0,0 +** vlvgf %v24,\1,0\(%r2\) +** br %r14 +*/ +V4SF +setsfn (V4SF x, float y, int n) +{ + x[n] = y; + /* Make sure to read all FPRs such that the "save GPRs in FPRs" optimization + cannot be used. That optimization has a memory clobber on SP restore + causing DSE to fail to eliminate dead stores in leaf functions using this + optimization. */ + asm volatile ("" : : "f" (y), "f" (y), "f" (y), "f" (y), "f" (y), "f" (y), + "f" (y), "f" (y), "f" (y), "f" (y), "f" (y), "f" (y), + "f" (y), "f" (y), "f" (y), "f" (y)); + return x; +} diff --git a/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c b/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c new file mode 100644 index 0000000..11df6c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c @@ -0,0 +1,71 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target s390_vx } */ +/* { dg-additional-options "-O2" } */ +/* { dg-final { scan-assembler-not {\tllg?[fhc]r\t} } } */ + +typedef unsigned char __attribute__ ((vector_size (1))) V1QI; +typedef unsigned char __attribute__ ((vector_size (2))) V2QI; +typedef unsigned char __attribute__ ((vector_size (4))) V4QI; +typedef unsigned char __attribute__ ((vector_size (8))) V8QI; +typedef unsigned char __attribute__ ((vector_size (16))) V16QI; + +typedef unsigned short __attribute__ ((vector_size (2))) V1HI; +typedef unsigned short __attribute__ ((vector_size (4))) V2HI; +typedef unsigned short __attribute__ ((vector_size (8))) V4HI; +typedef unsigned short __attribute__ ((vector_size (16))) V8HI; + +typedef unsigned int __attribute__ ((vector_size (4))) V1SI; +typedef unsigned int __attribute__ ((vector_size (8))) V2SI; +typedef unsigned int __attribute__ ((vector_size (16))) V4SI; + +unsigned short ushort; +unsigned int uint; + +#define TEST(T, U, I) \ + unsigned T test_ ## I ## _ ## U (U x) { return x[I]; } \ + void test_ ## I ## _ ## U ## _ushort (U x) { ushort = x[I]; } \ + void test_ ## I ## _ ## U ## _uint (U x) { uint = x[I]; } + +#define TEST1(T, U) \ + TEST(T, U, 0) + +#define TEST2(T, U) \ + TEST1 (T, U) \ + TEST(T, U, 1) + +#define TEST4(T, U) \ + TEST2 (T, U) \ + TEST(T, U, 2) \ + TEST(T, U, 3) + +#define TEST8(T, U) \ + TEST4 (T, U) \ + TEST(T, U, 4) \ + TEST(T, U, 5) \ + TEST(T, U, 6) \ + TEST(T, U, 7) + +#define TEST16(T, U) \ + TEST8 (T, U) \ + TEST(T, U, 9) \ + TEST(T, U, 10) \ + TEST(T, U, 11) \ + TEST(T, U, 12) \ + TEST(T, U, 13) \ + TEST(T, U, 14) \ + TEST(T, U, 15) + +TEST1 (char, V1QI) +TEST2 (char, V2QI) +TEST4 (char, V4QI) +TEST8 (char, V8QI) +TEST16 (char, V16QI) + +TEST1 (short, V1HI) +TEST2 (short, V2HI) +TEST4 (short, V4HI) +TEST8 (short, V8HI) + +TEST1 (int, V1SI) +TEST2 (int, V2SI) +TEST4 (int, V4SI) diff --git a/gcc/testsuite/gcc.target/sh/pr54236-2.c b/gcc/testsuite/gcc.target/sh/pr54236-2.c index 1e2f3bb..78befe4 100644 --- a/gcc/testsuite/gcc.target/sh/pr54236-2.c +++ b/gcc/testsuite/gcc.target/sh/pr54236-2.c @@ -4,10 +4,10 @@ /* { dg-do compile } */ /* { dg-options "-O1" } */ -/* { dg-final { scan-assembler-times "addc" 36 } } */ +/* { dg-final { scan-assembler-times "addc" 32 } } */ /* { dg-final { scan-assembler-times "shll" 14 } } */ -/* { dg-final { scan-assembler-times "add\tr" 12 } } */ -/* { dg-final { scan-assembler-not "movt" } } */ +/* { dg-final { scan-assembler-times "add\tr" 16 } } */ +/* { dg-final { scan-assembler-times "movt" 4 } } */ /* { dg-final { scan-assembler-times "add\t#1" 1 } } */ @@ -184,28 +184,28 @@ test_022 (int a, int b, int c, int d) int test_023 (int a, int b, int c, int d) { - // 1x shll, 1x addc + // 1x shll, 1x add return a + ((b >> 31) & 1); } int test_024 (int a, int b, int c, int d) { - // 1x shll, 1x addc + // 1x shll, 1x add return ((b >> 31) & 1) + a; } int test_025 (int a, int b, int c, int d) { - // 1x shll, 1x addc + // 1x shll, 1x add return ((a >> 31) & 1) + a; } int test_026 (int a, int b, int c, int d) { - // 1x shll, 1x addc + // 1x shll, 1x add return a + ((a >> 31) & 1); } diff --git a/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c b/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c index 5f3d3e1..46fc464 100644 --- a/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c +++ b/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -fno-tree-vectorize -mabi=sysv" } */ +/* { dg-options "-O2 -fno-tree-vectorize -mabi=sysv -fno-shrink-wrap-separate" } */ extern int glb1, gbl2, gbl3; diff --git a/gcc/testsuite/gcc.target/xtensa/BGEUI-BLTUI-32k-64k.c b/gcc/testsuite/gcc.target/xtensa/BGEUI-BLTUI-32k-64k.c new file mode 100644 index 0000000..05873b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/xtensa/BGEUI-BLTUI-32k-64k.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +extern void foo(void); + +void BGEUI_test(unsigned int a) +{ + if (a < 32768U) + foo(); +} + +void BLTUI_test(unsigned int a) +{ + if (a >= 65536U) + foo(); +} + +/* { dg-final { scan-assembler-times "bgeui" 1 } } */ +/* { dg-final { scan-assembler-times "bltui" 1 } } */ diff --git a/gcc/testsuite/gcc.target/xtensa/elim_GP_regmove_0.c b/gcc/testsuite/gcc.target/xtensa/elim_GP_regmove_0.c deleted file mode 100644 index 5c195c3..0000000 --- a/gcc/testsuite/gcc.target/xtensa/elim_GP_regmove_0.c +++ /dev/null @@ -1,23 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -fpeephole2" } */ - -/* can be processed */ -double test0(double a, double b) { - return __builtin_copysign(a, b); -} - -/* cannot be processed: due to violate '0' constraint of the 2nd source operand. */ -int test1(int a, int b) { - int c; - asm volatile ("" : "=a"(c) : "r"(a), "0"(b)); - return c; -} - -/* cannot be processed: due to violate '&' constraint of the destination operand. */ -int test2(int a) { - int b; - asm volatile ("" : "=&a"(b) : "r"(a)); - return b; -} - -/* { dg-final { scan-assembler-times "mov\t|mov.n\t" 2 } } */ diff --git a/gcc/testsuite/gcc.target/xtensa/elim_GP_regmove_1.c b/gcc/testsuite/gcc.target/xtensa/elim_GP_regmove_1.c deleted file mode 100644 index a13ef81..0000000 --- a/gcc/testsuite/gcc.target/xtensa/elim_GP_regmove_1.c +++ /dev/null @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -fpeephole2 -mabi=windowed" } */ - -/* cannot be processed: due to violate 'a' constraint of the destination operand of the stack adjustment instruction. */ -void test(void) { - int buffer[8192]; - asm volatile ("" : : "m"(buffer)); -} - -/* { dg-final { scan-assembler-times "movsp" 1 } } */ diff --git a/gcc/testsuite/gcc.target/xtensa/pr120888-1.c b/gcc/testsuite/gcc.target/xtensa/pr120888-1.c new file mode 100644 index 0000000..f438e4c --- /dev/null +++ b/gcc/testsuite/gcc.target/xtensa/pr120888-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -fdump-rtl-expand" } */ + +void u8(unsigned char c); +void cu8(unsigned char *p) +{ + u8(*p); +} + +/* { dg-final { scan-rtl-dump "zero_extend" "expand" } } */ +/* { dg-final { scan-rtl-dump-not "sign_extend" "expand" } } */ diff --git a/gcc/testsuite/gcc.target/xtensa/pr120888-2.c b/gcc/testsuite/gcc.target/xtensa/pr120888-2.c new file mode 100644 index 0000000..9b5caad --- /dev/null +++ b/gcc/testsuite/gcc.target/xtensa/pr120888-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -fdump-rtl-expand" } */ + +void s8(signed char c); +void cs8(signed char *p) +{ + s8(*p); +} + +/* { dg-final { scan-rtl-dump "sign_extend" "expand" } } */ +/* { dg-final { scan-rtl-dump-not "zero_extend" "expand" } } */ |