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-rw-r--r--gcc/testsuite/gcc.target/aarch64/_Float16_cmp_1.c54
-rw-r--r--gcc/testsuite/gcc.target/aarch64/_Float16_cmp_2.c7
-rw-r--r--gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c15
-rw-r--r--gcc/testsuite/gcc.target/i386/blendv-to-maxmin.c12
-rw-r--r--gcc/testsuite/gcc.target/i386/blendv-to-pand.c16
-rw-r--r--gcc/testsuite/gcc.target/i386/pr89618-2.c8
-rw-r--r--gcc/testsuite/gcc.target/i386/recip-vec-divf-fma.c12
-rw-r--r--gcc/testsuite/gcc.target/mips/clear-cache-1.c2
-rw-r--r--gcc/testsuite/gcc.target/mips/memcpy-2.c12
-rw-r--r--gcc/testsuite/gcc.target/powerpc/power11-3.c1
-rw-r--r--gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c48
-rw-r--r--gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c50
-rw-r--r--gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c35
-rw-r--r--gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c51
-rw-r--r--gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c34
-rw-r--r--gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c56
16 files changed, 410 insertions, 3 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_1.c b/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_1.c
new file mode 100644
index 0000000..e49ace1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_1.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.2-a+fp16" } */
+
+/*
+** test_fcmp_store:
+** fcmp h0, h1
+** cset w0, eq
+** ret
+*/
+int
+test_fcmp_store(_Float16 a, _Float16 b)
+{
+ return a == b;
+}
+
+/*
+** test_fcmpe_store:
+** fcmpe h0, h1
+** cset w0, mi
+** ret
+*/
+int
+test_fcmpe_store(_Float16 a, _Float16 b)
+{
+ return a < b;
+}
+
+/*
+** test_fcmp_branch:
+** fcmp h0, h1
+** ...
+*/
+_Float16
+test_fcmp_branch(_Float16 a, _Float16 b)
+{
+ if (a == b)
+ return a * b;
+ return a;
+}
+
+/*
+** test_fcmpe_branch:
+** fcmpe h0, h1
+** ...
+*/
+_Float16
+test_fcmpe_branch(_Float16 a, _Float16 b)
+{
+ if (a < b)
+ return a * b;
+ return a;
+}
+
+/* { dg-final { check-function-bodies "**" "" "" } } */ \ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_2.c b/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_2.c
new file mode 100644
index 0000000..0ff7cda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.2-a+nofp16" } */
+
+#include "_Float16_cmp_1.c"
+
+/* { dg-final { scan-assembler-not {\tfcmp\th[0-9]+} } } */
+/* { dg-final { scan-assembler-not {\tfcmpe\th[0-9]+} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
index dcac6d5..3799fb4 100644
--- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
@@ -315,3 +315,18 @@
#ifndef __ARM_FEATURE_FP8DOT2
#error Foo
#endif
+
+#pragma GCC target "arch=armv9.4-a"
+#ifdef __ARM_FEATURE_FAMINMAX
+#error Foo
+#endif
+
+#pragma GCC target "arch=armv9.5-a"
+#ifndef __ARM_FEATURE_FAMINMAX
+#error Foo
+#endif
+
+#pragma GCC target "arch=armv8-a+faminmax"
+#ifndef __ARM_FEATURE_FAMINMAX
+#error Foo
+#endif
diff --git a/gcc/testsuite/gcc.target/i386/blendv-to-maxmin.c b/gcc/testsuite/gcc.target/i386/blendv-to-maxmin.c
new file mode 100644
index 0000000..042eb7d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/blendv-to-maxmin.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64-v3 -O2 -mfpmath=sse" } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */
+
+double
+foo (double a)
+{
+ if (a > 0.0)
+ return a;
+ return 0.0;
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/blendv-to-pand.c b/gcc/testsuite/gcc.target/i386/blendv-to-pand.c
new file mode 100644
index 0000000..2896a2b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/blendv-to-pand.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64-v3 -mfpmath=sse" } */
+/* { dg-final { scan-assembler-not "vblendv" } } */
+
+void
+foo (float* a, float* b, float* c, float* __restrict d, int n)
+{
+ for (int i = 0; i != n; i++)
+ {
+ c[i] *= 2.0f;
+ if (a[i] > b[i])
+ d[i] = 0.0f;
+ else
+ d[i] = c[i];
+ }
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr89618-2.c b/gcc/testsuite/gcc.target/i386/pr89618-2.c
index c414053..11d658f 100644
--- a/gcc/testsuite/gcc.target/i386/pr89618-2.c
+++ b/gcc/testsuite/gcc.target/i386/pr89618-2.c
@@ -19,5 +19,9 @@ void foo (int n, int *off, double *a)
}
/* Make sure the cost model selects SSE vectors rather than AVX to avoid
- too many scalar ops for the address computes in the loop. */
-/* { dg-final { scan-tree-dump "loop vectorized using 16 byte vectors" "vect" { target { ! ia32 } } } } */
+ too many scalar ops for the address computes in the loop.
+
+ Since open-coded scatters are costed wrong, we no longer vectorize after fixing
+ COND_EXPR costs. See PR119902. */
+/* { dg-final { scan-tree-dump "loop vectorized using 16 byte vectors" "vect" { target { ! ia32 } xfail *-*-* } } } */
+/* { dg-final { scan-tree-dump-not "loop vectorized using 32 byte vectors" "vect" { target { ! ia32 } } } } */
diff --git a/gcc/testsuite/gcc.target/i386/recip-vec-divf-fma.c b/gcc/testsuite/gcc.target/i386/recip-vec-divf-fma.c
new file mode 100644
index 0000000..ad9e07b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/recip-vec-divf-fma.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast -mfma -mavx2" } */
+/* { dg-final { scan-assembler-times {(?n)vfn?m(add|sub)[1-3]*ps} 2 } } */
+
+typedef float v4sf __attribute__((vector_size(16)));
+/* (a - (rcp(b) * a * b)) * rcp(b) + rcp(b) * a */
+
+v4sf
+foo (v4sf a, v4sf b)
+{
+ return a / b;
+}
diff --git a/gcc/testsuite/gcc.target/mips/clear-cache-1.c b/gcc/testsuite/gcc.target/mips/clear-cache-1.c
index f1554f5..cd11c66 100644
--- a/gcc/testsuite/gcc.target/mips/clear-cache-1.c
+++ b/gcc/testsuite/gcc.target/mips/clear-cache-1.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-msynci isa_rev>=2" } */
/* { dg-final { scan-assembler "\tsynci\t" } } */
-/* { dg-final { scan-assembler "\tjr.hb\t" } } */
+/* { dg-final { scan-assembler "\tjrc?.hb\t" } } */
/* { dg-final { scan-assembler-not "_flush_cache|mips_sync_icache|_cacheflush" } } */
NOMIPS16 void f()
diff --git a/gcc/testsuite/gcc.target/mips/memcpy-2.c b/gcc/testsuite/gcc.target/mips/memcpy-2.c
new file mode 100644
index 0000000..df0cd18
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/memcpy-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "isa_rev<=5 -fdump-rtl-expand" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-Os" } { "" } } */
+
+__attribute__((nomips16))
+void
+f1 (char *p)
+{
+ __builtin_memcpy (p, "12345", 5);
+}
+
+/* { dg-final { scan-rtl-dump "mem/u.*mem/u" "expand" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c b/gcc/testsuite/gcc.target/powerpc/power11-3.c
index fa1aedd..56bf881 100644
--- a/gcc/testsuite/gcc.target/powerpc/power11-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+/* { dg-require-ifunc "" } */
/* Check if we can set the power11 target via a target_clones attribute. */
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
new file mode 100644
index 0000000..cb28baf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=xt-c908" { target { rv64 } } } */
+/* XuanTie C908 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_
+zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_sstc_svinval_svnapot_svpbmt_xtheadba_
+xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_
+xtheadmemidx_xtheadmempair_xtheadsync */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && defined(__riscv_mul) \
+ && defined(__riscv_atomic) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_compressed) \
+ && defined(__riscv_zicbom) \
+ && defined(__riscv_zicbop) \
+ && defined(__riscv_zicboz) \
+ && defined(__riscv_zicntr) \
+ && defined(__riscv_zicsr) \
+ && defined(__riscv_zifencei) \
+ && defined(__riscv_zihintpause) \
+ && defined(__riscv_zihpm) \
+ && defined(__riscv_zfh) \
+ && defined(__riscv_zba) \
+ && defined(__riscv_zbb) \
+ && defined(__riscv_zbc) \
+ && defined(__riscv_zbs) \
+ && defined(__riscv_sstc) \
+ && defined(__riscv_svinval) \
+ && defined(__riscv_svnapot) \
+ && defined(__riscv_svpbmt) \
+ && defined(__riscv_xtheadba) \
+ && defined(__riscv_xtheadbb) \
+ && defined(__riscv_xtheadbs) \
+ && defined(__riscv_xtheadcmo) \
+ && defined(__riscv_xtheadcondmov) \
+ && defined(__riscv_xtheadfmemidx) \
+ && defined(__riscv_xtheadmac) \
+ && defined(__riscv_xtheadmemidx) \
+ && defined(__riscv_xtheadmempair) \
+ && defined(__riscv_xtheadsync))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
new file mode 100644
index 0000000..1b1ee18
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=xt-c908v" { target { rv64 } } } */
+/* XuanTie C908v => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_
+zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_sstc_svinval_svnapot_svpbmt_xtheadba_
+xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_
+xtheadmemidx_xtheadmempair_xtheadsync_xtheadvdot */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && defined(__riscv_mul) \
+ && defined(__riscv_atomic) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_compressed) \
+ && defined(__riscv_v) \
+ && defined(__riscv_zicbom) \
+ && defined(__riscv_zicbop) \
+ && defined(__riscv_zicboz) \
+ && defined(__riscv_zicntr) \
+ && defined(__riscv_zicsr) \
+ && defined(__riscv_zifencei) \
+ && defined(__riscv_zihintpause) \
+ && defined(__riscv_zihpm) \
+ && defined(__riscv_zfh) \
+ && defined(__riscv_zba) \
+ && defined(__riscv_zbb) \
+ && defined(__riscv_zbc) \
+ && defined(__riscv_zbs) \
+ && defined(__riscv_sstc) \
+ && defined(__riscv_svinval) \
+ && defined(__riscv_svnapot) \
+ && defined(__riscv_svpbmt) \
+ && defined(__riscv_xtheadba) \
+ && defined(__riscv_xtheadbb) \
+ && defined(__riscv_xtheadbs) \
+ && defined(__riscv_xtheadcmo) \
+ && defined(__riscv_xtheadcondmov) \
+ && defined(__riscv_xtheadfmemidx) \
+ && defined(__riscv_xtheadmac) \
+ && defined(__riscv_xtheadmemidx) \
+ && defined(__riscv_xtheadmempair) \
+ && defined(__riscv_xtheadsync) \
+ && defined (__riscv__xtheadvdot))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
new file mode 100644
index 0000000..1e27665
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=xt-c910" { target { rv64 } } } */
+/* XuanTie C910 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_xtheadba_
+xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_
+xtheadmemidx_xtheadmempair_xtheadsync */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && defined(__riscv_mul) \
+ && defined(__riscv_atomic) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_compressed) \
+ && defined(__riscv_zicntr) \
+ && defined(__riscv_zicsr) \
+ && defined(__riscv_zifencei) \
+ && defined(__riscv_zihpm) \
+ && defined(__riscv_zfh) \
+ && defined(__riscv_xtheadba) \
+ && defined(__riscv_xtheadbb) \
+ && defined(__riscv_xtheadbs) \
+ && defined(__riscv_xtheadcmo) \
+ && defined(__riscv_xtheadcondmov) \
+ && defined(__riscv_xtheadfmemidx) \
+ && defined(__riscv_xtheadmac) \
+ && defined(__riscv_xtheadmemidx) \
+ && defined(__riscv_xtheadmempair) \
+ && defined(__riscv_xtheadsync))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
new file mode 100644
index 0000000..6a54f09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=xt-c910v2" { target { rv64 } } } */
+/* XuanTie C910v2 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_
+zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_
+zbb_zbc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_
+xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && defined(__riscv_mul) \
+ && defined(__riscv_atomic) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_compressed) \
+ && defined(__riscv_zicbom) \
+ && defined(__riscv_zicbop) \
+ && defined(__riscv_zicboz) \
+ && defined(__riscv_zicntr) \
+ && defined(__riscv_zicond) \
+ && defined(__riscv_zicsr) \
+ && defined(__riscv_zifencei ) \
+ && defined(__riscv_zihintntl) \
+ && defined(__riscv_zihintpause) \
+ && defined(__riscv_zihpm) \
+ && defined(__riscv_zawrs) \
+ && defined(__riscv_zfa) \
+ && defined(__riscv_zfbfmin) \
+ && defined(__riscv_zfh) \
+ && defined(__riscv_zca) \
+ && defined(__riscv_zcb) \
+ && defined(__riscv_zcd) \
+ && defined(__riscv_zba) \
+ && defined(__riscv_zbb) \
+ && defined(__riscv_zbc) \
+ && defined(__riscv_xtheadba) \
+ && defined(__riscv_xtheadbb) \
+ && defined(__riscv_xtheadbs) \
+ && defined(__riscv_xtheadcmo) \
+ && defined(__riscv_xtheadcondmov) \
+ && defined(__riscv_xtheadfmemidx) \
+ && defined(__riscv_xtheadmac) \
+ && defined(__riscv_xtheadmemidx) \
+ && defined(__riscv_xtheadmempair) \
+ && defined(__riscv_xtheadsync))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
new file mode 100644
index 0000000..6bcd687
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=xt-c920" { target { rv64 } } } */
+/* XuanTie c920 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync_xtheadvector */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && defined(__riscv_mul) \
+ && defined(__riscv_atomic) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_compressed) \
+ && defined(__riscv_zicntr) \
+ && defined(__riscv_zicsr) \
+ && defined(__riscv_zifencei) \
+ && defined(__riscv_zihpm) \
+ && defined(__riscv_zfh) \
+ && defined(__riscv_xtheadba) \
+ && defined(__riscv_xtheadbb) \
+ && defined(__riscv_xtheadbs) \
+ && defined(__riscv_xtheadcmo) \
+ && defined(__riscv_xtheadcondmov) \
+ && defined(__riscv_xtheadfmemidx) \
+ && defined(__riscv_xtheadmac) \
+ && defined(__riscv_xtheadmemidx) \
+ && defined(__riscv_xtheadmempair) \
+ && defined(__riscv_xtheadsync) \
+ && defined(__riscv_xtheadvector))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
new file mode 100644
index 0000000..36a6267
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
@@ -0,0 +1,56 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=xt-c920v2" { target { rv64 } } } */
+/* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync_xtheadvdot */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && defined(__riscv_mul) \
+ && defined(__riscv_atomic) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_compressed) \
+ && defined(__riscv_v) \
+ && defined(__riscv_zicbom) \
+ && defined(__riscv_zicbop) \
+ && defined(__riscv_zicboz) \
+ && defined(__riscv_zicntr) \
+ && defined(__riscv_zicond) \
+ && defined(__riscv_zicsr) \
+ && defined(__riscv_zifencei ) \
+ && defined(__riscv_zihintntl) \
+ && defined(__riscv_zihintpause) \
+ && defined(__riscv_zihpm) \
+ && defined(__riscv_zawrs) \
+ && defined(__riscv_zfa) \
+ && defined(__riscv_zfbfmin) \
+ && defined(__riscv_zfh) \
+ && defined(__riscv_zca) \
+ && defined(__riscv_zcb) \
+ && defined(__riscv_zcd) \
+ && defined(__riscv_zba) \
+ && defined(__riscv_zbb) \
+ && defined(__riscv_zbc) \
+ && defined(__riscv_zbs) \
+ && defined(__riscv_zvfbfmin) \
+ && defined(__riscv_zvfbfwma) \
+ && defined(__riscv_zvfh) \
+ && defined(__riscv_sscofpmf) \
+ && defined(__riscv_sstc) \
+ && defined(__riscv_svinval) \
+ && defined(__riscv_svnapot) \
+ && defined(__riscv_svpbmt) \
+ && defined(__riscv_xtheadba) \
+ && defined(__riscv_xtheadbb) \
+ && defined(__riscv_xtheadbs) \
+ && defined(__riscv_xtheadcmo) \
+ && defined(__riscv_xtheadcondmov) \
+ && defined(__riscv_xtheadfmemidx) \
+ && defined(__riscv_xtheadsync) \
+ && defined(__riscv_xtheadvdot))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
generated by cgit v1.1 at 2025-04-24 04:43:15 +0000