diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
47 files changed, 955 insertions, 310 deletions
diff --git a/gcc/testsuite/gcc.target/arm/ivopts.c b/gcc/testsuite/gcc.target/arm/ivopts.c index 582fdab..6e3e74c 100644 --- a/gcc/testsuite/gcc.target/arm/ivopts.c +++ b/gcc/testsuite/gcc.target/arm/ivopts.c @@ -12,5 +12,4 @@ tr5 (short array[], int n) /* { dg-final { scan-tree-dump-times "PHI <" 1 "ivopts"} } */ /* { dg-final { object-size text <= 20 { target { arm_thumb2_no_arm_v8_1m_lob } } } } */ -/* { dg-final { object-size text <= 32 { target { arm_nothumb && { ! arm_iwmmxt_ok } } } } } */ -/* { dg-final { object-size text <= 36 { target { arm_nothumb && arm_iwmmxt_ok } } } } */ +/* { dg-final { object-size text <= 32 { target { arm_nothumb } } } } */ diff --git a/gcc/testsuite/gcc.target/arm/mmx-1.c b/gcc/testsuite/gcc.target/arm/mmx-1.c deleted file mode 100644 index 8060dbd..0000000 --- a/gcc/testsuite/gcc.target/arm/mmx-1.c +++ /dev/null @@ -1,26 +0,0 @@ -/* Verify that if IP is saved to ensure stack alignment, we don't load - it into sp. */ -/* { dg-do compile } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ -/* { dg-options "-O -mno-apcs-frame -mcpu=iwmmxt -mabi=iwmmxt" } */ -/* { dg-require-effective-target arm32 } */ -/* { dg-require-effective-target arm_iwmmxt_ok } */ -/* { dg-final { scan-assembler "push.*ip,\[ ]*pc" } } */ -/* { dg-skip-if "r9 is reserved in FDPIC" { arm*-*-uclinuxfdpiceabi } "*" "" } */ - -/* This function uses all the call-saved registers, namely r4, r5, r6, - r7, r8, r9, sl, fp. Since we also save lr, that leaves an odd - number of registers, and the compiler will push ip to align the - stack. Make sure that we restore ip into ip, not into sp as is - done when using a frame pointer. The -mno-apcs-frame option - permits the frame pointer to be used as an ordinary register. */ - -void -foo(void) -{ - __asm volatile ("" : : : - "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "lr"); -} diff --git a/gcc/testsuite/gcc.target/arm/mmx-2.c b/gcc/testsuite/gcc.target/arm/mmx-2.c deleted file mode 100644 index 0540f65..0000000 --- a/gcc/testsuite/gcc.target/arm/mmx-2.c +++ /dev/null @@ -1,166 +0,0 @@ -/* { dg-do compile } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ -/* { dg-require-effective-target arm32 } */ -/* { dg-require-effective-target arm_iwmmxt_ok } */ -/* { dg-options "-mcpu=iwmmxt -flax-vector-conversions -std=gnu99" } */ - -/* Internal data types for implementing the intrinsics. */ -typedef int __v2si __attribute__ ((vector_size (8))); -typedef short __v4hi __attribute__ ((vector_size (8))); -typedef signed char __v8qi __attribute__ ((vector_size (8))); - -void -foo(void) -{ - volatile int isink; - volatile long long llsink; - volatile __v8qi v8sink; - volatile __v4hi v4sink; - volatile __v2si v2sink; - - isink = __builtin_arm_getwcgr0 (); - __builtin_arm_setwcgr0 (isink); - isink = __builtin_arm_getwcgr1 (); - __builtin_arm_setwcgr1 (isink); - isink = __builtin_arm_getwcgr2 (); - __builtin_arm_setwcgr2 (isink); - isink = __builtin_arm_getwcgr3 (); - __builtin_arm_setwcgr3 (isink); - - isink = __builtin_arm_textrmsb (v8sink, 0); - isink = __builtin_arm_textrmsh (v4sink, 0); - isink = __builtin_arm_textrmsw (v2sink, 0); - isink = __builtin_arm_textrmub (v8sink, 0); - isink = __builtin_arm_textrmuh (v4sink, 0); - isink = __builtin_arm_textrmuw (v2sink, 0); - v8sink = __builtin_arm_tinsrb (v8sink, isink, 0); - v4sink = __builtin_arm_tinsrh (v4sink, isink, 0); - v2sink = __builtin_arm_tinsrw (v2sink, isink, 0); - llsink = __builtin_arm_tmia (llsink, isink, isink); - llsink = __builtin_arm_tmiabb (llsink, isink, isink); - llsink = __builtin_arm_tmiabt (llsink, isink, isink); - llsink = __builtin_arm_tmiaph (llsink, isink, isink); - llsink = __builtin_arm_tmiatb (llsink, isink, isink); - llsink = __builtin_arm_tmiatt (llsink, isink, isink); - isink = __builtin_arm_tmovmskb (v8sink); - isink = __builtin_arm_tmovmskh (v4sink); - isink = __builtin_arm_tmovmskw (v2sink); - llsink = __builtin_arm_waccb (v8sink); - llsink = __builtin_arm_wacch (v4sink); - llsink = __builtin_arm_waccw (v2sink); - v8sink = __builtin_arm_waddb (v8sink, v8sink); - v8sink = __builtin_arm_waddbss (v8sink, v8sink); - v8sink = __builtin_arm_waddbus (v8sink, v8sink); - v4sink = __builtin_arm_waddh (v4sink, v4sink); - v4sink = __builtin_arm_waddhss (v4sink, v4sink); - v4sink = __builtin_arm_waddhus (v4sink, v4sink); - v2sink = __builtin_arm_waddw (v2sink, v2sink); - v2sink = __builtin_arm_waddwss (v2sink, v2sink); - v2sink = __builtin_arm_waddwus (v2sink, v2sink); - v8sink = __builtin_arm_walign (v8sink, v8sink, 0); /* waligni: 3-bit immediate. */ - v8sink = __builtin_arm_walign (v8sink, v8sink, isink); /* walignr: GP register. */ - llsink = __builtin_arm_wand(llsink, llsink); - llsink = __builtin_arm_wandn (llsink, llsink); - v8sink = __builtin_arm_wavg2b (v8sink, v8sink); - v8sink = __builtin_arm_wavg2br (v8sink, v8sink); - v4sink = __builtin_arm_wavg2h (v4sink, v4sink); - v4sink = __builtin_arm_wavg2hr (v4sink, v4sink); - v8sink = __builtin_arm_wcmpeqb (v8sink, v8sink); - v4sink = __builtin_arm_wcmpeqh (v4sink, v4sink); - v2sink = __builtin_arm_wcmpeqw (v2sink, v2sink); - v8sink = __builtin_arm_wcmpgtsb (v8sink, v8sink); - v4sink = __builtin_arm_wcmpgtsh (v4sink, v4sink); - v2sink = __builtin_arm_wcmpgtsw (v2sink, v2sink); - v8sink = __builtin_arm_wcmpgtub (v8sink, v8sink); - v4sink = __builtin_arm_wcmpgtuh (v4sink, v4sink); - v2sink = __builtin_arm_wcmpgtuw (v2sink, v2sink); - llsink = __builtin_arm_wmacs (llsink, v4sink, v4sink); - llsink = __builtin_arm_wmacsz (v4sink, v4sink); - llsink = __builtin_arm_wmacu (llsink, v4sink, v4sink); - llsink = __builtin_arm_wmacuz (v4sink, v4sink); - v4sink = __builtin_arm_wmadds (v4sink, v4sink); - v4sink = __builtin_arm_wmaddu (v4sink, v4sink); - v8sink = __builtin_arm_wmaxsb (v8sink, v8sink); - v4sink = __builtin_arm_wmaxsh (v4sink, v4sink); - v2sink = __builtin_arm_wmaxsw (v2sink, v2sink); - v8sink = __builtin_arm_wmaxub (v8sink, v8sink); - v4sink = __builtin_arm_wmaxuh (v4sink, v4sink); - v2sink = __builtin_arm_wmaxuw (v2sink, v2sink); - v8sink = __builtin_arm_wminsb (v8sink, v8sink); - v4sink = __builtin_arm_wminsh (v4sink, v4sink); - v2sink = __builtin_arm_wminsw (v2sink, v2sink); - v8sink = __builtin_arm_wminub (v8sink, v8sink); - v4sink = __builtin_arm_wminuh (v4sink, v4sink); - v2sink = __builtin_arm_wminuw (v2sink, v2sink); - v4sink = __builtin_arm_wmulsm (v4sink, v4sink); - v4sink = __builtin_arm_wmulul (v4sink, v4sink); - v4sink = __builtin_arm_wmulum (v4sink, v4sink); - llsink = __builtin_arm_wor (llsink, llsink); - v2sink = __builtin_arm_wpackdss (llsink, llsink); - v2sink = __builtin_arm_wpackdus (llsink, llsink); - v8sink = __builtin_arm_wpackhss (v4sink, v4sink); - v8sink = __builtin_arm_wpackhus (v4sink, v4sink); - v4sink = __builtin_arm_wpackwss (v2sink, v2sink); - v4sink = __builtin_arm_wpackwus (v2sink, v2sink); - llsink = __builtin_arm_wrord (llsink, llsink); - llsink = __builtin_arm_wrordi (llsink, isink); - v4sink = __builtin_arm_wrorh (v4sink, llsink); - v4sink = __builtin_arm_wrorhi (v4sink, isink); - v2sink = __builtin_arm_wrorw (v2sink, llsink); - v2sink = __builtin_arm_wrorwi (v2sink, isink); - v2sink = __builtin_arm_wsadb (v2sink, v8sink, v8sink); - v2sink = __builtin_arm_wsadbz (v8sink, v8sink); - v2sink = __builtin_arm_wsadh (v2sink, v4sink, v4sink); - v2sink = __builtin_arm_wsadhz (v4sink, v4sink); - v4sink = __builtin_arm_wshufh (v4sink, 0); - llsink = __builtin_arm_wslld (llsink, llsink); - llsink = __builtin_arm_wslldi (llsink, 0); - v4sink = __builtin_arm_wsllh (v4sink, llsink); - v4sink = __builtin_arm_wsllhi (v4sink, isink); - v2sink = __builtin_arm_wsllw (v2sink, llsink); - v2sink = __builtin_arm_wsllwi (v2sink, isink); - llsink = __builtin_arm_wsrad (llsink, llsink); - llsink = __builtin_arm_wsradi (llsink, isink); - v4sink = __builtin_arm_wsrah (v4sink, llsink); - v4sink = __builtin_arm_wsrahi (v4sink, isink); - v2sink = __builtin_arm_wsraw (v2sink, llsink); - v2sink = __builtin_arm_wsrawi (v2sink, isink); - llsink = __builtin_arm_wsrld (llsink, llsink); - llsink = __builtin_arm_wsrldi (llsink, isink); - v4sink = __builtin_arm_wsrlh (v4sink, llsink); - v4sink = __builtin_arm_wsrlhi (v4sink, isink); - v2sink = __builtin_arm_wsrlw (v2sink, llsink); - v2sink = __builtin_arm_wsrlwi (v2sink, isink); - v8sink = __builtin_arm_wsubb (v8sink, v8sink); - v8sink = __builtin_arm_wsubbss (v8sink, v8sink); - v8sink = __builtin_arm_wsubbus (v8sink, v8sink); - v4sink = __builtin_arm_wsubh (v4sink, v4sink); - v4sink = __builtin_arm_wsubhss (v4sink, v4sink); - v4sink = __builtin_arm_wsubhus (v4sink, v4sink); - v2sink = __builtin_arm_wsubw (v2sink, v2sink); - v2sink = __builtin_arm_wsubwss (v2sink, v2sink); - v2sink = __builtin_arm_wsubwus (v2sink, v2sink); - v4sink = __builtin_arm_wunpckehsb (v8sink); - v2sink = __builtin_arm_wunpckehsh (v4sink); - llsink = __builtin_arm_wunpckehsw (v2sink); - v4sink = __builtin_arm_wunpckehub (v8sink); - v2sink = __builtin_arm_wunpckehuh (v4sink); - llsink = __builtin_arm_wunpckehuw (v2sink); - v4sink = __builtin_arm_wunpckelsb (v8sink); - v2sink = __builtin_arm_wunpckelsh (v4sink); - llsink = __builtin_arm_wunpckelsw (v2sink); - v4sink = __builtin_arm_wunpckelub (v8sink); - v2sink = __builtin_arm_wunpckeluh (v4sink); - llsink = __builtin_arm_wunpckeluw (v2sink); - v8sink = __builtin_arm_wunpckihb (v8sink, v8sink); - v4sink = __builtin_arm_wunpckihh (v4sink, v4sink); - v2sink = __builtin_arm_wunpckihw (v2sink, v2sink); - v8sink = __builtin_arm_wunpckilb (v8sink, v8sink); - v4sink = __builtin_arm_wunpckilh (v4sink, v4sink); - v2sink = __builtin_arm_wunpckilw (v2sink, v2sink); - llsink = __builtin_arm_wxor (llsink, llsink); - llsink = __builtin_arm_wzero (); -} diff --git a/gcc/testsuite/gcc.target/arm/pr64208.c b/gcc/testsuite/gcc.target/arm/pr64208.c deleted file mode 100644 index 96fd56d..0000000 --- a/gcc/testsuite/gcc.target/arm/pr64208.c +++ /dev/null @@ -1,25 +0,0 @@ -/* { dg-do compile } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ -/* { dg-require-effective-target arm32 } */ -/* { dg-require-effective-target arm_iwmmxt_ok } */ -/* { dg-options "-O1 -mcpu=iwmmxt" } */ - -long long x6(void); -void x7(long long, long long); -void x8(long long); - -int x0; -long long *x1; - -void x2(void) { - long long *x3 = x1; - while (x1) { - long long x4 = x0, x5 = x6(); - x7(x4, x5); - x8(x5); - *x3 = 0; - } -} diff --git a/gcc/testsuite/gcc.target/arm/pr79145.c b/gcc/testsuite/gcc.target/arm/pr79145.c deleted file mode 100644 index 6678244..0000000 --- a/gcc/testsuite/gcc.target/arm/pr79145.c +++ /dev/null @@ -1,16 +0,0 @@ -/* { dg-do compile } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ -/* { dg-require-effective-target arm32 } */ -/* { dg-require-effective-target arm_iwmmxt_ok } */ -/* { dg-options "-mcpu=iwmmxt" } */ - -int -main (void) -{ - volatile long long t1; - t1 ^= 0x55; - return 0; -} diff --git a/gcc/testsuite/gcc.target/arm/pr99724.c b/gcc/testsuite/gcc.target/arm/pr99724.c deleted file mode 100644 index 5411078..0000000 --- a/gcc/testsuite/gcc.target/arm/pr99724.c +++ /dev/null @@ -1,31 +0,0 @@ -/* PR target/99724 */ -/* { dg-do compile } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ -/* { dg-require-effective-target arm32 } */ -/* { dg-require-effective-target arm_iwmmxt_ok } */ -/* { dg-options "-O1 -mcpu=iwmmxt" } */ - -typedef int V __attribute__((vector_size (8))); -struct __attribute__((packed)) S { char a; V b; char c[7]; }; - -void -foo (V *x) -{ - *x = ~*x; -} - -void -bar (V *x) -{ - *x = -*x; -} - -void -baz (V *x, struct S *p) -{ - V y = p->b; - *x = y; -} diff --git a/gcc/testsuite/gcc.target/arm/pr99786.c b/gcc/testsuite/gcc.target/arm/pr99786.c deleted file mode 100644 index 11d86f0..0000000 --- a/gcc/testsuite/gcc.target/arm/pr99786.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ -/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ -/* { dg-require-effective-target arm32 } */ -/* { dg-require-effective-target arm_iwmmxt_ok } */ -/* { dg-options "-O3 -mcpu=iwmmxt" } */ - -typedef signed char V __attribute__((vector_size (8))); - -void -foo (V *a) -{ - *a = *a * 3; -} - -typedef signed short Vshort __attribute__((vector_size (8))); -void -foo_short (Vshort *a) -{ - *a = *a * 3; -} - -typedef signed int Vint __attribute__((vector_size (8))); -void -foo_int (Vint *a) -{ - *a = *a * 3; -} diff --git a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c index 41ee994..d9f95a1 100644 --- a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c +++ b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c @@ -1,6 +1,31 @@ /* { dg-do compile } */ -/* { dg-require-effective-target arm_thumb2_ok_no_arm_v8_1m_lob } */ -/* { dg-options "-O" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-O2 -mthumb" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** foo: +** movs (r[0-9]+), #8 +** ( +** subs \1, \1, #1 +** ands \1, \1, #255 +** and r0, r1, r0, lsr #1 +** bne .L[0-9]+ +** bx lr +** | +** subs \1, \1, #1 +** and r0, r1, r0, lsr #1 +** ands \1, \1, #255 +** bne .L[0-9]+ +** bx lr +** | +** push {lr} +** dls lr, \1 +** and r0, r1, r0, lsr #1 +** le lr, .L[0-9]+ +** pop {pc} +** ) +*/ unsigned short foo (unsigned short x, unsigned short c) { @@ -12,7 +37,3 @@ unsigned short foo (unsigned short x, unsigned short c) } return x; } - -/* { dg-final { scan-assembler "ands" } } */ -/* { dg-final { scan-assembler-not "uxtb" } } */ -/* { dg-final { scan-assembler-not "cmp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr91446.c b/gcc/testsuite/gcc.target/i386/pr91446.c index 0243ca3..d129405 100644 --- a/gcc/testsuite/gcc.target/i386/pr91446.c +++ b/gcc/testsuite/gcc.target/i386/pr91446.c @@ -21,4 +21,4 @@ foo (unsigned long long width, unsigned long long height, bar (&t); } -/* { dg-final { scan-assembler-times "vmovdqa\[^\n\r\]*xmm\[0-9\]" 2 } } */ +/* { dg-final { scan-assembler-times "vmovdqa\[^\n\r\]*xmm\[0-9\]" 2 { xfail *-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr99881.c b/gcc/testsuite/gcc.target/i386/pr99881.c index 3e087eb..a1ec1d1b 100644 --- a/gcc/testsuite/gcc.target/i386/pr99881.c +++ b/gcc/testsuite/gcc.target/i386/pr99881.c @@ -1,7 +1,7 @@ /* PR target/99881. */ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-Ofast -march=skylake" } */ -/* { dg-final { scan-assembler-not "xmm\[0-9\]" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not "xmm\[0-9\]" } } */ void foo (int* __restrict a, int n, int c) diff --git a/gcc/testsuite/gcc.target/mips/pr54240.c b/gcc/testsuite/gcc.target/mips/pr54240.c index d3976f6..31b793b 100644 --- a/gcc/testsuite/gcc.target/mips/pr54240.c +++ b/gcc/testsuite/gcc.target/mips/pr54240.c @@ -27,4 +27,4 @@ NOMIPS16 int foo(S *s) return next->v; } -/* { dg-final { scan-tree-dump "Hoisting adjacent loads" "phiopt1" } } */ +/* { dg-final { scan-tree-dump "Hoisting adjacent loads" "phiopt2" } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_61.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_61.c index 742e25d..d6e8ce9 100644 --- a/gcc/testsuite/gcc.target/nvptx/march-map=sm_61.c +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_61.c @@ -2,7 +2,7 @@ /* { dg-options {-march-map=sm_61 -mptx=_} } */ /* { dg-additional-options -save-temps } */ /* { dg-final { scan-assembler-times {(?n)^ \.version 7\.3$} 1 } } */ -/* { dg-final { scan-assembler-times {(?n)^ \.target sm_53$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_61$} 1 } } */ #if __PTX_ISA_VERSION_MAJOR__ != 7 #error wrong value for __PTX_ISA_VERSION_MAJOR__ @@ -12,7 +12,7 @@ #error wrong value for __PTX_ISA_VERSION_MINOR__ #endif -#if __PTX_SM__ != 530 +#if __PTX_SM__ != 610 #error wrong value for __PTX_SM__ #endif diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_62.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_62.c index 02ced4c..ccce6f7 100644 --- a/gcc/testsuite/gcc.target/nvptx/march-map=sm_62.c +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_62.c @@ -2,7 +2,7 @@ /* { dg-options {-march-map=sm_62 -mptx=_} } */ /* { dg-additional-options -save-temps } */ /* { dg-final { scan-assembler-times {(?n)^ \.version 7\.3$} 1 } } */ -/* { dg-final { scan-assembler-times {(?n)^ \.target sm_53$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_61$} 1 } } */ #if __PTX_ISA_VERSION_MAJOR__ != 7 #error wrong value for __PTX_ISA_VERSION_MAJOR__ @@ -12,7 +12,7 @@ #error wrong value for __PTX_ISA_VERSION_MINOR__ #endif -#if __PTX_SM__ != 530 +#if __PTX_SM__ != 610 #error wrong value for __PTX_SM__ #endif diff --git a/gcc/testsuite/gcc.target/nvptx/march=sm_61.c b/gcc/testsuite/gcc.target/nvptx/march=sm_61.c new file mode 100644 index 0000000..d8bccb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march=sm_61.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march=sm_61 -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.3$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_61$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 3 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 610 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/mptx=5.0.c b/gcc/testsuite/gcc.target/nvptx/mptx=5.0.c new file mode 100644 index 0000000..5d6163e --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/mptx=5.0.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march=sm_30 -mptx=5.0} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 5\.0$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_30$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 5 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 0 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 300 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/riscv/arch-52.c b/gcc/testsuite/gcc.target/riscv/arch-52.c index da6aea8..6133370 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-52.c +++ b/gcc/testsuite/gcc.target/riscv/arch-52.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=rva22u64v -mabi=lp64" } */ -/* { dg-warning "*Should use \"_\" to contact Profiles with other extensions" } */ +/* { dg-warning "Should use \"_\" to contact Profiles with other extensions" "" { target *-*-* } 0 } */ int foo () {} diff --git a/gcc/testsuite/gcc.target/riscv/arch-ss-1.c b/gcc/testsuite/gcc.target/riscv/arch-ss-1.c new file mode 100644 index 0000000..8f95737 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-ss-1.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_ssnpm_smnpm_smmpm_sspm_supm -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-ss-2.c b/gcc/testsuite/gcc.target/riscv/arch-ss-2.c new file mode 100644 index 0000000..f1d7724 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-ss-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm -mabi=ilp32d" } */ +int foo() +{ +} +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-1.c b/gcc/testsuite/gcc.target/riscv/arch-zilsd-1.c new file mode 100644 index 0000000..452c04e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-1.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zilsd_zclsd -mabi=ilp32d" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c b/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c new file mode 100644 index 0000000..5d6185d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zilsd -mabi=ilp32d" } */ +int foo() +{ +} +/* { dg-error "'-march=rv64gc_zilsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c b/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c new file mode 100644 index 0000000..3cda120 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zclsd -mabi=ilp32d" } */ +int foo() +{ +} +/* { dg-error "'-march=rv64gc_zclsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64gc_zclsd': zclsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd_zclsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd_zclsd': zclsd extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h index 7db892c..983c9b4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h @@ -123,6 +123,22 @@ vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_ADD_FMT_9(WT, T) \ +void __attribute__((noinline)) \ +vec_sat_u_add_##WT##_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + T max = -1; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + WT val = (WT)x + (WT)y; \ + out[i] = val > max ? max : (T)val; \ + } \ +} +#define DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) DEF_VEC_SAT_U_ADD_FMT_9(WT, T) + #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N) @@ -147,6 +163,21 @@ vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_ADD_FMT_8(T, out, op_1, op_2, N) \ vec_sat_u_add_##T##_fmt_8(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16(T, out, op_1, op_2, N) \ + vec_sat_u_add_uint16_t_##T##_fmt_9(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16(T, out, op_1, op_2, N) + +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32(T, out, op_1, op_2, N) \ + vec_sat_u_add_uint32_t_##T##_fmt_9(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32(T, out, op_1, op_2, N) + +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64(T, out, op_1, op_2, N) \ + vec_sat_u_add_uint64_t_##T##_fmt_9(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64(T, out, op_1, op_2, N) + #define DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM) \ T __attribute__((noinline)) \ vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c new file mode 100644 index 0000000..6e9cbd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint32_t, uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c new file mode 100644 index 0000000..3ab4641 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint64_t, uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c new file mode 100644 index 0000000..57aa772 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint64_t, uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c new file mode 100644 index 0000000..d14fe00 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint16_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c new file mode 100644 index 0000000..240af94 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint32_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c new file mode 100644 index 0000000..706d4f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint64_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c new file mode 100644 index 0000000..06d3ba0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define WT uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 65534, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 9, + }, + { + 0, 1, 2, 65534, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c new file mode 100644 index 0000000..64dbde7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define WT uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 65534, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 9, + }, + { + 0, 1, 2, 65534, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c new file mode 100644 index 0000000..2523126 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint32_t +#define WT uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 9, + }, + { + 0, 1, 1, 4294967294, + 4294967294, 4294967294, 4294967294, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 9, + }, + { + 0, 1, 2, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c new file mode 100644 index 0000000..4cd4817 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define WT uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 254, 255, 9, + }, + { + 0, 1, 1, 254, + 254, 254, 254, 255, + 255, 255, 255, 255, + 255, 255, 255, 9, + }, + { + 0, 1, 2, 254, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c new file mode 100644 index 0000000..6b46465 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define WT uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 254, 255, 9, + }, + { + 0, 1, 1, 254, + 254, 254, 254, 255, + 255, 255, 255, 255, + 255, 255, 255, 9, + }, + { + 0, 1, 2, 254, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c new file mode 100644 index 0000000..4cd4817 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define WT uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 254, 255, 9, + }, + { + 0, 1, 1, 254, + 254, 254, 254, 255, + 255, 255, 255, 255, + 255, 255, 255, 9, + }, + { + 0, 1, 2, 254, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h index c8a135a..2225d30 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h @@ -53,12 +53,34 @@ sat_u_add_##T##_fmt_6 (T x, T y) \ return (T)(x + y) < x ? -1 : (x + y); \ } +#define DEF_SAT_U_ADD_FMT_7(WT, T) \ +T __attribute__((noinline)) \ +sat_u_add_##WT##_##T##_fmt_7(T x, T y) \ +{ \ + T max = -1; \ + WT val = (WT)x + (WT)y; \ + return val > max ? max : (T)val; \ +} +#define DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) DEF_SAT_U_ADD_FMT_7(WT, T) + #define RUN_SAT_U_ADD_FMT_1(T, x, y) sat_u_add_##T##_fmt_1(x, y) #define RUN_SAT_U_ADD_FMT_2(T, x, y) sat_u_add_##T##_fmt_2(x, y) #define RUN_SAT_U_ADD_FMT_3(T, x, y) sat_u_add_##T##_fmt_3(x, y) #define RUN_SAT_U_ADD_FMT_4(T, x, y) sat_u_add_##T##_fmt_4(x, y) #define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y) #define RUN_SAT_U_ADD_FMT_6(T, x, y) sat_u_add_##T##_fmt_6(x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U16(T, x, y) \ + sat_u_add_uint16_t_##T##_fmt_7(x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP(T, x, y) \ + RUN_SAT_U_ADD_FMT_7_FROM_U16(T, x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U32(T, x, y) \ + sat_u_add_uint32_t_##T##_fmt_7(x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP(T, x, y) \ + RUN_SAT_U_ADD_FMT_7_FROM_U32(T, x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U64(T, x, y) \ + sat_u_add_uint64_t_##T##_fmt_7(x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T, x, y) \ + RUN_SAT_U_ADD_FMT_7_FROM_U64(T, x, y) #define DEF_SAT_U_ADD_IMM_FMT_1(T, IMM) \ T __attribute__((noinline)) \ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c new file mode 100644 index 0000000..527f8de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint32_t_uint16_t_fmt_7: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_ADD_FMT_7(uint32_t, uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c new file mode 100644 index 0000000..e9031de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint64_t_uint16_t_fmt_7: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_ADD_FMT_7(uint64_t, uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c new file mode 100644 index 0000000..a71bd2f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint64_t_uint32_t_fmt_7: +** slli\s+[atx][0-9]+,\s*a0,\s*32 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] +** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** sext.w\s+a0,\s*a0 +** ret +*/ +DEF_SAT_U_ADD_FMT_7(uint64_t, uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c new file mode 100644 index 0000000..5892986 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint16_t_uint8_t_fmt_7: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_ADD_FMT_7(uint16_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c new file mode 100644 index 0000000..a42a712 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint32_t_uint8_t_fmt_7: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_ADD_FMT_7(uint32_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c new file mode 100644 index 0000000..f37ef1c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint64_t_uint8_t_fmt_7: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_ADD_FMT_7(uint64_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c new file mode 100644 index 0000000..25dc1d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint16_t +#define WT uint32_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP + +DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 65534, 65534, }, + { 1, 65534, 65535, }, + { 2, 65534, 65535, }, + { 0, 65535, 65535, }, + { 1, 65535, 65535, }, + { 2, 65535, 65535, }, + { 65535, 65535, 65535, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c new file mode 100644 index 0000000..565b108 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint16_t +#define WT uint64_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP + +DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 65534, 65534, }, + { 1, 65534, 65535, }, + { 2, 65534, 65535, }, + { 0, 65535, 65535, }, + { 1, 65535, 65535, }, + { 2, 65535, 65535, }, + { 65535, 65535, 65535, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c new file mode 100644 index 0000000..6ff34fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint32_t +#define WT uint64_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP + +DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 4294967294, 4294967294, }, + { 1, 4294967294, 4294967295, }, + { 2, 4294967294, 4294967295, }, + { 0, 4294967295, 4294967295, }, + { 1, 4294967295, 4294967295, }, + { 2, 4294967295, 4294967295, }, + { 4294967295, 4294967295, 4294967295, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c new file mode 100644 index 0000000..9e6e70a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint8_t +#define WT uint16_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP + +DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 254, 254, }, + { 1, 254, 255, }, + { 2, 254, 255, }, + { 0, 255, 255, }, + { 1, 255, 255, }, + { 2, 255, 255, }, + { 255, 255, 255, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c new file mode 100644 index 0000000..a1134ed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint8_t +#define WT uint32_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP + +DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 254, 254, }, + { 1, 254, 255, }, + { 2, 254, 255, }, + { 0, 255, 255, }, + { 1, 255, 255, }, + { 2, 255, 255, }, + { 255, 255, 255, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c new file mode 100644 index 0000000..ef9f7aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint8_t +#define WT uint64_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP + +DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 254, 254, }, + { 1, 254, 255, }, + { 2, 254, 255, }, + { 0, 255, 255, }, + { 1, 255, 255, }, + { 2, 255, 255, }, + { 255, 255, 255, }, +}; + +#include "scalar_sat_binary.h" |