diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
187 files changed, 3640 insertions, 476 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-inst-ldlogic.c b/gcc/testsuite/gcc.target/aarch64/atomic-inst-ldlogic.c index 11f9bfe..ccb89ce 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-inst-ldlogic.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-inst-ldlogic.c @@ -101,54 +101,54 @@ TEST (xor_load_notreturn, XOR_LOAD_NORETURN) /* Load-OR. */ -/* { dg-final { scan-assembler-times "ldsetb\t" 8} } */ -/* { dg-final { scan-assembler-times "ldsetab\t" 16} } */ -/* { dg-final { scan-assembler-times "ldsetlb\t" 8} } */ -/* { dg-final { scan-assembler-times "ldsetalb\t" 16} } */ +/* { dg-final { scan-assembler-times "ldsetb\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldsetab\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldsetlb\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldsetalb\t" 16 } } */ -/* { dg-final { scan-assembler-times "ldseth\t" 8} } */ -/* { dg-final { scan-assembler-times "ldsetah\t" 16} } */ -/* { dg-final { scan-assembler-times "ldsetlh\t" 8} } */ -/* { dg-final { scan-assembler-times "ldsetalh\t" 16} } */ +/* { dg-final { scan-assembler-times "ldseth\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldsetah\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldsetlh\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldsetalh\t" 16 } } */ -/* { dg-final { scan-assembler-times "ldset\t" 16} } */ -/* { dg-final { scan-assembler-times "ldseta\t" 32} } */ -/* { dg-final { scan-assembler-times "ldsetl\t" 16} } */ -/* { dg-final { scan-assembler-times "ldsetal\t" 32} } */ +/* { dg-final { scan-assembler-times "ldset\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldseta\t" 32 } } */ +/* { dg-final { scan-assembler-times "ldsetl\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldsetal\t" 32 } } */ /* Load-AND. */ -/* { dg-final { scan-assembler-times "ldclrb\t" 8} } */ -/* { dg-final { scan-assembler-times "ldclrab\t" 16} } */ -/* { dg-final { scan-assembler-times "ldclrlb\t" 8} } */ -/* { dg-final { scan-assembler-times "ldclralb\t" 16} } */ +/* { dg-final { scan-assembler-times "ldclrb\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldclrab\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldclrlb\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldclralb\t" 16 } } */ -/* { dg-final { scan-assembler-times "ldclrh\t" 8} } */ -/* { dg-final { scan-assembler-times "ldclrah\t" 16} } */ -/* { dg-final { scan-assembler-times "ldclrlh\t" 8} } */ -/* { dg-final { scan-assembler-times "ldclralh\t" 16} } */ +/* { dg-final { scan-assembler-times "ldclrh\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldclrah\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldclrlh\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldclralh\t" 16 } } */ -/* { dg-final { scan-assembler-times "ldclr\t" 16 } */ -/* { dg-final { scan-assembler-times "ldclra\t" 32} } */ -/* { dg-final { scan-assembler-times "ldclrl\t" 16} } */ -/* { dg-final { scan-assembler-times "ldclral\t" 32} } */ +/* { dg-final { scan-assembler-times "ldclr\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldclra\t" 32 } } */ +/* { dg-final { scan-assembler-times "ldclrl\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldclral\t" 32 } } */ /* Load-XOR. */ -/* { dg-final { scan-assembler-times "ldeorb\t" 8} } */ -/* { dg-final { scan-assembler-times "ldeorab\t" 16} } */ +/* { dg-final { scan-assembler-times "ldeorb\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldeorab\t" 16 } } */ /* { dg-final { scan-assembler-times "ldeorlb\t" 8 } } */ -/* { dg-final { scan-assembler-times "ldeoralb\t" 16} } */ +/* { dg-final { scan-assembler-times "ldeoralb\t" 16 } } */ -/* { dg-final { scan-assembler-times "ldeorh\t" 8} } */ -/* { dg-final { scan-assembler-times "ldeorah\t" 16} } */ -/* { dg-final { scan-assembler-times "ldeorlh\t" 8} } */ -/* { dg-final { scan-assembler-times "ldeoralh\t" 16} } */ +/* { dg-final { scan-assembler-times "ldeorh\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldeorah\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldeorlh\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldeoralh\t" 16 } } */ -/* { dg-final { scan-assembler-times "ldeor\t" 16} } */ -/* { dg-final { scan-assembler-times "ldeora\t" 32} } */ -/* { dg-final { scan-assembler-times "ldeorl\t" 16} } */ -/* { dg-final { scan-assembler-times "ldeoral\t" 32} } */ +/* { dg-final { scan-assembler-times "ldeor\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldeora\t" 32 } } */ +/* { dg-final { scan-assembler-times "ldeorl\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldeoral\t" 32 } } */ /* { dg-final { scan-assembler-not "ldaxr\t" } } */ /* { dg-final { scan-assembler-not "stlxr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/crc-crc32c-data16.c b/gcc/testsuite/gcc.target/aarch64/crc-crc32c-data16.c index d82e625..db08136 100644 --- a/gcc/testsuite/gcc.target/aarch64/crc-crc32c-data16.c +++ b/gcc/testsuite/gcc.target/aarch64/crc-crc32c-data16.c @@ -10,7 +10,7 @@ uint32_t _crc32_O0 (uint32_t crc, uint16_t data) { int i; crc = crc ^ data; - for (i = 0; i < 8; i++) { + for (i = 0; i < 16; i++) { if (crc & 1) crc = (crc >> 1) ^ 0x82F63B78; else @@ -24,7 +24,7 @@ uint32_t _crc32 (uint32_t crc, uint16_t data) { int i; crc = crc ^ data; - for (i = 0; i < 8; i++) { + for (i = 0; i < 16; i++) { if (crc & 1) crc = (crc >> 1) ^ 0x82F63B78; else diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-1.c b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-1.c new file mode 100644 index 0000000..e5bb2d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-skip-if "Do not override mcpu or march" { *-*-* } { -mcpu=* -march=* } { "" } } */ +/* { dg-options { "-march=armv8-a+sme" } } */ +/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" "" { target *-*-* } 0 } */ +int main (void) +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-2.c b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-2.c new file mode 100644 index 0000000..13f09b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" "" { target *-*-* } 0 } */ + +#pragma GCC target ("arch=armv8.2-a+ssve-fp8fma") + +int main (void) +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-3.c b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-3.c new file mode 100644 index 0000000..9e3cbeb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-3.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" "" { target *-*-* } 0 } */ + +int __attribute__ ((target( "arch=armv8.2-a+ssve-fp8fma"))) main (void) +{ + return 0; +} + diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-4.c b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-4.c new file mode 100644 index 0000000..04a33a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-4.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-skip-if "Do not override mcpu or march" { *-*-* } { -mcpu=* -march=* } { "" } } */ +/* { dg-options { "-march=armv8-a" } } */ +/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" "" { target *-*-* } 0 } */ + +#pragma GCC target "+sme" + +int main (void) +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt-le-1.c b/gcc/testsuite/gcc.target/aarch64/popcnt-le-1.c index b4141da..843fdac 100644 --- a/gcc/testsuite/gcc.target/aarch64/popcnt-le-1.c +++ b/gcc/testsuite/gcc.target/aarch64/popcnt-le-1.c @@ -8,7 +8,7 @@ /* ** le32: ** sub w([0-9]+), w0, #1 -** tst w0, w\1 +** tst (?:w0, w\1|w\1, w0) ** cset w0, eq ** ret */ @@ -20,7 +20,7 @@ unsigned le32 (const unsigned int a) { /* ** gt32: ** sub w([0-9]+), w0, #1 -** tst w0, w\1 +** tst (?:w0, w\1|w\1, w0) ** cset w0, ne ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt-le-3.c b/gcc/testsuite/gcc.target/aarch64/popcnt-le-3.c index b811e6f..3b558e9 100644 --- a/gcc/testsuite/gcc.target/aarch64/popcnt-le-3.c +++ b/gcc/testsuite/gcc.target/aarch64/popcnt-le-3.c @@ -8,7 +8,7 @@ /* ** le16: ** sub w([0-9]+), w0, #1 -** and w([0-9]+), w0, w\1 +** and w([0-9]+), (?:w0, w\1|w\1, w0) ** tst w\2, 65535 ** cset w0, eq ** ret @@ -21,7 +21,7 @@ unsigned le16 (const unsigned short a) { /* ** gt16: ** sub w([0-9]+), w0, #1 -** and w([0-9]+), w0, w\1 +** and w([0-9]+), (?:w0, w\1|w\1, w0) ** tst w\2, 65535 ** cset w0, ne ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/pr100056.c b/gcc/testsuite/gcc.target/aarch64/pr100056.c index 0b77824..70499772 100644 --- a/gcc/testsuite/gcc.target/aarch64/pr100056.c +++ b/gcc/testsuite/gcc.target/aarch64/pr100056.c @@ -1,7 +1,9 @@ /* PR target/100056 */ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-final { scan-assembler-not {\t[us]bfiz\tw[0-9]+, w[0-9]+, 11} } } */ +/* { dg-final { scan-assembler-not {\t[us]bfiz\tw[0-9]+, w[0-9]+, 11} { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\t[us]bfiz\tw[0-9]+, w[0-9]+, 11} 2 } } */ +/* { dg-final { scan-assembler-times {\tadd\tw[0-9]+, w[0-9]+, w[0-9]+, uxtb\n} 2 } } */ int or_shift_u8 (unsigned char i) diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c index 97d68b9..dcac6d5 100644 --- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c +++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c @@ -46,7 +46,7 @@ #error Foo #endif -#pragma GCC target "+sme" +#pragma GCC target "+sve2+sme" #ifndef __ARM_FEATURE_SME #error Foo #endif @@ -66,7 +66,7 @@ #error Foo #endif -#pragma GCC target "+nothing+sme" +#pragma GCC target "+nothing+sve2+sme" #ifdef __ARM_FEATURE_SME_I16I64 #error Foo #endif @@ -80,7 +80,7 @@ #error Foo #endif -#pragma GCC target "+nothing+sme-i16i64" +#pragma GCC target "+nothing+sve2+sme-i16i64" #ifndef __ARM_FEATURE_SME_I16I64 #error Foo #endif @@ -91,7 +91,7 @@ #error Foo #endif -#pragma GCC target "+nothing+sme-b16b16" +#pragma GCC target "+nothing+sve2+sme-b16b16" #ifndef __ARM_FEATURE_SME_B16B16 #error Foo #endif @@ -105,7 +105,7 @@ #error Foo #endif -#pragma GCC target "+nothing+sme-f16f16" +#pragma GCC target "+nothing+sve2+sme-f16f16" #ifndef __ARM_FEATURE_SME_F16F16 #error Foo #endif @@ -116,7 +116,7 @@ #error Foo #endif -#pragma GCC target "+nothing+sme-f64f64" +#pragma GCC target "+nothing+sve2+sme-f64f64" #ifndef __ARM_FEATURE_SME_F64F64 #error Foo #endif @@ -160,7 +160,7 @@ #error Foo #endif -#pragma GCC target "+nothing+sve-b16b16+sme2" +#pragma GCC target "+nothing+sve2+sve-b16b16+sme2" #ifndef __ARM_FEATURE_SVE_B16B16 #error Foo #endif @@ -168,7 +168,7 @@ #error Foo #endif -#pragma GCC target "+nothing+sme2p1" +#pragma GCC target "+nothing+sve2+sme2p1" #ifndef __ARM_FEATURE_SME #error Foo #endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c index 976d5af..7150d37 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c index 5cc8a4c..2823264 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c index aa7633b..52f2c09 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_int_opt_single_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_int_opt_single_1.c index 01cd88f..0e88c14 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_int_opt_single_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_int_opt_single_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint16_t s16, svint8_t s8, svuint8_t u8, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_1.c index 937d992..2c60d50 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint16_t s16, svuint16_t u16, svint32_t s32, svuint32_t u32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_2.c index 126a764..dd90ebc 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_2.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint16_t s16, svuint16_t u16, svint32_t s32, svuint32_t u32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_3.c index 17bed0c..f53cc55 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_3.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint16_t s16, svuint16_t u16, svint32_t s32, svuint32_t u32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_4.c index d2a67c6..83c659d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_4.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svint8_t s8, svuint8_t u8, svint16_t s16, svuint16_t u16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_1.c index 8307a28..a361f7f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint16_t s16, svint32_t s32, svuint32_t u32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_2.c index 181f509..959e222 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_2.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint16_t s16, svint32_t s32, svuint32_t u32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_3.c index 8c8414e..9cc42c0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_3.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2+nosme-i16i64") +#pragma GCC target ("+sve2+sme2+nosme-i16i64") void f1 (svint32x2_t s32x2, svuint32x2_t u32x2, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_uint_opt_single_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_uint_opt_single_1.c index b00c043..b289c9c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_uint_opt_single_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_uint_opt_single_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svuint16_t u16, svint8_t s8, svuint8_t u8, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c index 600b7fc..4f8ebf8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svbool_t pg, svcount_t pn, svuint8_t u8, svint16_t s16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c index 07e22d2..958c40a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svcount_t pn, svfloat16_t f16, svint16_t s16, svfloat32_t f32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c index 47077f7..4a4222c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c @@ -3,7 +3,7 @@ #include <arm_sve.h> #include <stdbool.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" enum signed_enum { SA = -1, SB }; enum unsigned_enum { UA, UB }; diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_int_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_int_lane_1.c index ca2a039..aed92b5 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_int_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_int_lane_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint8_t s8, svuint8_t u8, svint16_t s16, svuint16_t u16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_1.c index e37d24a..bb40868 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint8_t s8, svuint8_t u8, svint16_t s16, svuint16_t u16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_2.c index 7af3c6f..7d57bd1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_2.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint8_t s8, svuint8_t u8, svint16_t s16, svuint16_t u16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_uint_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_uint_lane_1.c index 2efa2eb..cba11a4 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_uint_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_uint_lane_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint8_t s8, svuint8_t u8, svint16_t s16, svuint16_t u16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c index ab5602f..685d070 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svboolx2_t pgx2, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c index 7ad4ca8..ba0096b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c @@ -3,7 +3,7 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" struct s { signed char x; }; diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_1.c index 6bdd3c0..c01710f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_1.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target ("arch=armv8.2-a+ssve-fp8fma") +#pragma GCC target ("arch=armv8.2-a+sve2+ssve-fp8fma") void f1 (svfloat16_t f16, svmfloat8_t f8, fpm_t fpm, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_group_selection_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_group_selection_1.c index f6fce2f..fecaf98 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_group_selection_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_group_selection_1.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target ("arch=armv8.2-a+ssve-fp8fma+ssve-fp8dot4+ssve-fp8dot2") +#pragma GCC target ("arch=armv8.2-a+sve2+ssve-fp8fma+ssve-fp8dot4+ssve-fp8dot2") void f1 (svfloat16_t f16, svmfloat8_t f8, fpm_t fpm, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c index b8968c8..5579e0d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svbool_t pg, svint8_t s8, svuint8_t u8, svint16_t s16, svuint16_t u16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c index 85f8b45..e14ec71 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c @@ -1,6 +1,6 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void test (svbool_t pg, float f, svint8_t s8, svfloat32_t f32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrow_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrow_1.c index d312e85..e93cc64 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrow_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrow_1.c @@ -1,6 +1,6 @@ #include <arm_sve.h> -#pragma GCC target "+sme2+fp8" +#pragma GCC target "+sve2+sme2+fp8" void test (svfloat16x2_t f16x2, svbfloat16x2_t bf16x2, svfloat32x2_t f32x2, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrowt_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrowt_1.c index ab97eef..da828f0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrowt_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrowt_1.c @@ -1,6 +1,6 @@ #include <arm_sve.h> -#pragma GCC target "+sme2+fp8" +#pragma GCC target "+sve2+sme2+fp8" void test (svmfloat8_t f8, svfloat32x2_t f32x2, fpm_t fpm0, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_za_slice_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_za_slice_1.c index e02fe54..c3052a0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_za_slice_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_za_slice_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint32_t s32, svint16x2_t s16x2, svint32x2_t s32x2, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c index f478945..e9656bc 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c @@ -1,6 +1,6 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void test (svfloat32_t f32, svfloat32x2_t f32x2, svfloat32x3_t f32x3, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_1.c index 3a45b58..95ead96 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svint8_t s8, svint8x2_t s8x2, svint8x3_t s8x3, svint8x4_t s8x4, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_slice_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_slice_1.c index dedd4b1..dae8892 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_slice_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_slice_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svint8_t s8, svint8x2_t s8x2, svint8x3_t s8x3, svint8x4_t s8x4, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/gomp/gomp.exp b/gcc/testsuite/gcc.target/aarch64/sve/gomp/gomp.exp new file mode 100644 index 0000000..376985d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/gomp/gomp.exp @@ -0,0 +1,46 @@ +# Copyright (C) 2006-2025 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an AArch64 target. +if {![istarget aarch64*-*-*] } then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +if ![check_effective_target_fopenmp] { + return +} + +if { [check_effective_target_aarch64_sve] } { + set sve_flags "" +} else { + set sve_flags "-march=armv8.2-a+sve" +} + +# Main loop. +dg-runtest [lsort [find $srcdir/$subdir *.c]] "$sve_flags -fopenmp" "" + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-device.c b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-device.c new file mode 100644 index 0000000..75dd39b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-device.c @@ -0,0 +1,201 @@ +/* { dg-do compile } */ +/* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */ + +#include <arm_sve.h> + +#define N __ARM_FEATURE_SVE_BITS + +int64_t __attribute__ ((noipa)) +target_device_ptr_vla (svbool_t vp, svint32_t *vptr) +{ + + int a[N], b[N], c[N]; + svint32_t va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } +/* { dg-error {SVE type 'svint32_t \*' not allowed in 'target' device clauses} "" { target *-*-* } .+1 } */ +#pragma omp target data use_device_ptr (vptr) map (to: b, c) +/* { dg-error {SVE type 'svint32_t \*' not allowed in 'target' device clauses} "" { target *-*-* } .+1 } */ +#pragma omp target is_device_ptr (vptr) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vb = *vptr; + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+2 } */ + /* { dg-error "cannot reference 'svbool_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vc = svld1_s32 (vp, c); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +int64_t __attribute__ ((noipa)) +target_device_addr_vla (svbool_t vp, svint32_t *vptr) +{ + + int a[N], b[N], c[N]; + svint32_t va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'target' device clauses" "" { target *-*-* } .+1 } */ +#pragma omp target data use_device_addr (vb) map (to: b, c) +/* { dg-error {SVE type 'svint32_t \*' not allowed in 'target' device clauses} "" { target *-*-* } .+1 } */ +#pragma omp target is_device_ptr (vptr) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vb = *vptr; + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+2 } */ + /* { dg-error "cannot reference 'svbool_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vc = svld1_s32 (vp, c); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +int64_t __attribute__ ((noipa)) +target_has_device_addr_vla (svbool_t vp, svint32_t *vptr) +{ + + int a[N], b[N], c[N]; + svint32_t va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'target' device clauses" "" { target *-*-* } .+1 } */ +#pragma omp target data use_device_addr (vb) map (to: b, c) +/* { dg-error "SVE type 'svint32_t' not allowed in 'target' device clauses" "" { target *-*-* } .+1 } */ +#pragma omp target has_device_addr (vb) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svbool_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vb = svld1_s32 (vp, b); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vc = svld1_s32 (vp, c); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +#define FIXED_ATTR __attribute__ ((arm_sve_vector_bits (N))) + +typedef __SVInt32_t v8si FIXED_ATTR; +typedef svbool_t v8bi FIXED_ATTR; + +int64_t __attribute__ ((noipa)) +target_device_ptr_vls (v8bi vp, v8si *vptr) +{ + + int a[N], b[N], c[N]; + v8si va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +#pragma omp target data use_device_ptr (vptr) map (to: b, c) +#pragma omp target is_device_ptr (vptr) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + vb = *vptr; + vc = svld1_s32 (vp, c); + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +int64_t __attribute__ ((noipa)) +target_device_addr_vls (v8bi vp, v8si *vptr) +{ + + int a[N], b[N], c[N]; + v8si va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +#pragma omp target data use_device_addr (vb) map (to: b, c) +#pragma omp target is_device_ptr (vptr) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + vb = *vptr; + vc = svld1_s32 (vp, c); + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +int64_t __attribute__ ((noipa)) +target_has_device_addr_vls (v8bi vp, v8si *vptr) +{ + + int a[N], b[N], c[N]; + v8si va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +#pragma omp target data use_device_addr (vb) map (to: b, c) +#pragma omp target has_device_addr (vb) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + vb = svld1_s32 (vp, b); + vc = svld1_s32 (vp, c); + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-link.c b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-link.c new file mode 100644 index 0000000..2f6184b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-link.c @@ -0,0 +1,57 @@ +/* { dg-do compile } */ +/* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */ + +#include <arm_sve.h> + +#define N __ARM_FEATURE_SVE_BITS +#define FIXED_ATTR __attribute__((arm_sve_vector_bits (N))) + +typedef __SVInt32_t v8si FIXED_ATTR; + +static v8si local_vec; +#pragma omp declare target link(local_vec) + +v8si global_vec; +#pragma omp declare target link(global_vec) + +/* { dg-error {SVE type 'svint32_t' does not have a fixed size} "" { target *-*-* } .+1 } */ +static svint32_t slocal_vec; + +/* { dg-error {'slocal_vec' does not have a mappable type in 'link' clause} "" { target *-*-* } .+1 } */ +#pragma omp declare target link(slocal_vec) + +void +one_get_inc2_local_vec_vls () +{ + v8si res, res2, tmp; + +#pragma omp target map(from: res, res2) + { + res = local_vec; + local_vec = svadd_s32_z (svptrue_b32 (), local_vec, local_vec); + res2 = local_vec; + } + + tmp = svadd_s32_z (svptrue_b32 (), res, res); + svbool_t p = svcmpne_s32 (svptrue_b32 (), tmp, res2); + if (svptest_any (svptrue_b32 (), p)) + __builtin_abort (); +} + +void +one_get_inc3_global_vec_vls () +{ + v8si res, res2, tmp; + +#pragma omp target map(from: res, res2) + { + res = global_vec; + global_vec = svadd_s32_z (svptrue_b32 (), global_vec, global_vec); + res2 = global_vec; + } + + tmp = svadd_s32_z (svptrue_b32 (), res, res); + svbool_t p = svcmpne_s32 (svptrue_b32 (), tmp, res2); + if (svptest_any (svptrue_b32 (), p)) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/gomp/target.c b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target.c new file mode 100644 index 0000000..812183d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target.c @@ -0,0 +1,2049 @@ +/* { dg-do compile } */ +/* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */ + +#include <arm_sve.h> + +#define N __ARM_FEATURE_SVE_BITS +#define FIXED_ATTR __attribute__((arm_sve_vector_bits (N))) + +typedef svint32_t v8si FIXED_ATTR; +typedef svbool_t v8bi FIXED_ATTR; + +void +target_vla1 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla1 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla1 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla1 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla1 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls1 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls1 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls1 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls1 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls1 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla2 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target parallel + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla2 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla2 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla2 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla2 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target parallel + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls2 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target parallel + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls2 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target parallel map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls2 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target parallel map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls2 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target parallel map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target parallel map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls2 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target parallel + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla3 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target parallel loop + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla3 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla3 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla3 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla3 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target parallel loop + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls3 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target parallel loop + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls3 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target parallel loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls3 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target parallel loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls3 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target parallel loop map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target parallel loop map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls3 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target parallel loop + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target parallel loop map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla4 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target simd + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla4 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla4 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla4 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla4 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target simd + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls4 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target simd + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls4 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls4 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls4 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target simd map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target simd map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls4 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target simd + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla5 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla5 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla5 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla5 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla5 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls5 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls5 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls5 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls5 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target teams map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls5 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla6 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams loop + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla6 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla6 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla6 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla6 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams loop + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls6 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams loop + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls6 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls6 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls6 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target teams loop map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams loop map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls6 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams loop + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target teams loop map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla7 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams distribute + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla7 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla7 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla7 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla7 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams distribute + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls7 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams distribute + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls7 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams distribute map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls7 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams distribute map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls7 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target teams distribute map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams distribute map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls7 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams distribute + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target teams distribute map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla8 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams distribute simd + for (i = 0; i < 8; i++) + { + svint32_t va; + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla8 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla8 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla8 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla8 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams distribute simd + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls8 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams distribute simd + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls8 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams distribute simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls8 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams distribute simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls8 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target teams distribute simd map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams distribute simd map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls8 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams distribute simd + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target teams distribute simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-1.c b/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-1.c index a7d2795..c9a8b82 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-1.c @@ -19,6 +19,6 @@ void f10(double * restrict z, double * restrict w, double * restrict x, double * } } -/* { dg-final { scan-assembler-not {\tbic\t} { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not {\tbic\t} } } */ +/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfcmgt\tp[0-9]+\.d, p[0-9]+/z, z[0-9]+\.d, #0} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-4.c b/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-4.c index 20cbd75..1845bd3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-4.c @@ -8,6 +8,6 @@ void f13(double * restrict z, double * restrict w, double * restrict x, double * } } -/* { dg-final { scan-assembler-not {\tbic\t} { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not {\tbic\t} } } */ +/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfcmuo\tp[0-9]+\.d, p[0-9]+/z, z[0-9]+\.d, z[0-9]+\.d} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c index 33b9f0f..b8afea7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c @@ -16,7 +16,8 @@ f (TYPE *x, TYPE *y, unsigned short n, unsigned short m) /* { dg-final { scan-assembler {\tldr\tw[0-9]+} } } */ /* { dg-final { scan-assembler {\tstr\tw[0-9]+} } } */ /* Should multiply by (257-1)*4 rather than (VF-1)*4 or (VF-2)*4. */ -/* { dg-final { scan-assembler-times {\tadd\tx[0-9]+, x[0-9]+, x[0-9]+, lsl 10\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tubfiz\tx[0-9]+, x2, 10, 16\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tubfiz\tx[0-9]+, x3, 10, 16\n} 1 } } */ /* { dg-final { scan-assembler-not {\tcmp\tx[0-9]+, 0} } } */ /* { dg-final { scan-assembler-not {\tcmp\tw[0-9]+, 0} } } */ /* { dg-final { scan-assembler-not {\tcsel\tx[0-9]+} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c index 71b826a..d2e74f9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c @@ -16,7 +16,8 @@ f (TYPE *x, TYPE *y, int n, int m) /* { dg-final { scan-assembler {\tldr\tw[0-9]+} } } */ /* { dg-final { scan-assembler {\tstr\tw[0-9]+} } } */ /* Should multiply by (257-1)*4 rather than (VF-1)*4. */ -/* { dg-final { scan-assembler-times {\t(?:lsl\tx[0-9]+, x[0-9]+, 10|sbfiz\tx[0-9]+, x[0-9]+, 10, 32)\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsbfiz\tx[0-9]+, x2, 10, 32\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsbfiz\tx[0-9]+, x3, 10, 32\n} 1 } } */ /* { dg-final { scan-assembler {\tcmp\tw2, 0} } } */ /* { dg-final { scan-assembler {\tcmp\tw3, 0} } } */ /* { dg-final { scan-assembler-times {\tcsel\tx[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vls_sve_vec_dup_1.c b/gcc/testsuite/gcc.target/aarch64/vls_sve_vec_dup_1.c new file mode 100644 index 0000000..ada0d4f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vls_sve_vec_dup_1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=armv8.2-a+sve -msve-vector-bits=128" } */ + +float fasten_main_etot_0; +void fasten_main() { + for (int l = 0; l < 2;) { + int phphb_nz; + for (; l < 32; l++) { + float dslv_e = l && phphb_nz; + fasten_main_etot_0 += dslv_e; + } + } +} + +/* { dg-final { scan-assembler-not {bfi\tw\[0-9\]+} } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr-safe-partial.c b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr-safe-partial.c new file mode 100644 index 0000000..15dc1b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr-safe-partial.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memclr-a2-o1-c9-ptr.c" + +/* Expect assembly such as: + + stb $31,1($16) + stw $31,2($16) + stw $31,4($16) + stw $31,6($16) + stw $31,8($16) + + that is with a byte store at offset 1, followed by word stores at + offsets 2, 4, 6, and 8. */ + +/* { dg-final { scan-assembler-times "\\sstb\\s\\\$31,1\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$31,2\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$31,4\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$31,6\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$31,8\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c index 3f7edc8..0ff1049 100644 --- a/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c +++ b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mbwx" } */ +/* { dg-options "-mbwx -mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ typedef unsigned int __attribute__ ((mode (QI))) int08_t; diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial-bwx.c new file mode 100644 index 0000000..1626261 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial-bwx.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-msafe-partial -mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memcpy-di-unaligned-dst.c" + +/* { dg-final { scan-assembler-times "\\sldq\\s" 7 } } */ +/* { dg-final { scan-assembler-times "\\sstb\\s" 16 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 6 } } */ +/* { dg-final { scan-assembler-not "\\sldq_l\\s" } } */ +/* { dg-final { scan-assembler-not "\\sldq_u\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstq\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstq_c\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial.c b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial.c new file mode 100644 index 0000000..869fdf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-msafe-partial -mno-bwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memcpy-di-unaligned-dst.c" + +/* { dg-final { scan-assembler-times "\\sldq\\s" 7 } } */ +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 6 } } */ +/* { dg-final { scan-assembler-not "\\sldq_u\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstq\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst.c b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst.c index 5e9b5c3..373e2aa 100644 --- a/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst.c +++ b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "" } */ +/* { dg-options "-mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ unsigned long unaligned_src_di[9] = { [0 ... 8] = 0xfefdfcfbfaf9f8f7 }; diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial-bwx.c new file mode 100644 index 0000000..2464005 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial-bwx.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-msafe-partial -mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memcpy-si-unaligned-dst.c" + +/* { dg-final { scan-assembler-times "\\sldl\\s" 15 } } */ +/* { dg-final { scan-assembler-times "\\sstb\\s" 20 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 6 } } */ +/* { dg-final { scan-assembler-not "\\sldq_l\\s" } } */ +/* { dg-final { scan-assembler-not "\\sldq_u\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstl\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstq_c\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial.c b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial.c new file mode 100644 index 0000000..6c9f877 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-msafe-partial -mno-bwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memcpy-si-unaligned-dst.c" + +/* { dg-final { scan-assembler-times "\\sldl\\s" 15 } } */ +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 4 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 4 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 6 } } */ +/* { dg-final { scan-assembler-not "\\sldq_u\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstl\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst.c b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst.c index a2efade..aef4e59 100644 --- a/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst.c +++ b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "" } */ +/* { dg-options "-mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ unsigned int unaligned_src_si[17] = { [0 ... 16] = 0xfefdfcfb }; diff --git a/gcc/testsuite/gcc.target/alpha/stb-bwa.c b/gcc/testsuite/gcc.target/alpha/stb-bwa.c new file mode 100644 index 0000000..d7a45db --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stb-bwa.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stb (char *p, char v) +{ + *p = v; +} + +/* Expect assembly such as: + + bic $16,7,$2 + insbl $17,$16,$17 +$L2: + ldq_l $1,0($2) + mskbl $1,$16,$1 + bis $17,$1,$1 + stq_c $1,0($2) + beq $1,$L2 + + with address masking. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sinsbl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskbl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stb-bwx.c b/gcc/testsuite/gcc.target/alpha/stb-bwx.c new file mode 100644 index 0000000..556397b --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stb-bwx.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stb (char *p, char v) +{ + *p = v; +} + +/* Expect assembly such as: + + stb $17,0($16) + */ + +/* { dg-final { scan-assembler-times "\\sstb\\s\\\$17,0\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stb.c b/gcc/testsuite/gcc.target/alpha/stb.c new file mode 100644 index 0000000..4953bc4 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stb.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -mno-safe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stb (char *p, char v) +{ + *p = v; +} + +/* Expect assembly such as: + + insbl $17,$16,$17 + ldq_u $1,0($16) + mskbl $1,$16,$1 + bis $17,$1,$17 + stq_u $17,0($16) + + without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldq_u\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sinsbl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskbl\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stba-bwa.c b/gcc/testsuite/gcc.target/alpha/stba-bwa.c new file mode 100644 index 0000000..07cf954 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stba-bwa.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + char c; + } +char_a; + +void +stba (char_a *p, char v) +{ + p->c = v; +} + +/* Expect assembly such as: + + and $17,0xff,$17 +$L2: + ldl_l $1,0($16) + bic $1,255,$1 + bis $17,$1,$1 + stl_c $1,0($16) + beq $1,$L2 + + without any INSBL or MSKBL instructions and without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldl_l\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl_c\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sand\\s\\\$\[0-9\]+,0xff,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sbic\\s\\\$\[0-9\]+,255,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:insbl|mskbl)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stba-bwx.c b/gcc/testsuite/gcc.target/alpha/stba-bwx.c new file mode 100644 index 0000000..08b51b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stba-bwx.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + char c; + } +char_a; + +void +stba (char_a *p, char v) +{ + p->c = v; +} + +/* Expect assembly such as: + + stb $17,0($16) + */ + +/* { dg-final { scan-assembler-times "\\sstb\\s\\\$17,0\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stba.c b/gcc/testsuite/gcc.target/alpha/stba.c new file mode 100644 index 0000000..fe7856c --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stba.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -mno-safe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + char c; + } +char_a; + +void +stba (char_a *p, char v) +{ + p->c = v; +} + +/* Expect assembly such as: + + and $17,0xff,$17 + ldl $1,0($16) + bic $1,255,$1 + bis $17,$1,$17 + stl $17,0($16) + + without any INSBL or MSKBL instructions and without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sand\\s\\\$\[0-9\]+,0xff,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sbic\\s\\\$\[0-9\]+,255,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:insbl|mskbl)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial-bwx.c new file mode 100644 index 0000000..70df631 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial-bwx.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stlx0.c" + +/* Expect assembly such as: + + stb $31,0($16) + stb $31,1($16) + stb $31,2($16) + stb $31,3($16) + + without any LDQ_U or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sstb\\s" 4 } } */ +/* { dg-final { scan-assembler-not "\\s(?:ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial.c b/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial.c new file mode 100644 index 0000000..dc3e86d --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stlx0.c" + +/* Expect assembly such as: + + lda $2,3($16) + bic $2,7,$2 +$L2: + ldq_l $1,0($2) + msklh $1,$16,$1 + stq_c $1,0($2) + beq $1,$L2 + bic $16,7,$2 +$L3: + ldq_l $1,0($2) + mskll $1,$16,$1 + stq_c $1,0($2) + beq $1,$L3 + + without any INSLH, INSLL, BIS, LDQ_U, or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\smsklh\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskll\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:bis|inslh|insll|ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stlx0.c b/gcc/testsuite/gcc.target/alpha/stlx0.c index 876eceb..3b340bc 100644 --- a/gcc/testsuite/gcc.target/alpha/stlx0.c +++ b/gcc/testsuite/gcc.target/alpha/stlx0.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "" } */ +/* { dg-options "-mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ typedef struct { int v __attribute__ ((packed)); } intx; diff --git a/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial-bwx.c new file mode 100644 index 0000000..62f6c78 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial-bwx.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stqx0.c" + +/* Expect assembly such as: + + stb $31,0($16) + stb $31,1($16) + stb $31,2($16) + stb $31,3($16) + stb $31,4($16) + stb $31,5($16) + stb $31,6($16) + stb $31,7($16) + + without any LDQ_U or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sstb\\s" 8 } } */ +/* { dg-final { scan-assembler-not "\\s(?:ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial.c b/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial.c new file mode 100644 index 0000000..7aa9e80 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stqx0.c" + +/* Expect assembly such as: + + lda $2,7($16) + bic $2,7,$2 +$L2: + ldq_l $1,0($2) + mskqh $1,$16,$1 + stq_c $1,0($2) + beq $1,$L2 + bic $16,7,$2 +$L3: + ldq_l $1,0($2) + mskql $1,$16,$1 + stq_c $1,0($2) + beq $1,$L3 + + without any INSLH, INSLL, BIS, LDQ_U, or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\smskqh\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskql\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:bis|insqh|insql|ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stqx0.c b/gcc/testsuite/gcc.target/alpha/stqx0.c index 042cdf0..80261a8 100644 --- a/gcc/testsuite/gcc.target/alpha/stqx0.c +++ b/gcc/testsuite/gcc.target/alpha/stqx0.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "" } */ +/* { dg-options "-mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ typedef struct { long v __attribute__ ((packed)); } longx; diff --git a/gcc/testsuite/gcc.target/alpha/stw-bwa.c b/gcc/testsuite/gcc.target/alpha/stw-bwa.c new file mode 100644 index 0000000..8b764b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stw-bwa.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stw (short *p, short v) +{ + *p = v; +} + +/* Expect assembly such as: + + bic $16,7,$2 + inswl $17,$16,$17 +$L2: + ldq_l $1,0($2) + mskwl $1,$16,$1 + bis $17,$1,$1 + stq_c $1,0($2) + beq $1,$L2 + + with address masking. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sinswl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskwl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stw-bwx.c b/gcc/testsuite/gcc.target/alpha/stw-bwx.c new file mode 100644 index 0000000..b4f18ad --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stw-bwx.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stw (short *p, short v) +{ + *p = v; +} + +/* Expect assembly such as: + + stw $17,0($16) + */ + +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$17,0\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stw.c b/gcc/testsuite/gcc.target/alpha/stw.c new file mode 100644 index 0000000..655fdd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stw.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -mno-safe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stw (short *p, short v) +{ + *p = v; +} + +/* Expect assembly such as: + + inswl $17,$16,$17 + ldq_u $1,0($16) + mskwl $1,$16,$1 + bis $17,$1,$17 + stq_u $17,0($16) + + without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldq_u\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sinswl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskwl\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwa-bwa.c b/gcc/testsuite/gcc.target/alpha/stwa-bwa.c new file mode 100644 index 0000000..9ee226e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwa-bwa.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + short c; + } +short_a; + +void +stwa (short_a *p, short v) +{ + p->c = v; +} + +/* Expect assembly such as: + + zapnot $17,3,$17 +$L2: + ldl_l $1,0($16) + zapnot $1,252,$1 + bis $17,$1,$1 + stl_c $1,0($16) + beq $1,$L2 + + without any INSWL or MSKWL instructions and without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldl_l\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl_c\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\szapnot\\s\\\$\[0-9\]+,3,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\szapnot\\s\\\$\[0-9\]+,252,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:inswl|mskwl)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwa-bwx.c b/gcc/testsuite/gcc.target/alpha/stwa-bwx.c new file mode 100644 index 0000000..6331d62 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwa-bwx.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + short c; + } +short_a; + +void +stwa (short_a *p, short v) +{ + p->c = v; +} + +/* Expect assembly such as: + + stw $17,0($16) + */ + +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$17,0\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwa.c b/gcc/testsuite/gcc.target/alpha/stwa.c new file mode 100644 index 0000000..6b273cf --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwa.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -mno-safe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + short c; + } +short_a; + +void +stwa (short_a *p, short v) +{ + p->c = v; +} + +/* Expect assembly such as: + + zapnot $17,3,$17 + ldl $1,0($16) + zapnot $1,252,$1 + bis $17,$1,$17 + stl $17,0($16) + + without any INSWL or MSKWL instructions and without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\szapnot\\s\\\$\[0-9\]+,3,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\szapnot\\s\\\$\[0-9\]+,252,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:inswl|mskwl)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwx0-bwx.c b/gcc/testsuite/gcc.target/alpha/stwx0-bwx.c index bba31df..6256f82 100644 --- a/gcc/testsuite/gcc.target/alpha/stwx0-bwx.c +++ b/gcc/testsuite/gcc.target/alpha/stwx0-bwx.c @@ -1,19 +1,15 @@ /* { dg-do compile } */ -/* { dg-options "-mbwx" } */ +/* { dg-options "-mbwx -mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ -typedef struct { short v __attribute__ ((packed)); } shortx; - -void -stwx0 (shortx *p) -{ - p->v = 0; -} +#include "stwx0.c" /* Expect assembly such as: stb $31,0($16) stb $31,1($16) - */ + + without any LDQ_U or STQ_U instructions. */ /* { dg-final { scan-assembler-times "\\sstb\\s\\\$31," 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial-bwx.c new file mode 100644 index 0000000..031d4c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial-bwx.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stwx0.c" + +/* Expect assembly such as: + + stb $31,0($16) + stb $31,1($16) + + without any LDQ_U or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sstb\\s\\\$31," 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial.c b/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial.c new file mode 100644 index 0000000..3d0eedd --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stwx0.c" + +/* Expect assembly such as: + + lda $2,1($16) + bic $2,7,$2 +$L2: + ldq_l $1,0($2) + mskwh $1,$16,$1 + stq_c $1,0($2) + beq $1,$L2 + bic $16,7,$2 +$L3: + ldq_l $1,0($2) + mskwl $1,$16,$1 + stq_c $1,0($2) + beq $1,$L3 + + without any INSWH, INSWL, BIS, LDQ_U, or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\smskwh\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskwl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:bis|inswh|inswl|ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwx0.c b/gcc/testsuite/gcc.target/alpha/stwx0.c index d60d33f..ad4e716 100644 --- a/gcc/testsuite/gcc.target/alpha/stwx0.c +++ b/gcc/testsuite/gcc.target/alpha/stwx0.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mno-bwx" } */ +/* { dg-options "-mno-bwx -mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ typedef struct { short v __attribute__ ((packed)); } shortx; diff --git a/gcc/testsuite/gcc.target/arm/ivopts.c b/gcc/testsuite/gcc.target/arm/ivopts.c index d7d72a5..582fdab 100644 --- a/gcc/testsuite/gcc.target/arm/ivopts.c +++ b/gcc/testsuite/gcc.target/arm/ivopts.c @@ -11,6 +11,6 @@ tr5 (short array[], int n) } /* { dg-final { scan-tree-dump-times "PHI <" 1 "ivopts"} } */ -/* { dg-final { object-size text <= 20 { target { arm_thumb2_no_arm_v8_1_lob } } } } */ +/* { dg-final { object-size text <= 20 { target { arm_thumb2_no_arm_v8_1m_lob } } } } */ /* { dg-final { object-size text <= 32 { target { arm_nothumb && { ! arm_iwmmxt_ok } } } } } */ /* { dg-final { object-size text <= 36 { target { arm_nothumb && arm_iwmmxt_ok } } } } */ diff --git a/gcc/testsuite/gcc.target/arm/lob1.c b/gcc/testsuite/gcc.target/arm/lob1.c index c8ce653..f42a367 100644 --- a/gcc/testsuite/gcc.target/arm/lob1.c +++ b/gcc/testsuite/gcc.target/arm/lob1.c @@ -1,7 +1,7 @@ /* Check that GCC generates Armv8.1-M low over head loop instructions for some simple loops. */ /* { dg-do run } */ -/* { dg-require-effective-target arm_v8_1_lob_ok } */ +/* { dg-require-effective-target arm_v8_1m_lob_hw } */ /* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "-mcpu=*" } } */ /* { dg-options "-march=armv8.1-m.main -mthumb -O3 --save-temps" } */ #include <stdlib.h> diff --git a/gcc/testsuite/gcc.target/arm/lob6.c b/gcc/testsuite/gcc.target/arm/lob6.c index 4fe116e..e19635b 100644 --- a/gcc/testsuite/gcc.target/arm/lob6.c +++ b/gcc/testsuite/gcc.target/arm/lob6.c @@ -1,7 +1,7 @@ /* Check that GCC generates Armv8.1-M low over head loop instructions with some less trivial loops and the result is correct. */ /* { dg-do run } */ -/* { dg-require-effective-target arm_v8_1_lob_ok } */ +/* { dg-require-effective-target arm_v8_1m_lob_hw } */ /* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "-mcpu=*" } } */ /* { dg-options "-march=armv8.1-m.main -mthumb -O3 --save-temps" } */ #include <stdlib.h> diff --git a/gcc/testsuite/gcc.target/arm/mve/mve.exp b/gcc/testsuite/gcc.target/arm/mve/mve.exp index a5d8511..9dc56c9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/mve.exp +++ b/gcc/testsuite/gcc.target/arm/mve/mve.exp @@ -35,6 +35,7 @@ global dg_runtest_extra_prunes set dg_runtest_extra_prunes "" lappend dg_runtest_extra_prunes "warning: switch '-m(cpu|arch)=.*' conflicts with switch '-m(cpu|arch)=.*'" +set saved-dg-do-what-default ${dg-do-what-default} set dg-do-what-default "assemble" # Initialize `dg'. @@ -53,6 +54,8 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/general-c/*.\[cCS\]]] \ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ "" $DEFAULT_CFLAGS +set dg-do-what-default ${saved-dg-do-what-default} + # All done. set dg_runtest_extra_prunes "" dg-finish diff --git a/gcc/testsuite/gcc.target/arm/short-vfp-1.c b/gcc/testsuite/gcc.target/arm/short-vfp-1.c index ddab09a..418fc27 100644 --- a/gcc/testsuite/gcc.target/arm/short-vfp-1.c +++ b/gcc/testsuite/gcc.target/arm/short-vfp-1.c @@ -1,45 +1,75 @@ /* { dg-do compile } */ -/* { dg-require-effective-target arm_vfp_ok } -/* { dg-add-options arm_vfp } */ +/* { dg-require-effective-target arm_arch_v7a_fp_hard_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v7a_fp_hard } */ +/* { dg-final { check-function-bodies "**" "" } } */ +/* +** test_sisf: +** vcvt.s32.f32 (s[0-9]+), s0 +** vmov r0, \1 @ int +** bx lr +*/ int test_sisf (float x) { return (int)x; } +/* +** test_hisf: +** vcvt.s32.f32 (s[0-9]+), s0 +** vmov (r[0-9]+), \1 @ int +** sxth r0, \2 +** bx lr +*/ short test_hisf (float x) { return (short)x; } +/* +** test_sfsi: +** vmov (s[0-9]+), r0 @ int +** vcvt.f32.s32 s0, \1 +** bx lr +*/ float test_sfsi (int x) { return (float)x; } +/* +** test_sfhi: +** vmov (s[0-9]+), r0 @ int +** vcvt.f32.s32 s0, \1 +** bx lr +*/ float test_sfhi (short x) { return (float)x; } +/* +** test_hisi: +** sxth r0, r0 +** bx lr +*/ short test_hisi (int x) { return (short)x; } +/* +** test_sihi: +** bx lr +*/ int test_sihi (short x) { return (int)x; } - -/* { dg-final { scan-assembler-times {vcvt\.s32\.f32\ts[0-9]+,s[0-9]+} 2 }} */ -/* { dg-final { scan-assembler-times {vcvt\.f32\.s32\ts[0-9]+,s[0-9]+} 2 }} */ -/* { dg-final { scan-assembler-times {vmov\tr[0-9]+,s[0-9]+} 2 }} */ -/* { dg-final { scan-assembler-times {vmov\ts[0-9]+,r[0-9]+} 2 }} */ -/* { dg-final { scan-assembler-times {sxth\tr[0-9]+,r[0-9]+} 2 }} */ diff --git a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c index 9272e4c..41ee994 100644 --- a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c +++ b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target arm_thumb2_ok_no_arm_v8_1_lob } */ +/* { dg-require-effective-target arm_thumb2_ok_no_arm_v8_1m_lob } */ /* { dg-options "-O" } */ unsigned short foo (unsigned short x, unsigned short c) diff --git a/gcc/testsuite/gcc.target/arm/vect-fmaxmin-2.c b/gcc/testsuite/gcc.target/arm/vect-fmaxmin-2.c new file mode 100644 index 0000000..57b0a3a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vect-fmaxmin-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_hard_ok } */ +/* { dg-options "-O2 -ftree-vectorize -funsafe-math-optimizations -fno-inline -save-temps" } */ +/* { dg-add-options arm_arch_v8a_hard } */ + +#include "fmaxmin.x" + +/* { dg-final { scan-assembler-times "vmaxnm.f32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "vminnm.f32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]+" 1 } } */ + +/* NOTE: There are no double precision vector versions of vmaxnm/vminnm. */ +/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/arm/vect-fmaxmin.c b/gcc/testsuite/gcc.target/arm/vect-fmaxmin.c index ba45c4d..89dc14b 100644 --- a/gcc/testsuite/gcc.target/arm/vect-fmaxmin.c +++ b/gcc/testsuite/gcc.target/arm/vect-fmaxmin.c @@ -1,14 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_neon_hw } */ -/* { dg-options "-O2 -ftree-vectorize -fno-inline -march=armv8-a -save-temps" } */ +/* { dg-options "-O2 -ftree-vectorize -fno-inline -funsafe-math-optimizations" } */ /* { dg-add-options arm_v8_neon } */ #include "fmaxmin.x" - -/* { dg-final { scan-assembler-times "vmaxnm.f32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]+" 1 } } */ -/* { dg-final { scan-assembler-times "vminnm.f32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]+" 1 } } */ - -/* NOTE: There are no double precision vector versions of vmaxnm/vminnm. */ -/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ -/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ - diff --git a/gcc/testsuite/gcc.target/i386/apx-nf-pr119539.c b/gcc/testsuite/gcc.target/i386/apx-nf-pr119539.c new file mode 100644 index 0000000..5dfec55 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-nf-pr119539.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mapx-features=nf -march=x86-64 -O2" } */ +/* { dg-final { scan-assembler-times "\{nf\} rol" 2 } } */ + +long int f1 (int x) { return ~(1ULL << (x & 0x3f)); } +long int f2 (char x) { return ~(1ULL << (x & 0x3f)); } diff --git a/gcc/testsuite/gcc.target/i386/pr111673.c b/gcc/testsuite/gcc.target/i386/pr111673.c index b9ceacf..0f08ba89 100644 --- a/gcc/testsuite/gcc.target/i386/pr111673.c +++ b/gcc/testsuite/gcc.target/i386/pr111673.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O2 -fdump-rtl-pro_and_epilogue" } */ +/* { dg-options "-O2 -fdump-rtl-pro_and_epilogue -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr115910.c b/gcc/testsuite/gcc.target/i386/pr115910.c new file mode 100644 index 0000000..5f1cd9a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr115910.c @@ -0,0 +1,20 @@ +/* PR target/115910 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=x86-64 -mtune=generic -masm=att" } */ +/* { dg-final { scan-assembler-times {\timulq\t} 2 } } */ +/* { dg-final { scan-assembler-times {\tshrq\t\$33,} 2 } } */ +/* { dg-final { scan-assembler-not {\tsarl\t} } } */ + +int +foo (int x) +{ + if (x < 0) + __builtin_unreachable (); + return x / 3U; +} + +int +bar (int x) +{ + return x / 3U; +} diff --git a/gcc/testsuite/gcc.target/i386/pr119473.c b/gcc/testsuite/gcc.target/i386/pr119473.c new file mode 100644 index 0000000..574c921 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119473.c @@ -0,0 +1,26 @@ +/* PR target/119473 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mapxf -m64 -mvaes" } */ + +typedef char __v32qi __attribute__ ((__vector_size__(32))); +typedef long long __m256i __attribute__((__vector_size__(32), __aligned__(32))); + +typedef union +{ + __v32qi qi[8]; +} tmp_u; + + +void foo () +{ + register tmp_u *tdst __asm__("%rdx"); + register tmp_u *src1 __asm__("%rcx"); + register tmp_u *src2 __asm__("%r26"); + + tdst->qi[0] = __builtin_ia32_vaesdec_v32qi(src1->qi[0], src2->qi[0]); + tdst->qi[0] = __builtin_ia32_vaesdeclast_v32qi(src1->qi[0], src2->qi[0]); + tdst->qi[0] = __builtin_ia32_vaesenc_v32qi(src1->qi[0], src2->qi[0]); + tdst->qi[0] = __builtin_ia32_vaesenclast_v32qi(src1->qi[0], src2->qi[0]); +} + +/* { dg-final { scan-assembler-not "\\\(%r26\\\), " } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr119549.c b/gcc/testsuite/gcc.target/i386/pr119549.c new file mode 100644 index 0000000..a465bec --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119549.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-msse4" } */ + +typedef long long v2di __attribute__((vector_size(16))); + +static inline __attribute__((always_inline)) +int rte_trace_feature_is_enabled() { return 1; } /* { dg-error "inlining failed" } */ + +void __attribute__((target ("no-sse3"))) __attribute__((target ("no-sse4"))) +rte_eal_trace_generic_void_init(void) +{ + if (!rte_trace_feature_is_enabled()) return; + __asm__ volatile ("" : : : "memory"); +} + diff --git a/gcc/testsuite/gcc.target/i386/pr67215-1.c b/gcc/testsuite/gcc.target/i386/pr67215-1.c index fd37f8e..ab69550 100644 --- a/gcc/testsuite/gcc.target/i386/pr67215-1.c +++ b/gcc/testsuite/gcc.target/i386/pr67215-1.c @@ -13,8 +13,8 @@ foo (void) arr[i] = bar (128); } -/* { dg-final { scan-assembler "call\[ \t\]*.bar@GOTPCREL" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "call\[ \t\]*.bar@GOT\\(" { target ia32 } } } */ -/* { dg-final { scan-assembler-not "mov(l|q)\[ \t\]*.bar@GOTPCREL" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-not "movl\[ \t\]*.bar@GOT\\(" { target ia32 } } } */ -/* { dg-final { scan-assembler-not "call\[ \t\]*.bar@PLT" } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*bar@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*bar@GOT\\(" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "mov(l|q)\[ \t\]+bar@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "movl\[ \t\]+bar@GOT\\(" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "call\[ \t\]+\\*bar@PLT" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr67215-2.c b/gcc/testsuite/gcc.target/i386/pr67215-2.c index ebf2919..9fd7469 100644 --- a/gcc/testsuite/gcc.target/i386/pr67215-2.c +++ b/gcc/testsuite/gcc.target/i386/pr67215-2.c @@ -13,8 +13,8 @@ foo (void) arr[i] = bar (128); } -/* { dg-final { scan-assembler "call\[ \t\]*.bar@GOTPCREL" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "call\[ \t\]*.bar@GOT\\(" { target ia32 } } } */ -/* { dg-final { scan-assembler-not "mov(l|q)\[ \t\]*.bar@GOTPCREL" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-not "movl\[ \t\]*.bar@GOT\\(" { target ia32 } } } */ -/* { dg-final { scan-assembler-not "call\[ \t\]*.bar@PLT" } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*bar@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*bar@GOT\\(" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "mov(l|q)\[ \t\]+bar@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "movl\[ \t\]+bar@GOT\\(" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "call\[ \t\]+\\*bar@PLT" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr82142a.c b/gcc/testsuite/gcc.target/i386/pr82142a.c index a40c038..a536150 100644 --- a/gcc/testsuite/gcc.target/i386/pr82142a.c +++ b/gcc/testsuite/gcc.target/i386/pr82142a.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O2 -mno-avx -msse2" } */ +/* { dg-options "-O2 -mno-avx -msse2 -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr82142b.c b/gcc/testsuite/gcc.target/i386/pr82142b.c index b1bf12d..d18b7c4 100644 --- a/gcc/testsuite/gcc.target/i386/pr82142b.c +++ b/gcc/testsuite/gcc.target/i386/pr82142b.c @@ -1,5 +1,5 @@ /* { dg-do compile { target ia32 } } */ -/* { dg-options "-O2 -mno-avx -msse2" } */ +/* { dg-options "-O2 -mno-avx -msse2 -mno-stackrealign -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/alloca-2-O0_-mfake-ptx-alloca.c b/gcc/testsuite/gcc.target/nvptx/alloca-2-O0_-mfake-ptx-alloca.c index 4cc4d0c..92562cd 100644 --- a/gcc/testsuite/gcc.target/nvptx/alloca-2-O0_-mfake-ptx-alloca.c +++ b/gcc/testsuite/gcc.target/nvptx/alloca-2-O0_-mfake-ptx-alloca.c @@ -1,4 +1,4 @@ -/* { dg-do link } */ +/* { dg-do run } */ /* { dg-options {-O0 -mno-soft-stack} } */ /* { dg-additional-options -march=sm_30 } */ /* { dg-additional-options -mfake-ptx-alloca } */ @@ -13,6 +13,7 @@ main(void) /* { dg-final { scan-assembler-times {(?n)^\.extern \.func \(\.param\.u64 %value_out\) __GCC_nvptx__PTX_alloca_not_supported \(\.param\.u64 %in_ar0\);$} 1 } } */ -/* { dg-message __GCC_nvptx__PTX_alloca_not_supported {unresolved symbol} { target *-*-* } 0 } */ +/* { dg-bogus __GCC_nvptx__PTX_alloca_not_supported {unresolved symbol} { target *-*-* } 0 } */ -/* { dg-final output-exists-not } */ +/* { dg-output {GCC/nvptx: sorry, unimplemented: dynamic stack allocation not supported[\r\n]+} } + { dg-shouldfail __GCC_nvptx__PTX_alloca_not_supported } */ diff --git a/gcc/testsuite/gcc.target/nvptx/decl.c b/gcc/testsuite/gcc.target/nvptx/decl.c index 190a64d..45dd699 100644 --- a/gcc/testsuite/gcc.target/nvptx/decl.c +++ b/gcc/testsuite/gcc.target/nvptx/decl.c @@ -13,8 +13,8 @@ int Foo () } /* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.visible .global \[^,\r\n\]*glob_export" } } */ -/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.visible .const \[^,\r\n\]*cst_export" } } */ +/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.visible .global \[^,\r\n\]*cst_export" } } */ /* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.global \[^,\r\n\]*glob_local" } } */ -/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.const \[^,\r\n\]*cst_local" } } */ +/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.global \[^,\r\n\]*cst_local" } } */ /* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.extern .global \[^,\r\n\]*glob_import" } } */ -/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.extern .const \[^,\r\n\]*cst_import" } } */ +/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.extern .global \[^,\r\n\]*cst_import" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c b/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c index e2369fc..326d5dc 100644 --- a/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c +++ b/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c @@ -10,10 +10,10 @@ func (int a, int b); **sum: ** ... ** cm.mvsa01 s1,s2 -** call func +** call func(?:@plt)? ** mv s0,a0 ** cm.mva01s s1,s2 -** call func +** call func(?:@plt)? ** ... */ int diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c index e40874f..581b5db 100644 --- a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile target { { rv64-*-*}} } */ +/* { dg-do compile { target rv64-*-* } } */ /* { dg-options "-march=rv64gc_zicbop -mabi=lp64" } */ void foo (char *p) diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c index dd6e1ea..3f7c1a4 100644 --- a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c @@ -1,4 +1,4 @@ -/* { dg-do compile target { { rv32-*-*}} } */ +/* { dg-do compile { target rv64-*-* } } */ /* { dg-options "-march=rv32gc_zicbop -mabi=ilp32" } */ void foo (char *p) diff --git a/gcc/testsuite/gcc.target/riscv/cpymem-64.c b/gcc/testsuite/gcc.target/riscv/cpymem-64.c index 37b8ef0..c91b015 100644 --- a/gcc/testsuite/gcc.target/riscv/cpymem-64.c +++ b/gcc/testsuite/gcc.target/riscv/cpymem-64.c @@ -95,7 +95,7 @@ COPY_ALIGNED_N(11) /* **copy_15: ** ... -** (call|tail)\tmemcpy +** (call|tail)\tmemcpy(?:@plt)? ** ... */ COPY_N(15) @@ -116,7 +116,7 @@ COPY_ALIGNED_N(15) /* **copy_27: ** ... -** (call|tail)\tmemcpy +** (call|tail)\tmemcpy(?:@plt)? ** ... */ COPY_N(27) diff --git a/gcc/testsuite/gcc.target/riscv/fmax-snan.c b/gcc/testsuite/gcc.target/riscv/fmax-snan.c index aabaad5..a1f6149 100644 --- a/gcc/testsuite/gcc.target/riscv/fmax-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fmax-snan.c @@ -10,4 +10,4 @@ fmax (double x, double y) /* { dg-final { scan-assembler-not "\tfmax\\.d\t" } } */ /* { dg-final { scan-assembler-not "\tfge\\.d\t" } } */ -/* { dg-final { scan-assembler "\t(call|tail)\tfmax\t" } } */ +/* { dg-final { scan-assembler "\t(call|tail)\tfmax(?:@plt)?\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c b/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c index f74a817..1daf3e9 100644 --- a/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c @@ -10,4 +10,4 @@ fmaxf (float x, float y) /* { dg-final { scan-assembler-not "\tfmax\\.s\t" } } */ /* { dg-final { scan-assembler-not "\tfge\\.s\t" } } */ -/* { dg-final { scan-assembler "\t(call|tail)\tfmaxf\t" } } */ +/* { dg-final { scan-assembler "\t(call|tail)\tfmaxf(?:@plt)?\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fmin-snan.c b/gcc/testsuite/gcc.target/riscv/fmin-snan.c index 3b2e8c3..cc0e16c 100644 --- a/gcc/testsuite/gcc.target/riscv/fmin-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fmin-snan.c @@ -10,4 +10,4 @@ fmin (double x, double y) /* { dg-final { scan-assembler-not "\tfmin\\.d\t" } } */ /* { dg-final { scan-assembler-not "\tfle\\.d\t" } } */ -/* { dg-final { scan-assembler "\t(call|tail)\tfmin\t" } } */ +/* { dg-final { scan-assembler "\t(call|tail)\tfmin(?:@plt)?\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fminf-snan.c b/gcc/testsuite/gcc.target/riscv/fminf-snan.c index d28822e..598644e 100644 --- a/gcc/testsuite/gcc.target/riscv/fminf-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fminf-snan.c @@ -10,4 +10,4 @@ fminf (float x, float y) /* { dg-final { scan-assembler-not "\tfmin\\.s\t" } } */ /* { dg-final { scan-assembler-not "\tfle\\.s\t" } } */ -/* { dg-final { scan-assembler "\t(call|tail)\tfminf\t" } } */ +/* { dg-final { scan-assembler "\t(call|tail)\tfminf(?:@plt)?\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/large-model.c b/gcc/testsuite/gcc.target/riscv/large-model.c index 244d14e..d5ef7a0 100644 --- a/gcc/testsuite/gcc.target/riscv/large-model.c +++ b/gcc/testsuite/gcc.target/riscv/large-model.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64 -fno-section-anchors -mcmodel=large" } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -fno-section-anchors -mcmodel=large -fno-pie" } */ /* { dg-skip-if "" { *-*-* } {"-O0"} } */ int a, b; int foo1() diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c index 2903c88..c2a374f 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c @@ -1,6 +1,6 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { rv64 } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ -/* { dg-options "-mcpu=xiangshan-nanhu" { target { rv64 } } } */ +/* { dg-options "-mcpu=xiangshan-nanhu" } */ /* XiangShan Nanhu => rv64imafdc_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd _zkne_zknh_zksed_zksh_svinval_zicbom_zicboz */ diff --git a/gcc/testsuite/gcc.target/riscv/predef-1.c b/gcc/testsuite/gcc.target/riscv/predef-1.c index 250812a..551346e 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-1.c +++ b/gcc/testsuite/gcc.target/riscv/predef-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32i -mabi=ilp32 -mcmodel=medlow" } */ +/* { dg-options "-march=rv32i -mabi=ilp32 -mcmodel=medlow -fno-pie" } */ int main () { #if !defined(__riscv) diff --git a/gcc/testsuite/gcc.target/riscv/predef-4.c b/gcc/testsuite/gcc.target/riscv/predef-4.c index ba8b5c7..7b3c054 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-4.c +++ b/gcc/testsuite/gcc.target/riscv/predef-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64ia -mabi=lp64 -mcmodel=medlow" } */ +/* { dg-options "-march=rv64ia -mabi=lp64 -mcmodel=medlow -fno-pie" } */ int main () { #if !defined(__riscv) diff --git a/gcc/testsuite/gcc.target/riscv/predef-7.c b/gcc/testsuite/gcc.target/riscv/predef-7.c index 833e2be..36caf8e 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-7.c +++ b/gcc/testsuite/gcc.target/riscv/predef-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32em -mabi=ilp32e -mno-div -mcmodel=medlow" } */ +/* { dg-options "-march=rv32em -mabi=ilp32e -mno-div -mcmodel=medlow -fno-pie" } */ int main () { #if !defined(__riscv) diff --git a/gcc/testsuite/gcc.target/riscv/predef-9.c b/gcc/testsuite/gcc.target/riscv/predef-9.c index b173d5d..fa072ad 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-9.c +++ b/gcc/testsuite/gcc.target/riscv/predef-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64em -mabi=lp64e -mno-div -mcmodel=medlow" } */ +/* { dg-options "-march=rv64em -mabi=lp64e -mno-div -mcmodel=medlow -fno-pie" } */ /* { dg-warning "LP64E ABI is marked for deprecation in GCC" "" { target *-*-* } 0 } */ /* { dg-note "if you need LP64E please notify the GCC project via PR116152" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c b/gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c index 250f9ec..44da4b2 100644 --- a/gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c +++ b/gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c @@ -1,4 +1,4 @@ -/* { dg-do compile target { { rv64-*-*}} } */ +/* { dg-do compile { target rv64-*-* } } */ /* { dg-options "-march=rv64gc_zicbop -mabi=lp64" } */ void foo (char *p) diff --git a/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c index 54e809f..43439d7 100644 --- a/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c +++ b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c @@ -1,4 +1,4 @@ -/* { dg-do compile target { { rv64-*-*}} } */ +/* { dg-do compile { target rv64-*-* } } */ /* { dg-options "-march=rv64gc_zicbop_zihintntl -mabi=lp64" } */ void foo (char *p) diff --git a/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c b/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c index 0af4d71..fd845f5 100644 --- a/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c @@ -244,9 +244,9 @@ test_f0 () /* **foo: ** cm.push {ra}, -16 -** call f1 +** call f1(?:@plt)? ** cm.pop {ra}, 16 -** tail f2 +** tail f2(?:@plt)? */ void foo (void) @@ -258,7 +258,7 @@ foo (void) /* **test_popretz: ** cm.push {ra}, -16 -** call f1 +** call f1(?:@plt)? ** li a0,0 ** cm.popret {ra}, 16 */ diff --git a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c b/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c index 723889f4..d90f4f4 100644 --- a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c @@ -244,9 +244,9 @@ test_f0 () /* **foo: ** cm.push {ra}, -16 -** call f1 +** call f1(?:@plt)? ** cm.pop {ra}, 16 -** tail f2 +** tail f2(?:@plt)? */ void foo (void) @@ -258,7 +258,7 @@ foo (void) /* **test_popretz: ** cm.push {ra}, -16 -** call f1 +** call f1(?:@plt)? ** li a0,0 ** cm.popret {ra}, 16 */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f16.c deleted file mode 100644 index e4ff310..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f16.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (float, _Float16) - -/* { dg-final { scan-assembler-times {\tvfwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f32.c deleted file mode 100644 index 7d2b448..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f32.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (double, float) - -/* { dg-final { scan-assembler-times {\tvfwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i16.c deleted file mode 100644 index dc7e1da..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i16.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (int32_t, int16_t) - -/* { dg-final { scan-assembler-times {\tvwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i32.c deleted file mode 100644 index de1072f..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i32.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (int64_t, int32_t) - -/* { dg-final { scan-assembler-times {\tvwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i8.c deleted file mode 100644 index 8de5ef4..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i8.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (int16_t, int8_t) - -/* { dg-final { scan-assembler-times {\tvwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u16.c deleted file mode 100644 index a4aafd2..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u16.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (uint32_t, uint16_t) - -/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u32.c deleted file mode 100644 index 0deeaa0..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u32.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (uint64_t, uint32_t) - -/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u8.c deleted file mode 100644 index a6afcd0..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u8.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (uint16_t, uint8_t) - -/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c new file mode 100644 index 0000000..d02a8e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ + +#include <stdint-gcc.h> + +#define TEST_TYPE(TYPE1, TYPE2) \ + __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 ( \ + TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3, \ + TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b, \ + TYPE2 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; i++) \ + { \ + dst[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b[i] : dst[i]; \ + dst2[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) b[i] : dst2[i]; \ + dst3[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) a[i] : dst3[i]; \ + dst4[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b2[i] : dst4[i]; \ + } \ + } + +#define TEST_ALL() \ + TEST_TYPE (int16_t, int8_t) \ + TEST_TYPE (uint16_t, uint8_t) \ + TEST_TYPE (int32_t, int16_t) \ + TEST_TYPE (uint32_t, uint16_t) \ + TEST_TYPE (int64_t, int32_t) \ + TEST_TYPE (uint64_t, uint32_t) \ + TEST_TYPE (float, _Float16) \ + TEST_TYPE (double, float) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvwmul\.vv} 12 } } */ +/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 12 } } */ +/* { dg-final { scan-assembler-times {\tvfwmul\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.h deleted file mode 100644 index 974846f..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef COND_WIDEN_COMPLICATE_3_H -#define COND_WIDEN_COMPLICATE_3_H - -#include <stdint-gcc.h> - -#define TEST_TYPE(TYPE1, TYPE2) \ - __attribute__ ((noipa)) void vwadd_##TYPE1##_##TYPE2 ( \ - TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3, \ - TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b, \ - TYPE2 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n) \ - { \ - for (int i = 0; i < n; i++) \ - { \ - dst[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b[i] : dst[i]; \ - dst2[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) b[i] : dst2[i]; \ - dst3[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) a[i] : dst3[i]; \ - dst4[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b2[i] : dst4[i]; \ - } \ - } - -#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c index 1f170c9..32db3a6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c @@ -3,7 +3,7 @@ #include "pr111391-1.c" -/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 } } +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 } } */ /* { dg-final { scan-assembler-times {vmv\.x\.s} 2 } } */ /* { dg-final { scan-assembler-times {vslidedown.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 1 } } */ /* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,[a-x0-9]+,32} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c index 493dab0..0267078 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c @@ -18,6 +18,5 @@ int pixel_sad_n(unsigned char *pix1, unsigned char *pix2, int n) return sum; } -/* { dg-final { scan-assembler {vrsub\.v} } } */ /* { dg-final { scan-assembler {vmax\.v} } } */ -/* { dg-final { scan-assembler {vwsubu\.v} } } */ +/* { dg-final { scan-assembler-times {vwsubu\.v} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-14.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-14.c index 163152a..222d8c2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-14.c @@ -1,20 +1,20 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=rv32gc_zve32x_zvl64b -mabi=ilp32d" } */ -void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} -void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} -void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} -void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} -void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} -void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} -void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} -void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} -void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} -void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} -void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} -void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} -void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} -void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x2_t'} } */ +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x2_t'} } */ +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x3_t'} } */ +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x3_t'} } */ +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x4_t'} } */ +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x4_t'} } */ +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x5_t'} } */ +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x5_t'} } */ +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x6_t'} } */ +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x6_t'} } */ +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x7_t'} } */ +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x7_t'} } */ +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x8_t'} } */ +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x8_t'} } */ void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} @@ -65,20 +65,20 @@ void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} -void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} -void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} -void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} -void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} -void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} -void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} -void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} -void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} -void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} -void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} -void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} -void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} -void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} -void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x2_t'} } */ +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x2_t'} } */ +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x3_t'} } */ +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x3_t'} } */ +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x4_t'} } */ +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x4_t'} } */ +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x5_t'} } */ +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x5_t'} } */ +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x6_t'} } */ +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x6_t'} } */ +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x7_t'} } */ +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x7_t'} } */ +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x8_t'} } */ +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x8_t'} } */ void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} @@ -115,20 +115,20 @@ void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} -void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} -void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} -void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} -void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} -void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} -void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} -void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} -void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} -void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} -void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} -void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} -void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} -void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} -void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x2_t'} } */ +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x2_t'} } */ +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x3_t'} } */ +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x3_t'} } */ +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x4_t'} } */ +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x4_t'} } */ +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x5_t'} } */ +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x5_t'} } */ +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x6_t'} } */ +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x6_t'} } */ +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x7_t'} } */ +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x7_t'} } */ +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x8_t'} } */ +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x8_t'} } */ void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c index 9e962a7..2762b7a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c @@ -1,20 +1,20 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=rv32gc_zve32f_zvl64b -mabi=ilp32d" } */ -void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} -void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} -void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} -void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} -void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} -void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} -void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} -void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} -void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} -void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} -void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} -void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} -void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} -void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x2_t'} } */ +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x2_t'} } */ +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x3_t'} } */ +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x3_t'} } */ +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x4_t'} } */ +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x4_t'} } */ +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x5_t'} } */ +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x5_t'} } */ +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x6_t'} } */ +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x6_t'} } */ +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x7_t'} } */ +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x7_t'} } */ +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x8_t'} } */ +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x8_t'} } */ void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} @@ -65,20 +65,20 @@ void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} -void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} -void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} -void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} -void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} -void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} -void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} -void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} -void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} -void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} -void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} -void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} -void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} -void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} -void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x2_t'} } */ +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x2_t'} } */ +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x3_t'} } */ +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x3_t'} } */ +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x4_t'} } */ +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x4_t'} } */ +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x5_t'} } */ +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x5_t'} } */ +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x6_t'} } */ +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x6_t'} } */ +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x7_t'} } */ +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x7_t'} } */ +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x8_t'} } */ +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x8_t'} } */ void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} @@ -115,20 +115,20 @@ void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} -void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} -void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} -void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} -void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} -void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} -void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} -void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} -void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} -void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} -void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} -void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} -void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} -void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} -void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x2_t'} } */ +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x2_t'} } */ +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x3_t'} } */ +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x3_t'} } */ +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x4_t'} } */ +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x4_t'} } */ +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x5_t'} } */ +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x5_t'} } */ +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x6_t'} } */ +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x6_t'} } */ +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x7_t'} } */ +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x7_t'} } */ +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x8_t'} } */ +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x8_t'} } */ void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} @@ -179,13 +179,13 @@ void f___rvv_float16m1_t () {__rvv_float16m1_t t;} /* { dg-error {unknown type n void f___rvv_float16m2_t () {__rvv_float16m2_t t;} /* { dg-error {unknown type name '__rvv_float16m2_t'} } */ void f___rvv_float16m4_t () {__rvv_float16m4_t t;} /* { dg-error {unknown type name '__rvv_float16m4_t'} } */ void f___rvv_float16m8_t () {__rvv_float16m8_t t;} /* { dg-error {unknown type name '__rvv_float16m8_t'} } */ -void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} -void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} -void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} -void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} -void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} -void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} -void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} +void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x2_t'} } */ +void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x3_t'} } */ +void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x4_t'} } */ +void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x5_t'} } */ +void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x6_t'} } */ +void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x7_t'} } */ +void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x8_t'} } */ void f___rvv_float32m1x2_t () {__rvv_float32m1x2_t t;} void f___rvv_float32m1x3_t () {__rvv_float32m1x3_t t;} void f___rvv_float32m1x4_t () {__rvv_float32m1x4_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-18.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-18.c index 402e8f6..95b760f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-18.c @@ -1,20 +1,20 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=rv32gc_zve32x_zvl64b_zvfhmin -mabi=ilp32d" } */ -void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} -void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} -void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} -void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} -void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} -void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} -void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} -void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} -void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} -void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} -void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} -void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} -void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} -void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x2_t'} } */ +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x2_t'} } */ +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x3_t'} } */ +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x3_t'} } */ +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x4_t'} } */ +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x4_t'} } */ +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x5_t'} } */ +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x5_t'} } */ +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x6_t'} } */ +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x6_t'} } */ +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x7_t'} } */ +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x7_t'} } */ +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x8_t'} } */ +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x8_t'} } */ void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} @@ -65,20 +65,20 @@ void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} -void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} -void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} -void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} -void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} -void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} -void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} -void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} -void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} -void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} -void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} -void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} -void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} -void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} -void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x2_t'} } */ +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x2_t'} } */ +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x3_t'} } */ +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x3_t'} } */ +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x4_t'} } */ +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x4_t'} } */ +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x5_t'} } */ +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x5_t'} } */ +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x6_t'} } */ +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x6_t'} } */ +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x7_t'} } */ +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x7_t'} } */ +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x8_t'} } */ +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x8_t'} } */ void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} @@ -115,20 +115,20 @@ void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} -void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} -void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} -void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} -void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} -void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} -void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} -void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} -void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} -void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} -void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} -void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} -void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} -void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} -void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x2_t'} } */ +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x2_t'} } */ +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x3_t'} } */ +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x3_t'} } */ +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x4_t'} } */ +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x4_t'} } */ +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x5_t'} } */ +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x5_t'} } */ +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x6_t'} } */ +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x6_t'} } */ +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x7_t'} } */ +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x7_t'} } */ +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x8_t'} } */ +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x8_t'} } */ void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} @@ -173,13 +173,13 @@ void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} /* { dg-error {unknown type n void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x4_t'} } */ void f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} /* { dg-error {unknown type name '__rvv_int64m4x2_t'} } */ void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m4x2_t'} } */ -void f___rvv_float16mf4x2_t () {__rvv_float16mf4x2_t t;} -void f___rvv_float16mf4x3_t () {__rvv_float16mf4x3_t t;} -void f___rvv_float16mf4x4_t () {__rvv_float16mf4x4_t t;} -void f___rvv_float16mf4x5_t () {__rvv_float16mf4x5_t t;} -void f___rvv_float16mf4x6_t () {__rvv_float16mf4x6_t t;} -void f___rvv_float16mf4x7_t () {__rvv_float16mf4x7_t t;} -void f___rvv_float16mf4x8_t () {__rvv_float16mf4x8_t t;} +void f___rvv_float16mf4x2_t () {__rvv_float16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_float16mf4x2_t'} } */ +void f___rvv_float16mf4x3_t () {__rvv_float16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_float16mf4x3_t'} } */ +void f___rvv_float16mf4x4_t () {__rvv_float16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_float16mf4x4_t'} } */ +void f___rvv_float16mf4x5_t () {__rvv_float16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_float16mf4x5_t'} } */ +void f___rvv_float16mf4x6_t () {__rvv_float16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_float16mf4x6_t'} } */ +void f___rvv_float16mf4x7_t () {__rvv_float16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_float16mf4x7_t'} } */ +void f___rvv_float16mf4x8_t () {__rvv_float16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_float16mf4x8_t'} } */ void f___rvv_float16mf2x2_t () {__rvv_float16mf2x2_t t;} void f___rvv_float16mf2x3_t () {__rvv_float16mf2x3_t t;} void f___rvv_float16mf2x4_t () {__rvv_float16mf2x4_t t;} @@ -198,13 +198,13 @@ void f___rvv_float16m2x2_t () {__rvv_float16m2x2_t t;} void f___rvv_float16m2x3_t () {__rvv_float16m2x3_t t;} void f___rvv_float16m2x4_t () {__rvv_float16m2x4_t t;} void f___rvv_float16m4x2_t () {__rvv_float16m4x2_t t;} -void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} -void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} -void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} -void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} -void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} -void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} -void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} +void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x2_t'} } */ +void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x3_t'} } */ +void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x4_t'} } */ +void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x5_t'} } */ +void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x6_t'} } */ +void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x7_t'} } */ +void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x8_t'} } */ void f___rvv_float32m1x2_t () {__rvv_float32m1x2_t t;} void f___rvv_float32m1x3_t () {__rvv_float32m1x3_t t;} void f___rvv_float32m1x4_t () {__rvv_float32m1x4_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c index 638e90f..69a94d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d -mrvv-vector-bits=zvl" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c index 380d0c1..5e0f136 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d -mrvv-vector-bits=zvl" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c index 9ed72a6..a3c0a6d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d -msave-restore" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c index b6b708f..b1cf6aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c index 13e3328..8838f0d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c index 39c8c00..77f1c7c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d -msave-restore" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar1 (vint8m1_t a); void bar2 (); @@ -51,7 +51,7 @@ foo1 (vint8m1_t a) ** vs1r\.v\tv30,0\(sp\) ** sub\tsp,sp,t0 ** vs1r\.v\tv31,0\(sp\) -** call\tbar2 +** call\tbar2(?:@plt)? ** csrr\tt0,vlenb ** vl1re64\.v\tv31,0\(sp\) ** add\tsp,sp,t0 @@ -96,8 +96,8 @@ foo2 (vint8m1_t a) ** foo3: ** call\tt0,__riscv_save_0 ** vl1re8\.v\tv8,0\(a0\) -** call\tbar1 -** call\tbar2 +** call\tbar1(?:@plt)? +** call\tbar2(?:@plt)? ** tail\t__riscv_restore_0 */ void diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c index 5f8f96f..37127a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar1 (vint8m1_t a); void bar2 (); @@ -10,7 +10,7 @@ void bar2 (); /* ** foo1: ** cm.push\t{ra},\s*-16 -** call\tbar1 +** call\tbar1(?:@plt)? ** cm.popret\t{ra},\s*16 */ void @@ -53,7 +53,7 @@ foo1 (vint8m1_t a) ** vs1r\.v\tv30,0\(sp\) ** sub\tsp,sp,t0 ** vs1r\.v\tv31,0\(sp\) -** call\tbar2 +** call\tbar2(?:@plt)? ** csrr\tt0,vlenb ** vl1re64\.v\tv31,0\(sp\) ** add\tsp,sp,t0 @@ -97,7 +97,7 @@ foo2 (vint8m1_t a) ** foo3: ** cm.push\t{ra},\s*-16 ** vl1re8\.v\tv8,0\(a0\) -** call\tbar1 +** call\tbar1(?:@plt)? ** cm.popret\t{ra},\s*16 */ void diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c index a9f3855..a8daeeb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar1 (vint8m1_t a); void bar2 (); @@ -11,7 +11,7 @@ void bar2 (); ** foo1: ** addi\tsp,sp,-16 ** sd\tra,8\(sp\) -** call\tbar1 +** call\tbar1(?:@plt)? ** ld\tra,8\(sp\) ** addi\tsp,sp,16 ** jr\tra @@ -57,7 +57,7 @@ foo1 (vint8m1_t a) ** vs1r\.v\tv30,0\(sp\) ** sub\tsp,sp,t0 ** vs1r\.v\tv31,0\(sp\) -** call\tbar2 +** call\tbar2(?:@plt)? ** csrr\tt0,vlenb ** vl1re64\.v\tv31,0\(sp\) ** add\tsp,sp,t0 @@ -105,7 +105,7 @@ foo2 (vint8m1_t a) ** addi\tsp,sp,-16 ** sd\tra,8\(sp\) ** vl1re8\.v\tv8,0\(a0\) -** call\tbar1 +** call\tbar1(?:@plt)? ** ld\tra,8\(sp\) ** addi\tsp,sp,16 ** jr\tra diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c index fe3a1ef..f8143b9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c @@ -4,7 +4,7 @@ /* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-options " -march=rv64gcv_zvfh -mabi=lp64d -O2" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" int8_t a[1]; uint16_t b[1]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c index 60fdfc4..05628d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c @@ -4,7 +4,7 @@ /* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-options " -march=rv64gcv_zvfh -mabi=lp64d -O2 --param=vsetvl-strategy=optim -fno-schedule-insns -fno-schedule-insns2 -fno-schedule-fusion " } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void __attribute__ ((noipa)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c index 28766ce..3180f71 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vint64m1_t f1 (vint64m1_t vd, vint64m1_t vs2, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c index 975f755..31b68c4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d -O0" { target { rv64 } } } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O0" { target { rv32 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vint64m1_t f1 (vint64m1_t vd, vint64m1_t vs2, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c index 8cfe965..f7c9ad1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vfloat16m1_t f0 (vfloat16m1_t vs2, vfloat16m1_t vs1, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c index 9edd6cb..3534720 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c @@ -21,7 +21,7 @@ f1 (void *a, void *b) /* Tiny __builtin_memcmp should use libc. ** f2: ** li\s+a\d,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f2 (void *a, void *b) @@ -79,7 +79,7 @@ f5 (void *a, void *b) /* Don't inline if the length is too large for one operation. ** f6: ** li\s+a2,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f6 (void *a, void *b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c index 82aa307..c1c1aae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c @@ -8,7 +8,7 @@ /* Tiny __builtin_memcmp should use libc. ** f1: ** li\s+a\d,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f1 (void *a, void *b) @@ -36,7 +36,7 @@ f2 (void *a, void *b) /* Don't inline if the length is too large for one operation. ** f3: ** li\s+a2,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f3 (void *a, void *b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c index e2dd6a1..ad87038 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c @@ -8,7 +8,7 @@ /* Tiny __builtin_memcmp should use libc. ** f1: ** li\s+a\d,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f1 (void *a, void *b) @@ -53,7 +53,7 @@ f3 (void *a, void *b) /* Don't inline if the length is too large for one operation. ** f4: ** li\s+a2,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f4 (void *a, void *b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c index 654c800..5e35204 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2 -fno-pie" } */ /* { dg-add-options riscv_v } */ /* { dg-final { check-function-bodies "**" "" } } */ @@ -109,4 +109,4 @@ void f3 () memcpy (&a_a, &a_b, sizeof a_a); } -/* { dg-final { scan-assembler-not {\m(tail|call)\s+memcpy\M} } } */ +/* { dg-final { scan-assembler-not {\m(tail|call)\s+memcpy(?:@plt)?\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c index 03e633b..44bf3d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c @@ -52,7 +52,7 @@ f3 (char *a, char const *b) /* Don't vectorise if the move is too large for one operation ** f4: ** li\s+a2,\d+ -** tail\s+memmove +** tail\s+memmove(?:@plt)? */ char * f4 (char *a, char const *b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110943.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110943.c index 8a6c00f..a08ac6e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110943.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110943.c @@ -2,7 +2,7 @@ /* { dg-options "-O3 -march=rv64gcv -mabi=lp64d" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" /* ** foo9: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c index 3e43c94..a0ed793 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-O3 -ansi -pedantic-errors -std=gnu99" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" size_t __attribute__ ((noinline)) sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c index 9bfa39c..4f375e5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c @@ -93,9 +93,9 @@ test_5 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count) /* ** test_6: ** ... -** call\s+__extendhfsf2 +** call\s+__extendhfsf2(?:@plt)? ** ... -** call\s+__truncsfhf2 +** call\s+__truncsfhf2(?:@plt)? ** ... */ void diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114639-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114639-1.c index 3ad91db..c5b35c8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114639-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114639-1.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" extern size_t get_vl (); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c index d552eb5..e9e41f7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target riscv_v_ok } */ /* { dg-add-options riscv_v } */ -/* { dg-additional-options "-std=gnu99" } */ +/* { dg-additional-options "-std=gnu99 -Wno-pedantic" } */ #include "pr115068.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c index af2cba6..ce9a389 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c @@ -1,9 +1,9 @@ /* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options riscv_v } */ -/* { dg-additional-options "-std=gnu99" } */ +/* { dg-additional-options "-std=gnu99 -Wno-pedantic" } */ #include <stdint.h> -#include <riscv_vector.h> +#include "riscv_vector.h" vfloat64m8_t test_vfwadd_wf_f64m8_m (vbool8_t vm, vfloat64m8_t vs2, float rs1, size_t vl) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c index dabb8ae..7b6eefe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O1" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" _Float16 a[10]; void func(){ int placeholder0 = 10; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117544.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117544.c index af3532a..81e0ec3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117544.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117544.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar() __attribute__((riscv_vector_cc)); vint32m1_t foo(vint32m1_t a, vint32m1_t b) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c index 81e3a6e..4904c92 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { rv64 } } } */ /* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" _Float16 a (uint64_t); int8_t b () { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c index adb54d6..d62751e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vfloat32m2_t foo (vfloat16m1_t a, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c index a22d366..490445f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c @@ -94,7 +94,7 @@ f6 (void *a, int const b) /* Don't vectorise if the move is too large for one operation. ** f7: ** li\s+a2,\d+ -** tail\s+memset +** tail\s+memset(?:@plt)? */ void * f7 (void *a, int const b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c index a108868..876929e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c @@ -44,7 +44,7 @@ f2 (void *a, int const b) /* Don't vectorise if the move is too large for requested lmul. ** f3: ** li\s+a2,\d+ -** tail\s+memset +** tail\s+memset(?:@plt)? */ void * f3 (void *a, int const b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c index 460a8f2..a185916 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c @@ -62,7 +62,7 @@ f3 (void *a, int const b) /* Don't vectorise if the move is too large for requested lmul. ** f4: ** li\s+a2,\d+ -** tail\s+memset +** tail\s+memset(?:@plt)? */ void * f4 (void *a, int const b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c index 7e5758b..375d316 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c @@ -18,7 +18,7 @@ void f (char*); ** ... ** addi\ta0,sp,15 ** andi\ta0,a0,-16 -** call\tf +** call\tf(?:@plt)? ** ... ** lw\tra,12\(sp\) ** lw\ts0,8\(sp\) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c index 4253729..6bb7e1c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) { return __riscv_vlmul_ext_v_i16mf4_i16m8(op1); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl_zve32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl_zve32-1.c new file mode 100644 index 0000000..f6899c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl_zve32-1.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32imafc_zve32f_zvl128b -mabi=ilp32 -O2" } */ + +struct S0 +{ + unsigned a : 15; + int b; + int c; +}; + +struct S1 +{ + struct S0 s0; + int e; +}; + +struct Z +{ + char c; + int z; +} __attribute__((packed)); + +union U +{ + struct S1 s1; + struct Z z; +}; + +int __attribute__((noinline, noclone)) +return_zero (void) +{ + return 0; +} + +volatile union U gu; +struct S0 gs; + +int __attribute__((noinline, noclone)) +check_outcome () +{ + if (gs.a != 6 + || gs.b != 80000) + __builtin_abort (); +} + +int +main (int argc, char *argv[]) +{ + union U u; + struct S1 m; + struct S0 l; + + if (return_zero ()) + u.z.z = 20000; + else + { + u.s1.s0.a = 6; + u.s1.s0.b = 80000; + u.s1.e = 2; + + m = u.s1; + m.s0.c = 0; + l = m.s0; + gs = l; + } + + gu = u; + check_outcome (); + return 0; +} + +/* { dg-final { scan-assembler {vsetivli\s+zero,\s*2,\s*e32,\s*m1,\s*t[au],\s*m[au]} } } */ +/* { dg-final { scan-assembler {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl_zve32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl_zve32-2.c new file mode 100644 index 0000000..dd81f8b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl_zve32-2.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g_zve32x_zvl128b -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +typedef unsigned int V2SI __attribute__((vector_size(8))); + +V2SI v1, v2; + +/* Make sure we won't use mf2 mode even vector register is OK to hold for + ELEN=32. */ +void foo1() +{ +/* +** foo1: +** ... +** vsetivli zero,2,e32,m1,ta,ma +** ... +** vle32\.v v[0-9]+,0\([a-x][0-9]+\) +** ... +** vse32\.v v[0-9]+,0\([a-x][0-9]+\) +** ... +** ret +*/ + v1 = v2; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c index 606854b..a278709 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=rv64gcv -mabi=lp64d" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vuint64m1_t test_vssubu_vx_u64m1(vuint64m1_t op1) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c index 78abd09..2f8c146 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=rv32gcv -mabi=ilp32d" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vuint64m1_t test_vssubu_vx_u64m1(vuint64m1_t op1) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c index 6e027a5..43be202 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c @@ -1,9 +1,9 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ +/* { dg-do compile { target { { ! riscv_abi_e } && rv64 } } } */ /* { dg-add-options riscv_v } */ -/* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns -fno-schedule-insns2 -Wno-pedantic" } */ #include <stdint.h> -#include <riscv_vector.h> +#include "riscv_vector.h" /* ** vwadd_wx_i64m8_m: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c index 871cf65..f594217 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void f (vint32m1_t *in, vint64m2_t *out, vbool32_t *m, int b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c index b76760b..48f200f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c @@ -2,7 +2,7 @@ /* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w -std=gnu17" } */ /* { dg-skip-if "" { *-*-* } { "-flto" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" static inline __attribute__(()) int vaddq_f32(); static inline __attribute__(()) int vload_tillz_f32(int nlane) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c index 7096159e..3867681 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" size_t foo () { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c index c155f56..3acbc73 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O2 -fdump-rtl-vsetvl-details" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" uint64_t a[2], b[2]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c index 04a8ff2..2b2fe27 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -fno-schedule-insns -fdump-rtl-vsetvl-details" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vuint16m1_t foo (vuint16m1_t a, vuint16m1_t b, size_t avl) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c index dfaf82c..ad27c38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32d -O2 -save-temps" { target { rv32 } } } */ /* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O2 -save-temps" { target { rv64 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void foo (float *a, int b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c index a7cd8c5..c8056a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gc_zfh_xtheadvector -mabi=lp64d -O2 -save-temps" { target { rv64 } } } */ #include <math.h> -#include <riscv_vector.h> +#include "riscv_vector.h" static vfloat32m8_t atan2_ps(vfloat32m8_t a, vfloat32m8_t b, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c index aebb0e3..b3c3428 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { rv64 } } } */ /* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O2" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vfloat16m4_t foo (float *ptr, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c new file mode 100644 index 0000000..42fa43e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +struct a +{ + int b[]; +} c (vint32m4_t), d; + +char e; +char *f; + +void g () +{ + int h; + vint32m4_t i; + vint8m1_t j = __riscv_vlse8_v_i8m1 (&e, d.b[3], h); + vint16m2_t k = __riscv_vwadd_vx_i16m2 (j, 0, h); + i = __riscv_vwmacc_vx_i32m4 (i, f[0], k, h); + c (i); +} + +/* { dg-final { scan-assembler-not {th\.vsext\.vf2} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c new file mode 100644 index 0000000..d622b72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +struct a +{ + int b[]; +} c (vuint32m4_t), d; + +char e; +char *f; + +void g () +{ + int h; + vuint32m4_t i; + vuint8m1_t j = __riscv_vlse8_v_u8m1 (&e, d.b[3], h); + vuint16m2_t k = __riscv_vwaddu_vx_u16m2 (j, 0, h); + i = __riscv_vwmaccu_vx_u32m4 (i, f[0], k, h); + c (i); +} + +/* { dg-final { scan-assembler-not {th\.vzext\.vf2} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c index c0d643d..929de16 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c @@ -15,7 +15,7 @@ ** li\s+[atx][0-9]+,\s*-1 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 ** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c index 470e6b7..a540198 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c @@ -15,7 +15,7 @@ ** li\s+[atx][0-9]+,\s*-1 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 ** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c index bb94775..e3fe6c7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c @@ -15,7 +15,7 @@ ** li\s+[atx][0-9]+,\s*-1 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 ** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c index cc598eb..f42ffea 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c @@ -15,7 +15,7 @@ ** li\s+[atx][0-9]+,\s*-1 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 ** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c new file mode 100644 index 0000000..303f3cb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long long sub (unsigned long long a, unsigned long long b) +{ + b = (b << 50) >> 49; + unsigned int x = a + b; + return x; +} + +/* { dg-final { scan-assembler-not {\msh1add} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c new file mode 100644 index 0000000..883cce2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c @@ -0,0 +1,21 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-options "-march=rv64gc_zba -mabi=lp64d -O2" } */ + +struct { + unsigned a : 14; + unsigned b : 3; +} c; + +unsigned long long d; +void e (unsigned long long *f, long p2) { *f = p2; } +signed g; +long i; + +int main () { + c.b = 4; + i = -(-c.a - (3023282U + c.a + g)); + e (&d, i); + if (d != 3023282) + __builtin_abort (); + __builtin_exit (0); +} diff --git a/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c b/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c index f7d8f44..be304e7 100644 --- a/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c +++ b/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c @@ -10,7 +10,7 @@ bar (); **fool_rv32e: ** cm.push {ra}, -32 ** ... -** call bar +** call bar(?:@plt)? ** ... ** lw a[0-5],32\(sp\) ** ... |