diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
324 files changed, 1378 insertions, 622 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_dup.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_dup.c index c42c7ac..da9370b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_dup.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_dup.c @@ -1,6 +1,6 @@ /* { dg-do assemble { target { aarch64*-*-* } } } */ +/* { dg-skip-if "no optimizations" { *-*-* } { "-O0" } { "" } } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ -/* { dg-options "-O2" } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ /* { dg-additional-options "-save-temps" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c index 3a5efa5..7478323 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c index 16a986a..ebae422 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c index 4b0e242..dd62e32b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c index 0bebec7..70279d2 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c index 68ce599..2e8205d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c index 1b5a09b..eae7189 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c index 766c783..f23900e 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c index 8f5c14b..a735602 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c index ccfecf42..2792c2c1 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c index 161c7a0..6b4e028 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c index 2d3cd8a..cf44631 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c index 0d35385..c95a455 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c index ca23e3f..a801785 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c index f51cac3..9d17b05 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c index 57901c8..94e2f5d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c index 3218873..a1c8c50 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c index af6a5b6..9620001 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c index 2084c30..05cda23 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c index ebfd62a..f567e9b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c index a27871b..842005b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c index 0642ae0..1e23056 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c index 5ae28fc..719769a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c index 2d197b4..77b226b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c index 540b637..32a7f92 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c index 2173a0e..a24f787 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c index 5f17dbe..7a7617d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c index 426700c..7c6ad5a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c index 1583202..afe6c03 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c index 3413de0..6c988e6 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c index 25265d1..87dcfe5 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c index 9ce9558..944b325 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c index f0adb09..2756d0e 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c index 74c4e60..874726d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c index d308c35..4ee9dc7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c index b393767..ef61a24 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c index 247f7c9..8e725c7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c index 6e2ee50..f09cab0 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c index 27502c2..668be0f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c index e5f57f1..d3aeb69 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c index 188f60c..c66ee58 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c index cfc33c2..dd2dfbd 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c index 9965654..21055db 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c index 6bff954..c6d8481 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c index c7b3d17..a8bb322 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c index e3c5d3a..a2300b4 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c index d5807d7..1de5551 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c index a904e5e..a5b346f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c index ef0132a..d20e2dc 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c index f4f7b37..474cd20 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c index 7b5b16f..b564749 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c index db56171..1e5c289 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c index 6cda3b6..3ee2194 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c index cae69a3..175bcf2 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c index dec8d85..ef5acbb 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c index 94c333e..2f9855c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c index 0048b5b..f159ac2 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c index 0a95cea..39d92ec 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c index 97d5fba..fe605b5 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c index 3b1b273..597a2e0 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c index 5ff0d22..d58cad8 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c index 105d236..a2a246d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c index 290c5b1..a4905b1 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c index e367dad..8e443bd 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c index d66adcd..63b793bc 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c index 0229099..b1238de 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c index c0103fb..99c3e95 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c index 6a99109..c5b458b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c index c9d553a..789d9e2 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c index 1ac6b67..aae9a94 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c index 00c95d3..363d25f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c index f01aefb..72416dc 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c index ea751da..57ff684 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c index 77021be..d2486f1 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c index 6e56ff1..0892ce7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c @@ -1,5 +1,4 @@ /* We haven't implemented these intrinsics for arm yet. */ -/* { dg-do run } */ /* { dg-skip-if "unimplemented" { arm*-*-* } } */ /* { dg-options "-O3" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c index 42aeadf..9465e4a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c @@ -1,5 +1,4 @@ /* We haven't implemented these intrinsics for arm yet. */ -/* { dg-do run } */ /* { dg-skip-if "unimplemented" { arm*-*-* } } */ /* { dg-options "-O3" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c index 694fda8..a1461fd 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c @@ -1,5 +1,4 @@ /* We haven't implemented these intrinsics for arm yet. */ -/* { dg-do run } */ /* { dg-skip-if "unimplemented" { arm*-*-* } } */ /* { dg-options "-O3" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c index 182463e..763eb47 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c index 4db4b84..5242d55 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c index ce9872f..3b12e62 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c index 39c4897..bcb56fe 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c index d8efbca..9ee302f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c index f6b0216..e70bc6c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c index b7c5101..1910d9f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c index c454a53..3ab5432 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c index 18d1767..8f1d012 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-skip-if "" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c index 6c51d04..f434564 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-skip-if "" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c index 1719d56..d470308 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c index 09684d2..85fe687 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c index 4cd5c37..fe7cc84 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c index 51bbead..1b5b869 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c index f90a36d..2a4f24f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c index 140647b..d1fd316 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c index 66c744c..1c85773 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c index 90a5be8..d2df24c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c index 421d827..37ce039 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c index c8df677..df3b83d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrn_high_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrn_high_n.c index 6ebe074..07d873d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrn_high_n.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrn_high_n.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrun_high_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrun_high_n.c index 49d319d..e8f464d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrun_high_n.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrun_high_n.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrn_high_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrn_high_n.c index 8d06f11..5a3ea62 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrn_high_n.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrn_high_n.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrun_high_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrun_high_n.c index e8235fe..80c66fd 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrun_high_n.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrun_high_n.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c index 3740d6a..f0d0da7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c index 3e6b24e..9dd8981 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c index fc02b6b..9593b18 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c index bcf47f6..6b40e29 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c index 3c4649e..691fcd7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c index 7a4620b..1c596b0 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c index 4a7b721..6cbcf7c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c index 9af357d..7accb45 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c index eb4b27d..bc841b5 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c index 3fa9749..856a661 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c index eb4b27d..bc841b5 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c index 7c0e619..02d8bb7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c index a9753a4..b32c44c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c index 82249a7..77f9460 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ /* { dg-skip-if "" { arm*-*-* } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c index 7d03827..89b910c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c index 69be40a..3cf5eb3 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c @@ -1,5 +1,4 @@ /* We haven't implemented these intrinsics for arm yet. */ -/* { dg-do run } */ /* { dg-skip-if "unimplemented" { arm*-*-* } } */ /* { dg-options "-O3" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c index 4d42bcc..c05f8e7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c @@ -1,5 +1,4 @@ /* We haven't implemented these intrinsics for arm yet. */ -/* { dg-do run } */ /* { dg-skip-if "unimplemented" { arm*-*-* } } */ /* { dg-options "-O3" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c index ddc7fa5..a9867c3 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c @@ -1,5 +1,4 @@ /* We haven't implemented these intrinsics for arm yet. */ -/* { dg-do run } */ /* { dg-skip-if "unimplemented" { arm*-*-* } } */ /* { dg-options "-O3" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c index a7aba11..d24a599 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c index 6debfe5..c9485c3 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c index fe35e15..12ae8b0 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c index 5914192..65bc140 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c @@ -1,4 +1,3 @@ -/* { dg-do run } */ /* { dg-skip-if "" { arm*-*-* } } */ #include <arm_neon.h> diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-inst-ldlogic.c b/gcc/testsuite/gcc.target/aarch64/atomic-inst-ldlogic.c index 4879d52..ccb89ce 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-inst-ldlogic.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-inst-ldlogic.c @@ -101,54 +101,54 @@ TEST (xor_load_notreturn, XOR_LOAD_NORETURN) /* Load-OR. */ -/* { dg-final { scan-assembler-times "ldsetb\t" 8} } */ -/* { dg-final { scan-assembler-times "ldsetab\t" 16} } */ -/* { dg-final { scan-assembler-times "ldsetlb\t" 8} } */ -/* { dg-final { scan-assembler-times "ldsetalb\t" 16} } */ +/* { dg-final { scan-assembler-times "ldsetb\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldsetab\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldsetlb\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldsetalb\t" 16 } } */ -/* { dg-final { scan-assembler-times "ldseth\t" 8} } */ -/* { dg-final { scan-assembler-times "ldsetah\t" 16} } */ -/* { dg-final { scan-assembler-times "ldsetlh\t" 8} } */ -/* { dg-final { scan-assembler-times "ldsetalh\t" 16} } */ +/* { dg-final { scan-assembler-times "ldseth\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldsetah\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldsetlh\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldsetalh\t" 16 } } */ -/* { dg-final { scan-assembler-times "ldset\t" 16} } */ -/* { dg-final { scan-assembler-times "ldseta\t" 32} } */ -/* { dg-final { scan-assembler-times "ldsetl\t" 16} } */ -/* { dg-final { scan-assembler-times "ldsetal\t" 32} } */ +/* { dg-final { scan-assembler-times "ldset\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldseta\t" 32 } } */ +/* { dg-final { scan-assembler-times "ldsetl\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldsetal\t" 32 } } */ /* Load-AND. */ -/* { dg-final { scan-assembler-times "ldclrb\t" 8} } */ -/* { dg-final { scan-assembler-times "ldclrab\t" 16} } */ -/* { dg-final { scan-assembler-times "ldclrlb\t" 8} } */ -/* { dg-final { scan-assembler-times "ldclralb\t" 16} } */ +/* { dg-final { scan-assembler-times "ldclrb\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldclrab\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldclrlb\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldclralb\t" 16 } } */ -/* { dg-final { scan-assembler-times "ldclrh\t" 8} } */ -/* { dg-final { scan-assembler-times "ldclrah\t" 16} } */ -/* { dg-final { scan-assembler-times "ldclrlh\t" 8} } */ -/* { dg-final { scan-assembler-times "ldclralh\t" 16} } */ +/* { dg-final { scan-assembler-times "ldclrh\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldclrah\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldclrlh\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldclralh\t" 16 } } */ -/* { dg-final { scan-assembler-times "ldclr\t" 16} */ -/* { dg-final { scan-assembler-times "ldclra\t" 32} } */ -/* { dg-final { scan-assembler-times "ldclrl\t" 16} } */ -/* { dg-final { scan-assembler-times "ldclral\t" 32} } */ +/* { dg-final { scan-assembler-times "ldclr\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldclra\t" 32 } } */ +/* { dg-final { scan-assembler-times "ldclrl\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldclral\t" 32 } } */ /* Load-XOR. */ -/* { dg-final { scan-assembler-times "ldeorb\t" 8} } */ -/* { dg-final { scan-assembler-times "ldeorab\t" 16} } */ -/* { dg-final { scan-assembler-times "ldeorlb\t" 8} } */ -/* { dg-final { scan-assembler-times "ldeoralb\t" 16} } */ +/* { dg-final { scan-assembler-times "ldeorb\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldeorab\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldeorlb\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldeoralb\t" 16 } } */ -/* { dg-final { scan-assembler-times "ldeorh\t" 8} } */ -/* { dg-final { scan-assembler-times "ldeorah\t" 16} } */ -/* { dg-final { scan-assembler-times "ldeorlh\t" 8} } */ -/* { dg-final { scan-assembler-times "ldeoralh\t" 16} } */ +/* { dg-final { scan-assembler-times "ldeorh\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldeorah\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldeorlh\t" 8 } } */ +/* { dg-final { scan-assembler-times "ldeoralh\t" 16 } } */ -/* { dg-final { scan-assembler-times "ldeor\t" 16} */ -/* { dg-final { scan-assembler-times "ldeora\t" 32} } */ -/* { dg-final { scan-assembler-times "ldeorl\t" 16} } */ -/* { dg-final { scan-assembler-times "ldeoral\t" 32} } */ +/* { dg-final { scan-assembler-times "ldeor\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldeora\t" 32 } } */ +/* { dg-final { scan-assembler-times "ldeorl\t" 16 } } */ +/* { dg-final { scan-assembler-times "ldeoral\t" 32 } } */ /* { dg-final { scan-assembler-not "ldaxr\t" } } */ /* { dg-final { scan-assembler-not "stlxr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/crc-crc32c-data16.c b/gcc/testsuite/gcc.target/aarch64/crc-crc32c-data16.c index d82e625..db08136 100644 --- a/gcc/testsuite/gcc.target/aarch64/crc-crc32c-data16.c +++ b/gcc/testsuite/gcc.target/aarch64/crc-crc32c-data16.c @@ -10,7 +10,7 @@ uint32_t _crc32_O0 (uint32_t crc, uint16_t data) { int i; crc = crc ^ data; - for (i = 0; i < 8; i++) { + for (i = 0; i < 16; i++) { if (crc & 1) crc = (crc >> 1) ^ 0x82F63B78; else @@ -24,7 +24,7 @@ uint32_t _crc32 (uint32_t crc, uint16_t data) { int i; crc = crc ^ data; - for (i = 0; i < 8; i++) { + for (i = 0; i < 16; i++) { if (crc & 1) crc = (crc >> 1) ^ 0x82F63B78; else diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-1.c b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-1.c new file mode 100644 index 0000000..e5bb2d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-skip-if "Do not override mcpu or march" { *-*-* } { -mcpu=* -march=* } { "" } } */ +/* { dg-options { "-march=armv8-a+sme" } } */ +/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" "" { target *-*-* } 0 } */ +int main (void) +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-2.c b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-2.c new file mode 100644 index 0000000..13f09b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" "" { target *-*-* } 0 } */ + +#pragma GCC target ("arch=armv8.2-a+ssve-fp8fma") + +int main (void) +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-3.c b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-3.c new file mode 100644 index 0000000..9e3cbeb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-3.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" "" { target *-*-* } 0 } */ + +int __attribute__ ((target( "arch=armv8.2-a+ssve-fp8fma"))) main (void) +{ + return 0; +} + diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-4.c b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-4.c new file mode 100644 index 0000000..04a33a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-4.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-skip-if "Do not override mcpu or march" { *-*-* } { -mcpu=* -march=* } { "" } } */ +/* { dg-options { "-march=armv8-a" } } */ +/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" "" { target *-*-* } 0 } */ + +#pragma GCC target "+sme" + +int main (void) +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c index 97d68b9..dcac6d5 100644 --- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c +++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c @@ -46,7 +46,7 @@ #error Foo #endif -#pragma GCC target "+sme" +#pragma GCC target "+sve2+sme" #ifndef __ARM_FEATURE_SME #error Foo #endif @@ -66,7 +66,7 @@ #error Foo #endif -#pragma GCC target "+nothing+sme" +#pragma GCC target "+nothing+sve2+sme" #ifdef __ARM_FEATURE_SME_I16I64 #error Foo #endif @@ -80,7 +80,7 @@ #error Foo #endif -#pragma GCC target "+nothing+sme-i16i64" +#pragma GCC target "+nothing+sve2+sme-i16i64" #ifndef __ARM_FEATURE_SME_I16I64 #error Foo #endif @@ -91,7 +91,7 @@ #error Foo #endif -#pragma GCC target "+nothing+sme-b16b16" +#pragma GCC target "+nothing+sve2+sme-b16b16" #ifndef __ARM_FEATURE_SME_B16B16 #error Foo #endif @@ -105,7 +105,7 @@ #error Foo #endif -#pragma GCC target "+nothing+sme-f16f16" +#pragma GCC target "+nothing+sve2+sme-f16f16" #ifndef __ARM_FEATURE_SME_F16F16 #error Foo #endif @@ -116,7 +116,7 @@ #error Foo #endif -#pragma GCC target "+nothing+sme-f64f64" +#pragma GCC target "+nothing+sve2+sme-f64f64" #ifndef __ARM_FEATURE_SME_F64F64 #error Foo #endif @@ -160,7 +160,7 @@ #error Foo #endif -#pragma GCC target "+nothing+sve-b16b16+sme2" +#pragma GCC target "+nothing+sve2+sve-b16b16+sme2" #ifndef __ARM_FEATURE_SVE_B16B16 #error Foo #endif @@ -168,7 +168,7 @@ #error Foo #endif -#pragma GCC target "+nothing+sme2p1" +#pragma GCC target "+nothing+sve2+sme2p1" #ifndef __ARM_FEATURE_SME #error Foo #endif diff --git a/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_1.c b/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_1.c index 2ac0c37..acd2e11 100644 --- a/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_1.c +++ b/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_1.c @@ -1,4 +1,4 @@ -/* { dg-do-compile } */ +/* { dg-do compile } */ /* { dg-options "-O2 --save-temps -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" "" } } */ @@ -33,4 +33,4 @@ #define UMAX UCHAR_MAX #define UMIN 0 -#include "saturating_arithmetic.inc"
\ No newline at end of file +#include "saturating_arithmetic.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_2.c b/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_2.c index 2a55aa9..86c88f8 100644 --- a/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_2.c +++ b/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_2.c @@ -1,4 +1,4 @@ -/* { dg-do-compile } */ +/* { dg-do compile } */ /* { dg-options "-O2 --save-temps -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" "" } } */ @@ -33,4 +33,4 @@ #define UMAX USHRT_MAX #define UMIN 0 -#include "saturating_arithmetic.inc"
\ No newline at end of file +#include "saturating_arithmetic.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect.inc b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect.inc index 1fadfd5..1fadfd5 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect.inc +++ b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect.inc diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_1.c b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_1.c index 2b72be7..2b72be7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_1.c diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_2.c b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_2.c index 0640361..0640361 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_2.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_2.c diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_3.c b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_3.c index ea6e0c7..ea6e0c7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_3.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_3.c diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_4.c b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_4.c index 0139063..0139063 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_4.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/saturating_arithmetic_autovect_4.c diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c index 976d5af..7150d37 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c index 5cc8a4c..2823264 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c index aa7633b..52f2c09 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_int_opt_single_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_int_opt_single_1.c index 01cd88f..0e88c14 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_int_opt_single_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_int_opt_single_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint16_t s16, svint8_t s8, svuint8_t u8, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_1.c index 937d992..2c60d50 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint16_t s16, svuint16_t u16, svint32_t s32, svuint32_t u32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_2.c index 126a764..dd90ebc 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_2.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint16_t s16, svuint16_t u16, svint32_t s32, svuint32_t u32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_3.c index 17bed0c..f53cc55 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_3.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint16_t s16, svuint16_t u16, svint32_t s32, svuint32_t u32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_4.c index d2a67c6..83c659d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_4.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svint8_t s8, svuint8_t u8, svint16_t s16, svuint16_t u16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_1.c index 8307a28..a361f7f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint16_t s16, svint32_t s32, svuint32_t u32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_2.c index 181f509..959e222 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_2.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint16_t s16, svint32_t s32, svuint32_t u32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_3.c index 8c8414e..9cc42c0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_3.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2+nosme-i16i64") +#pragma GCC target ("+sve2+sme2+nosme-i16i64") void f1 (svint32x2_t s32x2, svuint32x2_t u32x2, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_uint_opt_single_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_uint_opt_single_1.c index b00c043..b289c9c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_uint_opt_single_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_uint_opt_single_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svuint16_t u16, svint8_t s8, svuint8_t u8, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c index 600b7fc..4f8ebf8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svbool_t pg, svcount_t pn, svuint8_t u8, svint16_t s16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c index 07e22d2..958c40a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svcount_t pn, svfloat16_t f16, svint16_t s16, svfloat32_t f32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c index 47077f7..4a4222c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c @@ -3,7 +3,7 @@ #include <arm_sve.h> #include <stdbool.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" enum signed_enum { SA = -1, SB }; enum unsigned_enum { UA, UB }; diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_int_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_int_lane_1.c index ca2a039..aed92b5 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_int_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_int_lane_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint8_t s8, svuint8_t u8, svint16_t s16, svuint16_t u16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_1.c index e37d24a..bb40868 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint8_t s8, svuint8_t u8, svint16_t s16, svuint16_t u16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_2.c index 7af3c6f..7d57bd1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_lane_2.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint8_t s8, svuint8_t u8, svint16_t s16, svuint16_t u16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_uint_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_uint_lane_1.c index 2efa2eb..cba11a4 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_uint_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_za_slice_uint_lane_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint8_t s8, svuint8_t u8, svint16_t s16, svuint16_t u16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c index ab5602f..685d070 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svboolx2_t pgx2, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c index 7ad4ca8..ba0096b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c @@ -3,7 +3,7 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" struct s { signed char x; }; diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_1.c index 6bdd3c0..c01710f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_1.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target ("arch=armv8.2-a+ssve-fp8fma") +#pragma GCC target ("arch=armv8.2-a+sve2+ssve-fp8fma") void f1 (svfloat16_t f16, svmfloat8_t f8, fpm_t fpm, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_group_selection_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_group_selection_1.c index f6fce2f..fecaf98 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_group_selection_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_group_selection_1.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target ("arch=armv8.2-a+ssve-fp8fma+ssve-fp8dot4+ssve-fp8dot2") +#pragma GCC target ("arch=armv8.2-a+sve2+ssve-fp8fma+ssve-fp8dot4+ssve-fp8dot2") void f1 (svfloat16_t f16, svmfloat8_t f8, fpm_t fpm, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c index b8968c8..5579e0d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svbool_t pg, svint8_t s8, svuint8_t u8, svint16_t s16, svuint16_t u16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c index 85f8b45..e14ec71 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c @@ -1,6 +1,6 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void test (svbool_t pg, float f, svint8_t s8, svfloat32_t f32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrow_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrow_1.c index d312e85..e93cc64 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrow_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrow_1.c @@ -1,6 +1,6 @@ #include <arm_sve.h> -#pragma GCC target "+sme2+fp8" +#pragma GCC target "+sve2+sme2+fp8" void test (svfloat16x2_t f16x2, svbfloat16x2_t bf16x2, svfloat32x2_t f32x2, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrowt_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrowt_1.c index ab97eef..da828f0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrowt_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_narrowt_1.c @@ -1,6 +1,6 @@ #include <arm_sve.h> -#pragma GCC target "+sme2+fp8" +#pragma GCC target "+sve2+sme2+fp8" void test (svmfloat8_t f8, svfloat32x2_t f32x2, fpm_t fpm0, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_za_slice_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_za_slice_1.c index e02fe54..c3052a0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_za_slice_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_za_slice_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svbool_t pg, svint32_t s32, svint16x2_t s16x2, svint32x2_t s32x2, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c index f478945..e9656bc 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c @@ -1,6 +1,6 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void test (svfloat32_t f32, svfloat32x2_t f32x2, svfloat32x3_t f32x3, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_1.c index 3a45b58..95ead96 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svint8_t s8, svint8x2_t s8x2, svint8x3_t s8x3, svint8x4_t s8x4, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_slice_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_slice_1.c index dedd4b1..dae8892 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_slice_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/write_za_slice_1.c @@ -2,7 +2,7 @@ #include <arm_sme.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svint8_t s8, svint8x2_t s8x2, svint8x3_t s8x3, svint8x4_t s8x4, diff --git a/gcc/testsuite/gcc.target/aarch64/vls_sve_vec_dup_1.c b/gcc/testsuite/gcc.target/aarch64/vls_sve_vec_dup_1.c new file mode 100644 index 0000000..ada0d4f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vls_sve_vec_dup_1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=armv8.2-a+sve -msve-vector-bits=128" } */ + +float fasten_main_etot_0; +void fasten_main() { + for (int l = 0; l < 2;) { + int phphb_nz; + for (; l < 32; l++) { + float dslv_e = l && phphb_nz; + fasten_main_etot_0 += dslv_e; + } + } +} + +/* { dg-final { scan-assembler-not {bfi\tw\[0-9\]+} } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr-safe-partial.c b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr-safe-partial.c new file mode 100644 index 0000000..15dc1b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr-safe-partial.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memclr-a2-o1-c9-ptr.c" + +/* Expect assembly such as: + + stb $31,1($16) + stw $31,2($16) + stw $31,4($16) + stw $31,6($16) + stw $31,8($16) + + that is with a byte store at offset 1, followed by word stores at + offsets 2, 4, 6, and 8. */ + +/* { dg-final { scan-assembler-times "\\sstb\\s\\\$31,1\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$31,2\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$31,4\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$31,6\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$31,8\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c index 3f7edc8..0ff1049 100644 --- a/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c +++ b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mbwx" } */ +/* { dg-options "-mbwx -mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ typedef unsigned int __attribute__ ((mode (QI))) int08_t; diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial-bwx.c new file mode 100644 index 0000000..1626261 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial-bwx.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-msafe-partial -mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memcpy-di-unaligned-dst.c" + +/* { dg-final { scan-assembler-times "\\sldq\\s" 7 } } */ +/* { dg-final { scan-assembler-times "\\sstb\\s" 16 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 6 } } */ +/* { dg-final { scan-assembler-not "\\sldq_l\\s" } } */ +/* { dg-final { scan-assembler-not "\\sldq_u\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstq\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstq_c\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial.c b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial.c new file mode 100644 index 0000000..869fdf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-msafe-partial -mno-bwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memcpy-di-unaligned-dst.c" + +/* { dg-final { scan-assembler-times "\\sldq\\s" 7 } } */ +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 6 } } */ +/* { dg-final { scan-assembler-not "\\sldq_u\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstq\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst.c b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst.c index 5e9b5c3..373e2aa 100644 --- a/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst.c +++ b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "" } */ +/* { dg-options "-mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ unsigned long unaligned_src_di[9] = { [0 ... 8] = 0xfefdfcfbfaf9f8f7 }; diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial-bwx.c new file mode 100644 index 0000000..2464005 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial-bwx.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-msafe-partial -mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memcpy-si-unaligned-dst.c" + +/* { dg-final { scan-assembler-times "\\sldl\\s" 15 } } */ +/* { dg-final { scan-assembler-times "\\sstb\\s" 20 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 6 } } */ +/* { dg-final { scan-assembler-not "\\sldq_l\\s" } } */ +/* { dg-final { scan-assembler-not "\\sldq_u\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstl\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstq_c\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial.c b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial.c new file mode 100644 index 0000000..6c9f877 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-msafe-partial -mno-bwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memcpy-si-unaligned-dst.c" + +/* { dg-final { scan-assembler-times "\\sldl\\s" 15 } } */ +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 4 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 4 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 6 } } */ +/* { dg-final { scan-assembler-not "\\sldq_u\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstl\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst.c b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst.c index a2efade..aef4e59 100644 --- a/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst.c +++ b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "" } */ +/* { dg-options "-mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ unsigned int unaligned_src_si[17] = { [0 ... 16] = 0xfefdfcfb }; diff --git a/gcc/testsuite/gcc.target/alpha/stb-bwa.c b/gcc/testsuite/gcc.target/alpha/stb-bwa.c new file mode 100644 index 0000000..d7a45db --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stb-bwa.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stb (char *p, char v) +{ + *p = v; +} + +/* Expect assembly such as: + + bic $16,7,$2 + insbl $17,$16,$17 +$L2: + ldq_l $1,0($2) + mskbl $1,$16,$1 + bis $17,$1,$1 + stq_c $1,0($2) + beq $1,$L2 + + with address masking. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sinsbl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskbl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stb-bwx.c b/gcc/testsuite/gcc.target/alpha/stb-bwx.c new file mode 100644 index 0000000..556397b --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stb-bwx.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stb (char *p, char v) +{ + *p = v; +} + +/* Expect assembly such as: + + stb $17,0($16) + */ + +/* { dg-final { scan-assembler-times "\\sstb\\s\\\$17,0\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stb.c b/gcc/testsuite/gcc.target/alpha/stb.c new file mode 100644 index 0000000..4953bc4 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stb.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -mno-safe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stb (char *p, char v) +{ + *p = v; +} + +/* Expect assembly such as: + + insbl $17,$16,$17 + ldq_u $1,0($16) + mskbl $1,$16,$1 + bis $17,$1,$17 + stq_u $17,0($16) + + without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldq_u\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sinsbl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskbl\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stba-bwa.c b/gcc/testsuite/gcc.target/alpha/stba-bwa.c new file mode 100644 index 0000000..07cf954 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stba-bwa.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + char c; + } +char_a; + +void +stba (char_a *p, char v) +{ + p->c = v; +} + +/* Expect assembly such as: + + and $17,0xff,$17 +$L2: + ldl_l $1,0($16) + bic $1,255,$1 + bis $17,$1,$1 + stl_c $1,0($16) + beq $1,$L2 + + without any INSBL or MSKBL instructions and without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldl_l\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl_c\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sand\\s\\\$\[0-9\]+,0xff,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sbic\\s\\\$\[0-9\]+,255,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:insbl|mskbl)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stba-bwx.c b/gcc/testsuite/gcc.target/alpha/stba-bwx.c new file mode 100644 index 0000000..08b51b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stba-bwx.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + char c; + } +char_a; + +void +stba (char_a *p, char v) +{ + p->c = v; +} + +/* Expect assembly such as: + + stb $17,0($16) + */ + +/* { dg-final { scan-assembler-times "\\sstb\\s\\\$17,0\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stba.c b/gcc/testsuite/gcc.target/alpha/stba.c new file mode 100644 index 0000000..fe7856c --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stba.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -mno-safe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + char c; + } +char_a; + +void +stba (char_a *p, char v) +{ + p->c = v; +} + +/* Expect assembly such as: + + and $17,0xff,$17 + ldl $1,0($16) + bic $1,255,$1 + bis $17,$1,$17 + stl $17,0($16) + + without any INSBL or MSKBL instructions and without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sand\\s\\\$\[0-9\]+,0xff,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sbic\\s\\\$\[0-9\]+,255,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:insbl|mskbl)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial-bwx.c new file mode 100644 index 0000000..70df631 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial-bwx.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stlx0.c" + +/* Expect assembly such as: + + stb $31,0($16) + stb $31,1($16) + stb $31,2($16) + stb $31,3($16) + + without any LDQ_U or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sstb\\s" 4 } } */ +/* { dg-final { scan-assembler-not "\\s(?:ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial.c b/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial.c new file mode 100644 index 0000000..dc3e86d --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stlx0.c" + +/* Expect assembly such as: + + lda $2,3($16) + bic $2,7,$2 +$L2: + ldq_l $1,0($2) + msklh $1,$16,$1 + stq_c $1,0($2) + beq $1,$L2 + bic $16,7,$2 +$L3: + ldq_l $1,0($2) + mskll $1,$16,$1 + stq_c $1,0($2) + beq $1,$L3 + + without any INSLH, INSLL, BIS, LDQ_U, or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\smsklh\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskll\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:bis|inslh|insll|ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stlx0.c b/gcc/testsuite/gcc.target/alpha/stlx0.c index 876eceb..3b340bc 100644 --- a/gcc/testsuite/gcc.target/alpha/stlx0.c +++ b/gcc/testsuite/gcc.target/alpha/stlx0.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "" } */ +/* { dg-options "-mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ typedef struct { int v __attribute__ ((packed)); } intx; diff --git a/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial-bwx.c new file mode 100644 index 0000000..62f6c78 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial-bwx.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stqx0.c" + +/* Expect assembly such as: + + stb $31,0($16) + stb $31,1($16) + stb $31,2($16) + stb $31,3($16) + stb $31,4($16) + stb $31,5($16) + stb $31,6($16) + stb $31,7($16) + + without any LDQ_U or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sstb\\s" 8 } } */ +/* { dg-final { scan-assembler-not "\\s(?:ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial.c b/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial.c new file mode 100644 index 0000000..7aa9e80 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stqx0.c" + +/* Expect assembly such as: + + lda $2,7($16) + bic $2,7,$2 +$L2: + ldq_l $1,0($2) + mskqh $1,$16,$1 + stq_c $1,0($2) + beq $1,$L2 + bic $16,7,$2 +$L3: + ldq_l $1,0($2) + mskql $1,$16,$1 + stq_c $1,0($2) + beq $1,$L3 + + without any INSLH, INSLL, BIS, LDQ_U, or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\smskqh\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskql\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:bis|insqh|insql|ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stqx0.c b/gcc/testsuite/gcc.target/alpha/stqx0.c index 042cdf0..80261a8 100644 --- a/gcc/testsuite/gcc.target/alpha/stqx0.c +++ b/gcc/testsuite/gcc.target/alpha/stqx0.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "" } */ +/* { dg-options "-mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ typedef struct { long v __attribute__ ((packed)); } longx; diff --git a/gcc/testsuite/gcc.target/alpha/stw-bwa.c b/gcc/testsuite/gcc.target/alpha/stw-bwa.c new file mode 100644 index 0000000..8b764b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stw-bwa.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stw (short *p, short v) +{ + *p = v; +} + +/* Expect assembly such as: + + bic $16,7,$2 + inswl $17,$16,$17 +$L2: + ldq_l $1,0($2) + mskwl $1,$16,$1 + bis $17,$1,$1 + stq_c $1,0($2) + beq $1,$L2 + + with address masking. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sinswl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskwl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stw-bwx.c b/gcc/testsuite/gcc.target/alpha/stw-bwx.c new file mode 100644 index 0000000..b4f18ad --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stw-bwx.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stw (short *p, short v) +{ + *p = v; +} + +/* Expect assembly such as: + + stw $17,0($16) + */ + +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$17,0\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stw.c b/gcc/testsuite/gcc.target/alpha/stw.c new file mode 100644 index 0000000..655fdd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stw.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -mno-safe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stw (short *p, short v) +{ + *p = v; +} + +/* Expect assembly such as: + + inswl $17,$16,$17 + ldq_u $1,0($16) + mskwl $1,$16,$1 + bis $17,$1,$17 + stq_u $17,0($16) + + without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldq_u\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sinswl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskwl\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwa-bwa.c b/gcc/testsuite/gcc.target/alpha/stwa-bwa.c new file mode 100644 index 0000000..9ee226e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwa-bwa.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + short c; + } +short_a; + +void +stwa (short_a *p, short v) +{ + p->c = v; +} + +/* Expect assembly such as: + + zapnot $17,3,$17 +$L2: + ldl_l $1,0($16) + zapnot $1,252,$1 + bis $17,$1,$1 + stl_c $1,0($16) + beq $1,$L2 + + without any INSWL or MSKWL instructions and without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldl_l\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl_c\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\szapnot\\s\\\$\[0-9\]+,3,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\szapnot\\s\\\$\[0-9\]+,252,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:inswl|mskwl)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwa-bwx.c b/gcc/testsuite/gcc.target/alpha/stwa-bwx.c new file mode 100644 index 0000000..6331d62 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwa-bwx.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + short c; + } +short_a; + +void +stwa (short_a *p, short v) +{ + p->c = v; +} + +/* Expect assembly such as: + + stw $17,0($16) + */ + +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$17,0\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwa.c b/gcc/testsuite/gcc.target/alpha/stwa.c new file mode 100644 index 0000000..6b273cf --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwa.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -mno-safe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + short c; + } +short_a; + +void +stwa (short_a *p, short v) +{ + p->c = v; +} + +/* Expect assembly such as: + + zapnot $17,3,$17 + ldl $1,0($16) + zapnot $1,252,$1 + bis $17,$1,$17 + stl $17,0($16) + + without any INSWL or MSKWL instructions and without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\szapnot\\s\\\$\[0-9\]+,3,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\szapnot\\s\\\$\[0-9\]+,252,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:inswl|mskwl)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwx0-bwx.c b/gcc/testsuite/gcc.target/alpha/stwx0-bwx.c index bba31df..6256f82 100644 --- a/gcc/testsuite/gcc.target/alpha/stwx0-bwx.c +++ b/gcc/testsuite/gcc.target/alpha/stwx0-bwx.c @@ -1,19 +1,15 @@ /* { dg-do compile } */ -/* { dg-options "-mbwx" } */ +/* { dg-options "-mbwx -mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ -typedef struct { short v __attribute__ ((packed)); } shortx; - -void -stwx0 (shortx *p) -{ - p->v = 0; -} +#include "stwx0.c" /* Expect assembly such as: stb $31,0($16) stb $31,1($16) - */ + + without any LDQ_U or STQ_U instructions. */ /* { dg-final { scan-assembler-times "\\sstb\\s\\\$31," 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial-bwx.c new file mode 100644 index 0000000..031d4c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial-bwx.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stwx0.c" + +/* Expect assembly such as: + + stb $31,0($16) + stb $31,1($16) + + without any LDQ_U or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sstb\\s\\\$31," 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial.c b/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial.c new file mode 100644 index 0000000..3d0eedd --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stwx0.c" + +/* Expect assembly such as: + + lda $2,1($16) + bic $2,7,$2 +$L2: + ldq_l $1,0($2) + mskwh $1,$16,$1 + stq_c $1,0($2) + beq $1,$L2 + bic $16,7,$2 +$L3: + ldq_l $1,0($2) + mskwl $1,$16,$1 + stq_c $1,0($2) + beq $1,$L3 + + without any INSWH, INSWL, BIS, LDQ_U, or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\smskwh\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskwl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:bis|inswh|inswl|ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwx0.c b/gcc/testsuite/gcc.target/alpha/stwx0.c index d60d33f..ad4e716 100644 --- a/gcc/testsuite/gcc.target/alpha/stwx0.c +++ b/gcc/testsuite/gcc.target/alpha/stwx0.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mno-bwx" } */ +/* { dg-options "-mno-bwx -mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ typedef struct { short v __attribute__ ((packed)); } shortx; diff --git a/gcc/testsuite/gcc.target/arc/taux-1.c b/gcc/testsuite/gcc.target/arc/taux-1.c index a2b7778..41b0fc4 100644 --- a/gcc/testsuite/gcc.target/arc/taux-1.c +++ b/gcc/testsuite/gcc.target/arc/taux-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 */ +/* { dg-options "-O1" } */ #define __aux() __attribute__((aux)) diff --git a/gcc/testsuite/gcc.target/arc/taux-2.c b/gcc/testsuite/gcc.target/arc/taux-2.c index 5644bcd..3e57ac8 100644 --- a/gcc/testsuite/gcc.target/arc/taux-2.c +++ b/gcc/testsuite/gcc.target/arc/taux-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 */ +/* { dg-options "-O1" } */ #define __aux(r) __attribute__((aux(r))) static volatile __aux(0x1000) int var; diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-17.c b/gcc/testsuite/gcc.target/arm/cmse/cmse-17.c index a2cce09..c5be810 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/cmse-17.c +++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mcmse"} */ +/* { dg-options "-mcmse" } */ #include <arm_cmse.h> diff --git a/gcc/testsuite/gcc.target/arm/fmaxmin-2.c b/gcc/testsuite/gcc.target/arm/fmaxmin-2.c new file mode 100644 index 0000000..a9990e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/fmaxmin-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_hard_ok } */ +/* { dg-options "-O2 -fno-inline" } */ +/* { dg-add-options arm_arch_v8a_hard } */ + +#include "fmaxmin.x" + +/* { dg-final { scan-assembler-times "vmaxnm.f32\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "vminnm.f32\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ + +/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/fmaxmin.c b/gcc/testsuite/gcc.target/arm/fmaxmin.c index 5a6fb80..7f30c12 100644 --- a/gcc/testsuite/gcc.target/arm/fmaxmin.c +++ b/gcc/testsuite/gcc.target/arm/fmaxmin.c @@ -1,13 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_neon_hw } */ -/* { dg-options "-O2 -fno-inline -march=armv8-a -save-temps" } */ +/* { dg-options "-O2 -fno-inline" } */ /* { dg-add-options arm_v8_neon } */ #include "fmaxmin.x" - -/* { dg-final { scan-assembler-times "vmaxnm.f32\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ -/* { dg-final { scan-assembler-times "vminnm.f32\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ - -/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ -/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ - diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c index 447a8ec..63d57d4 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv4" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v4_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v4 } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c index 28fd2f7..d33beef 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv4t" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v4t_arm_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v4t } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c index 78878f7..8f43801 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv4t" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v4t_thumb_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v4t } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c index 8191299..cc139f1 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5t" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v5t_arm_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v5t } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c index b25d17d..1432018 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5t" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v5t_thumb_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v5t } */ @@ -14,4 +12,9 @@ #define NEED_ARM_ARCH_ISA_THUMB #define VALUE_ARM_ARCH_ISA_THUMB 1 +/* Not in the Thumb ISA, but does exist in Arm state. A call to the library + function should result in using that instruction in Arm state. */ +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + #include "ftest-support.h" diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c index e0c0d5c..2917ee6 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5te" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v5te_arm_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v5te } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c index 27a64a2..768dbaa 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5te" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v5te_thumb_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v5te } */ @@ -14,4 +12,9 @@ #define NEED_ARM_ARCH_ISA_THUMB #define VALUE_ARM_ARCH_ISA_THUMB 1 +/* Not in the Thumb ISA, but does exist in Arm state. A call to the library + function should result in using that instruction in Arm state. */ +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + #include "ftest-support.h" diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c index 5d447c3..648acb1 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v6_arm_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v6 } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c index 15a6d75..02360ee 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v6_thumb_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v6 } */ @@ -14,4 +12,9 @@ #define NEED_ARM_ARCH_ISA_THUMB #define VALUE_ARM_ARCH_ISA_THUMB 1 +/* Not in the Thumb ISA, but does exist in Arm state. A call to the library + function should result in using that instruction in Arm state. */ +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + #include "ftest-support.h" diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c index 0656e8f..ccc4e03 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6k" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v6k_arm_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v6k } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c index b3b6ecf..2c5490f 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6k" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v6k_thumb_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v6k } */ @@ -14,4 +12,9 @@ #define NEED_ARM_ARCH_ISA_THUMB #define VALUE_ARM_ARCH_ISA_THUMB 1 +/* Not in the Thumb ISA, but does exist in Arm state. A call to the library + function should result in using that instruction in Arm state. */ +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + #include "ftest-support.h" diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c index 27f71be..46cf957 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6-m" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v6m_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v6m } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c index 259d2b5..d24b08c 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6t2" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v6t2_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v6t2 } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c index e624ec5..27d2ccb 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6t2" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v6t2_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v6t2 } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c index 6e3a966..7de37ee 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6z" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm_arch_v6z_arm_ok } */ /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v6z } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c index 23a4fcd..d3e0393 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c @@ -1,6 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6z" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ /* { dg-require-effective-target arm_arch_v6z_thumb_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v6z } */ @@ -14,4 +12,9 @@ #define NEED_ARM_ARCH_ISA_THUMB #define VALUE_ARM_ARCH_ISA_THUMB 1 +/* Not in the Thumb ISA, but does exist in Arm state. A call to the library + function should result in using that instruction in Arm state. */ +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + #include "ftest-support.h" diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c index 43f52fe..ec70bc5 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-a" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v7a_ok } /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v7a } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c index 717f44c..d0ae786 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-a" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v7a_ok } /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v7a } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c index 688d766..353dbadc 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7e-m" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-require-effective-target arm_arch_v7em_ok } */ /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v7em } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c index 24b93ea..2809050 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-r" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v7r_ok } /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v7r } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c index a7c3772..7ee7981 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-r" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v7r_ok } /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v7r } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c index 72c4c1f..e6e6862 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7ve" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v7ve_ok } /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v7ve } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c index 772405b..5a2ffd8 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7ve" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v7ve_ok } /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v7ve } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c index feab5ee..40d2437 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv8-a" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v8a_ok } /* { dg-options "-marm" } */ /* { dg-add-options arm_arch_v8a } */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c index 28d54bf..9f13069 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c +++ b/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv8-a" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ -/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } { "-mpure-code" } } */ +/* { dg-require-effective-target arm_arch_v8a_ok } /* { dg-options "-mthumb" } */ /* { dg-add-options arm_arch_v8a } */ diff --git a/gcc/testsuite/gcc.target/arm/lto/pr96939_0.c b/gcc/testsuite/gcc.target/arm/lto/pr96939_0.c index 21d2c1d..8dfbc06 100644 --- a/gcc/testsuite/gcc.target/arm/lto/pr96939_0.c +++ b/gcc/testsuite/gcc.target/arm/lto/pr96939_0.c @@ -1,8 +1,7 @@ /* PR target/96939 */ /* { dg-lto-do link } */ /* { dg-require-effective-target arm_arch_v8a_link } */ -/* { dg-options "-mcpu=unset -march=armv8-a+simd -mfpu=auto" } */ -/* { dg-lto-options { { -flto -O2 } } } */ +/* { dg-lto-options { { -flto -O2 -mcpu=unset -march=armv8-a+simd -mfpu=auto} } } */ extern unsigned crc (unsigned, const void *); typedef unsigned (*fnptr) (unsigned, const void *); diff --git a/gcc/testsuite/gcc.target/arm/mtp_1.c b/gcc/testsuite/gcc.target/arm/mtp_1.c index 678d27d..f78ceb8 100644 --- a/gcc/testsuite/gcc.target/arm/mtp_1.c +++ b/gcc/testsuite/gcc.target/arm/mtp_1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target tls_native } */ +/* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mtp=cp15" } */ #include "mtp.c" diff --git a/gcc/testsuite/gcc.target/arm/mtp_2.c b/gcc/testsuite/gcc.target/arm/mtp_2.c index bcb308f..1368fe4 100644 --- a/gcc/testsuite/gcc.target/arm/mtp_2.c +++ b/gcc/testsuite/gcc.target/arm/mtp_2.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target tls_native } */ +/* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mtp=tpidrprw" } */ #include "mtp.c" diff --git a/gcc/testsuite/gcc.target/arm/mtp_3.c b/gcc/testsuite/gcc.target/arm/mtp_3.c index 7d5cea3..2ef2e95 100644 --- a/gcc/testsuite/gcc.target/arm/mtp_3.c +++ b/gcc/testsuite/gcc.target/arm/mtp_3.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target tls_native } */ +/* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mtp=tpidruro" } */ #include "mtp.c" diff --git a/gcc/testsuite/gcc.target/arm/mtp_4.c b/gcc/testsuite/gcc.target/arm/mtp_4.c index 068078d..121fc83 100644 --- a/gcc/testsuite/gcc.target/arm/mtp_4.c +++ b/gcc/testsuite/gcc.target/arm/mtp_4.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target tls_native } */ +/* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mtp=tpidrurw" } */ #include "mtp.c" diff --git a/gcc/testsuite/gcc.target/arm/mve/mve.exp b/gcc/testsuite/gcc.target/arm/mve/mve.exp index a5d8511..9dc56c9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/mve.exp +++ b/gcc/testsuite/gcc.target/arm/mve/mve.exp @@ -35,6 +35,7 @@ global dg_runtest_extra_prunes set dg_runtest_extra_prunes "" lappend dg_runtest_extra_prunes "warning: switch '-m(cpu|arch)=.*' conflicts with switch '-m(cpu|arch)=.*'" +set saved-dg-do-what-default ${dg-do-what-default} set dg-do-what-default "assemble" # Initialize `dg'. @@ -53,6 +54,8 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/general-c/*.\[cCS\]]] \ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ "" $DEFAULT_CFLAGS +set dg-do-what-default ${saved-dg-do-what-default} + # All done. set dg_runtest_extra_prunes "" dg-finish diff --git a/gcc/testsuite/gcc.target/arm/pr42575.c b/gcc/testsuite/gcc.target/arm/pr42575.c index 1998e32..3906c77 100644 --- a/gcc/testsuite/gcc.target/arm/pr42575.c +++ b/gcc/testsuite/gcc.target/arm/pr42575.c @@ -1,4 +1,5 @@ /* { dg-options "-O2" } */ +/* { dg-skip-if "Thumb1 lacks UMULL" { arm_thumb1 } } */ /* Make sure RA does good job allocating registers and avoids unnecessary moves. */ /* { dg-final { scan-assembler-not "mov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr65647.c b/gcc/testsuite/gcc.target/arm/pr65647.c index e0c534b..663157c 100644 --- a/gcc/testsuite/gcc.target/arm/pr65647.c +++ b/gcc/testsuite/gcc.target/arm/pr65647.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_arch_v6m_ok } */ -/* { dg-options "-O3 -w -fpermissive" } */ +/* { dg-options "-O3 -w -fpermissive -std=gnu17" } */ /* { dg-add-options arm_arch_v6m } */ a, b, c, e, g = &e, h, i = 7, l = 1, m, n, o, q = &m, r, s = &r, u, w = 9, x, diff --git a/gcc/testsuite/gcc.target/arm/short-vfp-1.c b/gcc/testsuite/gcc.target/arm/short-vfp-1.c index 3ca1ffc..f6866c4 100644 --- a/gcc/testsuite/gcc.target/arm/short-vfp-1.c +++ b/gcc/testsuite/gcc.target/arm/short-vfp-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target arm_vfp_ok } +/* { dg-require-effective-target arm_vfp_ok } */ /* { dg-add-options arm_vfp } */ int @@ -38,8 +38,8 @@ test_sihi (short x) return (int)x; } -/* {dg-final { scan-assembler-times {vcvt\.s32\.f32\ts[0-9]+,s[0-9]+} 2 }} */ -/* {dg-final { scan-assembler-times {vcvt\.f32\.s32\ts[0-9]+,s[0-9]+} 2 }} */ -/* {dg-final { scan-assembler-times {vmov\tr[0-9]+,s[0-9]+} 2 }} */ -/* {dg-final { scan-assembler-times {vmov\ts[0-9]+,r[0-9]+} 2 }} */ -/* {dg-final { scan-assembler-times {sxth\tr[0-9]+,r[0-9]+} 2 }} */ +/* { dg-final { scan-assembler-times {vcvt\.s32\.f32\ts[0-9]+, s[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vcvt\.f32\.s32\ts[0-9]+, s[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vmov\tr[0-9]+, s[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vmov\ts[0-9]+, r[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {sxth\tr[0-9]+, r[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c index 3f074e3..1c79f3b 100644 --- a/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c +++ b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c @@ -23,4 +23,4 @@ int main () } /* There should be no 'unaligned' comments. */ -/* { dg-final { scan-assembler-not "unaligned" } } */ +/* { dg-final { scan-assembler-not "@ unaligned" } } */ diff --git a/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c b/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c index 4dc0edd..045f143 100644 --- a/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c +++ b/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c @@ -18,7 +18,7 @@ int b[N] = {0}; ** vmov r[0-9]+, s[0-9]+ @ int ** ( ** cmp r[0-9]+, #0 -** bne \.L[0-9]+ +** b(ne|eq) \.L[0-9]+ ** | ** cbn?z r[0-9]+, \.L.+ ** ) @@ -43,7 +43,7 @@ void f1 () ** vmov r[0-9]+, s[0-9]+ @ int ** ( ** cmp r[0-9]+, #0 -** bne \.L[0-9]+ +** b(ne|eq) \.L[0-9]+ ** | ** cbn?z r[0-9]+, \.L.+ ** ) @@ -68,7 +68,7 @@ void f2 () ** vmov r[0-9]+, s[0-9]+ @ int ** ( ** cmp r[0-9]+, #0 -** bne \.L[0-9]+ +** b(ne|eq) \.L[0-9]+ ** | ** cbn?z r[0-9]+, \.L.+ ** ) @@ -94,7 +94,7 @@ void f3 () ** vmov r[0-9]+, s[0-9]+ @ int ** ( ** cmp r[0-9]+, #0 -** bne \.L[0-9]+ +** b(ne|eq) \.L[0-9]+ ** | ** cbn?z r[0-9]+, \.L.+ ** ) @@ -119,7 +119,7 @@ void f4 () ** vmov r[0-9]+, s[0-9]+ @ int ** ( ** cmp r[0-9]+, #0 -** bne \.L[0-9]+ +** b(ne|eq) \.L[0-9]+ ** | ** cbn?z r[0-9]+, \.L.+ ** ) @@ -144,7 +144,7 @@ void f5 () ** vmov r[0-9]+, s[0-9]+ @ int ** ( ** cmp r[0-9]+, #0 -** bne \.L[0-9]+ +** b(ne|eq) \.L[0-9]+ ** | ** cbn?z r[0-9]+, \.L.+ ** ) diff --git a/gcc/testsuite/gcc.target/arm/vect-fmaxmin-2.c b/gcc/testsuite/gcc.target/arm/vect-fmaxmin-2.c new file mode 100644 index 0000000..57b0a3a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vect-fmaxmin-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_hard_ok } */ +/* { dg-options "-O2 -ftree-vectorize -funsafe-math-optimizations -fno-inline -save-temps" } */ +/* { dg-add-options arm_arch_v8a_hard } */ + +#include "fmaxmin.x" + +/* { dg-final { scan-assembler-times "vmaxnm.f32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "vminnm.f32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]+" 1 } } */ + +/* NOTE: There are no double precision vector versions of vmaxnm/vminnm. */ +/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/arm/vect-fmaxmin.c b/gcc/testsuite/gcc.target/arm/vect-fmaxmin.c index ba45c4d..89dc14b 100644 --- a/gcc/testsuite/gcc.target/arm/vect-fmaxmin.c +++ b/gcc/testsuite/gcc.target/arm/vect-fmaxmin.c @@ -1,14 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_neon_hw } */ -/* { dg-options "-O2 -ftree-vectorize -fno-inline -march=armv8-a -save-temps" } */ +/* { dg-options "-O2 -ftree-vectorize -fno-inline -funsafe-math-optimizations" } */ /* { dg-add-options arm_v8_neon } */ #include "fmaxmin.x" - -/* { dg-final { scan-assembler-times "vmaxnm.f32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]+" 1 } } */ -/* { dg-final { scan-assembler-times "vminnm.f32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]+" 1 } } */ - -/* NOTE: There are no double precision vector versions of vmaxnm/vminnm. */ -/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ -/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ - diff --git a/gcc/testsuite/gcc.target/bfin/l2.c b/gcc/testsuite/gcc.target/bfin/l2.c index 56f64cc..2d39c46 100644 --- a/gcc/testsuite/gcc.target/bfin/l2.c +++ b/gcc/testsuite/gcc.target/bfin/l2.c @@ -1,5 +1,5 @@ /* { dg-do run { target bfin-*-linux-uclibc } } */ -/* { dg-bfin-processors bf544 bf547 bf548 bf549 bf561} */ +/* { dg-bfin-processors bf544 bf547 bf548 bf549 bf561 } */ #if defined(__ADSPBF544__) #define L2_START 0xFEB00000 diff --git a/gcc/testsuite/gcc.target/i386/addr-space-1.c b/gcc/testsuite/gcc.target/i386/addr-space-1.c index 1e13147..9a5ce9c 100644 --- a/gcc/testsuite/gcc.target/i386/addr-space-1.c +++ b/gcc/testsuite/gcc.target/i386/addr-space-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile */ +/* { dg-do compile } */ /* { dg-options "-O2" } */ /* { dg-final { scan-assembler "movl\[ \t\]%gs:\\((%eax|%rax)\\), %eax" } } */ diff --git a/gcc/testsuite/gcc.target/i386/apx-nf-pr119539.c b/gcc/testsuite/gcc.target/i386/apx-nf-pr119539.c new file mode 100644 index 0000000..5dfec55 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-nf-pr119539.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mapx-features=nf -march=x86-64 -O2" } */ +/* { dg-final { scan-assembler-times "\{nf\} rol" 2 } } */ + +long int f1 (int x) { return ~(1ULL << (x & 0x3f)); } +long int f2 (char x) { return ~(1ULL << (x & 0x3f)); } diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c index e932362..ff103d0 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c @@ -86,9 +86,9 @@ avx10_2_vcvtbiasph2bf8_test (void) void extern avx10_2_vcvtbiasph2bf8s_test (void) { - x256i = _mm512_cvtbiassph_bf8 (x512i, x512h); - x256i = _mm512_mask_cvtbiassph_bf8 (x256i, m32, x512i, x512h); - x256i = _mm512_maskz_cvtbiassph_bf8 (m32, x512i, x512h); + x256i = _mm512_cvts_biasph_bf8 (x512i, x512h); + x256i = _mm512_mask_cvts_biasph_bf8 (x256i, m32, x512i, x512h); + x256i = _mm512_maskz_cvts_biasph_bf8 (m32, x512i, x512h); } void extern @@ -102,9 +102,9 @@ avx10_2_vcvtbiasph2hf8_test (void) void extern avx10_2_vcvtbiasph2hf8s_test (void) { - x256i = _mm512_cvtbiassph_hf8 (x512i, x512h); - x256i = _mm512_mask_cvtbiassph_hf8 (x256i, m32, x512i, x512h); - x256i = _mm512_maskz_cvtbiassph_hf8 (m32, x512i, x512h); + x256i = _mm512_cvts_biasph_hf8 (x512i, x512h); + x256i = _mm512_mask_cvts_biasph_hf8 (x256i, m32, x512i, x512h); + x256i = _mm512_maskz_cvts_biasph_hf8 (m32, x512i, x512h); } void extern @@ -118,9 +118,9 @@ avx10_2_vcvt2ph2bf8_test (void) void extern avx10_2_vcvt2ph2bf8s_test (void) { - x512i = _mm512_cvts2ph_bf8 (x512h, x512h); - x512i = _mm512_mask_cvts2ph_bf8 (x512i, m64, x512h, x512h); - x512i = _mm512_maskz_cvts2ph_bf8 (m64, x512h, x512h); + x512i = _mm512_cvts_2ph_bf8 (x512h, x512h); + x512i = _mm512_mask_cvts_2ph_bf8 (x512i, m64, x512h, x512h); + x512i = _mm512_maskz_cvts_2ph_bf8 (m64, x512h, x512h); } void extern @@ -134,9 +134,9 @@ avx10_2_vcvt2ph2hf8_test (void) void extern avx10_2_vcvt2ph2hf8s_test (void) { - x512i = _mm512_cvts2ph_hf8 (x512h, x512h); - x512i = _mm512_mask_cvts2ph_hf8 (x512i, m64, x512h, x512h); - x512i = _mm512_maskz_cvts2ph_hf8 (m64, x512h, x512h); + x512i = _mm512_cvts_2ph_hf8 (x512h, x512h); + x512i = _mm512_mask_cvts_2ph_hf8 (x512i, m64, x512h, x512h); + x512i = _mm512_maskz_cvts_2ph_hf8 (m64, x512h, x512h); } void extern @@ -158,9 +158,9 @@ avx10_2_vcvtph2bf8_test (void) void extern avx10_2_vcvtph2bf8s_test (void) { - x256i = _mm512_cvtsph_bf8 (x512h); - x256i = _mm512_mask_cvtsph_bf8 (x256i, m32, x512h); - x256i = _mm512_maskz_cvtsph_bf8 (m32, x512h); + x256i = _mm512_cvts_ph_bf8 (x512h); + x256i = _mm512_mask_cvts_ph_bf8 (x256i, m32, x512h); + x256i = _mm512_maskz_cvts_ph_bf8 (m32, x512h); } void extern @@ -174,9 +174,9 @@ avx10_2_vcvtph2hf8_test (void) void extern avx10_2_vcvtph2hf8s_test (void) { - x256i = _mm512_cvtsph_hf8 (x512h); - x256i = _mm512_mask_cvtsph_hf8 (x256i, m32, x512h); - x256i = _mm512_maskz_cvtsph_hf8 (m32, x512h); + x256i = _mm512_cvts_ph_hf8 (x512h); + x256i = _mm512_mask_cvts_ph_hf8 (x256i, m32, x512h); + x256i = _mm512_maskz_cvts_ph_hf8 (m32, x512h); } void extern diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2bf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2bf8s-2.c index aa8545c..33d9c0c 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2bf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2bf8s-2.c @@ -64,16 +64,16 @@ TEST (void) CALC(res_ref, src1.a, src2.a); - res1.x = INTRINSIC (_cvts2ph_bf8) (src1.x, src2.x); + res1.x = INTRINSIC (_cvts_2ph_bf8) (src1.x, src2.x); if (UNION_CHECK (AVX512F_LEN, i_b) (res1, res_ref)) abort (); - res2.x = INTRINSIC (_mask_cvts2ph_bf8) (res2.x, mask, src1.x, src2.x); + res2.x = INTRINSIC (_mask_cvts_2ph_bf8) (res2.x, mask, src1.x, src2.x); MASK_MERGE (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN, i_b) (res2, res_ref)) abort (); - res3.x = INTRINSIC (_maskz_cvts2ph_bf8) (mask, src1.x, src2.x); + res3.x = INTRINSIC (_maskz_cvts_2ph_bf8) (mask, src1.x, src2.x); MASK_ZERO (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN, i_b) (res3, res_ref)) abort (); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2hf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2hf8s-2.c index afed1d1..b9fdfac 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2hf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ph2hf8s-2.c @@ -64,16 +64,16 @@ TEST (void) CALC(res_ref, src1.a, src2.a); - res1.x = INTRINSIC (_cvts2ph_hf8) (src1.x, src2.x); + res1.x = INTRINSIC (_cvts_2ph_hf8) (src1.x, src2.x); if (UNION_CHECK (AVX512F_LEN, i_b) (res1, res_ref)) abort (); - res2.x = INTRINSIC (_mask_cvts2ph_hf8) (res2.x, mask, src1.x, src2.x); + res2.x = INTRINSIC (_mask_cvts_2ph_hf8) (res2.x, mask, src1.x, src2.x); MASK_MERGE (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN, i_b) (res2, res_ref)) abort (); - res3.x = INTRINSIC (_maskz_cvts2ph_hf8) (mask, src1.x, src2.x); + res3.x = INTRINSIC (_maskz_cvts_2ph_hf8) (mask, src1.x, src2.x); MASK_ZERO (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN, i_b) (res3, res_ref)) abort (); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8s-2.c index 88ced07..93de7ea 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8s-2.c @@ -61,16 +61,16 @@ TEST (void) CALC (res_ref, src1.a, src2.a); - res1.x = INTRINSIC (_cvtbiassph_bf8) (src1.x, src2.x); + res1.x = INTRINSIC (_cvts_biasph_bf8) (src1.x, src2.x); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res1, res_ref)) abort (); - res2.x = INTRINSIC (_mask_cvtbiassph_bf8) (res2.x, mask, src1.x, src2.x); + res2.x = INTRINSIC (_mask_cvts_biasph_bf8) (res2.x, mask, src1.x, src2.x); MASK_MERGE (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res2, res_ref)) abort (); - res3.x = INTRINSIC (_maskz_cvtbiassph_bf8) (mask, src1.x, src2.x); + res3.x = INTRINSIC (_maskz_cvts_biasph_bf8) (mask, src1.x, src2.x); MASK_ZERO (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res3, res_ref)) abort (); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2hf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2hf8s-2.c index 1a8b4d6..0333f08 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2hf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2hf8s-2.c @@ -60,16 +60,16 @@ TEST (void) CALC (res_ref, src1.a, src2.a); - res1.x = INTRINSIC (_cvtbiassph_hf8) (src1.x, src2.x); + res1.x = INTRINSIC (_cvts_biasph_hf8) (src1.x, src2.x); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res1, res_ref)) abort (); - res2.x = INTRINSIC (_mask_cvtbiassph_hf8) (res2.x, mask, src1.x, src2.x); + res2.x = INTRINSIC (_mask_cvts_biasph_hf8) (res2.x, mask, src1.x, src2.x); MASK_MERGE (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res2, res_ref)) abort (); - res3.x = INTRINSIC (_maskz_cvtbiassph_hf8) (mask, src1.x, src2.x); + res3.x = INTRINSIC (_maskz_cvts_biasph_hf8) (mask, src1.x, src2.x); MASK_ZERO (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res3, res_ref)) abort (); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2bf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2bf8s-2.c index f4853ce..c22e1aa 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2bf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2bf8s-2.c @@ -60,16 +60,16 @@ TEST (void) CALC(res_ref, src.a); - res1.x = INTRINSIC (_cvtsph_bf8) (src.x); + res1.x = INTRINSIC (_cvts_ph_bf8) (src.x); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res1, res_ref)) abort (); - res2.x = INTRINSIC (_mask_cvtsph_bf8) (res2.x, mask, src.x); + res2.x = INTRINSIC (_mask_cvts_ph_bf8) (res2.x, mask, src.x); MASK_MERGE (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res2, res_ref)) abort (); - res3.x = INTRINSIC (_maskz_cvtsph_bf8) (mask, src.x); + res3.x = INTRINSIC (_maskz_cvts_ph_bf8) (mask, src.x); MASK_ZERO (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res3, res_ref)) abort (); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2hf8s-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2hf8s-2.c index 43610bf..e6872e8 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2hf8s-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtph2hf8s-2.c @@ -60,16 +60,16 @@ TEST (void) CALC(res_ref, src.a); - res1.x = INTRINSIC (_cvtsph_hf8) (src.x); + res1.x = INTRINSIC (_cvts_ph_hf8) (src.x); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res1, res_ref)) abort (); - res2.x = INTRINSIC (_mask_cvtsph_hf8) (res2.x, mask, src.x); + res2.x = INTRINSIC (_mask_cvts_ph_hf8) (res2.x, mask, src.x); MASK_MERGE (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res2, res_ref)) abort (); - res3.x = INTRINSIC (_maskz_cvtsph_hf8) (mask, src.x); + res3.x = INTRINSIC (_maskz_cvts_ph_hf8) (mask, src.x); MASK_ZERO (i_b) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN_HALF, i_b) (res3, res_ref)) abort (); diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c index d057c83..1db5a89 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c @@ -9,6 +9,7 @@ #endif #include "avx10-helper.h" #include <limits.h> +#include <string.h> #define SIZE (AVX512F_LEN / 16) #include "avx512f-mask-type.h" @@ -37,7 +38,7 @@ TEST (void) UNION_TYPE (AVX512F_LEN, h) s; UNION_TYPE (AVX512F_LEN, i_w) res1, res2, res3; MASK_TYPE mask = MASK_VALUE; - short res_ref[SIZE] = { 0 }; + short res_ref[SIZE] = { 0 }, res_ref2[SIZE] = { 0 }; int i, sign = 1; for (i = 0; i < SIZE; i++) @@ -54,11 +55,7 @@ TEST (void) res3.x = INTRINSIC (_maskz_ipcvtts_ph_epu8) (mask, s.x); CALC (s.a, res_ref); - -#if AVX512F_LEN == 512 - res1.x = INTRINSIC (_ipcvtts_roundph_epu8) (s.x, 8); - res2.x = INTRINSIC (_mask_ipcvtts_roundph_epu8) (res2.x, mask, s.x, 8); - res3.x = INTRINSIC (_maskz_ipcvtts_roundph_epu8) (mask, s.x, 8); + memcpy(res_ref2, res_ref, sizeof(res_ref)); if (UNION_CHECK (AVX512F_LEN, i_w) (res1, res_ref)) abort (); @@ -70,5 +67,24 @@ TEST (void) MASK_ZERO (i_w) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN, i_w) (res3, res_ref)) abort (); + +#if AVX512F_LEN == 512 + for (i = 0; i < SIZE; i++) + res2.a[i] = DEFAULT_VALUE; + + res1.x = INTRINSIC (_ipcvtts_roundph_epu8) (s.x, 8); + res2.x = INTRINSIC (_mask_ipcvtts_roundph_epu8) (res2.x, mask, s.x, 8); + res3.x = INTRINSIC (_maskz_ipcvtts_roundph_epu8) (mask, s.x, 8); + + if (UNION_CHECK (AVX512F_LEN, i_w) (res1, res_ref2)) + abort (); + + MASK_MERGE (i_w) (res_ref2, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_w) (res2, res_ref2)) + abort (); + + MASK_ZERO (i_w) (res_ref2, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_w) (res3, res_ref2)) + abort (); #endif } diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-convert-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-convert-1.c index 62791d0..3d5e921 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-convert-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-convert-1.c @@ -138,13 +138,13 @@ avx10_2_vcvtbiasph2bf8_test (void) void extern avx10_2_vcvtbiasph2bf8s_test (void) { - x128i = _mm_cvtbiassph_bf8 (x128i, x128h); - x128i = _mm_mask_cvtbiassph_bf8 (x128i, m8, x128i, x128h); - x128i = _mm_maskz_cvtbiassph_bf8 (m8, x128i, x128h); + x128i = _mm_cvts_biasph_bf8 (x128i, x128h); + x128i = _mm_mask_cvts_biasph_bf8 (x128i, m8, x128i, x128h); + x128i = _mm_maskz_cvts_biasph_bf8 (m8, x128i, x128h); - x128i = _mm256_cvtbiassph_bf8 (x256i, x256h); - x128i = _mm256_mask_cvtbiassph_bf8 (x128i, m16, x256i, x256h); - x128i = _mm256_maskz_cvtbiassph_bf8 (m16, x256i, x256h); + x128i = _mm256_cvts_biasph_bf8 (x256i, x256h); + x128i = _mm256_mask_cvts_biasph_bf8 (x128i, m16, x256i, x256h); + x128i = _mm256_maskz_cvts_biasph_bf8 (m16, x256i, x256h); } void extern @@ -162,13 +162,13 @@ avx10_2_vcvtbiasph2hf8_test (void) void extern avx10_2_vcvtbiasph2hf8s_test (void) { - x128i = _mm_cvtbiassph_hf8 (x128i, x128h); - x128i = _mm_mask_cvtbiassph_hf8 (x128i, m8, x128i, x128h); - x128i = _mm_maskz_cvtbiassph_hf8 (m8, x128i, x128h); + x128i = _mm_cvts_biasph_hf8 (x128i, x128h); + x128i = _mm_mask_cvts_biasph_hf8 (x128i, m8, x128i, x128h); + x128i = _mm_maskz_cvts_biasph_hf8 (m8, x128i, x128h); - x128i = _mm256_cvtbiassph_hf8 (x256i, x256h); - x128i = _mm256_mask_cvtbiassph_hf8 (x128i, m16, x256i, x256h); - x128i = _mm256_maskz_cvtbiassph_hf8 (m16, x256i, x256h); + x128i = _mm256_cvts_biasph_hf8 (x256i, x256h); + x128i = _mm256_mask_cvts_biasph_hf8 (x128i, m16, x256i, x256h); + x128i = _mm256_maskz_cvts_biasph_hf8 (m16, x256i, x256h); } void extern @@ -185,12 +185,12 @@ avx10_2_vcvt2ph2bf8_test (void) void extern avx10_2_vcvt2ph2bf8s_test (void) { - x128i = _mm_cvts2ph_bf8 (x128h, x128h); - x128i = _mm_mask_cvts2ph_bf8 (x128i, m16, x128h, x128h); - x128i = _mm_maskz_cvts2ph_bf8 (m16, x128h, x128h); - x256i = _mm256_cvts2ph_bf8 (x256h, x256h); - x256i = _mm256_mask_cvts2ph_bf8 (x256i, m32, x256h, x256h); - x256i = _mm256_maskz_cvts2ph_bf8 (m32, x256h, x256h); + x128i = _mm_cvts_2ph_bf8 (x128h, x128h); + x128i = _mm_mask_cvts_2ph_bf8 (x128i, m16, x128h, x128h); + x128i = _mm_maskz_cvts_2ph_bf8 (m16, x128h, x128h); + x256i = _mm256_cvts_2ph_bf8 (x256h, x256h); + x256i = _mm256_mask_cvts_2ph_bf8 (x256i, m32, x256h, x256h); + x256i = _mm256_maskz_cvts_2ph_bf8 (m32, x256h, x256h); } void extern @@ -207,12 +207,12 @@ avx10_2_vcvt2ph2hf8_test (void) void extern avx10_2_vcvt2ph2hf8s_test (void) { - x128i = _mm_cvts2ph_hf8 (x128h, x128h); - x128i = _mm_mask_cvts2ph_hf8 (x128i, m16, x128h, x128h); - x128i = _mm_maskz_cvts2ph_hf8 (m16, x128h, x128h); - x256i = _mm256_cvts2ph_hf8 (x256h, x256h); - x256i = _mm256_mask_cvts2ph_hf8 (x256i, m32, x256h, x256h); - x256i = _mm256_maskz_cvts2ph_hf8 (m32, x256h, x256h); + x128i = _mm_cvts_2ph_hf8 (x128h, x128h); + x128i = _mm_mask_cvts_2ph_hf8 (x128i, m16, x128h, x128h); + x128i = _mm_maskz_cvts_2ph_hf8 (m16, x128h, x128h); + x256i = _mm256_cvts_2ph_hf8 (x256h, x256h); + x256i = _mm256_mask_cvts_2ph_hf8 (x256i, m32, x256h, x256h); + x256i = _mm256_maskz_cvts_2ph_hf8 (m32, x256h, x256h); } void extern @@ -242,13 +242,13 @@ avx10_2_vcvtph2bf8_test (void) void extern avx10_2_vcvtph2bf8s_test (void) { - x128i = _mm_cvtsph_bf8 (x128h); - x128i = _mm_mask_cvtsph_bf8 (x128i, m8, x128h); - x128i = _mm_maskz_cvtsph_bf8 (m8, x128h); + x128i = _mm_cvts_ph_bf8 (x128h); + x128i = _mm_mask_cvts_ph_bf8 (x128i, m8, x128h); + x128i = _mm_maskz_cvts_ph_bf8 (m8, x128h); - x128i = _mm256_cvtsph_bf8 (x256h); - x128i = _mm256_mask_cvtsph_bf8 (x128i, m16, x256h); - x128i = _mm256_maskz_cvtsph_bf8 (m16, x256h); + x128i = _mm256_cvts_ph_bf8 (x256h); + x128i = _mm256_mask_cvts_ph_bf8 (x128i, m16, x256h); + x128i = _mm256_maskz_cvts_ph_bf8 (m16, x256h); } void extern @@ -266,13 +266,13 @@ avx10_2_vcvtph2hf8_test (void) void extern avx10_2_vcvtph2hf8s_test (void) { - x128i = _mm_cvtsph_hf8 (x128h); - x128i = _mm_mask_cvtsph_hf8 (x128i, m8, x128h); - x128i = _mm_maskz_cvtsph_hf8 (m8, x128h); + x128i = _mm_cvts_ph_hf8 (x128h); + x128i = _mm_mask_cvts_ph_hf8 (x128i, m8, x128h); + x128i = _mm_maskz_cvts_ph_hf8 (m8, x128h); - x128i = _mm256_cvtsph_hf8 (x256h); - x128i = _mm256_mask_cvtsph_hf8 (x128i, m16, x256h); - x128i = _mm256_maskz_cvtsph_hf8 (m16, x256h); + x128i = _mm256_cvts_ph_hf8 (x256h); + x128i = _mm256_mask_cvts_ph_hf8 (x128i, m16, x256h); + x128i = _mm256_maskz_cvts_ph_hf8 (m16, x256h); } void extern diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1b.c index a96007d..9b08f5a 100644 --- a/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1b.c +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1b.c @@ -1,4 +1,4 @@ -/* { dg-do run {target avx512fp16} } */ +/* { dg-do run { target avx512fp16 } } */ /* { dg-options "-O2 -mavx512fp16" } */ static void do_test (void); diff --git a/gcc/testsuite/gcc.target/i386/pr111673.c b/gcc/testsuite/gcc.target/i386/pr111673.c index b9ceacf..0f08ba89 100644 --- a/gcc/testsuite/gcc.target/i386/pr111673.c +++ b/gcc/testsuite/gcc.target/i386/pr111673.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O2 -fdump-rtl-pro_and_epilogue" } */ +/* { dg-options "-O2 -fdump-rtl-pro_and_epilogue -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr115910.c b/gcc/testsuite/gcc.target/i386/pr115910.c new file mode 100644 index 0000000..5f1cd9a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr115910.c @@ -0,0 +1,20 @@ +/* PR target/115910 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=x86-64 -mtune=generic -masm=att" } */ +/* { dg-final { scan-assembler-times {\timulq\t} 2 } } */ +/* { dg-final { scan-assembler-times {\tshrq\t\$33,} 2 } } */ +/* { dg-final { scan-assembler-not {\tsarl\t} } } */ + +int +foo (int x) +{ + if (x < 0) + __builtin_unreachable (); + return x / 3U; +} + +int +bar (int x) +{ + return x / 3U; +} diff --git a/gcc/testsuite/gcc.target/i386/pr117946.c b/gcc/testsuite/gcc.target/i386/pr117946.c index c4bf825..b46921c 100644 --- a/gcc/testsuite/gcc.target/i386/pr117946.c +++ b/gcc/testsuite/gcc.target/i386/pr117946.c @@ -1,4 +1,5 @@ /* { dg-do compile { target { ! ia32 } } } */ +/* { dg-require-effective-target dfp } */ /* { dg-options "-O -favoid-store-forwarding -mavx10.1 -mprefer-avx128 --param=store-forwarding-max-distance=128 -Wno-psabi" } */ /* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ typedef __attribute__((__vector_size__ (64))) _Decimal32 V; diff --git a/gcc/testsuite/gcc.target/i386/pr118017.c b/gcc/testsuite/gcc.target/i386/pr118017.c index 28797a0..831ec6e 100644 --- a/gcc/testsuite/gcc.target/i386/pr118017.c +++ b/gcc/testsuite/gcc.target/i386/pr118017.c @@ -1,5 +1,7 @@ /* PR target/118017 */ -/* { dg-do compile { target int128 } } */ +/* { dg-do compile } */ +/* { dg-require-effective-target int128 } */ +/* { dg-require-effective-target dfp } */ /* { dg-options "-Og -frounding-math -mno-80387 -mno-mmx -Wno-psabi" } */ typedef __attribute__((__vector_size__ (64))) _Float128 F; diff --git a/gcc/testsuite/gcc.target/i386/pr119425.c b/gcc/testsuite/gcc.target/i386/pr119425.c new file mode 100644 index 0000000..b926979 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119425.c @@ -0,0 +1,37 @@ +/* PR target/119425 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-Os -fno-vect-cost-model -ftree-slp-vectorize -mavxneconvert -mapxf" } */ +extern long K512[]; +extern long sha512_block_data_order_ctx[]; + +#define Ch(x, y, z) ~x &z +#define ROUND_00_15(i, a, b, c, d, e, f, g, h) \ + T1 += ~e & g + K512[i]; \ +h = 0; \ +d += h += T1 +#define ROUND_16_80(i, j, a, b, c, d, e, f, g, h, X) \ + ROUND_00_15(i + j, , , , d, e, , g, h) + +unsigned sha512_block_data_order_f, sha512_block_data_order_g; + +void +sha512_block_data_order() +{ + unsigned a, b, c, d, e, h, T1; + int i = 6; + for (; i < 80; i += 6) { + ROUND_16_80(i, 0, , , , d, e, , , h, ); + ROUND_16_80(i, 11, , , , a, b, , d, e, ); + ROUND_16_80(i, 12, , , , h, a, , c, d, ); + ROUND_16_80(i, 13, , , , sha512_block_data_order_g, h, , b, c, ); + ROUND_16_80(i, 14, , , , sha512_block_data_order_f, + sha512_block_data_order_g, , a, b, ); + ROUND_16_80(i, 15, , , , e, sha512_block_data_order_f, , , a, ); + + } + sha512_block_data_order_ctx[0] += a; + sha512_block_data_order_ctx[1] += b; + sha512_block_data_order_ctx[2] += c; + sha512_block_data_order_ctx[3] += d; + +} diff --git a/gcc/testsuite/gcc.target/i386/pr119450.c b/gcc/testsuite/gcc.target/i386/pr119450.c new file mode 100644 index 0000000..fa4bbda --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119450.c @@ -0,0 +1,15 @@ +/* PR target/119450 */ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +long *a; +int b; + +void +foo (void) +{ + unsigned d = b >> 30; + a = (long *) (__UINTPTR_TYPE__) d; + if (*a & 1 << 30) + *a = 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr119473.c b/gcc/testsuite/gcc.target/i386/pr119473.c new file mode 100644 index 0000000..574c921 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119473.c @@ -0,0 +1,26 @@ +/* PR target/119473 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mapxf -m64 -mvaes" } */ + +typedef char __v32qi __attribute__ ((__vector_size__(32))); +typedef long long __m256i __attribute__((__vector_size__(32), __aligned__(32))); + +typedef union +{ + __v32qi qi[8]; +} tmp_u; + + +void foo () +{ + register tmp_u *tdst __asm__("%rdx"); + register tmp_u *src1 __asm__("%rcx"); + register tmp_u *src2 __asm__("%r26"); + + tdst->qi[0] = __builtin_ia32_vaesdec_v32qi(src1->qi[0], src2->qi[0]); + tdst->qi[0] = __builtin_ia32_vaesdeclast_v32qi(src1->qi[0], src2->qi[0]); + tdst->qi[0] = __builtin_ia32_vaesenc_v32qi(src1->qi[0], src2->qi[0]); + tdst->qi[0] = __builtin_ia32_vaesenclast_v32qi(src1->qi[0], src2->qi[0]); +} + +/* { dg-final { scan-assembler-not "\\\(%r26\\\), " } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr119549.c b/gcc/testsuite/gcc.target/i386/pr119549.c new file mode 100644 index 0000000..a465bec --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119549.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-msse4" } */ + +typedef long long v2di __attribute__((vector_size(16))); + +static inline __attribute__((always_inline)) +int rte_trace_feature_is_enabled() { return 1; } /* { dg-error "inlining failed" } */ + +void __attribute__((target ("no-sse3"))) __attribute__((target ("no-sse4"))) +rte_eal_trace_generic_void_init(void) +{ + if (!rte_trace_feature_is_enabled()) return; + __asm__ volatile ("" : : : "memory"); +} + diff --git a/gcc/testsuite/gcc.target/i386/pr55583.c b/gcc/testsuite/gcc.target/i386/pr55583.c index ea6a2d5..8773451 100644 --- a/gcc/testsuite/gcc.target/i386/pr55583.c +++ b/gcc/testsuite/gcc.target/i386/pr55583.c @@ -1,9 +1,8 @@ /* { dg-do compile } */ /* { dg-options "-O2 -Wno-shift-count-overflow" } */ -/* { dg-final { scan-assembler-times {(?n)shrd[ql]?[\t ]*\$2} 4 { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-times {(?n)shrdl?[\t ]*\$2} 2 { target ia32 } } } */ -/* { dg-final { scan-assembler-times {(?n)shldl?[\t ]*\$2} 1 { target ia32 } } } */ -/* { dg-final { scan-assembler-times {(?n)shld[ql]?[\t ]*\$2} 2 { target { ! ia32 } } } } */ +/* { dg-additional-options "-mno-sse -mno-mmx" { target ia32 } } */ +/* { dg-final { scan-assembler-times {(?n)shrd[ql]?[\t ]*\$2} 4 } } */ +/* { dg-final { scan-assembler-times {(?n)shld[ql]?[\t ]*\$2} 2 } } */ typedef unsigned long long u64; typedef unsigned int u32; diff --git a/gcc/testsuite/gcc.target/i386/pr82142a.c b/gcc/testsuite/gcc.target/i386/pr82142a.c index a40c038..a536150 100644 --- a/gcc/testsuite/gcc.target/i386/pr82142a.c +++ b/gcc/testsuite/gcc.target/i386/pr82142a.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O2 -mno-avx -msse2" } */ +/* { dg-options "-O2 -mno-avx -msse2 -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr82142b.c b/gcc/testsuite/gcc.target/i386/pr82142b.c index b1bf12d..d18b7c4 100644 --- a/gcc/testsuite/gcc.target/i386/pr82142b.c +++ b/gcc/testsuite/gcc.target/i386/pr82142b.c @@ -1,5 +1,5 @@ /* { dg-do compile { target ia32 } } */ -/* { dg-options "-O2 -mno-avx -msse2" } */ +/* { dg-options "-O2 -mno-avx -msse2 -mno-stackrealign -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/sse2-float16-5.c b/gcc/testsuite/gcc.target/i386/sse2-float16-5.c index c3ed23b..8207842 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-float16-5.c +++ b/gcc/testsuite/gcc.target/i386/sse2-float16-5.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target ia32} } */ +/* { dg-do compile { target ia32 } } */ /* { dg-options "-O2 -mno-sse2" } */ _Float16 a; diff --git a/gcc/testsuite/gcc.target/i386/strub-pr118006.c b/gcc/testsuite/gcc.target/i386/strub-pr118006.c index f116790..88f66c1 100644 --- a/gcc/testsuite/gcc.target/i386/strub-pr118006.c +++ b/gcc/testsuite/gcc.target/i386/strub-pr118006.c @@ -1,5 +1,5 @@ -/* { dg-require-effective-target strub } */ /* { dg-do compile } */ +/* { dg-require-effective-target strub } */ /* { dg-options "-fstrub=all -O2 -mno-accumulate-outgoing-args" } */ __attribute__((noipa)) diff --git a/gcc/testsuite/gcc.target/ia64/mfused-madd-vect.c b/gcc/testsuite/gcc.target/ia64/mfused-madd-vect.c index 5bf6976..d1dc3c1 100644 --- a/gcc/testsuite/gcc.target/ia64/mfused-madd-vect.c +++ b/gcc/testsuite/gcc.target/ia64/mfused-madd-vect.c @@ -1,4 +1,4 @@ -/* { dg-do compile */ +/* { dg-do compile } */ /* { dg-options "-O2 -ftree-vectorize" } */ /* { dg-final { scan-assembler-not "fpmpy" } } */ diff --git a/gcc/testsuite/gcc.target/ia64/mfused-madd.c b/gcc/testsuite/gcc.target/ia64/mfused-madd.c index 8ecb31f..04fd95a 100644 --- a/gcc/testsuite/gcc.target/ia64/mfused-madd.c +++ b/gcc/testsuite/gcc.target/ia64/mfused-madd.c @@ -1,4 +1,4 @@ -/* { dg-do compile */ +/* { dg-do compile } */ /* { dg-options "-O2" } */ /* { dg-final { scan-assembler-not "fmpy" } } */ /* { dg-final { scan-assembler-not "fadd" } } */ diff --git a/gcc/testsuite/gcc.target/ia64/mno-fused-madd-vect.c b/gcc/testsuite/gcc.target/ia64/mno-fused-madd-vect.c index 10b047b..a80ce8b 100644 --- a/gcc/testsuite/gcc.target/ia64/mno-fused-madd-vect.c +++ b/gcc/testsuite/gcc.target/ia64/mno-fused-madd-vect.c @@ -1,4 +1,4 @@ -/* { dg-do compile */ +/* { dg-do compile } */ /* { dg-options "-O2 -ffp-contract=off -ftree-vectorize" } */ /* { dg-final { scan-assembler "fpmpy" } } */ diff --git a/gcc/testsuite/gcc.target/ia64/mno-fused-madd.c b/gcc/testsuite/gcc.target/ia64/mno-fused-madd.c index 487519a..1f29225 100644 --- a/gcc/testsuite/gcc.target/ia64/mno-fused-madd.c +++ b/gcc/testsuite/gcc.target/ia64/mno-fused-madd.c @@ -1,4 +1,4 @@ -/* { dg-do compile */ +/* { dg-do compile } */ /* { dg-options "-O2 -ffp-contract=off" } */ /* { dg-final { scan-assembler-not "fma" } } */ /* { dg-final { scan-assembler-not "fms" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/pr119408.c b/gcc/testsuite/gcc.target/loongarch/pr119408.c new file mode 100644 index 0000000..f46399a --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr119408.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-pedantic" } */ + +__float128 a; +__float128 b; +void +test (void) +{ + a = 1.11111111Q; + b = 1.434345q; +} + diff --git a/gcc/testsuite/gcc.target/nvptx/decl.c b/gcc/testsuite/gcc.target/nvptx/decl.c index 190a64d..45dd699 100644 --- a/gcc/testsuite/gcc.target/nvptx/decl.c +++ b/gcc/testsuite/gcc.target/nvptx/decl.c @@ -13,8 +13,8 @@ int Foo () } /* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.visible .global \[^,\r\n\]*glob_export" } } */ -/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.visible .const \[^,\r\n\]*cst_export" } } */ +/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.visible .global \[^,\r\n\]*cst_export" } } */ /* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.global \[^,\r\n\]*glob_local" } } */ -/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.const \[^,\r\n\]*cst_local" } } */ +/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.global \[^,\r\n\]*cst_local" } } */ /* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.extern .global \[^,\r\n\]*glob_import" } } */ -/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.extern .const \[^,\r\n\]*cst_import" } } */ +/* { dg-final { scan-assembler "\[\r\n\]\[\t \]*.extern .global \[^,\r\n\]*cst_import" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-longlong.c index 06d6c1b..4facb82 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-longlong.c @@ -1,7 +1,7 @@ /* Verify that overloaded built-ins for vec_perm with long long inputs produce the right code. */ -/* { dg-do compile {target lp64} } */ +/* { dg-do compile { target lp64 } } */ // 'long long' in Altivec types is invalid without -mvsx. /* { dg-options "-mvsx -O2" } */ /* { dg-require-effective-target powerpc_vsx } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243.c b/gcc/testsuite/gcc.target/powerpc/pr70243.c index 1152518..512c199 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr70243.c +++ b/gcc/testsuite/gcc.target/powerpc/pr70243.c @@ -1,4 +1,4 @@ -/* { dg-do compile */ +/* { dg-do compile } */ /* { dg-options "-O2 -mvsx" } */ /* { dg-require-effective-target powerpc_vsx } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr91903.c b/gcc/testsuite/gcc.target/powerpc/pr91903.c index d70a0c6..b147d0e 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr91903.c +++ b/gcc/testsuite/gcc.target/powerpc/pr91903.c @@ -1,4 +1,4 @@ -/* { dg-do compile */ +/* { dg-do compile } */ /* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* { dg-require-effective-target powerpc_vsx } */ diff --git a/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c b/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c index e2369fc..326d5dc 100644 --- a/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c +++ b/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c @@ -10,10 +10,10 @@ func (int a, int b); **sum: ** ... ** cm.mvsa01 s1,s2 -** call func +** call func(?:@plt)? ** mv s0,a0 ** cm.mva01s s1,s2 -** call func +** call func(?:@plt)? ** ... */ int diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c index 9718115..581b5db 100644 --- a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile target { { rv64-*-*}}} */ +/* { dg-do compile { target rv64-*-* } } */ /* { dg-options "-march=rv64gc_zicbop -mabi=lp64" } */ void foo (char *p) diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c index 4871a97..3f7c1a4 100644 --- a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c @@ -1,4 +1,4 @@ -/* { dg-do compile target { { rv32-*-*}}} */ +/* { dg-do compile { target rv64-*-* } } */ /* { dg-options "-march=rv32gc_zicbop -mabi=ilp32" } */ void foo (char *p) diff --git a/gcc/testsuite/gcc.target/riscv/cpymem-64.c b/gcc/testsuite/gcc.target/riscv/cpymem-64.c index 37b8ef0..c91b015 100644 --- a/gcc/testsuite/gcc.target/riscv/cpymem-64.c +++ b/gcc/testsuite/gcc.target/riscv/cpymem-64.c @@ -95,7 +95,7 @@ COPY_ALIGNED_N(11) /* **copy_15: ** ... -** (call|tail)\tmemcpy +** (call|tail)\tmemcpy(?:@plt)? ** ... */ COPY_N(15) @@ -116,7 +116,7 @@ COPY_ALIGNED_N(15) /* **copy_27: ** ... -** (call|tail)\tmemcpy +** (call|tail)\tmemcpy(?:@plt)? ** ... */ COPY_N(27) diff --git a/gcc/testsuite/gcc.target/riscv/fmax-snan.c b/gcc/testsuite/gcc.target/riscv/fmax-snan.c index aabaad5..a1f6149 100644 --- a/gcc/testsuite/gcc.target/riscv/fmax-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fmax-snan.c @@ -10,4 +10,4 @@ fmax (double x, double y) /* { dg-final { scan-assembler-not "\tfmax\\.d\t" } } */ /* { dg-final { scan-assembler-not "\tfge\\.d\t" } } */ -/* { dg-final { scan-assembler "\t(call|tail)\tfmax\t" } } */ +/* { dg-final { scan-assembler "\t(call|tail)\tfmax(?:@plt)?\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c b/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c index f74a817..1daf3e9 100644 --- a/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c @@ -10,4 +10,4 @@ fmaxf (float x, float y) /* { dg-final { scan-assembler-not "\tfmax\\.s\t" } } */ /* { dg-final { scan-assembler-not "\tfge\\.s\t" } } */ -/* { dg-final { scan-assembler "\t(call|tail)\tfmaxf\t" } } */ +/* { dg-final { scan-assembler "\t(call|tail)\tfmaxf(?:@plt)?\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fmin-snan.c b/gcc/testsuite/gcc.target/riscv/fmin-snan.c index 3b2e8c3..cc0e16c 100644 --- a/gcc/testsuite/gcc.target/riscv/fmin-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fmin-snan.c @@ -10,4 +10,4 @@ fmin (double x, double y) /* { dg-final { scan-assembler-not "\tfmin\\.d\t" } } */ /* { dg-final { scan-assembler-not "\tfle\\.d\t" } } */ -/* { dg-final { scan-assembler "\t(call|tail)\tfmin\t" } } */ +/* { dg-final { scan-assembler "\t(call|tail)\tfmin(?:@plt)?\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fminf-snan.c b/gcc/testsuite/gcc.target/riscv/fminf-snan.c index d28822e..598644e 100644 --- a/gcc/testsuite/gcc.target/riscv/fminf-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fminf-snan.c @@ -10,4 +10,4 @@ fminf (float x, float y) /* { dg-final { scan-assembler-not "\tfmin\\.s\t" } } */ /* { dg-final { scan-assembler-not "\tfle\\.s\t" } } */ -/* { dg-final { scan-assembler "\t(call|tail)\tfminf\t" } } */ +/* { dg-final { scan-assembler "\t(call|tail)\tfminf(?:@plt)?\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/large-model.c b/gcc/testsuite/gcc.target/riscv/large-model.c index 244d14e..d5ef7a0 100644 --- a/gcc/testsuite/gcc.target/riscv/large-model.c +++ b/gcc/testsuite/gcc.target/riscv/large-model.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64 -fno-section-anchors -mcmodel=large" } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -fno-section-anchors -mcmodel=large -fno-pie" } */ /* { dg-skip-if "" { *-*-* } {"-O0"} } */ int a, b; int foo1() diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c index 2903c88..c2a374f 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c @@ -1,6 +1,6 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { rv64 } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ -/* { dg-options "-mcpu=xiangshan-nanhu" { target { rv64 } } } */ +/* { dg-options "-mcpu=xiangshan-nanhu" } */ /* XiangShan Nanhu => rv64imafdc_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd _zkne_zknh_zksed_zksh_svinval_zicbom_zicboz */ diff --git a/gcc/testsuite/gcc.target/riscv/predef-1.c b/gcc/testsuite/gcc.target/riscv/predef-1.c index 250812a..551346e 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-1.c +++ b/gcc/testsuite/gcc.target/riscv/predef-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32i -mabi=ilp32 -mcmodel=medlow" } */ +/* { dg-options "-march=rv32i -mabi=ilp32 -mcmodel=medlow -fno-pie" } */ int main () { #if !defined(__riscv) diff --git a/gcc/testsuite/gcc.target/riscv/predef-4.c b/gcc/testsuite/gcc.target/riscv/predef-4.c index ba8b5c7..7b3c054 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-4.c +++ b/gcc/testsuite/gcc.target/riscv/predef-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64ia -mabi=lp64 -mcmodel=medlow" } */ +/* { dg-options "-march=rv64ia -mabi=lp64 -mcmodel=medlow -fno-pie" } */ int main () { #if !defined(__riscv) diff --git a/gcc/testsuite/gcc.target/riscv/predef-7.c b/gcc/testsuite/gcc.target/riscv/predef-7.c index 833e2be..36caf8e 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-7.c +++ b/gcc/testsuite/gcc.target/riscv/predef-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32em -mabi=ilp32e -mno-div -mcmodel=medlow" } */ +/* { dg-options "-march=rv32em -mabi=ilp32e -mno-div -mcmodel=medlow -fno-pie" } */ int main () { #if !defined(__riscv) diff --git a/gcc/testsuite/gcc.target/riscv/predef-9.c b/gcc/testsuite/gcc.target/riscv/predef-9.c index b173d5d..fa072ad 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-9.c +++ b/gcc/testsuite/gcc.target/riscv/predef-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64em -mabi=lp64e -mno-div -mcmodel=medlow" } */ +/* { dg-options "-march=rv64em -mabi=lp64e -mno-div -mcmodel=medlow -fno-pie" } */ /* { dg-warning "LP64E ABI is marked for deprecation in GCC" "" { target *-*-* } 0 } */ /* { dg-note "if you need LP64E please notify the GCC project via PR116152" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c b/gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c index 0faa120..44da4b2 100644 --- a/gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c +++ b/gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c @@ -1,4 +1,4 @@ -/* { dg-do compile target { { rv64-*-*}}} */ +/* { dg-do compile { target rv64-*-* } } */ /* { dg-options "-march=rv64gc_zicbop -mabi=lp64" } */ void foo (char *p) diff --git a/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c index 78a3afe..43439d7 100644 --- a/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c +++ b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c @@ -1,4 +1,4 @@ -/* { dg-do compile target { { rv64-*-*}}} */ +/* { dg-do compile { target rv64-*-* } } */ /* { dg-options "-march=rv64gc_zicbop_zihintntl -mabi=lp64" } */ void foo (char *p) diff --git a/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c b/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c index 0af4d71..fd845f5 100644 --- a/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c @@ -244,9 +244,9 @@ test_f0 () /* **foo: ** cm.push {ra}, -16 -** call f1 +** call f1(?:@plt)? ** cm.pop {ra}, 16 -** tail f2 +** tail f2(?:@plt)? */ void foo (void) @@ -258,7 +258,7 @@ foo (void) /* **test_popretz: ** cm.push {ra}, -16 -** call f1 +** call f1(?:@plt)? ** li a0,0 ** cm.popret {ra}, 16 */ diff --git a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c b/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c index 723889f4..d90f4f4 100644 --- a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c @@ -244,9 +244,9 @@ test_f0 () /* **foo: ** cm.push {ra}, -16 -** call f1 +** call f1(?:@plt)? ** cm.pop {ra}, 16 -** tail f2 +** tail f2(?:@plt)? */ void foo (void) @@ -258,7 +258,7 @@ foo (void) /* **test_popretz: ** cm.push {ra}, -16 -** call f1 +** call f1(?:@plt)? ** li a0,0 ** cm.popret {ra}, 16 */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c index 1f170c9..32db3a6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c @@ -3,7 +3,7 @@ #include "pr111391-1.c" -/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 } } +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 } } */ /* { dg-final { scan-assembler-times {vmv\.x\.s} 2 } } */ /* { dg-final { scan-assembler-times {vslidedown.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 1 } } */ /* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,[a-x0-9]+,32} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c index f255ceb..493dab0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c @@ -18,6 +18,6 @@ int pixel_sad_n(unsigned char *pix1, unsigned char *pix2, int n) return sum; } -/* { dg-final { scan-assembler {vminu\.v} } } */ -/* { dg-final { scan-assembler {vmaxu\.v} } } */ -/* { dg-final { scan-assembler {vsub\.v} } } */ +/* { dg-final { scan-assembler {vrsub\.v} } } */ +/* { dg-final { scan-assembler {vmax\.v} } } */ +/* { dg-final { scan-assembler {vwsubu\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr119224.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr119224.c new file mode 100644 index 0000000..fa3386c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr119224.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -ffast-math -march=rv64gcv_zvl256b -mabi=lp64d -mtune=generic-ooo -mrvv-vector-bits=zvl" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O2" "-Og" "-Os" "-Oz" } } */ + +/* A core routine of x264 which should not spill for OoO VLS build. */ + +inline int abs(int i) +{ + return (i < 0 ? -i : i); +} + +int x264_sad_16x16(unsigned char *p1, int st1, unsigned char *p2, int st2) +{ + int sum = 0; + + for(int y = 0; y < 16; y++) + { + for(int x = 0; x < 16; x++) + sum += abs (p1[x] - p2[x]); + p1 += st1; p2 += st2; + } + + return sum; +} + +/* { dg-final { scan-assembler-not {addi\t[a-x0-9]+,sp} } } */ +/* { dg-final { scan-assembler-not {addi\tsp,sp} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c index 3095a6d..a043b33 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c @@ -119,4 +119,4 @@ merge10 (vnx16df x, vnx16df y, vnx16df *out) *(vnx16df*)out = v; } -/* dg-final scan-assembler-times {\tvmerge.vvm} 11 */ +/* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c index 1dfd828..4ae341a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c @@ -3,6 +3,6 @@ #include "../vls-vlmax/merge-4.c" -/* dg-final scan-assembler-times {\tvmerge.vvm} 11 */ +/* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */ /* { dg-final { scan-assembler-not {\tvms} } } */ /* { dg-final { scan-assembler-times {\tvlm.v} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-14.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-14.c index 163152a..222d8c2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-14.c @@ -1,20 +1,20 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=rv32gc_zve32x_zvl64b -mabi=ilp32d" } */ -void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} -void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} -void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} -void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} -void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} -void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} -void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} -void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} -void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} -void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} -void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} -void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} -void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} -void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x2_t'} } */ +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x2_t'} } */ +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x3_t'} } */ +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x3_t'} } */ +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x4_t'} } */ +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x4_t'} } */ +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x5_t'} } */ +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x5_t'} } */ +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x6_t'} } */ +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x6_t'} } */ +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x7_t'} } */ +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x7_t'} } */ +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x8_t'} } */ +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x8_t'} } */ void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} @@ -65,20 +65,20 @@ void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} -void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} -void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} -void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} -void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} -void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} -void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} -void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} -void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} -void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} -void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} -void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} -void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} -void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} -void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x2_t'} } */ +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x2_t'} } */ +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x3_t'} } */ +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x3_t'} } */ +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x4_t'} } */ +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x4_t'} } */ +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x5_t'} } */ +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x5_t'} } */ +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x6_t'} } */ +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x6_t'} } */ +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x7_t'} } */ +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x7_t'} } */ +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x8_t'} } */ +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x8_t'} } */ void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} @@ -115,20 +115,20 @@ void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} -void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} -void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} -void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} -void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} -void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} -void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} -void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} -void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} -void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} -void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} -void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} -void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} -void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} -void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x2_t'} } */ +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x2_t'} } */ +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x3_t'} } */ +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x3_t'} } */ +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x4_t'} } */ +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x4_t'} } */ +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x5_t'} } */ +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x5_t'} } */ +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x6_t'} } */ +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x6_t'} } */ +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x7_t'} } */ +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x7_t'} } */ +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x8_t'} } */ +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x8_t'} } */ void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c index 9e962a7..2762b7a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c @@ -1,20 +1,20 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=rv32gc_zve32f_zvl64b -mabi=ilp32d" } */ -void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} -void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} -void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} -void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} -void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} -void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} -void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} -void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} -void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} -void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} -void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} -void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} -void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} -void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x2_t'} } */ +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x2_t'} } */ +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x3_t'} } */ +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x3_t'} } */ +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x4_t'} } */ +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x4_t'} } */ +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x5_t'} } */ +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x5_t'} } */ +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x6_t'} } */ +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x6_t'} } */ +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x7_t'} } */ +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x7_t'} } */ +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x8_t'} } */ +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x8_t'} } */ void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} @@ -65,20 +65,20 @@ void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} -void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} -void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} -void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} -void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} -void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} -void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} -void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} -void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} -void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} -void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} -void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} -void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} -void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} -void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x2_t'} } */ +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x2_t'} } */ +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x3_t'} } */ +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x3_t'} } */ +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x4_t'} } */ +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x4_t'} } */ +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x5_t'} } */ +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x5_t'} } */ +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x6_t'} } */ +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x6_t'} } */ +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x7_t'} } */ +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x7_t'} } */ +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x8_t'} } */ +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x8_t'} } */ void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} @@ -115,20 +115,20 @@ void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} -void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} -void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} -void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} -void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} -void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} -void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} -void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} -void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} -void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} -void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} -void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} -void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} -void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} -void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x2_t'} } */ +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x2_t'} } */ +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x3_t'} } */ +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x3_t'} } */ +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x4_t'} } */ +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x4_t'} } */ +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x5_t'} } */ +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x5_t'} } */ +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x6_t'} } */ +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x6_t'} } */ +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x7_t'} } */ +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x7_t'} } */ +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x8_t'} } */ +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x8_t'} } */ void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} @@ -179,13 +179,13 @@ void f___rvv_float16m1_t () {__rvv_float16m1_t t;} /* { dg-error {unknown type n void f___rvv_float16m2_t () {__rvv_float16m2_t t;} /* { dg-error {unknown type name '__rvv_float16m2_t'} } */ void f___rvv_float16m4_t () {__rvv_float16m4_t t;} /* { dg-error {unknown type name '__rvv_float16m4_t'} } */ void f___rvv_float16m8_t () {__rvv_float16m8_t t;} /* { dg-error {unknown type name '__rvv_float16m8_t'} } */ -void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} -void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} -void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} -void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} -void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} -void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} -void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} +void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x2_t'} } */ +void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x3_t'} } */ +void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x4_t'} } */ +void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x5_t'} } */ +void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x6_t'} } */ +void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x7_t'} } */ +void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x8_t'} } */ void f___rvv_float32m1x2_t () {__rvv_float32m1x2_t t;} void f___rvv_float32m1x3_t () {__rvv_float32m1x3_t t;} void f___rvv_float32m1x4_t () {__rvv_float32m1x4_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-18.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-18.c index 402e8f6..95b760f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-18.c @@ -1,20 +1,20 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=rv32gc_zve32x_zvl64b_zvfhmin -mabi=ilp32d" } */ -void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} -void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} -void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} -void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} -void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} -void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} -void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} -void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} -void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} -void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} -void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} -void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} -void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} -void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x2_t'} } */ +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x2_t'} } */ +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x3_t'} } */ +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x3_t'} } */ +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x4_t'} } */ +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x4_t'} } */ +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x5_t'} } */ +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x5_t'} } */ +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x6_t'} } */ +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x6_t'} } */ +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x7_t'} } */ +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x7_t'} } */ +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x8_t'} } */ +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x8_t'} } */ void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} @@ -65,20 +65,20 @@ void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} -void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} -void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} -void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} -void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} -void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} -void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} -void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} -void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} -void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} -void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} -void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} -void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} -void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} -void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x2_t'} } */ +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x2_t'} } */ +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x3_t'} } */ +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x3_t'} } */ +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x4_t'} } */ +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x4_t'} } */ +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x5_t'} } */ +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x5_t'} } */ +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x6_t'} } */ +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x6_t'} } */ +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x7_t'} } */ +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x7_t'} } */ +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x8_t'} } */ +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x8_t'} } */ void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} @@ -115,20 +115,20 @@ void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} -void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} -void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} -void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} -void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} -void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} -void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} -void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} -void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} -void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} -void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} -void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} -void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} -void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} -void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x2_t'} } */ +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x2_t'} } */ +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x3_t'} } */ +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x3_t'} } */ +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x4_t'} } */ +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x4_t'} } */ +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x5_t'} } */ +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x5_t'} } */ +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x6_t'} } */ +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x6_t'} } */ +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x7_t'} } */ +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x7_t'} } */ +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x8_t'} } */ +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x8_t'} } */ void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} @@ -173,13 +173,13 @@ void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} /* { dg-error {unknown type n void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x4_t'} } */ void f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} /* { dg-error {unknown type name '__rvv_int64m4x2_t'} } */ void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m4x2_t'} } */ -void f___rvv_float16mf4x2_t () {__rvv_float16mf4x2_t t;} -void f___rvv_float16mf4x3_t () {__rvv_float16mf4x3_t t;} -void f___rvv_float16mf4x4_t () {__rvv_float16mf4x4_t t;} -void f___rvv_float16mf4x5_t () {__rvv_float16mf4x5_t t;} -void f___rvv_float16mf4x6_t () {__rvv_float16mf4x6_t t;} -void f___rvv_float16mf4x7_t () {__rvv_float16mf4x7_t t;} -void f___rvv_float16mf4x8_t () {__rvv_float16mf4x8_t t;} +void f___rvv_float16mf4x2_t () {__rvv_float16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_float16mf4x2_t'} } */ +void f___rvv_float16mf4x3_t () {__rvv_float16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_float16mf4x3_t'} } */ +void f___rvv_float16mf4x4_t () {__rvv_float16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_float16mf4x4_t'} } */ +void f___rvv_float16mf4x5_t () {__rvv_float16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_float16mf4x5_t'} } */ +void f___rvv_float16mf4x6_t () {__rvv_float16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_float16mf4x6_t'} } */ +void f___rvv_float16mf4x7_t () {__rvv_float16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_float16mf4x7_t'} } */ +void f___rvv_float16mf4x8_t () {__rvv_float16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_float16mf4x8_t'} } */ void f___rvv_float16mf2x2_t () {__rvv_float16mf2x2_t t;} void f___rvv_float16mf2x3_t () {__rvv_float16mf2x3_t t;} void f___rvv_float16mf2x4_t () {__rvv_float16mf2x4_t t;} @@ -198,13 +198,13 @@ void f___rvv_float16m2x2_t () {__rvv_float16m2x2_t t;} void f___rvv_float16m2x3_t () {__rvv_float16m2x3_t t;} void f___rvv_float16m2x4_t () {__rvv_float16m2x4_t t;} void f___rvv_float16m4x2_t () {__rvv_float16m4x2_t t;} -void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} -void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} -void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} -void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} -void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} -void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} -void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} +void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x2_t'} } */ +void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x3_t'} } */ +void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x4_t'} } */ +void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x5_t'} } */ +void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x6_t'} } */ +void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x7_t'} } */ +void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x8_t'} } */ void f___rvv_float32m1x2_t () {__rvv_float32m1x2_t t;} void f___rvv_float32m1x3_t () {__rvv_float32m1x3_t t;} void f___rvv_float32m1x4_t () {__rvv_float32m1x4_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c index 39c8c00..d21b810 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c @@ -51,7 +51,7 @@ foo1 (vint8m1_t a) ** vs1r\.v\tv30,0\(sp\) ** sub\tsp,sp,t0 ** vs1r\.v\tv31,0\(sp\) -** call\tbar2 +** call\tbar2(?:@plt)? ** csrr\tt0,vlenb ** vl1re64\.v\tv31,0\(sp\) ** add\tsp,sp,t0 @@ -96,8 +96,8 @@ foo2 (vint8m1_t a) ** foo3: ** call\tt0,__riscv_save_0 ** vl1re8\.v\tv8,0\(a0\) -** call\tbar1 -** call\tbar2 +** call\tbar1(?:@plt)? +** call\tbar2(?:@plt)? ** tail\t__riscv_restore_0 */ void diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c index 5f8f96f..70a32d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c @@ -10,7 +10,7 @@ void bar2 (); /* ** foo1: ** cm.push\t{ra},\s*-16 -** call\tbar1 +** call\tbar1(?:@plt)? ** cm.popret\t{ra},\s*16 */ void @@ -53,7 +53,7 @@ foo1 (vint8m1_t a) ** vs1r\.v\tv30,0\(sp\) ** sub\tsp,sp,t0 ** vs1r\.v\tv31,0\(sp\) -** call\tbar2 +** call\tbar2(?:@plt)? ** csrr\tt0,vlenb ** vl1re64\.v\tv31,0\(sp\) ** add\tsp,sp,t0 @@ -97,7 +97,7 @@ foo2 (vint8m1_t a) ** foo3: ** cm.push\t{ra},\s*-16 ** vl1re8\.v\tv8,0\(a0\) -** call\tbar1 +** call\tbar1(?:@plt)? ** cm.popret\t{ra},\s*16 */ void diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c index a9f3855..3f2cb2f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c @@ -11,7 +11,7 @@ void bar2 (); ** foo1: ** addi\tsp,sp,-16 ** sd\tra,8\(sp\) -** call\tbar1 +** call\tbar1(?:@plt)? ** ld\tra,8\(sp\) ** addi\tsp,sp,16 ** jr\tra @@ -57,7 +57,7 @@ foo1 (vint8m1_t a) ** vs1r\.v\tv30,0\(sp\) ** sub\tsp,sp,t0 ** vs1r\.v\tv31,0\(sp\) -** call\tbar2 +** call\tbar2(?:@plt)? ** csrr\tt0,vlenb ** vl1re64\.v\tv31,0\(sp\) ** add\tsp,sp,t0 @@ -105,7 +105,7 @@ foo2 (vint8m1_t a) ** addi\tsp,sp,-16 ** sd\tra,8\(sp\) ** vl1re8\.v\tv8,0\(a0\) -** call\tbar1 +** call\tbar1(?:@plt)? ** ld\tra,8\(sp\) ** addi\tsp,sp,16 ** jr\tra diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c index 9edd6cb..3534720 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c @@ -21,7 +21,7 @@ f1 (void *a, void *b) /* Tiny __builtin_memcmp should use libc. ** f2: ** li\s+a\d,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f2 (void *a, void *b) @@ -79,7 +79,7 @@ f5 (void *a, void *b) /* Don't inline if the length is too large for one operation. ** f6: ** li\s+a2,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f6 (void *a, void *b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c index 82aa307..c1c1aae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c @@ -8,7 +8,7 @@ /* Tiny __builtin_memcmp should use libc. ** f1: ** li\s+a\d,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f1 (void *a, void *b) @@ -36,7 +36,7 @@ f2 (void *a, void *b) /* Don't inline if the length is too large for one operation. ** f3: ** li\s+a2,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f3 (void *a, void *b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c index e2dd6a1..ad87038 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c @@ -8,7 +8,7 @@ /* Tiny __builtin_memcmp should use libc. ** f1: ** li\s+a\d,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f1 (void *a, void *b) @@ -53,7 +53,7 @@ f3 (void *a, void *b) /* Don't inline if the length is too large for one operation. ** f4: ** li\s+a2,\d+ -** tail\s+memcmp +** tail\s+memcmp(?:@plt)? */ int f4 (void *a, void *b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c index 654c800..5e35204 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2 -fno-pie" } */ /* { dg-add-options riscv_v } */ /* { dg-final { check-function-bodies "**" "" } } */ @@ -109,4 +109,4 @@ void f3 () memcpy (&a_a, &a_b, sizeof a_a); } -/* { dg-final { scan-assembler-not {\m(tail|call)\s+memcpy\M} } } */ +/* { dg-final { scan-assembler-not {\m(tail|call)\s+memcpy(?:@plt)?\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c index 03e633b..44bf3d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c @@ -52,7 +52,7 @@ f3 (char *a, char const *b) /* Don't vectorise if the move is too large for one operation ** f4: ** li\s+a2,\d+ -** tail\s+memmove +** tail\s+memmove(?:@plt)? */ char * f4 (char *a, char const *b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c index 9bfa39c..4f375e5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c @@ -93,9 +93,9 @@ test_5 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count) /* ** test_6: ** ... -** call\s+__extendhfsf2 +** call\s+__extendhfsf2(?:@plt)? ** ... -** call\s+__truncsfhf2 +** call\s+__truncsfhf2(?:@plt)? ** ... */ void diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c index a22d366..490445f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c @@ -94,7 +94,7 @@ f6 (void *a, int const b) /* Don't vectorise if the move is too large for one operation. ** f7: ** li\s+a2,\d+ -** tail\s+memset +** tail\s+memset(?:@plt)? */ void * f7 (void *a, int const b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c index a108868..876929e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c @@ -44,7 +44,7 @@ f2 (void *a, int const b) /* Don't vectorise if the move is too large for requested lmul. ** f3: ** li\s+a2,\d+ -** tail\s+memset +** tail\s+memset(?:@plt)? */ void * f3 (void *a, int const b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c index 460a8f2..a185916 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c @@ -62,7 +62,7 @@ f3 (void *a, int const b) /* Don't vectorise if the move is too large for requested lmul. ** f4: ** li\s+a2,\d+ -** tail\s+memset +** tail\s+memset(?:@plt)? */ void * f4 (void *a, int const b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c index 7e5758b..375d316 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c @@ -18,7 +18,7 @@ void f (char*); ** ... ** addi\ta0,sp,15 ** andi\ta0,a0,-16 -** call\tf +** call\tf(?:@plt)? ** ... ** lw\tra,12\(sp\) ** lw\ts0,8\(sp\) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl_zve32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl_zve32-1.c new file mode 100644 index 0000000..f6899c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl_zve32-1.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32imafc_zve32f_zvl128b -mabi=ilp32 -O2" } */ + +struct S0 +{ + unsigned a : 15; + int b; + int c; +}; + +struct S1 +{ + struct S0 s0; + int e; +}; + +struct Z +{ + char c; + int z; +} __attribute__((packed)); + +union U +{ + struct S1 s1; + struct Z z; +}; + +int __attribute__((noinline, noclone)) +return_zero (void) +{ + return 0; +} + +volatile union U gu; +struct S0 gs; + +int __attribute__((noinline, noclone)) +check_outcome () +{ + if (gs.a != 6 + || gs.b != 80000) + __builtin_abort (); +} + +int +main (int argc, char *argv[]) +{ + union U u; + struct S1 m; + struct S0 l; + + if (return_zero ()) + u.z.z = 20000; + else + { + u.s1.s0.a = 6; + u.s1.s0.b = 80000; + u.s1.e = 2; + + m = u.s1; + m.s0.c = 0; + l = m.s0; + gs = l; + } + + gu = u; + check_outcome (); + return 0; +} + +/* { dg-final { scan-assembler {vsetivli\s+zero,\s*2,\s*e32,\s*m1,\s*t[au],\s*m[au]} } } */ +/* { dg-final { scan-assembler {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl_zve32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl_zve32-2.c new file mode 100644 index 0000000..dd81f8b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl_zve32-2.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g_zve32x_zvl128b -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +typedef unsigned int V2SI __attribute__((vector_size(8))); + +V2SI v1, v2; + +/* Make sure we won't use mf2 mode even vector register is OK to hold for + ELEN=32. */ +void foo1() +{ +/* +** foo1: +** ... +** vsetivli zero,2,e32,m1,ta,ma +** ... +** vle32\.v v[0-9]+,0\([a-x][0-9]+\) +** ... +** vse32\.v v[0-9]+,0\([a-x][0-9]+\) +** ... +** ret +*/ + v1 = v2; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c index 6e027a5..84d3c4c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ +/* { dg-do compile { target { { ! riscv_abi_e } && rv64 } } } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c new file mode 100644 index 0000000..303f3cb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long long sub (unsigned long long a, unsigned long long b) +{ + b = (b << 50) >> 49; + unsigned int x = a + b; + return x; +} + +/* { dg-final { scan-assembler-not {\msh1add} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c new file mode 100644 index 0000000..883cce2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c @@ -0,0 +1,21 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-options "-march=rv64gc_zba -mabi=lp64d -O2" } */ + +struct { + unsigned a : 14; + unsigned b : 3; +} c; + +unsigned long long d; +void e (unsigned long long *f, long p2) { *f = p2; } +signed g; +long i; + +int main () { + c.b = 4; + i = -(-c.a - (3023282U + c.a + g)); + e (&d, i); + if (d != 3023282) + __builtin_abort (); + __builtin_exit (0); +} diff --git a/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c b/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c index f7d8f44..be304e7 100644 --- a/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c +++ b/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c @@ -10,7 +10,7 @@ bar (); **fool_rv32e: ** cm.push {ra}, -32 ** ... -** call bar +** call bar(?:@plt)? ** ... ** lw a[0-5],32\(sp\) ** ... diff --git a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-1.c b/gcc/testsuite/gcc.target/s390/target-attribute/tattr-1.c index ff57344..7344af3 100644 --- a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-1.c +++ b/gcc/testsuite/gcc.target/s390/target-attribute/tattr-1.c @@ -1,6 +1,6 @@ /* Functional tests for the "target" attribute and pragma. */ -/* { dg-do compile */ +/* { dg-do compile } */ /* { dg-require-effective-target target_attribute } */ /* { dg-options "-O3 -march=zEC12 -mzarch" } */ diff --git a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-2.c b/gcc/testsuite/gcc.target/s390/target-attribute/tattr-2.c index 739c2ea..3a6e4bb 100644 --- a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-2.c +++ b/gcc/testsuite/gcc.target/s390/target-attribute/tattr-2.c @@ -1,6 +1,6 @@ /* Functional tests for the "target" attribute and pragma. */ -/* { dg-do compile */ +/* { dg-do compile } */ /* { dg-require-effective-target target_attribute } */ /* { dg-options "-O3 -march=zEC12 -mno-htm -fno-ipa-icf" } */ |