diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
101 files changed, 2338 insertions, 158 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/attributes_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/attributes_6.c index 907637f..eeba533 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/attributes_6.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/attributes_6.c @@ -29,7 +29,7 @@ test_add (fixed_int8_t x, fixed_int8_t y) } /* -** test_add_gnu: +** test_add_gnu: {target aarch64_big_endian } ** ( ** add (z[0-9]+\.b), (?:z0\.b, z1\.b|z1\.b, z0\.b) ** ptrue (p[0-7])\.b, vl32 @@ -41,6 +41,12 @@ test_add (fixed_int8_t x, fixed_int8_t y) ** ) ** ret */ +/* +** test_add_gnu: {target aarch64_little_endian } +** add (z[0-9]+)\.b, (?:z0\.b, z1\.b|z1\.b, z0\.b) +** str \1, \[x8\] +** ret +*/ gnu_int8_t test_add_gnu (fixed_int8_t x, fixed_int8_t y) { diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_5.c index f06a74a..05e266a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_5.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_5.c @@ -11,8 +11,7 @@ extern "C" { /* ** load_vl1: -** ptrue (p[0-7])\.[bhsd], vl1 -** ld1h z0\.h, \1/z, \[x0\] +** ldr h0, \[x0\] ** ret */ svint16_t @@ -22,7 +21,12 @@ load_vl1 (int16_t *ptr) } /* -** load_vl2: +** load_vl2: { target aarch64_little_endian } +** ldr s0, \[x0\] +** ret +*/ +/* +** load_vl2: { target aarch64_big_endian } ** ptrue (p[0-7])\.h, vl2 ** ld1h z0\.h, \1/z, \[x0\] ** ret @@ -46,7 +50,12 @@ load_vl3 (int16_t *ptr) } /* -** load_vl4: +** load_vl4: { target aarch64_little_endian } +** ldr d0, \[x0\] +** ret +*/ +/* +** load_vl4: { target aarch64_big_endian } ** ptrue (p[0-7])\.h, vl4 ** ld1h z0\.h, \1/z, \[x0\] ** ret @@ -94,7 +103,12 @@ load_vl7 (int16_t *ptr) } /* -** load_vl8: +** load_vl8: { target aarch64_little_endian } +** ldr q0, \[x0\] +** ret +*/ +/* +** load_vl8: { target aarch64_big_endian } ** ptrue (p[0-7])\.h, vl8 ** ld1h z0\.h, \1/z, \[x0\] ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_14.c b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_14.c index b65826b..d423dcf 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_14.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_14.c @@ -9,5 +9,7 @@ uint64_t f2(uint64_t *ptr, int n) { return res; } -/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d,} 5 } } */ +/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d,} 5 {target aarch64_big_endian} } } */ +/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d,} 1 {target aarch64_little_endian} } } */ +/* { dg-final { scan-assembler-times {\tldr\tz[0-9]+,} 4 {target aarch64_little_endian} } } */ /* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.d,} 8 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_4.c b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_4.c index a7ecfe3..93af4c1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_4.c @@ -9,4 +9,5 @@ vset (int *restrict dst, int *restrict src, int count) *dst++ = 1; } -/* { dg-final { scan-assembler-times {\tst1w\tz} 1 } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz} 1 {target aarch64_big_endian} } } */ +/* { dg-final { scan-assembler-times {\tstr\tz} 1 {target aarch64_little_endian} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_5.c b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_5.c index f3a29fc..fab49ed 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_5.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_5.c @@ -9,5 +9,6 @@ vset (int *restrict dst, int *restrict src, int count) *dst++ = 1; } -/* { dg-final { scan-assembler-times {\tst1w\tz} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz} 2 {target aarch64_big_endian} } } */ +/* { dg-final { scan-assembler-times {\tstr\tz} 2 {target aarch64_little_endian} } } */ /* { dg-final { scan-assembler-not {\tstp\tq} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_6.c b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_6.c index 565e1e3..160667b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_6.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_6.c @@ -9,4 +9,5 @@ vset (int *restrict dst, int *restrict src, int count) *dst++ = 1; } -/* { dg-final { scan-assembler-times {\tst1w\tz} 1 } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz} 1 {target aarch64_big_endian} } } */ +/* { dg-final { scan-assembler-times {\tstr\tz} 1 {target aarch64_little_endian} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_7.c b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_7.c index 31057c0..b71c673 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_7.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_7.c @@ -9,4 +9,5 @@ vset (int *restrict dst, int *restrict src, int count) *dst++ = 1; } -/* { dg-final { scan-assembler-times {\tst1w\tz} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz} 2 {target aarch64_big_endian} } } */ +/* { dg-final { scan-assembler-times {\tstr\tz} 2 {target aarch64_little_endian} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/ldst_ptrue_pat_128_to_neon.c b/gcc/testsuite/gcc.target/aarch64/sve/ldst_ptrue_pat_128_to_neon.c new file mode 100644 index 0000000..2d47c1f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/ldst_ptrue_pat_128_to_neon.c @@ -0,0 +1,81 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target aarch64_little_endian } */ + +#include <arm_sve.h> + +#define TEST(TYPE, TY, W, B) \ + sv##TYPE \ + ld1_##TY##W##B##_1 (TYPE *x) \ + { \ + svbool_t pg = svwhilelt_b##B (0, W); \ + return svld1_##TY##B (pg, x); \ + } \ + sv##TYPE \ + ld1_##TY##W##B##_2 (TYPE *x) \ + { \ + svbool_t pg = svptrue_pat_b##B ((enum svpattern) (W > 8 ? 9 : W)); \ + return svld1_##TY##B (pg, x); \ + } \ + void \ + st1_##TY##W##B##_1 (TYPE *x, sv##TYPE data) \ + { \ + svbool_t pg = svwhilelt_b##B (0, W); \ + return svst1_##TY##B (pg, x, data); \ + } \ + void \ + st1_##TY##W##B##_2 (TYPE *x, sv##TYPE data) \ + { \ + svbool_t pg = svptrue_pat_b##B ((enum svpattern) (W > 8 ? 9 : W)); \ + return svst1_##TY##B (pg, x, data); \ + } \ + +#define TEST64(TYPE, TY, B) \ + TEST (TYPE, TY, 1, B) \ + TEST (TYPE, TY, 2, B) \ + +#define TEST32(TYPE, TY, B) \ + TEST64 (TYPE, TY, B) \ + TEST (TYPE, TY, 4, B) \ + +#define TEST16(TYPE, TY, B) \ + TEST32 (TYPE, TY, B) \ + TEST (TYPE, TY, 8, B) \ + +#define TEST8(TYPE, TY, B) \ + TEST16 (TYPE, TY, B) \ + TEST (TYPE, TY, 16, B) + +#define T(TYPE, TY, B) \ + TEST##B (TYPE, TY, B) + +T (bfloat16_t, bf, 16) +T (float16_t, f, 16) +T (float32_t, f, 32) +T (float64_t, f, 64) +T (int8_t, s, 8) +T (int16_t, s, 16) +T (int32_t, s, 32) +T (int64_t, s, 64) +T (uint8_t, u, 8) +T (uint16_t, u, 16) +T (uint32_t, u, 32) +T (uint64_t, u, 64) + +/* { dg-final { scan-assembler-times {\tldr\tq0, \[x0\]} 24 } } */ +/* { dg-final { scan-assembler-times {\tldr\td0, \[x0\]} 24 } } */ +/* { dg-final { scan-assembler-times {\tldr\ts0, \[x0\]} 18 } } */ +/* { dg-final { scan-assembler-times {\tldr\th0, \[x0\]} 12 } } */ +/* { dg-final { scan-assembler-times {\tldr\tb0, \[x0\]} 4 } } */ + +/* { dg-final { scan-assembler-times {\tstr\tq0, \[x0\]} 24 } } */ +/* { dg-final { scan-assembler-times {\tstr\td0, \[x0\]} 24 } } */ +/* { dg-final { scan-assembler-times {\tstr\ts0, \[x0\]} 18 } } */ +/* { dg-final { scan-assembler-times {\tstr\th0, \[x0\]} 12 } } */ +/* { dg-final { scan-assembler-times {\tstr\tb0, \[x0\]} 4 } } */ + +svint8_t foo (int8_t *x) +{ + return svld1_s8 (svptrue_b16 (), x); +} +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.h, all\n\tld1b} 1 } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f16.c index 50e77f9..8d480a8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f16.c @@ -6,7 +6,7 @@ #include <stdarg.h> /* -** callee_0: +** callee_0: {target aarch64_big_endian} ** ... ** ld1h (z[0-9]+\.h), (p[0-7])/z, \[x1\] ** ... @@ -14,6 +14,15 @@ ** ... ** ret */ +/* +** callee_0: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x1\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_0 (int16_t *ptr, ...) { @@ -27,7 +36,7 @@ callee_0 (int16_t *ptr, ...) } /* -** caller_0: +** caller_0: {target aarch64_big_endian} ** ... ** fmov (z[0-9]+\.h), #9\.0[^\n]* ** ... @@ -35,6 +44,15 @@ callee_0 (int16_t *ptr, ...) ** ... ** ret */ +/* +** caller_0: {target aarch64_little_endian} +** ... +** fmov (z[0-9]+)\.h, #9\.0[^\n]* +** ... +** str \1, \[x1\] +** ... +** ret +*/ void __attribute__((noipa)) caller_0 (int16_t *ptr) { @@ -42,7 +60,7 @@ caller_0 (int16_t *ptr) } /* -** callee_1: +** callee_1: {target aarch64_big_endian} ** ... ** ld1h (z[0-9]+\.h), (p[0-7])/z, \[x2\] ** ... @@ -50,6 +68,15 @@ caller_0 (int16_t *ptr) ** ... ** ret */ +/* +** callee_1: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x2\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_1 (int16_t *ptr, ...) { @@ -64,7 +91,7 @@ callee_1 (int16_t *ptr, ...) } /* -** caller_1: +** caller_1: {target aarch64_big_endian} ** ... ** fmov (z[0-9]+\.h), #9\.0[^\n]* ** ... @@ -72,6 +99,15 @@ callee_1 (int16_t *ptr, ...) ** ... ** ret */ +/* +** caller_1: {target aarch64_little_endian} +** ... +** fmov (z[0-9]+)\.h, #9\.0[^\n]* +** ... +** str \1, \[x2\] +** ... +** ret +*/ void __attribute__((noipa)) caller_1 (int16_t *ptr) { @@ -79,7 +115,7 @@ caller_1 (int16_t *ptr) } /* -** callee_7: +** callee_7: {target aarch64_big_endian} ** ... ** ld1h (z[0-9]+\.h), (p[0-7])/z, \[x7\] ** ... @@ -87,6 +123,15 @@ caller_1 (int16_t *ptr) ** ... ** ret */ +/* +** callee_7: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x7\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_7 (int16_t *ptr, ...) { @@ -106,7 +151,7 @@ callee_7 (int16_t *ptr, ...) } /* -** caller_7: +** caller_7: {target aarch64_big_endian} ** ... ** fmov (z[0-9]+\.h), #9\.0[^\n]* ** ... @@ -114,6 +159,15 @@ callee_7 (int16_t *ptr, ...) ** ... ** ret */ +/* +** caller_7: {target aarch64_little_endian} +** ... +** fmov (z[0-9]+)\.h, #9\.0[^\n]* +** ... +** str \1, \[x7\] +** ... +** ret +*/ void __attribute__((noipa)) caller_7 (int16_t *ptr) { @@ -122,7 +176,7 @@ caller_7 (int16_t *ptr) /* FIXME: We should be able to get rid of the va_list object. */ /* -** callee_8: +** callee_8: {target aarch64_big_endian} ** sub sp, sp, #([0-9]+) ** ... ** ldr (x[0-9]+), \[sp, \1\] @@ -133,6 +187,18 @@ caller_7 (int16_t *ptr) ** ... ** ret */ +/* +** callee_8: {target aarch64_little_endian} +** sub sp, sp, #([0-9]+) +** ... +** ldr (x[0-9]+), \[sp, \1\] +** ... +** ldr (z[0-9]+), \[\2\] +** ... +** str \3, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_8 (int16_t *ptr, ...) { @@ -153,7 +219,7 @@ callee_8 (int16_t *ptr, ...) } /* -** caller_8: +** caller_8: {target aarch64_big_endian} ** ... ** fmov (z[0-9]+\.h), #9\.0[^\n]* ** ... @@ -163,6 +229,17 @@ callee_8 (int16_t *ptr, ...) ** ... ** ret */ +/* +** caller_8: {target aarch64_little_endian} +** ... +** fmov (z[0-9]+)\.h, #9\.0[^\n]* +** ... +** str \1, \[(x[0-9]+)\] +** ... +** str \2, \[sp\] +** ... +** ret +*/ void __attribute__((noipa)) caller_8 (int16_t *ptr) { diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f32.c index e7b092a..b3c699d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f32.c @@ -6,7 +6,7 @@ #include <stdarg.h> /* -** callee_0: +** callee_0: {target aarch64_big_endian} ** ... ** ld1w (z[0-9]+\.s), (p[0-7])/z, \[x1\] ** ... @@ -14,6 +14,15 @@ ** ... ** ret */ +/* +** callee_0: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x1\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_0 (int32_t *ptr, ...) { @@ -27,7 +36,7 @@ callee_0 (int32_t *ptr, ...) } /* -** caller_0: +** caller_0: {target aarch64_big_endian} ** ... ** fmov (z[0-9]+\.s), #9\.0[^\n]* ** ... @@ -35,6 +44,15 @@ callee_0 (int32_t *ptr, ...) ** ... ** ret */ +/* +** caller_0: {target aarch64_little_endian} +** ... +** fmov (z[0-9]+)\.s, #9\.0[^\n]* +** ... +** str \1, \[x1\] +** ... +** ret +*/ void __attribute__((noipa)) caller_0 (int32_t *ptr) { @@ -42,7 +60,7 @@ caller_0 (int32_t *ptr) } /* -** callee_1: +** callee_1: {target aarch64_big_endian} ** ... ** ld1w (z[0-9]+\.s), (p[0-7])/z, \[x2\] ** ... @@ -50,6 +68,15 @@ caller_0 (int32_t *ptr) ** ... ** ret */ +/* +** callee_1: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x2\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_1 (int32_t *ptr, ...) { @@ -64,7 +91,7 @@ callee_1 (int32_t *ptr, ...) } /* -** caller_1: +** caller_1: {target aarch64_big_endian} ** ... ** fmov (z[0-9]+\.s), #9\.0[^\n]* ** ... @@ -72,6 +99,15 @@ callee_1 (int32_t *ptr, ...) ** ... ** ret */ +/* +** caller_1: {target aarch64_little_endian} +** ... +** fmov (z[0-9]+)\.s, #9\.0[^\n]* +** ... +** str \1, \[x2\] +** ... +** ret +*/ void __attribute__((noipa)) caller_1 (int32_t *ptr) { @@ -79,7 +115,7 @@ caller_1 (int32_t *ptr) } /* -** callee_7: +** callee_7: {target aarch64_big_endian} ** ... ** ld1w (z[0-9]+\.s), (p[0-7])/z, \[x7\] ** ... @@ -87,6 +123,15 @@ caller_1 (int32_t *ptr) ** ... ** ret */ +/* +** callee_7: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x7\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_7 (int32_t *ptr, ...) { @@ -106,7 +151,7 @@ callee_7 (int32_t *ptr, ...) } /* -** caller_7: +** caller_7: {target aarch64_big_endian} ** ... ** fmov (z[0-9]+\.s), #9\.0[^\n]* ** ... @@ -114,6 +159,15 @@ callee_7 (int32_t *ptr, ...) ** ... ** ret */ +/* +** caller_7: {target aarch64_little_endian} +** ... +** fmov (z[0-9]+)\.s, #9\.0[^\n]* +** ... +** str \1, \[x7\] +** ... +** ret +*/ void __attribute__((noipa)) caller_7 (int32_t *ptr) { @@ -122,7 +176,7 @@ caller_7 (int32_t *ptr) /* FIXME: We should be able to get rid of the va_list object. */ /* -** callee_8: +** callee_8: {target aarch64_big_endian} ** sub sp, sp, #([0-9]+) ** ... ** ldr (x[0-9]+), \[sp, \1\] @@ -133,6 +187,18 @@ caller_7 (int32_t *ptr) ** ... ** ret */ +/* +** callee_8: {target aarch64_little_endian} +** sub sp, sp, #([0-9]+) +** ... +** ldr (x[0-9]+), \[sp, \1\] +** ... +** ldr (z[0-9]+), \[\2\] +** ... +** str \3, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_8 (int32_t *ptr, ...) { @@ -153,7 +219,7 @@ callee_8 (int32_t *ptr, ...) } /* -** caller_8: +** caller_8: {target aarch64_big_endian} ** ... ** fmov (z[0-9]+\.s), #9\.0[^\n]* ** ... @@ -163,6 +229,17 @@ callee_8 (int32_t *ptr, ...) ** ... ** ret */ +/* +** caller_8: {target aarch64_little_endian} +** ... +** fmov (z[0-9]+)\.s, #9\.0[^\n]* +** ... +** str \1, \[(x[0-9]+)\] +** ... +** str \2, \[sp\] +** ... +** ret +*/ void __attribute__((noipa)) caller_8 (int32_t *ptr) { diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f64.c index c3389a8..7078afc 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f64.c @@ -6,7 +6,7 @@ #include <stdarg.h> /* -** callee_0: +** callee_0: {target aarch64_big_endian} ** ... ** ld1d (z[0-9]+\.d), (p[0-7])/z, \[x1\] ** ... @@ -14,6 +14,15 @@ ** ... ** ret */ +/* +** callee_0: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x1\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_0 (int64_t *ptr, ...) { @@ -27,7 +36,7 @@ callee_0 (int64_t *ptr, ...) } /* -** caller_0: +** caller_0: {target aarch64_big_endian} ** ... ** fmov (z[0-9]+\.d), #9\.0[^\n]* ** ... @@ -35,6 +44,15 @@ callee_0 (int64_t *ptr, ...) ** ... ** ret */ +/* +** caller_0: {target aarch64_little_endian} +** ... +** fmov (z[0-9]+)\.d, #9\.0[^\n]* +** ... +** str \1, \[x1\] +** ... +** ret +*/ void __attribute__((noipa)) caller_0 (int64_t *ptr) { @@ -42,7 +60,7 @@ caller_0 (int64_t *ptr) } /* -** callee_1: +** callee_1: {target aarch64_big_endian} ** ... ** ld1d (z[0-9]+\.d), (p[0-7])/z, \[x2\] ** ... @@ -50,6 +68,15 @@ caller_0 (int64_t *ptr) ** ... ** ret */ +/* +** callee_1: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x2\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_1 (int64_t *ptr, ...) { @@ -64,7 +91,7 @@ callee_1 (int64_t *ptr, ...) } /* -** caller_1: +** caller_1: {target aarch64_big_endian} ** ... ** fmov (z[0-9]+\.d), #9\.0[^\n]* ** ... @@ -72,6 +99,15 @@ callee_1 (int64_t *ptr, ...) ** ... ** ret */ +/* +** caller_1: {target aarch64_little_endian} +** ... +** fmov (z[0-9]+)\.d, #9\.0[^\n]* +** ... +** str \1, \[x2\] +** ... +** ret +*/ void __attribute__((noipa)) caller_1 (int64_t *ptr) { @@ -79,7 +115,7 @@ caller_1 (int64_t *ptr) } /* -** callee_7: +** callee_7: {target aarch64_big_endian} ** ... ** ld1d (z[0-9]+\.d), (p[0-7])/z, \[x7\] ** ... @@ -87,6 +123,15 @@ caller_1 (int64_t *ptr) ** ... ** ret */ +/* +** callee_7: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x7\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_7 (int64_t *ptr, ...) { @@ -106,7 +151,7 @@ callee_7 (int64_t *ptr, ...) } /* -** caller_7: +** caller_7: {target aarch64_big_endian} ** ... ** fmov (z[0-9]+\.d), #9\.0[^\n]* ** ... @@ -114,6 +159,15 @@ callee_7 (int64_t *ptr, ...) ** ... ** ret */ +/* +** caller_7: {target aarch64_little_endian} +** ... +** fmov (z[0-9]+)\.d, #9\.0[^\n]* +** ... +** str \1, \[x7\] +** ... +** ret +*/ void __attribute__((noipa)) caller_7 (int64_t *ptr) { @@ -122,7 +176,7 @@ caller_7 (int64_t *ptr) /* FIXME: We should be able to get rid of the va_list object. */ /* -** callee_8: +** callee_8: {target aarch64_big_endian} ** sub sp, sp, #([0-9]+) ** ... ** ldr (x[0-9]+), \[sp, \1\] @@ -133,6 +187,18 @@ caller_7 (int64_t *ptr) ** ... ** ret */ +/* +** callee_8: +** sub sp, sp, #([0-9]+) +** ... +** ldr (x[0-9]+), \[sp, \1\] +** ... +** ldr (z[0-9]+), \[\2\] +** ... +** str \3, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_8 (int64_t *ptr, ...) { @@ -153,7 +219,7 @@ callee_8 (int64_t *ptr, ...) } /* -** caller_8: +** caller_8: {target aarch64_big_endian} ** ... ** fmov (z[0-9]+\.d), #9\.0[^\n]* ** ... @@ -163,6 +229,17 @@ callee_8 (int64_t *ptr, ...) ** ... ** ret */ +/* +** caller_8: {target aarch64_little_endian} +** ... +** fmov (z[0-9]+)\.d, #9\.0[^\n]* +** ... +** str \1, \[(x[0-9]+)\] +** ... +** str \2, \[sp\] +** ... +** ret +*/ void __attribute__((noipa)) caller_8 (int64_t *ptr) { diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_mf8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_mf8.c index 2877787..fcbac37 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_mf8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_mf8.c @@ -8,9 +8,9 @@ /* ** callee_0: ** ... -** ld1b (z[0-9]+\.b), (p[0-7])/z, \[x1\] +** ldr (z[0-9]+), \[x1\] ** ... -** st1b \1, \2, \[x0\] +** str \1, \[x0\] ** ... ** ret */ @@ -32,9 +32,9 @@ callee_0 (mfloat8_t *ptr, ...) ** ... ** umov (w[0-9]+), v0.b\[0\] ** ... -** mov (z[0-9]+\.b), \1 +** mov (z[0-9]+)\.b, \1 ** ... -** st1b \2, p[0-7], \[x1\] +** str \2, \[x1\] ** ... ** ret */ @@ -47,9 +47,9 @@ caller_0 (mfloat8_t *ptr, mfloat8_t in) /* ** callee_1: ** ... -** ld1b (z[0-9]+\.b), (p[0-7])/z, \[x2\] +** ldr (z[0-9]+), \[x2\] ** ... -** st1b \1, p[0-7], \[x0\] +** str \1, \[x0\] ** ... ** ret */ @@ -72,9 +72,9 @@ callee_1 (mfloat8_t *ptr, ...) ** ... ** umov (w[0-9]+), v0.b\[0\] ** ... -** mov (z[0-9]+\.b), \1 +** mov (z[0-9]+)\.b, \1 ** ... -** st1b \2, p[0-7], \[x2\] +** str \2, \[x2\] ** ... ** ret */ @@ -87,9 +87,9 @@ caller_1 (mfloat8_t *ptr, mfloat8_t in) /* ** callee_7: ** ... -** ld1b (z[0-9]+\.b), (p[0-7])/z, \[x7\] +** ldr (z[0-9]+), \[x7\] ** ... -** st1b \1, p[0-7], \[x0\] +** str \1, \[x0\] ** ... ** ret */ @@ -117,9 +117,9 @@ callee_7 (mfloat8_t *ptr, ...) ** ... ** umov (w[0-9]+), v0.b\[0\] ** ... -** mov (z[0-9]+\.b), \1 +** mov (z[0-9]+)\.b, \1 ** ... -** st1b \2, p[0-7], \[x7\] +** str \2, \[x7\] ** ... ** ret */ @@ -136,9 +136,9 @@ caller_7 (mfloat8_t *ptr, mfloat8_t in) ** ... ** ldr (x[0-9]+), \[sp, \1\] ** ... -** ld1b (z[0-9]+\.b), (p[0-7])/z, \[\2\] +** ldr (z[0-9]+), \[\2\] ** ... -** st1b \3, \4, \[x0\] +** str \3, \[x0\] ** ... ** ret */ @@ -167,9 +167,9 @@ callee_8 (mfloat8_t *ptr, ...) ** ... ** umov (w[0-9]+), v0.b\[0\] ** ... -** mov (z[0-9]+\.b), \1 +** mov (z[0-9]+)\.b, \1 ** ... -** st1b \2, p[0-7], \[(x[0-9]+)\] +** str \2, \[(x[0-9]+)\] ** ... ** str \3, \[sp\] ** ... diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s16.c index 3c644e1..e65e64f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s16.c @@ -6,7 +6,7 @@ #include <stdarg.h> /* -** callee_0: +** callee_0: {target aarch64_big_endian} ** ... ** ld1h (z[0-9]+\.h), (p[0-7])/z, \[x1\] ** ... @@ -14,6 +14,15 @@ ** ... ** ret */ +/* +** callee_0: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x1\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_0 (int16_t *ptr, ...) { @@ -27,7 +36,7 @@ callee_0 (int16_t *ptr, ...) } /* -** caller_0: +** caller_0: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.h), #42 ** ... @@ -35,6 +44,15 @@ callee_0 (int16_t *ptr, ...) ** ... ** ret */ +/* +** caller_0: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.h, #42 +** ... +** str \1, \[x1\] +** ... +** ret +*/ void __attribute__((noipa)) caller_0 (int16_t *ptr) { @@ -42,7 +60,7 @@ caller_0 (int16_t *ptr) } /* -** callee_1: +** callee_1: {target aarch64_big_endian} ** ... ** ld1h (z[0-9]+\.h), (p[0-7])/z, \[x2\] ** ... @@ -50,6 +68,15 @@ caller_0 (int16_t *ptr) ** ... ** ret */ +/* +** callee_1: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x2\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_1 (int16_t *ptr, ...) { @@ -64,7 +91,7 @@ callee_1 (int16_t *ptr, ...) } /* -** caller_1: +** caller_1: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.h), #42 ** ... @@ -72,6 +99,15 @@ callee_1 (int16_t *ptr, ...) ** ... ** ret */ +/* +** caller_1: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.h, #42 +** ... +** str \1, \[x2\] +** ... +** ret +*/ void __attribute__((noipa)) caller_1 (int16_t *ptr) { @@ -79,7 +115,7 @@ caller_1 (int16_t *ptr) } /* -** callee_7: +** callee_7: {target aarch64_big_endian} ** ... ** ld1h (z[0-9]+\.h), (p[0-7])/z, \[x7\] ** ... @@ -87,6 +123,15 @@ caller_1 (int16_t *ptr) ** ... ** ret */ +/* +** callee_7: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x7\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_7 (int16_t *ptr, ...) { @@ -106,7 +151,7 @@ callee_7 (int16_t *ptr, ...) } /* -** caller_7: +** caller_7: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.h), #42 ** ... @@ -114,6 +159,15 @@ callee_7 (int16_t *ptr, ...) ** ... ** ret */ +/* +** caller_7: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.h, #42 +** ... +** str \1, \[x7\] +** ... +** ret +*/ void __attribute__((noipa)) caller_7 (int16_t *ptr) { @@ -122,7 +176,7 @@ caller_7 (int16_t *ptr) /* FIXME: We should be able to get rid of the va_list object. */ /* -** callee_8: +** callee_8: {target aarch64_big_endian} ** sub sp, sp, #([0-9]+) ** ... ** ldr (x[0-9]+), \[sp, \1\] @@ -133,6 +187,18 @@ caller_7 (int16_t *ptr) ** ... ** ret */ +/* +** callee_8: {target aarch64_little_endian} +** sub sp, sp, #([0-9]+) +** ... +** ldr (x[0-9]+), \[sp, \1\] +** ... +** ldr (z[0-9]+), \[\2\] +** ... +** str \3, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_8 (int16_t *ptr, ...) { @@ -153,7 +219,7 @@ callee_8 (int16_t *ptr, ...) } /* -** caller_8: +** caller_8: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.h), #42 ** ... @@ -163,6 +229,17 @@ callee_8 (int16_t *ptr, ...) ** ... ** ret */ +/* +** caller_8: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.h, #42 +** ... +** str \1, \[(x[0-9]+)\] +** ... +** str \2, \[sp\] +** ... +** ret +*/ void __attribute__((noipa)) caller_8 (int16_t *ptr) { diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s32.c index 652d609..6488a5f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s32.c @@ -6,7 +6,7 @@ #include <stdarg.h> /* -** callee_0: +** callee_0: {target aarch64_big_endian} ** ... ** ld1w (z[0-9]+\.s), (p[0-7])/z, \[x1\] ** ... @@ -14,6 +14,15 @@ ** ... ** ret */ +/* +** callee_0: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x1\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_0 (int32_t *ptr, ...) { @@ -27,7 +36,7 @@ callee_0 (int32_t *ptr, ...) } /* -** caller_0: +** caller_0: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.s), #42 ** ... @@ -35,6 +44,15 @@ callee_0 (int32_t *ptr, ...) ** ... ** ret */ +/* +** caller_0: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.s, #42 +** ... +** str \1, \[x1\] +** ... +** ret +*/ void __attribute__((noipa)) caller_0 (int32_t *ptr) { @@ -42,7 +60,7 @@ caller_0 (int32_t *ptr) } /* -** callee_1: +** callee_1: {target aarch64_big_endian} ** ... ** ld1w (z[0-9]+\.s), (p[0-7])/z, \[x2\] ** ... @@ -50,6 +68,15 @@ caller_0 (int32_t *ptr) ** ... ** ret */ +/* +** callee_1: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x2\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_1 (int32_t *ptr, ...) { @@ -64,7 +91,7 @@ callee_1 (int32_t *ptr, ...) } /* -** caller_1: +** caller_1: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.s), #42 ** ... @@ -72,6 +99,15 @@ callee_1 (int32_t *ptr, ...) ** ... ** ret */ +/* +** caller_1: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.s, #42 +** ... +** str \1, \[x2\] +** ... +** ret +*/ void __attribute__((noipa)) caller_1 (int32_t *ptr) { @@ -79,7 +115,7 @@ caller_1 (int32_t *ptr) } /* -** callee_7: +** callee_7: {target aarch64_big_endian} ** ... ** ld1w (z[0-9]+\.s), (p[0-7])/z, \[x7\] ** ... @@ -87,6 +123,15 @@ caller_1 (int32_t *ptr) ** ... ** ret */ +/* +** callee_7: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x7\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_7 (int32_t *ptr, ...) { @@ -106,7 +151,7 @@ callee_7 (int32_t *ptr, ...) } /* -** caller_7: +** caller_7: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.s), #42 ** ... @@ -114,6 +159,15 @@ callee_7 (int32_t *ptr, ...) ** ... ** ret */ +/* +** caller_7: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.s, #42 +** ... +** str \1, \[x7\] +** ... +** ret +*/ void __attribute__((noipa)) caller_7 (int32_t *ptr) { @@ -122,7 +176,7 @@ caller_7 (int32_t *ptr) /* FIXME: We should be able to get rid of the va_list object. */ /* -** callee_8: +** callee_8: {target aarch64_big_endian} ** sub sp, sp, #([0-9]+) ** ... ** ldr (x[0-9]+), \[sp, \1\] @@ -133,6 +187,18 @@ caller_7 (int32_t *ptr) ** ... ** ret */ +/* +** callee_8: {target aarch64_little_endian} +** sub sp, sp, #([0-9]+) +** ... +** ldr (x[0-9]+), \[sp, \1\] +** ... +** ldr (z[0-9]+), \[\2\] +** ... +** str \3, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_8 (int32_t *ptr, ...) { @@ -153,7 +219,7 @@ callee_8 (int32_t *ptr, ...) } /* -** caller_8: +** caller_8: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.s), #42 ** ... @@ -163,6 +229,17 @@ callee_8 (int32_t *ptr, ...) ** ... ** ret */ +/* +** caller_8: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.s, #42 +** ... +** str \1, \[(x[0-9]+)\] +** ... +** str \2, \[sp\] +** ... +** ret +*/ void __attribute__((noipa)) caller_8 (int32_t *ptr) { diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s64.c index 72ea6a3..4b77b4f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s64.c @@ -6,7 +6,7 @@ #include <stdarg.h> /* -** callee_0: +** callee_0: {target aarch64_big_endian} ** ... ** ld1d (z[0-9]+\.d), (p[0-7])/z, \[x1\] ** ... @@ -14,6 +14,15 @@ ** ... ** ret */ +/* +** callee_0: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x1\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_0 (int64_t *ptr, ...) { @@ -27,7 +36,7 @@ callee_0 (int64_t *ptr, ...) } /* -** caller_0: +** caller_0: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.d), #42 ** ... @@ -35,6 +44,15 @@ callee_0 (int64_t *ptr, ...) ** ... ** ret */ +/* +** caller_0: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.d, #42 +** ... +** str \1, \[x1\] +** ... +** ret +*/ void __attribute__((noipa)) caller_0 (int64_t *ptr) { @@ -42,7 +60,7 @@ caller_0 (int64_t *ptr) } /* -** callee_1: +** callee_1: {target aarch64_big_endian} ** ... ** ld1d (z[0-9]+\.d), (p[0-7])/z, \[x2\] ** ... @@ -50,6 +68,15 @@ caller_0 (int64_t *ptr) ** ... ** ret */ +/* +** callee_1: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x2\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_1 (int64_t *ptr, ...) { @@ -64,7 +91,7 @@ callee_1 (int64_t *ptr, ...) } /* -** caller_1: +** caller_1: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.d), #42 ** ... @@ -72,6 +99,15 @@ callee_1 (int64_t *ptr, ...) ** ... ** ret */ +/* +** caller_1: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.d, #42 +** ... +** str \1, \[x2\] +** ... +** ret +*/ void __attribute__((noipa)) caller_1 (int64_t *ptr) { @@ -79,7 +115,7 @@ caller_1 (int64_t *ptr) } /* -** callee_7: +** callee_7: {target aarch64_big_endian} ** ... ** ld1d (z[0-9]+\.d), (p[0-7])/z, \[x7\] ** ... @@ -87,6 +123,15 @@ caller_1 (int64_t *ptr) ** ... ** ret */ +/* +** callee_7: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x7\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_7 (int64_t *ptr, ...) { @@ -106,7 +151,7 @@ callee_7 (int64_t *ptr, ...) } /* -** caller_7: +** caller_7: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.d), #42 ** ... @@ -114,6 +159,15 @@ callee_7 (int64_t *ptr, ...) ** ... ** ret */ +/* +** caller_7: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.d, #42 +** ... +** str \1, \[x7\] +** ... +** ret +*/ void __attribute__((noipa)) caller_7 (int64_t *ptr) { @@ -122,7 +176,7 @@ caller_7 (int64_t *ptr) /* FIXME: We should be able to get rid of the va_list object. */ /* -** callee_8: +** callee_8: {target aarch64_big_endian} ** sub sp, sp, #([0-9]+) ** ... ** ldr (x[0-9]+), \[sp, \1\] @@ -133,6 +187,18 @@ caller_7 (int64_t *ptr) ** ... ** ret */ +/* +** callee_8: {target aarch64_little_endian} +** sub sp, sp, #([0-9]+) +** ... +** ldr (x[0-9]+), \[sp, \1\] +** ... +** ldr (z[0-9]+), \[\2\] +** ... +** str \3, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_8 (int64_t *ptr, ...) { @@ -153,7 +219,7 @@ callee_8 (int64_t *ptr, ...) } /* -** caller_8: +** caller_8: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.d), #42 ** ... @@ -163,6 +229,17 @@ callee_8 (int64_t *ptr, ...) ** ... ** ret */ +/* +** caller_8: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.d, #42 +** ... +** str \1, \[(x[0-9]+)\] +** ... +** str \2, \[sp\] +** ... +** ret +*/ void __attribute__((noipa)) caller_8 (int64_t *ptr) { diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s8.c index 02f4bec..e686b3e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s8.c @@ -8,9 +8,9 @@ /* ** callee_0: ** ... -** ld1b (z[0-9]+\.b), (p[0-7])/z, \[x1\] +** ldr (z[0-9]+), \[x1\] ** ... -** st1b \1, \2, \[x0\] +** str \1, \[x0\] ** ... ** ret */ @@ -29,9 +29,9 @@ callee_0 (int8_t *ptr, ...) /* ** caller_0: ** ... -** mov (z[0-9]+\.b), #42 +** mov (z[0-9]+)\.b, #42 ** ... -** st1b \1, p[0-7], \[x1\] +** str \1, \[x1\] ** ... ** ret */ @@ -44,9 +44,9 @@ caller_0 (int8_t *ptr) /* ** callee_1: ** ... -** ld1b (z[0-9]+\.b), (p[0-7])/z, \[x2\] +** ldr (z[0-9]+), \[x2\] ** ... -** st1b \1, p[0-7], \[x0\] +** str \1, \[x0\] ** ... ** ret */ @@ -66,9 +66,9 @@ callee_1 (int8_t *ptr, ...) /* ** caller_1: ** ... -** mov (z[0-9]+\.b), #42 +** mov (z[0-9]+)\.b, #42 ** ... -** st1b \1, p[0-7], \[x2\] +** str \1, \[x2\] ** ... ** ret */ @@ -81,9 +81,9 @@ caller_1 (int8_t *ptr) /* ** callee_7: ** ... -** ld1b (z[0-9]+\.b), (p[0-7])/z, \[x7\] +** ldr (z[0-9]+), \[x7\] ** ... -** st1b \1, p[0-7], \[x0\] +** str \1, \[x0\] ** ... ** ret */ @@ -108,9 +108,9 @@ callee_7 (int8_t *ptr, ...) /* ** caller_7: ** ... -** mov (z[0-9]+\.b), #42 +** mov (z[0-9]+)\.b, #42 ** ... -** st1b \1, p[0-7], \[x7\] +** str \1, \[x7\] ** ... ** ret */ @@ -127,9 +127,9 @@ caller_7 (int8_t *ptr) ** ... ** ldr (x[0-9]+), \[sp, \1\] ** ... -** ld1b (z[0-9]+\.b), (p[0-7])/z, \[\2\] +** ldr (z[0-9]+), \[\2\] ** ... -** st1b \3, \4, \[x0\] +** str \3, \[x0\] ** ... ** ret */ @@ -155,9 +155,9 @@ callee_8 (int8_t *ptr, ...) /* ** caller_8: ** ... -** mov (z[0-9]+\.b), #42 +** mov (z[0-9]+)\.b, #42 ** ... -** st1b \1, p[0-7], \[(x[0-9]+)\] +** str \1, \[(x[0-9]+)\] ** ... ** str \2, \[sp\] ** ... diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u16.c index b60d448..74ef4da 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u16.c @@ -6,7 +6,7 @@ #include <stdarg.h> /* -** callee_0: +** callee_0: {target aarch64_big_endian} ** ... ** ld1h (z[0-9]+\.h), (p[0-7])/z, \[x1\] ** ... @@ -14,6 +14,15 @@ ** ... ** ret */ +/* +** callee_0: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x1\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_0 (int16_t *ptr, ...) { @@ -27,7 +36,7 @@ callee_0 (int16_t *ptr, ...) } /* -** caller_0: +** caller_0: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.h), #42 ** ... @@ -35,6 +44,15 @@ callee_0 (int16_t *ptr, ...) ** ... ** ret */ +/* +** caller_0: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.h, #42 +** ... +** str \1, \[x1\] +** ... +** ret +*/ void __attribute__((noipa)) caller_0 (int16_t *ptr) { @@ -42,7 +60,7 @@ caller_0 (int16_t *ptr) } /* -** callee_1: +** callee_1: {target aarch64_big_endian} ** ... ** ld1h (z[0-9]+\.h), (p[0-7])/z, \[x2\] ** ... @@ -50,6 +68,15 @@ caller_0 (int16_t *ptr) ** ... ** ret */ +/* +** callee_1: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x2\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_1 (int16_t *ptr, ...) { @@ -64,7 +91,7 @@ callee_1 (int16_t *ptr, ...) } /* -** caller_1: +** caller_1: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.h), #42 ** ... @@ -72,6 +99,15 @@ callee_1 (int16_t *ptr, ...) ** ... ** ret */ +/* +** caller_1: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.h, #42 +** ... +** str \1, \[x2\] +** ... +** ret +*/ void __attribute__((noipa)) caller_1 (int16_t *ptr) { @@ -79,7 +115,7 @@ caller_1 (int16_t *ptr) } /* -** callee_7: +** callee_7: {target aarch64_big_endian} ** ... ** ld1h (z[0-9]+\.h), (p[0-7])/z, \[x7\] ** ... @@ -87,6 +123,15 @@ caller_1 (int16_t *ptr) ** ... ** ret */ +/* +** callee_7: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x7\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_7 (int16_t *ptr, ...) { @@ -106,7 +151,7 @@ callee_7 (int16_t *ptr, ...) } /* -** caller_7: +** caller_7: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.h), #42 ** ... @@ -114,6 +159,15 @@ callee_7 (int16_t *ptr, ...) ** ... ** ret */ +/* +** caller_7: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.h, #42 +** ... +** str \1, \[x7\] +** ... +** ret +*/ void __attribute__((noipa)) caller_7 (int16_t *ptr) { @@ -122,7 +176,7 @@ caller_7 (int16_t *ptr) /* FIXME: We should be able to get rid of the va_list object. */ /* -** callee_8: +** callee_8: {target aarch64_big_endian} ** sub sp, sp, #([0-9]+) ** ... ** ldr (x[0-9]+), \[sp, \1\] @@ -133,6 +187,18 @@ caller_7 (int16_t *ptr) ** ... ** ret */ +/* +** callee_8: {target aarch64_little_endian} +** sub sp, sp, #([0-9]+) +** ... +** ldr (x[0-9]+), \[sp, \1\] +** ... +** ldr (z[0-9]+), \[\2\] +** ... +** str \3, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_8 (int16_t *ptr, ...) { @@ -153,7 +219,7 @@ callee_8 (int16_t *ptr, ...) } /* -** caller_8: +** caller_8: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.h), #42 ** ... @@ -163,6 +229,17 @@ callee_8 (int16_t *ptr, ...) ** ... ** ret */ +/* +** caller_8: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.h, #42 +** ... +** str \1, \[(x[0-9]+)\] +** ... +** str \2, \[sp\] +** ... +** ret +*/ void __attribute__((noipa)) caller_8 (int16_t *ptr) { diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u32.c index 5f01464..4f9ff78 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u32.c @@ -6,7 +6,7 @@ #include <stdarg.h> /* -** callee_0: +** callee_0: {target aarch64_big_endian} ** ... ** ld1w (z[0-9]+\.s), (p[0-7])/z, \[x1\] ** ... @@ -14,6 +14,15 @@ ** ... ** ret */ +/* +** callee_0: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x1\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_0 (int32_t *ptr, ...) { @@ -27,7 +36,7 @@ callee_0 (int32_t *ptr, ...) } /* -** caller_0: +** caller_0: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.s), #42 ** ... @@ -35,6 +44,15 @@ callee_0 (int32_t *ptr, ...) ** ... ** ret */ +/* +** caller_0: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.s, #42 +** ... +** str \1, \[x1\] +** ... +** ret +*/ void __attribute__((noipa)) caller_0 (int32_t *ptr) { @@ -42,7 +60,7 @@ caller_0 (int32_t *ptr) } /* -** callee_1: +** callee_1: {target aarch64_big_endian} ** ... ** ld1w (z[0-9]+\.s), (p[0-7])/z, \[x2\] ** ... @@ -50,6 +68,15 @@ caller_0 (int32_t *ptr) ** ... ** ret */ +/* +** callee_1: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x2\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_1 (int32_t *ptr, ...) { @@ -64,7 +91,7 @@ callee_1 (int32_t *ptr, ...) } /* -** caller_1: +** caller_1: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.s), #42 ** ... @@ -72,6 +99,15 @@ callee_1 (int32_t *ptr, ...) ** ... ** ret */ +/* +** caller_1: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.s, #42 +** ... +** str \1, \[x2\] +** ... +** ret +*/ void __attribute__((noipa)) caller_1 (int32_t *ptr) { @@ -79,7 +115,7 @@ caller_1 (int32_t *ptr) } /* -** callee_7: +** callee_7: {target aarch64_big_endian} ** ... ** ld1w (z[0-9]+\.s), (p[0-7])/z, \[x7\] ** ... @@ -87,6 +123,15 @@ caller_1 (int32_t *ptr) ** ... ** ret */ +/* +** callee_7: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x7\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_7 (int32_t *ptr, ...) { @@ -106,7 +151,7 @@ callee_7 (int32_t *ptr, ...) } /* -** caller_7: +** caller_7: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.s), #42 ** ... @@ -114,6 +159,15 @@ callee_7 (int32_t *ptr, ...) ** ... ** ret */ +/* +** caller_7: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.s, #42 +** ... +** str \1, \[x7\] +** ... +** ret +*/ void __attribute__((noipa)) caller_7 (int32_t *ptr) { @@ -122,7 +176,7 @@ caller_7 (int32_t *ptr) /* FIXME: We should be able to get rid of the va_list object. */ /* -** callee_8: +** callee_8: {target aarch64_big_endian} ** sub sp, sp, #([0-9]+) ** ... ** ldr (x[0-9]+), \[sp, \1\] @@ -133,6 +187,18 @@ caller_7 (int32_t *ptr) ** ... ** ret */ +/* +** callee_8: {target aarch64_little_endian} +** sub sp, sp, #([0-9]+) +** ... +** ldr (x[0-9]+), \[sp, \1\] +** ... +** ldr (z[0-9]+), \[\2\] +** ... +** str \3, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_8 (int32_t *ptr, ...) { @@ -153,7 +219,7 @@ callee_8 (int32_t *ptr, ...) } /* -** caller_8: +** caller_8: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.s), #42 ** ... @@ -163,6 +229,17 @@ callee_8 (int32_t *ptr, ...) ** ... ** ret */ +/* +** caller_8: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.s, #42 +** ... +** str \1, \[(x[0-9]+)\] +** ... +** str \2, \[sp\] +** ... +** ret +*/ void __attribute__((noipa)) caller_8 (int32_t *ptr) { diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u64.c index 986739f..27e437b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u64.c @@ -6,7 +6,7 @@ #include <stdarg.h> /* -** callee_0: +** callee_0: {target aarch64_big_endian} ** ... ** ld1d (z[0-9]+\.d), (p[0-7])/z, \[x1\] ** ... @@ -14,6 +14,15 @@ ** ... ** ret */ +/* +** callee_0: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x1\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_0 (int64_t *ptr, ...) { @@ -27,7 +36,7 @@ callee_0 (int64_t *ptr, ...) } /* -** caller_0: +** caller_0: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.d), #42 ** ... @@ -35,6 +44,15 @@ callee_0 (int64_t *ptr, ...) ** ... ** ret */ +/* +** caller_0: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.d, #42 +** ... +** str \1, \[x1\] +** ... +** ret +*/ void __attribute__((noipa)) caller_0 (int64_t *ptr) { @@ -42,7 +60,7 @@ caller_0 (int64_t *ptr) } /* -** callee_1: +** callee_1: {target aarch64_big_endian} ** ... ** ld1d (z[0-9]+\.d), (p[0-7])/z, \[x2\] ** ... @@ -50,6 +68,15 @@ caller_0 (int64_t *ptr) ** ... ** ret */ +/* +** callee_1: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x2\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_1 (int64_t *ptr, ...) { @@ -64,7 +91,7 @@ callee_1 (int64_t *ptr, ...) } /* -** caller_1: +** caller_1: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.d), #42 ** ... @@ -72,6 +99,15 @@ callee_1 (int64_t *ptr, ...) ** ... ** ret */ +/* +** caller_1: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.d, #42 +** ... +** str \1, \[x2\] +** ... +** ret +*/ void __attribute__((noipa)) caller_1 (int64_t *ptr) { @@ -79,7 +115,7 @@ caller_1 (int64_t *ptr) } /* -** callee_7: +** callee_7: {target aarch64_big_endian} ** ... ** ld1d (z[0-9]+\.d), (p[0-7])/z, \[x7\] ** ... @@ -87,6 +123,15 @@ caller_1 (int64_t *ptr) ** ... ** ret */ +/* +** callee_7: {target aarch64_little_endian} +** ... +** ldr (z[0-9]+), \[x7\] +** ... +** str \1, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_7 (int64_t *ptr, ...) { @@ -106,7 +151,7 @@ callee_7 (int64_t *ptr, ...) } /* -** caller_7: +** caller_7: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.d), #42 ** ... @@ -114,6 +159,15 @@ callee_7 (int64_t *ptr, ...) ** ... ** ret */ +/* +** caller_7: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.d, #42 +** ... +** str \1, \[x7\] +** ... +** ret +*/ void __attribute__((noipa)) caller_7 (int64_t *ptr) { @@ -122,7 +176,7 @@ caller_7 (int64_t *ptr) /* FIXME: We should be able to get rid of the va_list object. */ /* -** callee_8: +** callee_8: {target aarch64_big_endian} ** sub sp, sp, #([0-9]+) ** ... ** ldr (x[0-9]+), \[sp, \1\] @@ -133,6 +187,18 @@ caller_7 (int64_t *ptr) ** ... ** ret */ +/* +** callee_8: {target aarch64_little_endian} +** sub sp, sp, #([0-9]+) +** ... +** ldr (x[0-9]+), \[sp, \1\] +** ... +** ldr (z[0-9]+), \[\2\] +** ... +** str \3, \[x0\] +** ... +** ret +*/ void __attribute__((noipa)) callee_8 (int64_t *ptr, ...) { @@ -153,7 +219,7 @@ callee_8 (int64_t *ptr, ...) } /* -** caller_8: +** caller_8: {target aarch64_big_endian} ** ... ** mov (z[0-9]+\.d), #42 ** ... @@ -163,6 +229,17 @@ callee_8 (int64_t *ptr, ...) ** ... ** ret */ +/* +** caller_8: {target aarch64_little_endian} +** ... +** mov (z[0-9]+)\.d, #42 +** ... +** str \1, \[(x[0-9]+)\] +** ... +** str \2, \[sp\] +** ... +** ret +*/ void __attribute__((noipa)) caller_8 (int64_t *ptr) { diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u8.c index 533cba67..d43a6da 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u8.c @@ -8,9 +8,9 @@ /* ** callee_0: ** ... -** ld1b (z[0-9]+\.b), (p[0-7])/z, \[x1\] +** ldr (z[0-9]+), \[x1\] ** ... -** st1b \1, \2, \[x0\] +** str \1, \[x0\] ** ... ** ret */ @@ -29,9 +29,9 @@ callee_0 (int8_t *ptr, ...) /* ** caller_0: ** ... -** mov (z[0-9]+\.b), #42 +** mov (z[0-9]+)\.b, #42 ** ... -** st1b \1, p[0-7], \[x1\] +** str \1, \[x1\] ** ... ** ret */ @@ -44,9 +44,9 @@ caller_0 (int8_t *ptr) /* ** callee_1: ** ... -** ld1b (z[0-9]+\.b), (p[0-7])/z, \[x2\] +** ldr (z[0-9]+), \[x2\] ** ... -** st1b \1, p[0-7], \[x0\] +** str \1, \[x0\] ** ... ** ret */ @@ -66,9 +66,9 @@ callee_1 (int8_t *ptr, ...) /* ** caller_1: ** ... -** mov (z[0-9]+\.b), #42 +** mov (z[0-9]+)\.b, #42 ** ... -** st1b \1, p[0-7], \[x2\] +** str \1, \[x2\] ** ... ** ret */ @@ -81,9 +81,9 @@ caller_1 (int8_t *ptr) /* ** callee_7: ** ... -** ld1b (z[0-9]+\.b), (p[0-7])/z, \[x7\] +** ldr (z[0-9]+), \[x7\] ** ... -** st1b \1, p[0-7], \[x0\] +** str \1, \[x0\] ** ... ** ret */ @@ -108,9 +108,9 @@ callee_7 (int8_t *ptr, ...) /* ** caller_7: ** ... -** mov (z[0-9]+\.b), #42 +** mov (z[0-9]+)\.b, #42 ** ... -** st1b \1, p[0-7], \[x7\] +** str \1, \[x7\] ** ... ** ret */ @@ -127,9 +127,9 @@ caller_7 (int8_t *ptr) ** ... ** ldr (x[0-9]+), \[sp, \1\] ** ... -** ld1b (z[0-9]+\.b), (p[0-7])/z, \[\2\] +** ldr (z[0-9]+), \[\2\] ** ... -** st1b \3, \4, \[x0\] +** str \3, \[x0\] ** ... ** ret */ @@ -155,9 +155,9 @@ callee_8 (int8_t *ptr, ...) /* ** caller_8: ** ... -** mov (z[0-9]+\.b), #42 +** mov (z[0-9]+)\.b, #42 ** ... -** st1b \1, p[0-7], \[(x[0-9]+)\] +** str \1, \[(x[0-9]+)\] ** ... ** str \2, \[sp\] ** ... diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c index 985cd0c..f07900b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c @@ -19,5 +19,7 @@ foo (void) /* We should operate on aligned vectors. */ /* { dg-final { scan-assembler {\t(adrp|adr)\tx[0-9]+, (x|\.LANCHOR0)\n} } } */ /* We should unroll the loop three times. */ -/* { dg-final { scan-assembler-times "\tst1w\t" 3 } } */ +/* { dg-final { scan-assembler-times "\tst1w\t" 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times "\tst1w\t" 2 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times "\tstr\t" 1 { target aarch64_little_endian } } } */ /* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.s, vl7\n.*\teor\tp[0-9]+\.b, (p[0-9]+)/z, (\1\.b, \2\.b|\2\.b, \1\.b)\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/ptrue_ldr_str.c b/gcc/testsuite/gcc.target/aarch64/sve/ptrue_ldr_str.c new file mode 100644 index 0000000..c3bfa98 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/ptrue_ldr_str.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target aarch64_little_endian } */ + +#include <arm_sve.h> + +#define TEST(TYPE, TY, B) \ + sv##TYPE ld_##TY (TYPE *x) \ + { \ + return svld1_##TY(svptrue_b##B (), x); \ + } \ + void st_##TY (TYPE *x, sv##TYPE data) \ + { \ + svst1_##TY(svptrue_b##B (), x, data); \ + } + +TEST(bfloat16_t, bf16, 16) +TEST(float16_t, f16, 16) +TEST(float32_t, f32, 32) +TEST(float64_t, f64, 64) +TEST(uint8_t, u8, 8) +TEST(uint16_t, u16, 16) +TEST(uint32_t, u32, 32) +TEST(uint64_t, u64, 64) +TEST(int8_t, s8, 8) +TEST(int16_t, s16, 16) +TEST(int32_t, s32, 32) +TEST(int64_t, s64, 64) + +/* { dg-final { scan-assembler-times {\tldr\tz0, \[x0\]} 12 } } */ +/* { dg-final { scan-assembler-times {\tstr\tz0, \[x0\]} 12 } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/aarch64/sve/single_1.c b/gcc/testsuite/gcc.target/aarch64/sve/single_1.c index d9bb97e..be71921 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/single_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/single_1.c @@ -40,12 +40,13 @@ TEST_LOOP (double, 3.0) /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0e\+0\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #3\.0e\+0\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b, vl32\n} 11 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b, vl32\n} 9 { target aarch64_big_endian } } } */ -/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.b,} 2 } } */ -/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.h,} 3 } } */ -/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 } } */ -/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 } } */ +/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.h,} 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tstr\tz[0-9]+, \[x0\]} 2 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tstr\tz[0-9]+, \[x0\]} 11 { target aarch64_little_endian } } } */ /* { dg-final { scan-assembler-not {\twhile} } } */ /* { dg-final { scan-assembler-not {\tb} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/single_2.c b/gcc/testsuite/gcc.target/aarch64/sve/single_2.c index d27eead..8692984 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/single_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/single_2.c @@ -16,12 +16,13 @@ /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0e\+0\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #3\.0e\+0\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b, vl64\n} 11 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b, vl64\n} 9 { target aarch64_big_endian } } } */ -/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.b,} 2 } } */ -/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.h,} 3 } } */ -/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 } } */ -/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 } } */ +/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.h,} 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tstr\tz[0-9]+, \[x0\]} 2 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tstr\tz[0-9]+, \[x0\]} 11 { target aarch64_little_endian } } } */ /* { dg-final { scan-assembler-not {\twhile} } } */ /* { dg-final { scan-assembler-not {\tb} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/single_3.c b/gcc/testsuite/gcc.target/aarch64/sve/single_3.c index 313a72d..10799fd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/single_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/single_3.c @@ -16,12 +16,13 @@ /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0e\+0\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #3\.0e\+0\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b, vl128\n} 11 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b, vl128\n} 9 { target aarch64_big_endian } } } */ -/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.b,} 2 } } */ -/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.h,} 3 } } */ -/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 } } */ -/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 } } */ +/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.h,} 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tstr\tz[0-9]+, \[x0\]} 2 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tstr\tz[0-9]+, \[x0\]} 11 { target aarch64_little_endian } } } */ /* { dg-final { scan-assembler-not {\twhile} } } */ /* { dg-final { scan-assembler-not {\tb} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/single_4.c b/gcc/testsuite/gcc.target/aarch64/sve/single_4.c index 4f46654..53658a8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/single_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/single_4.c @@ -16,12 +16,13 @@ /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0e\+0\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #3\.0e\+0\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b, vl256\n} 11 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b, vl256\n} 9 { target aarch64_big_endian } } } */ -/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.b,} 2 } } */ -/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.h,} 3 } } */ -/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 } } */ -/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 } } */ +/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.h,} 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tstr\tz[0-9]+, \[x0\]} 2 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {\tstr\tz[0-9]+, \[x0\]} 11 { target aarch64_little_endian } } } */ /* { dg-final { scan-assembler-not {\twhile} } } */ /* { dg-final { scan-assembler-not {\tb} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/while_7.c b/gcc/testsuite/gcc.target/aarch64/sve/while_7.c index a66a20d..ab2fa36 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/while_7.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/while_7.c @@ -19,7 +19,7 @@ TEST_ALL (ADD_LOOP) -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b, vl8\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.h, vl8\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tldr\td[0-9]+, \[x0\]} 1 } } */ +/* { dg-final { scan-assembler-times {\tldr\tq[0-9]+, \[x0\]} 1 } } */ /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.s,} 2 } } */ /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/while_9.c b/gcc/testsuite/gcc.target/aarch64/sve/while_9.c index dd3f404..99940dd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/while_9.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/while_9.c @@ -19,7 +19,7 @@ TEST_ALL (ADD_LOOP) -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b, vl16\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tldr\tq[0-9]+\, \[x0\]} 1 } } */ /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.h,} 2 } } */ /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.s,} 2 } } */ /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-arith-1.c b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-arith-1.c index 52b8737..f3fea52 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-arith-1.c +++ b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-arith-1.c @@ -106,8 +106,7 @@ TEST_CMP (greaterthanqual, >=, int16x8_t, float16x8_t) /* { dg-final { scan-assembler-times {vdiv\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 13 } } */ /* For float16_t. */ -/* { dg-final { scan-assembler-times {vcmp\.f32\ts[0-9]+, s[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {vcmpe\.f32\ts[0-9]+, s[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {vcmp\.f32\ts[0-9]+, s[0-9]+} 6 } } */ /* For float16x4_t. */ /* { dg-final { scan-assembler-times {vceq\.f16\td[0-9]+, d[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr117839-3a.c b/gcc/testsuite/gcc.target/i386/pr117839-3a.c new file mode 100644 index 0000000..81afa9d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr117839-3a.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ +/* { dg-final { scan-assembler-times "xor\[a-z\]*\[\t \]*%xmm\[0-9\]\+,\[^,\]*" 1 } } */ + +typedef char v4qi __attribute__((vector_size(4))); +typedef char v16qi __attribute__((vector_size(16))); + +v4qi a; +v16qi b; +void +foo (v4qi* c, v16qi* d) +{ + v4qi sum = __extension__(v4qi){0, 0, 0, 0}; + v16qi sum2 = __extension__(v16qi){0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0}; + for (int i = 0; i != 100; i++) + sum += c[i]; + for (int i = 0 ; i != 100; i++) + sum2 += d[i]; + a = sum; + b = sum2; +} diff --git a/gcc/testsuite/gcc.target/i386/pr117839-3b.c b/gcc/testsuite/gcc.target/i386/pr117839-3b.c new file mode 100644 index 0000000..a599c28 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr117839-3b.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3" } */ +/* { dg-final { scan-assembler-times "xor\[a-z\]*\[\t \]*%xmm\[0-9\]\+,\[^,\]*" 1 } } */ + +#include "pr117839-3a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr119919.c b/gcc/testsuite/gcc.target/i386/pr119919.c index ed64656..e39819f 100644 --- a/gcc/testsuite/gcc.target/i386/pr119919.c +++ b/gcc/testsuite/gcc.target/i386/pr119919.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -msse2 -fdump-tree-vect-details" } */ +/* { dg-options "-O2 -msse2 -fdump-tree-vect-details -mtune=znver1" } */ int a[9*9]; bool b[9]; void test() diff --git a/gcc/testsuite/gcc.target/riscv/arch-45.c b/gcc/testsuite/gcc.target/riscv/arch-45.c new file mode 100644 index 0000000..afffb99 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-45.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_svadu -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-46.c b/gcc/testsuite/gcc.target/riscv/arch-46.c new file mode 100644 index 0000000..2a06217 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-46.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_svade -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-47.c b/gcc/testsuite/gcc.target/riscv/arch-47.c new file mode 100644 index 0000000..06bc80f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-47.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_sdtrig_ssstrict -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-48.c b/gcc/testsuite/gcc.target/riscv/arch-48.c new file mode 100644 index 0000000..58a558e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-48.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zama16b -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/pr114512.c b/gcc/testsuite/gcc.target/riscv/pr114512.c new file mode 100644 index 0000000..205071c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114512.c @@ -0,0 +1,109 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define MASK 0x1f +typedef unsigned int utype; +#else +#define ONE 1ULL +#define MASK 0x3f +typedef unsigned long utype; +#endif + + +_Bool my_isxdigit_1(unsigned char ch) { + utype mask1 = 0x03FF007E; + if (!((mask1 >> (ch & MASK)) & 1)) + return 0; + + return 1; +} + +_Bool my_isxdigit_1a(unsigned char ch) { + utype mask2 = 0x58; + if (!((mask2 >> (ch >> 4)) & 1)) + return 0; + + return 1; +} + +_Bool my_isxdigit_2(unsigned char ch) { + utype mask1 = 0x03FF007E; + if (!(mask1 & (ONE << (ch & MASK)))) + return 0; + + return 1; +} + +_Bool my_isxdigit_2a(unsigned char ch) { + utype mask2 = 0x58; + if (!(mask2 & (ONE << (ch >> 4)))) + return 0; + + return 1; +} + +_Bool my_isxdigit_3(unsigned char ch) { + utype mask1 = 0x7E00FFC0; + if (!((mask1 << (MASK - (ch & MASK))) >> MASK)) + return 0; + + return 1; +} + +_Bool my_isxdigit_3a(unsigned char ch) { + utype mask2 = 0x7E00FFC0; + if (!((mask2 << (MASK - ((ch >> 4) & MASK))) >> MASK)) + return 0; + + return 1; +} + +_Bool my_isxdigit_1_parm(unsigned char ch, utype mask1) { + if (!((mask1 >> (ch & MASK)) & 1)) + return 0; + + return 1; +} + +_Bool my_isxdigit_1a_parm(unsigned char ch, utype mask2) { + if (!((mask2 >> (ch >> 4)) & 1)) + return 0; + + return 1; +} + +_Bool my_isxdigit_2_parm(unsigned char ch, utype mask1) { + if (!(mask1 & (ONE << (ch & MASK)))) + return 0; + + return 1; +} + +_Bool my_isxdigit_2a_parm(unsigned char ch, utype mask2) { + if (!(mask2 & (ONE << (ch >> 4)))) + return 0; + + return 1; +} + +_Bool my_isxdigit_3_parm(unsigned char ch, utype mask1) { + if (!((mask1 << (MASK - (ch & MASK))) >> MASK)) + return 0; + + return 1; +} + +_Bool my_isxdigit_3a_parm(unsigned char ch, utype mask2) { + if (!((mask2 << (MASK - ((ch >> 4) & MASK))) >> MASK)) + return 0; + + return 1; +} + +/* Each test should generate a single bext. */ +/* { dg-final { scan-assembler-times "bext\t" 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr120137.c b/gcc/testsuite/gcc.target/riscv/pr120137.c new file mode 100644 index 0000000..c55a1c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120137.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mrvv-vector-bits=zvl -mabi=lp64" } */ + +char b[13][13]; +void c() { + for (int d = 0; d < 13; ++d) + for (int e = 0; e < 13; ++e) + b[d][e] = e == 0 ? -98 : 38; +} + + + diff --git a/gcc/testsuite/gcc.target/riscv/pr120154.c b/gcc/testsuite/gcc.target/riscv/pr120154.c new file mode 100644 index 0000000..fd849ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120154.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gv -mabi=lp64" } */ + + + +typedef __attribute__((__vector_size__(4))) char V; + +V g; + +V +bar(V a, V b) +{ + V s = a + b + g; + return s; +} + +V +foo() +{ + return bar((V){20}, (V){23, 150}); +} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h new file mode 100644 index 0000000..db802bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h @@ -0,0 +1,61 @@ +#ifndef HAVE_DEFINED_VX_VF_BINARY_H +#define HAVE_DEFINED_VX_VF_BINARY_H + +#include <stdint.h> + +#define DEF_VX_BINARY_CASE_0(T, OP) \ +void \ +test_vx_binary_case_0 (T * restrict out, T * restrict in, T x, unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + out[i] = in[i] OP x; \ +} +#define DEF_VX_BINARY_CASE_0_WRAP(T, OP) DEF_VX_BINARY_CASE_0(T, OP) +#define RUN_VX_BINARY_CASE_0(out, in, x, n) test_vx_binary_case_0(out, in, x, n) +#define RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) RUN_VX_BINARY_CASE_0(out, in, x, n) + +#define VX_BINARY_BODY(op) \ + out[k + 0] = in[k + 0] op tmp; \ + out[k + 1] = in[k + 1] op tmp; \ + k += 2; + +#define VX_BINARY_BODY_X4(op) \ + VX_BINARY_BODY(op) \ + VX_BINARY_BODY(op) + +#define VX_BINARY_BODY_X8(op) \ + VX_BINARY_BODY_X4(op) \ + VX_BINARY_BODY_X4(op) + +#define VX_BINARY_BODY_X16(op) \ + VX_BINARY_BODY_X8(op) \ + VX_BINARY_BODY_X8(op) + +#define VX_BINARY_BODY_X32(op) \ + VX_BINARY_BODY_X16(op) \ + VX_BINARY_BODY_X16(op) + +#define VX_BINARY_BODY_X64(op) \ + VX_BINARY_BODY_X32(op) \ + VX_BINARY_BODY_X32(op) + +#define VX_BINARY_BODY_X128(op) \ + VX_BINARY_BODY_X64(op) \ + VX_BINARY_BODY_X64(op) + +#define DEF_VX_BINARY_CASE_1(T, OP, BODY) \ +void \ +test_vx_binary_case_1 (T * restrict out, T * restrict in, T x, unsigned n) \ +{ \ + unsigned k = 0; \ + T tmp = x + 3; \ + \ + while (k < n) \ + { \ + tmp = tmp ^ 0x3f; \ + BODY(OP) \ + } \ +} +#define DEF_VX_BINARY_CASE_1_WRAP(T, OP, BODY) DEF_VX_BINARY_CASE_1(T, OP, BODY) + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h new file mode 100644 index 0000000..11a32cb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -0,0 +1,401 @@ +#ifndef HAVE_DEFINED_VX_BINARY_DATA_H +#define HAVE_DEFINED_VX_BINARY_DATA_H + +#define N 16 + +#define TEST_BINARY_DATA(T, NAME) test_##T##_##NAME##_data +#define TEST_BINARY_DATA_WRAP(T, NAME) TEST_BINARY_DATA(T, NAME) + +int8_t TEST_BINARY_DATA(int8_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + }, + { + { 127 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 127, 127, 127, 127, + 126, 126, 126, 126, + -1, -1, -1, -1, + 125, 125, 125, 125, + }, + }, + { + { -128 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + -128, -128, -128, -128, + -127, -127, -127, -127, + -1, -1, -1, -1, + -126, -126, -126, -126, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + }, + { + { 32767 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 32767, 32767, 32767, 32767, + 32766, 32766, 32766, 32766, + -1, -1, -1, -1, + 32765, 32765, 32765, 32765, + }, + }, + { + { -32768 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + -1, -1, -1, -1, + -32766, -32766, -32766, -32766, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + }, + { + { 2147483647 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483646, 2147483646, 2147483646, 2147483646, + -1, -1, -1, -1, + 2147483645, 2147483645, 2147483645, 2147483645, + }, + }, + { + { -2147483648 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + -1, -1, -1, -1, + -2147483646, -2147483646, -2147483646, -2147483646, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + }, + { + { 9223372036854775807ll }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, + -1, -1, -1, -1, + 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, + }, + }, + { + { -9223372036854775808ull }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + }, + { + { 127 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 128, 128, 128, 128, + }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 254, 254, 254, 254, + 255, 255, 255, 255, + }, + }, + { + { 253 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 255, 255, 255, 255, + }, + { + 253, 253, 253, 253, + 254, 254, 254, 254, + 255, 255, 255, 255, + 252, 252, 252, 252, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + }, + { + { 32767 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + }, + }, + { + { 65533 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 65535, 65535, 65535, 65535, + }, + { + 65533, 65533, 65533, 65533, + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + 65532, 65532, 65532, 65532, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + }, + { + { 2147483647 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + }, + { + { 4294967293 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 4294967293, 4294967293, 4294967293, 4294967293, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967292, 4294967292, 4294967292, 4294967292, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + }, + { + { 9223372036854775807ull }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + }, + { + { 18446744073709551613ull }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + { + 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, + }, + }, +}; + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h new file mode 100644 index 0000000..bb35184 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h @@ -0,0 +1,26 @@ +#ifndef HAVE_DEFINED_VX_BINARY_RUN_H +#define HAVE_DEFINED_VX_BINARY_RUN_H + +int +main () +{ + unsigned i, k; + T out[N]; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + T x = TEST_DATA[i][0][0]; + T *in = TEST_DATA[i][1]; + T *expect = TEST_DATA[i][2]; + + TEST_RUN (out, in, x, N); + + for (k = 0; k < N; k++) + if (out[k] != expect[k]) + __builtin_abort (); + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c new file mode 100644 index 0000000..6de21a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(int16_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c new file mode 100644 index 0000000..f46be7a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(int32_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c new file mode 100644 index 0000000..2b57b28 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(int64_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c new file mode 100644 index 0000000..e139284 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(int8_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c new file mode 100644 index 0000000..0266d44 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint16_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c new file mode 100644 index 0000000..c541733 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint32_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c new file mode 100644 index 0000000..e9e2162 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint64_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c new file mode 100644 index 0000000..da71fff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint8_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c new file mode 100644 index 0000000..b40d0b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(int16_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c new file mode 100644 index 0000000..af3a40d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(int32_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c new file mode 100644 index 0000000..5f7c51c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(int64_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c new file mode 100644 index 0000000..420cf0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(int8_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c new file mode 100644 index 0000000..7741d06 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint16_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c new file mode 100644 index 0000000..10ff20e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint32_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c new file mode 100644 index 0000000..fa5ab40 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint64_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c new file mode 100644 index 0000000..0374e1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint8_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c new file mode 100644 index 0000000..f766907 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(int16_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c new file mode 100644 index 0000000..1b47a59 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(int32_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c new file mode 100644 index 0000000..92ab1e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(int64_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c new file mode 100644 index 0000000..444707e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(int8_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c new file mode 100644 index 0000000..e3fc112 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint16_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c new file mode 100644 index 0000000..f76971b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint32_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c new file mode 100644 index 0000000..09a4b42 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint64_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c new file mode 100644 index 0000000..5a0679f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint8_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c new file mode 100644 index 0000000..9a26601 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X16) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c new file mode 100644 index 0000000..55b51fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int32_t, +, VX_BINARY_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c new file mode 100644 index 0000000..8ad6098 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c new file mode 100644 index 0000000..193e020 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int8_t, +, VX_BINARY_BODY_X16) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c new file mode 100644 index 0000000..a093fca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint16_t, +, VX_BINARY_BODY_X16) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c new file mode 100644 index 0000000..9f5843b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint32_t, +, VX_BINARY_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c new file mode 100644 index 0000000..0f00688 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint64_t, +, VX_BINARY_BODY) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c new file mode 100644 index 0000000..47707e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint8_t, +, VX_BINARY_BODY_X16) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c new file mode 100644 index 0000000..e5ec888 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X8) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c new file mode 100644 index 0000000..ed6c22d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int32_t, +, VX_BINARY_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c new file mode 100644 index 0000000..ef44012 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c new file mode 100644 index 0000000..d61f9df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int8_t, +, VX_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c new file mode 100644 index 0000000..3d1ba7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint16_t, +, VX_BINARY_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c new file mode 100644 index 0000000..2e9862b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint32_t, +, VX_BINARY_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c new file mode 100644 index 0000000..72e6786 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint64_t, +, VX_BINARY_BODY) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c new file mode 100644 index 0000000..e935be1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint8_t, +, VX_BINARY_BODY_X16) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c new file mode 100644 index 0000000..d80f0c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X8) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c new file mode 100644 index 0000000..99f6614 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int32_t, +, VX_BINARY_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c new file mode 100644 index 0000000..ab06c51 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c new file mode 100644 index 0000000..7ead9d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int8_t, +, VX_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c new file mode 100644 index 0000000..79b754b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c @@ -0,0 +1,9 @@ + +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint16_t, +, VX_BINARY_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c new file mode 100644 index 0000000..2f70dcd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint32_t, +, VX_BINARY_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c new file mode 100644 index 0000000..8094a2c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint64_t, +, VX_BINARY_BODY) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c new file mode 100644 index 0000000..56d040b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint8_t, +, VX_BINARY_BODY_X16) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c new file mode 100644 index 0000000..306ad76 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t + +DEF_VX_BINARY_CASE_0_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c new file mode 100644 index 0000000..6ccdf7a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t + +DEF_VX_BINARY_CASE_0_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c new file mode 100644 index 0000000..9484aa8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t + +DEF_VX_BINARY_CASE_0_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c new file mode 100644 index 0000000..aeb330e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t + +DEF_VX_BINARY_CASE_0_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c new file mode 100644 index 0000000..dafaa29 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t + +DEF_VX_BINARY_CASE_0_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c new file mode 100644 index 0000000..6b285c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t + +DEF_VX_BINARY_CASE_0_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c new file mode 100644 index 0000000..eeee4e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t + +DEF_VX_BINARY_CASE_0_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c new file mode 100644 index 0000000..22d7a0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t + +DEF_VX_BINARY_CASE_0_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 3824997..d76a2d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -132,5 +132,22 @@ foreach op $AUTOVEC_TEST_OPTS { "$op" "" } +# vx_vf tests +set AUTOVEC_TEST_OPTS [list \ + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=dynamic -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m4 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m8 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=dynamic -ffast-math} ] +foreach op $AUTOVEC_TEST_OPTS { + dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vx_vf/*.\[cS\]]] \ + "$op" "" +} + # All done. dg-finish diff --git a/gcc/testsuite/gcc.target/s390/vector/cstoreti-1.c b/gcc/testsuite/gcc.target/s390/vector/cstoreti-1.c new file mode 100644 index 0000000..f2a131b --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/cstoreti-1.c @@ -0,0 +1,127 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -march=z13" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** test_le: +** vl (%v.),0\(%r2\),3 +** vl (%v.),0\(%r3\),3 +** vecg \2,\1 +** jne \.L.+ +** vchlgs %v.,\1,\2 +** lghi %r2,0 +** locghinl %r2,1 +** br %r14 +*/ + +int test_le (__int128 x, __int128 y) { return x <= y; } + +/* +** test_leu: +** vl (%v.),0\(%r2\),3 +** vl (%v.),0\(%r3\),3 +** veclg \2,\1 +** jne \.L.+ +** vchlgs %v.,\1,\2 +** lghi %r2,0 +** locghinl %r2,1 +** br %r14 +*/ + +int test_leu (unsigned __int128 x, unsigned __int128 y) { return x <= y; } + +/* +** test_lt: +** vl (%v.),0\(%r2\),3 +** vl (%v.),0\(%r3\),3 +** vecg \1,\2 +** jne \.L.+ +** vchlgs %v.,\2,\1 +** lghi %r2,0 +** locghil %r2,1 +** br %r14 +*/ + +int test_lt (__int128 x, __int128 y) { return x < y; } + +/* +** test_ltu: +** vl (%v.),0\(%r2\),3 +** vl (%v.),0\(%r3\),3 +** veclg \1,\2 +** jne \.L.+ +** vchlgs %v.,\2,\1 +** lghi %r2,0 +** locghil %r2,1 +** br %r14 +*/ + +int test_ltu (unsigned __int128 x, unsigned __int128 y) { return x < y; } + +/* +** test_ge: +** vl (%v.),0\(%r2\),3 +** vl (%v.),0\(%r3\),3 +** vecg \1,\2 +** jne \.L.+ +** vchlgs %v.,\2,\1 +** lghi %r2,0 +** locghinl %r2,1 +** br %r14 +*/ + +int test_ge (__int128 x, __int128 y) { return x >= y; } + +/* +** test_geu: +** vl (%v.),0\(%r2\),3 +** vl (%v.),0\(%r3\),3 +** veclg \1,\2 +** jne \.L.+ +** vchlgs %v.,\2,\1 +** lghi %r2,0 +** locghinl %r2,1 +** br %r14 +*/ + +int test_geu (unsigned __int128 x, unsigned __int128 y) { return x >= y; } + +/* +** test_gt: +** vl (%v.),0\(%r2\),3 +** vl (%v.),0\(%r3\),3 +** vecg \2,\1 +** jne \.L.+ +** vchlgs %v.,\1,\2 +** lghi %r2,0 +** locghil %r2,1 +** br %r14 +*/ + +int test_gt (__int128 x, __int128 y) { return x > y; } + +/* +** test_gtu: +** vl (%v.),0\(%r2\),3 +** vl (%v.),0\(%r3\),3 +** veclg \2,\1 +** jne \.L.+ +** vchlgs %v.,\1,\2 +** lghi %r2,0 +** locghil %r2,1 +** br %r14 +*/ + +int test_gtu (unsigned __int128 x, unsigned __int128 y) { return x > y; } + +/* { dg-final { scan-assembler-times {vceqgs\t} 4 } } */ +/* { dg-final { scan-assembler-times {locghie\t} 2 } } */ +/* { dg-final { scan-assembler-times {locghine\t} 2 } } */ + +int test_eq (__int128 x, __int128 y) { return x == y; } + +int test_equ (unsigned __int128 x, unsigned __int128 y) { return x == y; } + +int test_ne (__int128 x, __int128 y) { return x != y; } + +int test_neu (unsigned __int128 x, unsigned __int128 y) { return x != y; } diff --git a/gcc/testsuite/gcc.target/s390/vector/cstoreti-2.c b/gcc/testsuite/gcc.target/s390/vector/cstoreti-2.c new file mode 100644 index 0000000..d7b0382 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/cstoreti-2.c @@ -0,0 +1,25 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -march=z17" } */ +/* { dg-final { scan-assembler-times {vecq\t} 8 } } */ +/* { dg-final { scan-assembler-times {veclq\t} 4 } } */ +/* { dg-final { scan-assembler-times {locghile\t} 1 } } LE */ +/* { dg-final { scan-assembler-times {slbgr\t} 1 } } LEU */ +/* { dg-final { scan-assembler-times {locghil\t} 2 } } LT LTU */ +/* { dg-final { scan-assembler-times {locghihe\t} 2 } } GE GEU */ +/* { dg-final { scan-assembler-times {locghih\t} 1 } } GT */ +/* { dg-final { scan-assembler-times {alcgr\t} 1 } } GTU */ +/* { dg-final { scan-assembler-times {locghie\t} 2 } } EQ EQU */ +/* { dg-final { scan-assembler-times {locghine\t} 2 } } NE NEU */ + +int test_le (__int128 x, __int128 y) { return x <= y; } +int test_leu (unsigned __int128 x, unsigned __int128 y) { return x <= y; } +int test_lt (__int128 x, __int128 y) { return x < y; } +int test_ltu (unsigned __int128 x, unsigned __int128 y) { return x < y; } +int test_ge (__int128 x, __int128 y) { return x >= y; } +int test_geu (unsigned __int128 x, unsigned __int128 y) { return x >= y; } +int test_gt (__int128 x, __int128 y) { return x > y; } +int test_gtu (unsigned __int128 x, unsigned __int128 y) { return x > y; } +int test_eq (__int128 x, __int128 y) { return x == y; } +int test_equ (unsigned __int128 x, unsigned __int128 y) { return x == y; } +int test_ne (__int128 x, __int128 y) { return x != y; } +int test_neu (unsigned __int128 x, unsigned __int128 y) { return x != y; } |