diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
70 files changed, 2549 insertions, 171 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt-le-1.c b/gcc/testsuite/gcc.target/aarch64/popcnt-le-1.c index b4141da..843fdac 100644 --- a/gcc/testsuite/gcc.target/aarch64/popcnt-le-1.c +++ b/gcc/testsuite/gcc.target/aarch64/popcnt-le-1.c @@ -8,7 +8,7 @@ /* ** le32: ** sub w([0-9]+), w0, #1 -** tst w0, w\1 +** tst (?:w0, w\1|w\1, w0) ** cset w0, eq ** ret */ @@ -20,7 +20,7 @@ unsigned le32 (const unsigned int a) { /* ** gt32: ** sub w([0-9]+), w0, #1 -** tst w0, w\1 +** tst (?:w0, w\1|w\1, w0) ** cset w0, ne ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt-le-3.c b/gcc/testsuite/gcc.target/aarch64/popcnt-le-3.c index b811e6f..3b558e9 100644 --- a/gcc/testsuite/gcc.target/aarch64/popcnt-le-3.c +++ b/gcc/testsuite/gcc.target/aarch64/popcnt-le-3.c @@ -8,7 +8,7 @@ /* ** le16: ** sub w([0-9]+), w0, #1 -** and w([0-9]+), w0, w\1 +** and w([0-9]+), (?:w0, w\1|w\1, w0) ** tst w\2, 65535 ** cset w0, eq ** ret @@ -21,7 +21,7 @@ unsigned le16 (const unsigned short a) { /* ** gt16: ** sub w([0-9]+), w0, #1 -** and w([0-9]+), w0, w\1 +** and w([0-9]+), (?:w0, w\1|w\1, w0) ** tst w\2, 65535 ** cset w0, ne ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/pr100056.c b/gcc/testsuite/gcc.target/aarch64/pr100056.c index 0b77824..70499772 100644 --- a/gcc/testsuite/gcc.target/aarch64/pr100056.c +++ b/gcc/testsuite/gcc.target/aarch64/pr100056.c @@ -1,7 +1,9 @@ /* PR target/100056 */ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-final { scan-assembler-not {\t[us]bfiz\tw[0-9]+, w[0-9]+, 11} } } */ +/* { dg-final { scan-assembler-not {\t[us]bfiz\tw[0-9]+, w[0-9]+, 11} { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\t[us]bfiz\tw[0-9]+, w[0-9]+, 11} 2 } } */ +/* { dg-final { scan-assembler-times {\tadd\tw[0-9]+, w[0-9]+, w[0-9]+, uxtb\n} 2 } } */ int or_shift_u8 (unsigned char i) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/gomp/gomp.exp b/gcc/testsuite/gcc.target/aarch64/sve/gomp/gomp.exp new file mode 100644 index 0000000..376985d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/gomp/gomp.exp @@ -0,0 +1,46 @@ +# Copyright (C) 2006-2025 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an AArch64 target. +if {![istarget aarch64*-*-*] } then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +if ![check_effective_target_fopenmp] { + return +} + +if { [check_effective_target_aarch64_sve] } { + set sve_flags "" +} else { + set sve_flags "-march=armv8.2-a+sve" +} + +# Main loop. +dg-runtest [lsort [find $srcdir/$subdir *.c]] "$sve_flags -fopenmp" "" + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-device.c b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-device.c new file mode 100644 index 0000000..75dd39b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-device.c @@ -0,0 +1,201 @@ +/* { dg-do compile } */ +/* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */ + +#include <arm_sve.h> + +#define N __ARM_FEATURE_SVE_BITS + +int64_t __attribute__ ((noipa)) +target_device_ptr_vla (svbool_t vp, svint32_t *vptr) +{ + + int a[N], b[N], c[N]; + svint32_t va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } +/* { dg-error {SVE type 'svint32_t \*' not allowed in 'target' device clauses} "" { target *-*-* } .+1 } */ +#pragma omp target data use_device_ptr (vptr) map (to: b, c) +/* { dg-error {SVE type 'svint32_t \*' not allowed in 'target' device clauses} "" { target *-*-* } .+1 } */ +#pragma omp target is_device_ptr (vptr) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vb = *vptr; + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+2 } */ + /* { dg-error "cannot reference 'svbool_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vc = svld1_s32 (vp, c); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +int64_t __attribute__ ((noipa)) +target_device_addr_vla (svbool_t vp, svint32_t *vptr) +{ + + int a[N], b[N], c[N]; + svint32_t va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'target' device clauses" "" { target *-*-* } .+1 } */ +#pragma omp target data use_device_addr (vb) map (to: b, c) +/* { dg-error {SVE type 'svint32_t \*' not allowed in 'target' device clauses} "" { target *-*-* } .+1 } */ +#pragma omp target is_device_ptr (vptr) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vb = *vptr; + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+2 } */ + /* { dg-error "cannot reference 'svbool_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vc = svld1_s32 (vp, c); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +int64_t __attribute__ ((noipa)) +target_has_device_addr_vla (svbool_t vp, svint32_t *vptr) +{ + + int a[N], b[N], c[N]; + svint32_t va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'target' device clauses" "" { target *-*-* } .+1 } */ +#pragma omp target data use_device_addr (vb) map (to: b, c) +/* { dg-error "SVE type 'svint32_t' not allowed in 'target' device clauses" "" { target *-*-* } .+1 } */ +#pragma omp target has_device_addr (vb) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svbool_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vb = svld1_s32 (vp, b); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + vc = svld1_s32 (vp, c); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +#define FIXED_ATTR __attribute__ ((arm_sve_vector_bits (N))) + +typedef __SVInt32_t v8si FIXED_ATTR; +typedef svbool_t v8bi FIXED_ATTR; + +int64_t __attribute__ ((noipa)) +target_device_ptr_vls (v8bi vp, v8si *vptr) +{ + + int a[N], b[N], c[N]; + v8si va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +#pragma omp target data use_device_ptr (vptr) map (to: b, c) +#pragma omp target is_device_ptr (vptr) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + vb = *vptr; + vc = svld1_s32 (vp, c); + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +int64_t __attribute__ ((noipa)) +target_device_addr_vls (v8bi vp, v8si *vptr) +{ + + int a[N], b[N], c[N]; + v8si va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +#pragma omp target data use_device_addr (vb) map (to: b, c) +#pragma omp target is_device_ptr (vptr) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + vb = *vptr; + vc = svld1_s32 (vp, c); + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} + +int64_t __attribute__ ((noipa)) +target_has_device_addr_vls (v8bi vp, v8si *vptr) +{ + + int a[N], b[N], c[N]; + v8si va, vb, vc; + int64_t res; + int i; + +#pragma omp parallel for + for (i = 0; i < N; i++) + { + b[i] = i; + c[i] = i + 1; + } + +#pragma omp target data use_device_addr (vb) map (to: b, c) +#pragma omp target has_device_addr (vb) map (to: b, c) map (from: res) + for (i = 0; i < 8; i++) + { + vb = svld1_s32 (vp, b); + vc = svld1_s32 (vp, c); + va = svadd_s32_z (vp, vb, vc); + res = svaddv_s32 (svptrue_b32 (), va); + } + + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-link.c b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-link.c new file mode 100644 index 0000000..2f6184b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target-link.c @@ -0,0 +1,57 @@ +/* { dg-do compile } */ +/* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */ + +#include <arm_sve.h> + +#define N __ARM_FEATURE_SVE_BITS +#define FIXED_ATTR __attribute__((arm_sve_vector_bits (N))) + +typedef __SVInt32_t v8si FIXED_ATTR; + +static v8si local_vec; +#pragma omp declare target link(local_vec) + +v8si global_vec; +#pragma omp declare target link(global_vec) + +/* { dg-error {SVE type 'svint32_t' does not have a fixed size} "" { target *-*-* } .+1 } */ +static svint32_t slocal_vec; + +/* { dg-error {'slocal_vec' does not have a mappable type in 'link' clause} "" { target *-*-* } .+1 } */ +#pragma omp declare target link(slocal_vec) + +void +one_get_inc2_local_vec_vls () +{ + v8si res, res2, tmp; + +#pragma omp target map(from: res, res2) + { + res = local_vec; + local_vec = svadd_s32_z (svptrue_b32 (), local_vec, local_vec); + res2 = local_vec; + } + + tmp = svadd_s32_z (svptrue_b32 (), res, res); + svbool_t p = svcmpne_s32 (svptrue_b32 (), tmp, res2); + if (svptest_any (svptrue_b32 (), p)) + __builtin_abort (); +} + +void +one_get_inc3_global_vec_vls () +{ + v8si res, res2, tmp; + +#pragma omp target map(from: res, res2) + { + res = global_vec; + global_vec = svadd_s32_z (svptrue_b32 (), global_vec, global_vec); + res2 = global_vec; + } + + tmp = svadd_s32_z (svptrue_b32 (), res, res); + svbool_t p = svcmpne_s32 (svptrue_b32 (), tmp, res2); + if (svptest_any (svptrue_b32 (), p)) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/gomp/target.c b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target.c new file mode 100644 index 0000000..812183d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/gomp/target.c @@ -0,0 +1,2049 @@ +/* { dg-do compile } */ +/* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */ + +#include <arm_sve.h> + +#define N __ARM_FEATURE_SVE_BITS +#define FIXED_ATTR __attribute__((arm_sve_vector_bits (N))) + +typedef svint32_t v8si FIXED_ATTR; +typedef svbool_t v8bi FIXED_ATTR; + +void +target_vla1 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla1 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla1 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla1 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla1 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls1 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls1 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls1 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls1 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls1 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla2 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target parallel + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla2 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla2 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla2 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla2 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target parallel + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls2 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target parallel + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls2 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target parallel map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls2 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target parallel map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls2 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target parallel map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target parallel map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls2 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target parallel + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla3 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target parallel loop + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla3 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla3 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla3 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla3 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target parallel loop + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target parallel loop map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls3 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target parallel loop + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls3 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target parallel loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls3 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target parallel loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target parallel map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls3 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target parallel loop map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target parallel loop map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls3 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target parallel loop + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target parallel loop map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla4 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target simd + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla4 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla4 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla4 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla4 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target simd + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls4 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target simd + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls4 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls4 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls4 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target simd map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target simd map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls4 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target simd + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla5 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla5 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla5 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla5 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla5 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls5 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls5 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls5 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls5 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target teams map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls5 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla6 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams loop + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla6 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla6 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla6 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla6 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams loop + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams loop map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls6 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams loop + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls6 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls6 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams loop map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls6 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target teams loop map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams loop map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls6 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams loop + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target teams loop map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla7 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams distribute + for (i = 0; i < 8; i++) + { + svint32_t va; + + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla7 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla7 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla7 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla7 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams distribute + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls7 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams distribute + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls7 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams distribute map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls7 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams distribute map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls7 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target teams distribute map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams distribute map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls7 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams distribute + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target teams distribute map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vla8 (svint32_t vb, svint32_t vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams distribute simd + for (i = 0; i < 8; i++) + { + svint32_t va; + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +svint32_t +target_data_map_1_vla8 (svint32_t vb, svint32_t vc, int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +svint32_t +target_data_map_2_vla8 (svint32_t vb, svint32_t vc, int *a, int *b, + int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +svint32_t +target_map_data_enter_exit_vla8 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target enter data map(to: b, c, vb, vc) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(from: va) + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target exit data map(from: va) + + return va; +} + +svint32_t +target_map_data_alloc_update_vla8 (svint32_t vb, svint32_t vc, int *a, + int *b, int *c) +{ + svint32_t va; + int i; + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams distribute simd + for (i = 0; i < 8; i++) + { + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + /* { dg-error "cannot reference 'svint32_t' object types in 'target' region" "" { target *-*-* } .+1 } */ + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +/* { dg-error "SVE type 'svint32_t' not allowed in 'map' clause" "" { target *-*-* } .+1 } */ +#pragma omp target teams distribute simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +void +target_vls8 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + int i; + +#pragma omp target teams distribute simd + for (i = 0; i < 8; i++) + { + v8si va; + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + va = svadd_s32_z (svptrue_b32 (), vb, vc); + svst1_s32 (svptrue_b32 (), a + i * 8, va); + } +} + +v8si +target_data_map_1_vls8 (v8si vb, v8si vc, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams distribute simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + return va; +} + +v8si +target_data_map_2_vls8 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target teams distribute simd map(to: b, c, vb, vc) map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} + +v8si +target_map_data_enter_exit_vls8 (v8si vb, v8si vc, int *a, int *b, int *c) +{ + v8si va; + int i; + +#pragma omp target enter data map(to: b, c, vb, vc) + +#pragma omp target teams distribute simd map(from: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target teams distribute simd map(to: va) map(to: a) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + +#pragma omp target exit data map(from: va) + + return va; +} + +v8si +target_map_data_alloc_update_vls8 (v8si vb, v8si vc, int *a, int *b, + int *c) +{ + v8si va; + int i; + +#pragma omp target data map(to: b, c, vb, vc) map(alloc: va) + +#pragma omp target teams distribute simd + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), b + i * 8, vb); + svst1_s32 (svptrue_b32 (), c + i * 8, vc); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), vb, vc); + } + +#pragma omp target update from(va) + +#pragma omp target teams distribute simd map(to: a) map(tofrom: va) + for (i = 0; i < 8; i++) + { + svst1_s32 (svptrue_b32 (), a + i * 8, va); + if (i == 7) + va = svadd_s32_z (svptrue_b32 (), va, svindex_s32 (1, 1)); + } + return va; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-1.c b/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-1.c index a7d2795..c9a8b82 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-1.c @@ -19,6 +19,6 @@ void f10(double * restrict z, double * restrict w, double * restrict x, double * } } -/* { dg-final { scan-assembler-not {\tbic\t} { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not {\tbic\t} } } */ +/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfcmgt\tp[0-9]+\.d, p[0-9]+/z, z[0-9]+\.d, #0} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-4.c b/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-4.c index 20cbd75..1845bd3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-4.c @@ -8,6 +8,6 @@ void f13(double * restrict z, double * restrict w, double * restrict x, double * } } -/* { dg-final { scan-assembler-not {\tbic\t} { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not {\tbic\t} } } */ +/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfcmuo\tp[0-9]+\.d, p[0-9]+/z, z[0-9]+\.d, z[0-9]+\.d} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c index 33b9f0f..b8afea7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c @@ -16,7 +16,8 @@ f (TYPE *x, TYPE *y, unsigned short n, unsigned short m) /* { dg-final { scan-assembler {\tldr\tw[0-9]+} } } */ /* { dg-final { scan-assembler {\tstr\tw[0-9]+} } } */ /* Should multiply by (257-1)*4 rather than (VF-1)*4 or (VF-2)*4. */ -/* { dg-final { scan-assembler-times {\tadd\tx[0-9]+, x[0-9]+, x[0-9]+, lsl 10\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tubfiz\tx[0-9]+, x2, 10, 16\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tubfiz\tx[0-9]+, x3, 10, 16\n} 1 } } */ /* { dg-final { scan-assembler-not {\tcmp\tx[0-9]+, 0} } } */ /* { dg-final { scan-assembler-not {\tcmp\tw[0-9]+, 0} } } */ /* { dg-final { scan-assembler-not {\tcsel\tx[0-9]+} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c index 71b826a..d2e74f9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c @@ -16,7 +16,8 @@ f (TYPE *x, TYPE *y, int n, int m) /* { dg-final { scan-assembler {\tldr\tw[0-9]+} } } */ /* { dg-final { scan-assembler {\tstr\tw[0-9]+} } } */ /* Should multiply by (257-1)*4 rather than (VF-1)*4. */ -/* { dg-final { scan-assembler-times {\t(?:lsl\tx[0-9]+, x[0-9]+, 10|sbfiz\tx[0-9]+, x[0-9]+, 10, 32)\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsbfiz\tx[0-9]+, x2, 10, 32\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsbfiz\tx[0-9]+, x3, 10, 32\n} 1 } } */ /* { dg-final { scan-assembler {\tcmp\tw2, 0} } } */ /* { dg-final { scan-assembler {\tcmp\tw3, 0} } } */ /* { dg-final { scan-assembler-times {\tcsel\tx[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/arm/ivopts.c b/gcc/testsuite/gcc.target/arm/ivopts.c index d7d72a5..582fdab 100644 --- a/gcc/testsuite/gcc.target/arm/ivopts.c +++ b/gcc/testsuite/gcc.target/arm/ivopts.c @@ -11,6 +11,6 @@ tr5 (short array[], int n) } /* { dg-final { scan-tree-dump-times "PHI <" 1 "ivopts"} } */ -/* { dg-final { object-size text <= 20 { target { arm_thumb2_no_arm_v8_1_lob } } } } */ +/* { dg-final { object-size text <= 20 { target { arm_thumb2_no_arm_v8_1m_lob } } } } */ /* { dg-final { object-size text <= 32 { target { arm_nothumb && { ! arm_iwmmxt_ok } } } } } */ /* { dg-final { object-size text <= 36 { target { arm_nothumb && arm_iwmmxt_ok } } } } */ diff --git a/gcc/testsuite/gcc.target/arm/lob1.c b/gcc/testsuite/gcc.target/arm/lob1.c index c8ce653..f42a367 100644 --- a/gcc/testsuite/gcc.target/arm/lob1.c +++ b/gcc/testsuite/gcc.target/arm/lob1.c @@ -1,7 +1,7 @@ /* Check that GCC generates Armv8.1-M low over head loop instructions for some simple loops. */ /* { dg-do run } */ -/* { dg-require-effective-target arm_v8_1_lob_ok } */ +/* { dg-require-effective-target arm_v8_1m_lob_hw } */ /* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "-mcpu=*" } } */ /* { dg-options "-march=armv8.1-m.main -mthumb -O3 --save-temps" } */ #include <stdlib.h> diff --git a/gcc/testsuite/gcc.target/arm/lob6.c b/gcc/testsuite/gcc.target/arm/lob6.c index 4fe116e..e19635b 100644 --- a/gcc/testsuite/gcc.target/arm/lob6.c +++ b/gcc/testsuite/gcc.target/arm/lob6.c @@ -1,7 +1,7 @@ /* Check that GCC generates Armv8.1-M low over head loop instructions with some less trivial loops and the result is correct. */ /* { dg-do run } */ -/* { dg-require-effective-target arm_v8_1_lob_ok } */ +/* { dg-require-effective-target arm_v8_1m_lob_hw } */ /* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "-mcpu=*" } } */ /* { dg-options "-march=armv8.1-m.main -mthumb -O3 --save-temps" } */ #include <stdlib.h> diff --git a/gcc/testsuite/gcc.target/arm/short-vfp-1.c b/gcc/testsuite/gcc.target/arm/short-vfp-1.c index f6866c4..418fc27 100644 --- a/gcc/testsuite/gcc.target/arm/short-vfp-1.c +++ b/gcc/testsuite/gcc.target/arm/short-vfp-1.c @@ -1,45 +1,75 @@ /* { dg-do compile } */ -/* { dg-require-effective-target arm_vfp_ok } */ -/* { dg-add-options arm_vfp } */ +/* { dg-require-effective-target arm_arch_v7a_fp_hard_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v7a_fp_hard } */ +/* { dg-final { check-function-bodies "**" "" } } */ +/* +** test_sisf: +** vcvt.s32.f32 (s[0-9]+), s0 +** vmov r0, \1 @ int +** bx lr +*/ int test_sisf (float x) { return (int)x; } +/* +** test_hisf: +** vcvt.s32.f32 (s[0-9]+), s0 +** vmov (r[0-9]+), \1 @ int +** sxth r0, \2 +** bx lr +*/ short test_hisf (float x) { return (short)x; } +/* +** test_sfsi: +** vmov (s[0-9]+), r0 @ int +** vcvt.f32.s32 s0, \1 +** bx lr +*/ float test_sfsi (int x) { return (float)x; } +/* +** test_sfhi: +** vmov (s[0-9]+), r0 @ int +** vcvt.f32.s32 s0, \1 +** bx lr +*/ float test_sfhi (short x) { return (float)x; } +/* +** test_hisi: +** sxth r0, r0 +** bx lr +*/ short test_hisi (int x) { return (short)x; } +/* +** test_sihi: +** bx lr +*/ int test_sihi (short x) { return (int)x; } - -/* { dg-final { scan-assembler-times {vcvt\.s32\.f32\ts[0-9]+, s[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {vcvt\.f32\.s32\ts[0-9]+, s[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {vmov\tr[0-9]+, s[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {vmov\ts[0-9]+, r[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {sxth\tr[0-9]+, r[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c index 9272e4c..41ee994 100644 --- a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c +++ b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target arm_thumb2_ok_no_arm_v8_1_lob } */ +/* { dg-require-effective-target arm_thumb2_ok_no_arm_v8_1m_lob } */ /* { dg-options "-O" } */ unsigned short foo (unsigned short x, unsigned short c) diff --git a/gcc/testsuite/gcc.target/i386/pr67215-1.c b/gcc/testsuite/gcc.target/i386/pr67215-1.c index fd37f8e..ab69550 100644 --- a/gcc/testsuite/gcc.target/i386/pr67215-1.c +++ b/gcc/testsuite/gcc.target/i386/pr67215-1.c @@ -13,8 +13,8 @@ foo (void) arr[i] = bar (128); } -/* { dg-final { scan-assembler "call\[ \t\]*.bar@GOTPCREL" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "call\[ \t\]*.bar@GOT\\(" { target ia32 } } } */ -/* { dg-final { scan-assembler-not "mov(l|q)\[ \t\]*.bar@GOTPCREL" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-not "movl\[ \t\]*.bar@GOT\\(" { target ia32 } } } */ -/* { dg-final { scan-assembler-not "call\[ \t\]*.bar@PLT" } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*bar@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*bar@GOT\\(" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "mov(l|q)\[ \t\]+bar@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "movl\[ \t\]+bar@GOT\\(" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "call\[ \t\]+\\*bar@PLT" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr67215-2.c b/gcc/testsuite/gcc.target/i386/pr67215-2.c index ebf2919..9fd7469 100644 --- a/gcc/testsuite/gcc.target/i386/pr67215-2.c +++ b/gcc/testsuite/gcc.target/i386/pr67215-2.c @@ -13,8 +13,8 @@ foo (void) arr[i] = bar (128); } -/* { dg-final { scan-assembler "call\[ \t\]*.bar@GOTPCREL" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "call\[ \t\]*.bar@GOT\\(" { target ia32 } } } */ -/* { dg-final { scan-assembler-not "mov(l|q)\[ \t\]*.bar@GOTPCREL" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-not "movl\[ \t\]*.bar@GOT\\(" { target ia32 } } } */ -/* { dg-final { scan-assembler-not "call\[ \t\]*.bar@PLT" } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*bar@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*bar@GOT\\(" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "mov(l|q)\[ \t\]+bar@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "movl\[ \t\]+bar@GOT\\(" { target ia32 } } } */ +/* { dg-final { scan-assembler-not "call\[ \t\]+\\*bar@PLT" } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/alloca-2-O0_-mfake-ptx-alloca.c b/gcc/testsuite/gcc.target/nvptx/alloca-2-O0_-mfake-ptx-alloca.c index 4cc4d0c..92562cd 100644 --- a/gcc/testsuite/gcc.target/nvptx/alloca-2-O0_-mfake-ptx-alloca.c +++ b/gcc/testsuite/gcc.target/nvptx/alloca-2-O0_-mfake-ptx-alloca.c @@ -1,4 +1,4 @@ -/* { dg-do link } */ +/* { dg-do run } */ /* { dg-options {-O0 -mno-soft-stack} } */ /* { dg-additional-options -march=sm_30 } */ /* { dg-additional-options -mfake-ptx-alloca } */ @@ -13,6 +13,7 @@ main(void) /* { dg-final { scan-assembler-times {(?n)^\.extern \.func \(\.param\.u64 %value_out\) __GCC_nvptx__PTX_alloca_not_supported \(\.param\.u64 %in_ar0\);$} 1 } } */ -/* { dg-message __GCC_nvptx__PTX_alloca_not_supported {unresolved symbol} { target *-*-* } 0 } */ +/* { dg-bogus __GCC_nvptx__PTX_alloca_not_supported {unresolved symbol} { target *-*-* } 0 } */ -/* { dg-final output-exists-not } */ +/* { dg-output {GCC/nvptx: sorry, unimplemented: dynamic stack allocation not supported[\r\n]+} } + { dg-shouldfail __GCC_nvptx__PTX_alloca_not_supported } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f16.c deleted file mode 100644 index e4ff310..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f16.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (float, _Float16) - -/* { dg-final { scan-assembler-times {\tvfwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f32.c deleted file mode 100644 index 7d2b448..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f32.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (double, float) - -/* { dg-final { scan-assembler-times {\tvfwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i16.c deleted file mode 100644 index dc7e1da..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i16.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (int32_t, int16_t) - -/* { dg-final { scan-assembler-times {\tvwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i32.c deleted file mode 100644 index de1072f..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i32.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (int64_t, int32_t) - -/* { dg-final { scan-assembler-times {\tvwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i8.c deleted file mode 100644 index 8de5ef4..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i8.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (int16_t, int8_t) - -/* { dg-final { scan-assembler-times {\tvwmul\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u16.c deleted file mode 100644 index a4aafd2..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u16.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (uint32_t, uint16_t) - -/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u32.c deleted file mode 100644 index 0deeaa0..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u32.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (uint64_t, uint32_t) - -/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u8.c deleted file mode 100644 index a6afcd0..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u8.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ - -#include "cond_widen_complicate-3.h" - -TEST_TYPE (uint16_t, uint8_t) - -/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 1 } } */ -/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c new file mode 100644 index 0000000..d02a8e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ + +#include <stdint-gcc.h> + +#define TEST_TYPE(TYPE1, TYPE2) \ + __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 ( \ + TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3, \ + TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b, \ + TYPE2 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; i++) \ + { \ + dst[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b[i] : dst[i]; \ + dst2[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) b[i] : dst2[i]; \ + dst3[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) a[i] : dst3[i]; \ + dst4[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b2[i] : dst4[i]; \ + } \ + } + +#define TEST_ALL() \ + TEST_TYPE (int16_t, int8_t) \ + TEST_TYPE (uint16_t, uint8_t) \ + TEST_TYPE (int32_t, int16_t) \ + TEST_TYPE (uint32_t, uint16_t) \ + TEST_TYPE (int64_t, int32_t) \ + TEST_TYPE (uint64_t, uint32_t) \ + TEST_TYPE (float, _Float16) \ + TEST_TYPE (double, float) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvwmul\.vv} 12 } } */ +/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 12 } } */ +/* { dg-final { scan-assembler-times {\tvfwmul\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.h deleted file mode 100644 index 974846f..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef COND_WIDEN_COMPLICATE_3_H -#define COND_WIDEN_COMPLICATE_3_H - -#include <stdint-gcc.h> - -#define TEST_TYPE(TYPE1, TYPE2) \ - __attribute__ ((noipa)) void vwadd_##TYPE1##_##TYPE2 ( \ - TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3, \ - TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b, \ - TYPE2 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n) \ - { \ - for (int i = 0; i < n; i++) \ - { \ - dst[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b[i] : dst[i]; \ - dst2[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) b[i] : dst2[i]; \ - dst3[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) a[i] : dst3[i]; \ - dst4[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b2[i] : dst4[i]; \ - } \ - } - -#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c index 493dab0..0267078 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c @@ -18,6 +18,5 @@ int pixel_sad_n(unsigned char *pix1, unsigned char *pix2, int n) return sum; } -/* { dg-final { scan-assembler {vrsub\.v} } } */ /* { dg-final { scan-assembler {vmax\.v} } } */ -/* { dg-final { scan-assembler {vwsubu\.v} } } */ +/* { dg-final { scan-assembler-times {vwsubu\.v} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c index 638e90f..69a94d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d -mrvv-vector-bits=zvl" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c index 380d0c1..5e0f136 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d -mrvv-vector-bits=zvl" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c index 9ed72a6..a3c0a6d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d -msave-restore" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c index b6b708f..b1cf6aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c index 13e3328..8838f0d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar (int8_t *data); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c index d21b810..77f1c7c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d -msave-restore" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar1 (vint8m1_t a); void bar2 (); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c index 70a32d7..37127a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar1 (vint8m1_t a); void bar2 (); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c index 3f2cb2f..a8daeeb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c @@ -2,7 +2,7 @@ /* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar1 (vint8m1_t a); void bar2 (); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c index fe3a1ef..f8143b9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c @@ -4,7 +4,7 @@ /* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-options " -march=rv64gcv_zvfh -mabi=lp64d -O2" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" int8_t a[1]; uint16_t b[1]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c index 60fdfc4..05628d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c @@ -4,7 +4,7 @@ /* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-options " -march=rv64gcv_zvfh -mabi=lp64d -O2 --param=vsetvl-strategy=optim -fno-schedule-insns -fno-schedule-insns2 -fno-schedule-fusion " } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void __attribute__ ((noipa)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c index 28766ce..3180f71 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vint64m1_t f1 (vint64m1_t vd, vint64m1_t vs2, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c index 975f755..31b68c4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d -O0" { target { rv64 } } } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O0" { target { rv32 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vint64m1_t f1 (vint64m1_t vd, vint64m1_t vs2, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c index 8cfe965..f7c9ad1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vfloat16m1_t f0 (vfloat16m1_t vs2, vfloat16m1_t vs1, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110943.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110943.c index 8a6c00f..a08ac6e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110943.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110943.c @@ -2,7 +2,7 @@ /* { dg-options "-O3 -march=rv64gcv -mabi=lp64d" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" /* ** foo9: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c index 3e43c94..a0ed793 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-O3 -ansi -pedantic-errors -std=gnu99" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" size_t __attribute__ ((noinline)) sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114639-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114639-1.c index 3ad91db..c5b35c8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114639-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114639-1.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" extern size_t get_vl (); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c index d552eb5..e9e41f7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target riscv_v_ok } */ /* { dg-add-options riscv_v } */ -/* { dg-additional-options "-std=gnu99" } */ +/* { dg-additional-options "-std=gnu99 -Wno-pedantic" } */ #include "pr115068.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c index af2cba6..ce9a389 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c @@ -1,9 +1,9 @@ /* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options riscv_v } */ -/* { dg-additional-options "-std=gnu99" } */ +/* { dg-additional-options "-std=gnu99 -Wno-pedantic" } */ #include <stdint.h> -#include <riscv_vector.h> +#include "riscv_vector.h" vfloat64m8_t test_vfwadd_wf_f64m8_m (vbool8_t vm, vfloat64m8_t vs2, float rs1, size_t vl) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c index dabb8ae..7b6eefe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O1" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" _Float16 a[10]; void func(){ int placeholder0 = 10; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117544.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117544.c index af3532a..81e0ec3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117544.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117544.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void bar() __attribute__((riscv_vector_cc)); vint32m1_t foo(vint32m1_t a, vint32m1_t b) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c index 81e3a6e..4904c92 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { rv64 } } } */ /* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" _Float16 a (uint64_t); int8_t b () { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c index adb54d6..d62751e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vfloat32m2_t foo (vfloat16m1_t a, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c index 4253729..6bb7e1c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) { return __riscv_vlmul_ext_v_i16mf4_i16m8(op1); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c index 606854b..a278709 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=rv64gcv -mabi=lp64d" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vuint64m1_t test_vssubu_vx_u64m1(vuint64m1_t op1) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c index 78abd09..2f8c146 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=rv32gcv -mabi=ilp32d" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vuint64m1_t test_vssubu_vx_u64m1(vuint64m1_t op1) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c index 84d3c4c..43be202 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c @@ -1,9 +1,9 @@ /* { dg-do compile { target { { ! riscv_abi_e } && rv64 } } } */ /* { dg-add-options riscv_v } */ -/* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns -fno-schedule-insns2 -Wno-pedantic" } */ #include <stdint.h> -#include <riscv_vector.h> +#include "riscv_vector.h" /* ** vwadd_wx_i64m8_m: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c index 871cf65..f594217 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void f (vint32m1_t *in, vint64m2_t *out, vbool32_t *m, int b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c index b76760b..48f200f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c @@ -2,7 +2,7 @@ /* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w -std=gnu17" } */ /* { dg-skip-if "" { *-*-* } { "-flto" } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" static inline __attribute__(()) int vaddq_f32(); static inline __attribute__(()) int vload_tillz_f32(int nlane) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c index 7096159e..3867681 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" size_t foo () { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c index c155f56..3acbc73 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O2 -fdump-rtl-vsetvl-details" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" uint64_t a[2], b[2]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c index 04a8ff2..2b2fe27 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -fno-schedule-insns -fdump-rtl-vsetvl-details" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vuint16m1_t foo (vuint16m1_t a, vuint16m1_t b, size_t avl) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c index dfaf82c..ad27c38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32d -O2 -save-temps" { target { rv32 } } } */ /* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O2 -save-temps" { target { rv64 } } } */ -#include <riscv_vector.h> +#include "riscv_vector.h" void foo (float *a, int b) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c index a7cd8c5..c8056a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c @@ -3,7 +3,7 @@ /* { dg-options "-march=rv64gc_zfh_xtheadvector -mabi=lp64d -O2 -save-temps" { target { rv64 } } } */ #include <math.h> -#include <riscv_vector.h> +#include "riscv_vector.h" static vfloat32m8_t atan2_ps(vfloat32m8_t a, vfloat32m8_t b, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c index aebb0e3..b3c3428 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { rv64 } } } */ /* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O2" } */ -#include <riscv_vector.h> +#include "riscv_vector.h" vfloat16m4_t foo (float *ptr, size_t vl) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c new file mode 100644 index 0000000..42fa43e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +struct a +{ + int b[]; +} c (vint32m4_t), d; + +char e; +char *f; + +void g () +{ + int h; + vint32m4_t i; + vint8m1_t j = __riscv_vlse8_v_i8m1 (&e, d.b[3], h); + vint16m2_t k = __riscv_vwadd_vx_i16m2 (j, 0, h); + i = __riscv_vwmacc_vx_i32m4 (i, f[0], k, h); + c (i); +} + +/* { dg-final { scan-assembler-not {th\.vsext\.vf2} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c new file mode 100644 index 0000000..d622b72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +struct a +{ + int b[]; +} c (vuint32m4_t), d; + +char e; +char *f; + +void g () +{ + int h; + vuint32m4_t i; + vuint8m1_t j = __riscv_vlse8_v_u8m1 (&e, d.b[3], h); + vuint16m2_t k = __riscv_vwaddu_vx_u16m2 (j, 0, h); + i = __riscv_vwmaccu_vx_u32m4 (i, f[0], k, h); + c (i); +} + +/* { dg-final { scan-assembler-not {th\.vzext\.vf2} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c index c0d643d..929de16 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c @@ -15,7 +15,7 @@ ** li\s+[atx][0-9]+,\s*-1 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 ** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c index 470e6b7..a540198 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c @@ -15,7 +15,7 @@ ** li\s+[atx][0-9]+,\s*-1 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 ** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c index bb94775..e3fe6c7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c @@ -15,7 +15,7 @@ ** li\s+[atx][0-9]+,\s*-1 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 ** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c index cc598eb..f42ffea 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c @@ -15,7 +15,7 @@ ** li\s+[atx][0-9]+,\s*-1 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 ** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ |