diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
64 files changed, 1008 insertions, 30 deletions
diff --git a/gcc/testsuite/gcc.target/i386/pr111657-1.c b/gcc/testsuite/gcc.target/i386/pr111657-1.c index 99acd1f..a4ba210 100644 --- a/gcc/testsuite/gcc.target/i386/pr111657-1.c +++ b/gcc/testsuite/gcc.target/i386/pr111657-1.c @@ -1,5 +1,5 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -mno-sse -mtune=generic -masm=att" } */ +/* { dg-do assemble } */ +/* { dg-options "-O2 -mno-sse -mtune=generic -save-temps" } */ typedef unsigned long uword __attribute__ ((mode (word))); @@ -8,5 +8,5 @@ struct a { uword arr[30]; }; __seg_gs struct a m; void bar (struct a *dst) { *dst = m; } -/* { dg-final { scan-assembler "rep\[; \t\]+movs(l|q)\[ \t\]+%gs:" { target { ! x32 } } } } */ -/* { dg-final { scan-assembler-not "rep\[; \t\]+movs(l|q)\[ \t\]+%gs:" { target x32 } } } */ +/* { dg-final { scan-assembler "gs\[ \t\]+rep\[; \t\]+movs(l|q)" { target { ! x32 } } } } */ +/* { dg-final { scan-assembler-not "gs\[ \t\]+rep\[; \t\]+movs(l|q)" { target x32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr117839-3a.c b/gcc/testsuite/gcc.target/i386/pr117839-3a.c new file mode 100644 index 0000000..81afa9d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr117839-3a.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ +/* { dg-final { scan-assembler-times "xor\[a-z\]*\[\t \]*%xmm\[0-9\]\+,\[^,\]*" 1 } } */ + +typedef char v4qi __attribute__((vector_size(4))); +typedef char v16qi __attribute__((vector_size(16))); + +v4qi a; +v16qi b; +void +foo (v4qi* c, v16qi* d) +{ + v4qi sum = __extension__(v4qi){0, 0, 0, 0}; + v16qi sum2 = __extension__(v16qi){0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0}; + for (int i = 0; i != 100; i++) + sum += c[i]; + for (int i = 0 ; i != 100; i++) + sum2 += d[i]; + a = sum; + b = sum2; +} diff --git a/gcc/testsuite/gcc.target/i386/pr117839-3b.c b/gcc/testsuite/gcc.target/i386/pr117839-3b.c new file mode 100644 index 0000000..a599c28 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr117839-3b.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3" } */ +/* { dg-final { scan-assembler-times "xor\[a-z\]*\[\t \]*%xmm\[0-9\]\+,\[^,\]*" 1 } } */ + +#include "pr117839-3a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr120031.c b/gcc/testsuite/gcc.target/i386/pr120031.c new file mode 100644 index 0000000..e329cbc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120031.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi" } */ + +unsigned int +ZSTD_countTrailingZeros32_fallback (unsigned int val) +{ + static const unsigned int DeBruijn[32] + = { 0, 1, 28, 2, 29, 14, 24, 3, + 30, 22, 20, 15, 25, 17, 4, 8, + 31, 27, 13, 23, 21, 19, 16, 7, + 26, 12, 18, 6, 11, 5, 10, 9}; + return DeBruijn[((unsigned int) ((val & -(int) val) * 0x077CB531U)) >> 27]; +} + +/* { dg-final { scan-assembler "tzcnt" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-45.c b/gcc/testsuite/gcc.target/riscv/arch-45.c new file mode 100644 index 0000000..afffb99 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-45.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_svadu -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-46.c b/gcc/testsuite/gcc.target/riscv/arch-46.c new file mode 100644 index 0000000..2a06217 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-46.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_svade -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-47.c b/gcc/testsuite/gcc.target/riscv/arch-47.c new file mode 100644 index 0000000..06bc80f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-47.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_sdtrig_ssstrict -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/modifier-H-error-1.c b/gcc/testsuite/gcc.target/riscv/modifier-H-error-1.c new file mode 100644 index 0000000..43ecff6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/modifier-H-error-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -O0" } */ + +float foo () +{ + float ret; + asm ("fld\t%H0,(a0)\n\t":"=f"(ret)); + + return ret; +} + +/* { dg-error "modifier 'H' is for integer registers only" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/modifier-H-error-2.c b/gcc/testsuite/gcc.target/riscv/modifier-H-error-2.c new file mode 100644 index 0000000..db478b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/modifier-H-error-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -O0 " } */ + +void foo () +{ + register int x31 __asm__ ("x31"); + asm ("li\t%H0,1\n\t":"=r"(x31)); +} + +/* { dg-error "modifier 'H' cannot be applied to R31" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/modifier-H.c b/gcc/testsuite/gcc.target/riscv/modifier-H.c new file mode 100644 index 0000000..3571ea9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/modifier-H.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -O0" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +typedef long long __int64; + +__int64 foo () +{ +/* +** foo: +** ... +** li\t[atx][0-9]+,1 +** li\t[atx][0-9]+,1 +** ... +*/ + __int64 ret; + asm ("li\t%0,1\n\tli\t%H0,1\n\t":"=r"(ret)); + + return ret; +} + diff --git a/gcc/testsuite/gcc.target/riscv/pr114512.c b/gcc/testsuite/gcc.target/riscv/pr114512.c new file mode 100644 index 0000000..205071c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114512.c @@ -0,0 +1,109 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define MASK 0x1f +typedef unsigned int utype; +#else +#define ONE 1ULL +#define MASK 0x3f +typedef unsigned long utype; +#endif + + +_Bool my_isxdigit_1(unsigned char ch) { + utype mask1 = 0x03FF007E; + if (!((mask1 >> (ch & MASK)) & 1)) + return 0; + + return 1; +} + +_Bool my_isxdigit_1a(unsigned char ch) { + utype mask2 = 0x58; + if (!((mask2 >> (ch >> 4)) & 1)) + return 0; + + return 1; +} + +_Bool my_isxdigit_2(unsigned char ch) { + utype mask1 = 0x03FF007E; + if (!(mask1 & (ONE << (ch & MASK)))) + return 0; + + return 1; +} + +_Bool my_isxdigit_2a(unsigned char ch) { + utype mask2 = 0x58; + if (!(mask2 & (ONE << (ch >> 4)))) + return 0; + + return 1; +} + +_Bool my_isxdigit_3(unsigned char ch) { + utype mask1 = 0x7E00FFC0; + if (!((mask1 << (MASK - (ch & MASK))) >> MASK)) + return 0; + + return 1; +} + +_Bool my_isxdigit_3a(unsigned char ch) { + utype mask2 = 0x7E00FFC0; + if (!((mask2 << (MASK - ((ch >> 4) & MASK))) >> MASK)) + return 0; + + return 1; +} + +_Bool my_isxdigit_1_parm(unsigned char ch, utype mask1) { + if (!((mask1 >> (ch & MASK)) & 1)) + return 0; + + return 1; +} + +_Bool my_isxdigit_1a_parm(unsigned char ch, utype mask2) { + if (!((mask2 >> (ch >> 4)) & 1)) + return 0; + + return 1; +} + +_Bool my_isxdigit_2_parm(unsigned char ch, utype mask1) { + if (!(mask1 & (ONE << (ch & MASK)))) + return 0; + + return 1; +} + +_Bool my_isxdigit_2a_parm(unsigned char ch, utype mask2) { + if (!(mask2 & (ONE << (ch >> 4)))) + return 0; + + return 1; +} + +_Bool my_isxdigit_3_parm(unsigned char ch, utype mask1) { + if (!((mask1 << (MASK - (ch & MASK))) >> MASK)) + return 0; + + return 1; +} + +_Bool my_isxdigit_3a_parm(unsigned char ch, utype mask2) { + if (!((mask2 << (MASK - ((ch >> 4) & MASK))) >> MASK)) + return 0; + + return 1; +} + +/* Each test should generate a single bext. */ +/* { dg-final { scan-assembler-times "bext\t" 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr119971.c b/gcc/testsuite/gcc.target/riscv/pr119971.c new file mode 100644 index 0000000..c3f23b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr119971.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target rv64 } } */ +/* { dg-options "-march=rv64gcb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-Oz" "-Os" } } */ + +__attribute__ ((noipa)) unsigned +foo (unsigned b, unsigned e, unsigned i) +{ + e >>= b; + i >>= e & 31; + return i & 1; +} + +int main() +{ + if (foo (0x18, 0xfe000000, 0x40000000) != 1) + __builtin_abort (); + return 0; +} + +/* { dg-final { scan-assembler-times "andi\t" 1 } } */ +/* { dg-final { scan-assembler-times "srlw\t" 2 } } */ +/* { dg-final { scan-assembler-not "bext\t" } } */ + + diff --git a/gcc/testsuite/gcc.target/riscv/predef-19.c b/gcc/testsuite/gcc.target/riscv/predef-19.c index ca3d57a..f2b4d9b 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-19.c +++ b/gcc/testsuite/gcc.target/riscv/predef-19.c @@ -27,10 +27,6 @@ int main () { #error "__riscv_zicsr" #endif -#if !defined(_riscv_zmmul) -#error "__riscv_zmmul" -#endif - #if !defined(__riscv_zve32x) #error "__riscv_zve32x" #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h new file mode 100644 index 0000000..66654eb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h @@ -0,0 +1,17 @@ +#ifndef HAVE_DEFINED_VX_VF_BINARY_H +#define HAVE_DEFINED_VX_VF_BINARY_H + +#include <stdint.h> + +#define DEF_VX_BINARY(T, OP) \ +void \ +test_vx_binary (T * restrict out, T * restrict in, T x, unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + out[i] = in[i] OP x; \ +} +#define DEF_VX_BINARY_WRAP(T, OP) DEF_VX_BINARY(T, OP) +#define RUN_VX_BINARY(out, in, x, n) test_vx_binary(out, in, x, n) +#define RUN_VX_BINARY_WRAP(out, in, x, n) RUN_VX_BINARY(out, in, x, n) + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h new file mode 100644 index 0000000..11a32cb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -0,0 +1,401 @@ +#ifndef HAVE_DEFINED_VX_BINARY_DATA_H +#define HAVE_DEFINED_VX_BINARY_DATA_H + +#define N 16 + +#define TEST_BINARY_DATA(T, NAME) test_##T##_##NAME##_data +#define TEST_BINARY_DATA_WRAP(T, NAME) TEST_BINARY_DATA(T, NAME) + +int8_t TEST_BINARY_DATA(int8_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + }, + { + { 127 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 127, 127, 127, 127, + 126, 126, 126, 126, + -1, -1, -1, -1, + 125, 125, 125, 125, + }, + }, + { + { -128 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + -128, -128, -128, -128, + -127, -127, -127, -127, + -1, -1, -1, -1, + -126, -126, -126, -126, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + }, + { + { 32767 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 32767, 32767, 32767, 32767, + 32766, 32766, 32766, 32766, + -1, -1, -1, -1, + 32765, 32765, 32765, 32765, + }, + }, + { + { -32768 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + -1, -1, -1, -1, + -32766, -32766, -32766, -32766, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + }, + { + { 2147483647 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483646, 2147483646, 2147483646, 2147483646, + -1, -1, -1, -1, + 2147483645, 2147483645, 2147483645, 2147483645, + }, + }, + { + { -2147483648 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + -1, -1, -1, -1, + -2147483646, -2147483646, -2147483646, -2147483646, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + }, + { + { 9223372036854775807ll }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, + -1, -1, -1, -1, + 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, + }, + }, + { + { -9223372036854775808ull }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + }, + { + { 127 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 128, 128, 128, 128, + }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 254, 254, 254, 254, + 255, 255, 255, 255, + }, + }, + { + { 253 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 255, 255, 255, 255, + }, + { + 253, 253, 253, 253, + 254, 254, 254, 254, + 255, 255, 255, 255, + 252, 252, 252, 252, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + }, + { + { 32767 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + }, + }, + { + { 65533 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 65535, 65535, 65535, 65535, + }, + { + 65533, 65533, 65533, 65533, + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + 65532, 65532, 65532, 65532, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + }, + { + { 2147483647 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + }, + { + { 4294967293 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 4294967293, 4294967293, 4294967293, 4294967293, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967292, 4294967292, 4294967292, 4294967292, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, vadd)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + }, + { + { 9223372036854775807ull }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + }, + { + { 18446744073709551613ull }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + { + 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, + }, + }, +}; + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h new file mode 100644 index 0000000..bb35184 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h @@ -0,0 +1,26 @@ +#ifndef HAVE_DEFINED_VX_BINARY_RUN_H +#define HAVE_DEFINED_VX_BINARY_RUN_H + +int +main () +{ + unsigned i, k; + T out[N]; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + T x = TEST_DATA[i][0][0]; + T *in = TEST_DATA[i][1]; + T *expect = TEST_DATA[i][2]; + + TEST_RUN (out, in, x, N); + + for (k = 0; k < N; k++) + if (out[k] != expect[k]) + __builtin_abort (); + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c new file mode 100644 index 0000000..488bc75 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int16_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c new file mode 100644 index 0000000..aeba835 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int32_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c new file mode 100644 index 0000000..ed0b937 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int64_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c new file mode 100644 index 0000000..781d3c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int8_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c new file mode 100644 index 0000000..c01fc23 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint16_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c new file mode 100644 index 0000000..63198492 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint32_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c new file mode 100644 index 0000000..36eec53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint64_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c new file mode 100644 index 0000000..6bf4b61 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint8_t, +) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c new file mode 100644 index 0000000..eb19938 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int16_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c new file mode 100644 index 0000000..24182c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int32_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c new file mode 100644 index 0000000..b3d3d4b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int64_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c new file mode 100644 index 0000000..fb35315 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int8_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c new file mode 100644 index 0000000..6ba2658 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint16_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c new file mode 100644 index 0000000..b60412c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint32_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c new file mode 100644 index 0000000..a273294 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint64_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c new file mode 100644 index 0000000..f3c41f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint8_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c new file mode 100644 index 0000000..f3a2627 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int16_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c new file mode 100644 index 0000000..490854c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int32_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c new file mode 100644 index 0000000..a7448df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int64_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c new file mode 100644 index 0000000..72c7cd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int8_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c new file mode 100644 index 0000000..552b4ed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint16_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c new file mode 100644 index 0000000..e319672 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint32_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c new file mode 100644 index 0000000..6e2a89e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint64_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c new file mode 100644 index 0000000..d3383e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint8_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c new file mode 100644 index 0000000..fb5375d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t + +DEF_VX_BINARY_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c new file mode 100644 index 0000000..c2c79f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t + +DEF_VX_BINARY_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c new file mode 100644 index 0000000..541ed21 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t + +DEF_VX_BINARY_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c new file mode 100644 index 0000000..d507bbb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t + +DEF_VX_BINARY_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c new file mode 100644 index 0000000..52c0749 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t + +DEF_VX_BINARY_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c new file mode 100644 index 0000000..70dc347 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t + +DEF_VX_BINARY_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c new file mode 100644 index 0000000..6ce0060 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t + +DEF_VX_BINARY_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c new file mode 100644 index 0000000..a0e80b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c @@ -0,0 +1,14 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t + +DEF_VX_BINARY_WRAP(T, +) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) +#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_WRAP(out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c index af89f62..3e8a980 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c @@ -32,5 +32,5 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 3 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c index 5b75935..e8fc7bb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c @@ -32,5 +32,5 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 3 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c index cd23141..9828987 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c @@ -32,5 +32,5 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 3 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c index fb57803..c8a5800 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c @@ -34,6 +34,6 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c index 09067d3..186f6c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c @@ -34,6 +34,6 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 1 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 1 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 3824997..4283d12 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -130,6 +130,8 @@ foreach op $AUTOVEC_TEST_OPTS { "$op" "" dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/sat/*.\[cS\]]] \ "$op" "" + dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vx_vf/*.\[cS\]]] \ + "$op" "" } # All done. diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c index 0379429..edb12a1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-thread-jumps" } */ int d0, sj, v0, rp, zi; @@ -38,4 +38,4 @@ ka: goto ka; } -/* { dg-final { scan-assembler-times {vsetivli\tzero,\s*1} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\tzero,\s*1} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c index 5db1a40..3d3c5d6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c index 3f22fc8..013d32c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c index 64666d3..aef8325 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c index 07a64b4..fa4328f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" } */ #include "riscv_vector.h" @@ -50,5 +50,5 @@ void f (int8_t * restrict in, int8_t * restrict out, int l, int n, int m, size_t } } -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 4 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c index 6746c31..38966fe 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c @@ -35,6 +35,4 @@ double foo (int i, int j) return z; } -/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */ -/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c index fb1ac2b..f0d9c80 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c @@ -35,6 +35,4 @@ double foo (int i, int j) return z; } -/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */ -/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c index 9b4e237..81b240e 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { rv32 } } } */ /* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */ double ll2d (long long ll) diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c index f85c20e..3121cb6 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c @@ -10,7 +10,7 @@ unsigned int rol(unsigned int rs1, unsigned int rs2) } unsigned int ror(unsigned int rs1, unsigned int rs2) { - int shamt = rs2 & (64 - 1); + int shamt = rs2 & (32 - 1); return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1))); } diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c index 5a52adc..150cfd7 100644 --- a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c +++ b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32g_zfa -mabi=ilp32 -O0" } */ +/* { dg-options "-march=rv32g_zfa -mabi=ilp32 -O0 -mtune=sifive-p400-series" } */ double foo(long long a) { |