diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/alpha')
30 files changed, 543 insertions, 15 deletions
diff --git a/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr-safe-partial.c b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr-safe-partial.c new file mode 100644 index 0000000..15dc1b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr-safe-partial.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memclr-a2-o1-c9-ptr.c" + +/* Expect assembly such as: + + stb $31,1($16) + stw $31,2($16) + stw $31,4($16) + stw $31,6($16) + stw $31,8($16) + + that is with a byte store at offset 1, followed by word stores at + offsets 2, 4, 6, and 8. */ + +/* { dg-final { scan-assembler-times "\\sstb\\s\\\$31,1\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$31,2\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$31,4\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$31,6\\\(\\\$16\\\)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$31,8\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c index 3f7edc8..0ff1049 100644 --- a/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c +++ b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mbwx" } */ +/* { dg-options "-mbwx -mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ typedef unsigned int __attribute__ ((mode (QI))) int08_t; diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial-bwx.c new file mode 100644 index 0000000..1626261 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial-bwx.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-msafe-partial -mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memcpy-di-unaligned-dst.c" + +/* { dg-final { scan-assembler-times "\\sldq\\s" 7 } } */ +/* { dg-final { scan-assembler-times "\\sstb\\s" 16 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 6 } } */ +/* { dg-final { scan-assembler-not "\\sldq_l\\s" } } */ +/* { dg-final { scan-assembler-not "\\sldq_u\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstq\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstq_c\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial.c b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial.c new file mode 100644 index 0000000..869fdf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst-safe-partial.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-msafe-partial -mno-bwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memcpy-di-unaligned-dst.c" + +/* { dg-final { scan-assembler-times "\\sldq\\s" 7 } } */ +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 6 } } */ +/* { dg-final { scan-assembler-not "\\sldq_u\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstq\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst.c b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst.c index 5e9b5c3..373e2aa 100644 --- a/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst.c +++ b/gcc/testsuite/gcc.target/alpha/memcpy-di-unaligned-dst.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "" } */ +/* { dg-options "-mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ unsigned long unaligned_src_di[9] = { [0 ... 8] = 0xfefdfcfbfaf9f8f7 }; diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial-bwx.c new file mode 100644 index 0000000..2464005 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial-bwx.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-msafe-partial -mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memcpy-si-unaligned-dst.c" + +/* { dg-final { scan-assembler-times "\\sldl\\s" 15 } } */ +/* { dg-final { scan-assembler-times "\\sstb\\s" 20 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 6 } } */ +/* { dg-final { scan-assembler-not "\\sldq_l\\s" } } */ +/* { dg-final { scan-assembler-not "\\sldq_u\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstl\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstq_c\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial.c b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial.c new file mode 100644 index 0000000..6c9f877 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst-safe-partial.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-msafe-partial -mno-bwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "memcpy-si-unaligned-dst.c" + +/* { dg-final { scan-assembler-times "\\sldl\\s" 15 } } */ +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 4 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 4 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 6 } } */ +/* { dg-final { scan-assembler-not "\\sldq_u\\s" } } */ +/* { dg-final { scan-assembler-not "\\sstl\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst.c b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst.c index a2efade..aef4e59 100644 --- a/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst.c +++ b/gcc/testsuite/gcc.target/alpha/memcpy-si-unaligned-dst.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "" } */ +/* { dg-options "-mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ unsigned int unaligned_src_si[17] = { [0 ... 16] = 0xfefdfcfb }; diff --git a/gcc/testsuite/gcc.target/alpha/stb-bwa.c b/gcc/testsuite/gcc.target/alpha/stb-bwa.c new file mode 100644 index 0000000..d7a45db --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stb-bwa.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stb (char *p, char v) +{ + *p = v; +} + +/* Expect assembly such as: + + bic $16,7,$2 + insbl $17,$16,$17 +$L2: + ldq_l $1,0($2) + mskbl $1,$16,$1 + bis $17,$1,$1 + stq_c $1,0($2) + beq $1,$L2 + + with address masking. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sinsbl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskbl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stb-bwx.c b/gcc/testsuite/gcc.target/alpha/stb-bwx.c new file mode 100644 index 0000000..556397b --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stb-bwx.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stb (char *p, char v) +{ + *p = v; +} + +/* Expect assembly such as: + + stb $17,0($16) + */ + +/* { dg-final { scan-assembler-times "\\sstb\\s\\\$17,0\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stb.c b/gcc/testsuite/gcc.target/alpha/stb.c new file mode 100644 index 0000000..4953bc4 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stb.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -mno-safe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stb (char *p, char v) +{ + *p = v; +} + +/* Expect assembly such as: + + insbl $17,$16,$17 + ldq_u $1,0($16) + mskbl $1,$16,$1 + bis $17,$1,$17 + stq_u $17,0($16) + + without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldq_u\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sinsbl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskbl\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stba-bwa.c b/gcc/testsuite/gcc.target/alpha/stba-bwa.c new file mode 100644 index 0000000..07cf954 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stba-bwa.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + char c; + } +char_a; + +void +stba (char_a *p, char v) +{ + p->c = v; +} + +/* Expect assembly such as: + + and $17,0xff,$17 +$L2: + ldl_l $1,0($16) + bic $1,255,$1 + bis $17,$1,$1 + stl_c $1,0($16) + beq $1,$L2 + + without any INSBL or MSKBL instructions and without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldl_l\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl_c\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sand\\s\\\$\[0-9\]+,0xff,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sbic\\s\\\$\[0-9\]+,255,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:insbl|mskbl)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stba-bwx.c b/gcc/testsuite/gcc.target/alpha/stba-bwx.c new file mode 100644 index 0000000..08b51b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stba-bwx.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + char c; + } +char_a; + +void +stba (char_a *p, char v) +{ + p->c = v; +} + +/* Expect assembly such as: + + stb $17,0($16) + */ + +/* { dg-final { scan-assembler-times "\\sstb\\s\\\$17,0\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stba.c b/gcc/testsuite/gcc.target/alpha/stba.c new file mode 100644 index 0000000..fe7856c --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stba.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -mno-safe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + char c; + } +char_a; + +void +stba (char_a *p, char v) +{ + p->c = v; +} + +/* Expect assembly such as: + + and $17,0xff,$17 + ldl $1,0($16) + bic $1,255,$1 + bis $17,$1,$17 + stl $17,0($16) + + without any INSBL or MSKBL instructions and without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sand\\s\\\$\[0-9\]+,0xff,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sbic\\s\\\$\[0-9\]+,255,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:insbl|mskbl)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial-bwx.c new file mode 100644 index 0000000..70df631 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial-bwx.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stlx0.c" + +/* Expect assembly such as: + + stb $31,0($16) + stb $31,1($16) + stb $31,2($16) + stb $31,3($16) + + without any LDQ_U or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sstb\\s" 4 } } */ +/* { dg-final { scan-assembler-not "\\s(?:ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial.c b/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial.c new file mode 100644 index 0000000..dc3e86d --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stlx0-safe-partial.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stlx0.c" + +/* Expect assembly such as: + + lda $2,3($16) + bic $2,7,$2 +$L2: + ldq_l $1,0($2) + msklh $1,$16,$1 + stq_c $1,0($2) + beq $1,$L2 + bic $16,7,$2 +$L3: + ldq_l $1,0($2) + mskll $1,$16,$1 + stq_c $1,0($2) + beq $1,$L3 + + without any INSLH, INSLL, BIS, LDQ_U, or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\smsklh\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskll\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:bis|inslh|insll|ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stlx0.c b/gcc/testsuite/gcc.target/alpha/stlx0.c index 876eceb..3b340bc 100644 --- a/gcc/testsuite/gcc.target/alpha/stlx0.c +++ b/gcc/testsuite/gcc.target/alpha/stlx0.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "" } */ +/* { dg-options "-mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ typedef struct { int v __attribute__ ((packed)); } intx; diff --git a/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial-bwx.c new file mode 100644 index 0000000..62f6c78 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial-bwx.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stqx0.c" + +/* Expect assembly such as: + + stb $31,0($16) + stb $31,1($16) + stb $31,2($16) + stb $31,3($16) + stb $31,4($16) + stb $31,5($16) + stb $31,6($16) + stb $31,7($16) + + without any LDQ_U or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sstb\\s" 8 } } */ +/* { dg-final { scan-assembler-not "\\s(?:ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial.c b/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial.c new file mode 100644 index 0000000..7aa9e80 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stqx0-safe-partial.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stqx0.c" + +/* Expect assembly such as: + + lda $2,7($16) + bic $2,7,$2 +$L2: + ldq_l $1,0($2) + mskqh $1,$16,$1 + stq_c $1,0($2) + beq $1,$L2 + bic $16,7,$2 +$L3: + ldq_l $1,0($2) + mskql $1,$16,$1 + stq_c $1,0($2) + beq $1,$L3 + + without any INSLH, INSLL, BIS, LDQ_U, or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\smskqh\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskql\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:bis|insqh|insql|ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stqx0.c b/gcc/testsuite/gcc.target/alpha/stqx0.c index 042cdf0..80261a8 100644 --- a/gcc/testsuite/gcc.target/alpha/stqx0.c +++ b/gcc/testsuite/gcc.target/alpha/stqx0.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "" } */ +/* { dg-options "-mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ typedef struct { long v __attribute__ ((packed)); } longx; diff --git a/gcc/testsuite/gcc.target/alpha/stw-bwa.c b/gcc/testsuite/gcc.target/alpha/stw-bwa.c new file mode 100644 index 0000000..8b764b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stw-bwa.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stw (short *p, short v) +{ + *p = v; +} + +/* Expect assembly such as: + + bic $16,7,$2 + inswl $17,$16,$17 +$L2: + ldq_l $1,0($2) + mskwl $1,$16,$1 + bis $17,$1,$1 + stq_c $1,0($2) + beq $1,$L2 + + with address masking. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sinswl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskwl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stw-bwx.c b/gcc/testsuite/gcc.target/alpha/stw-bwx.c new file mode 100644 index 0000000..b4f18ad --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stw-bwx.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stw (short *p, short v) +{ + *p = v; +} + +/* Expect assembly such as: + + stw $17,0($16) + */ + +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$17,0\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stw.c b/gcc/testsuite/gcc.target/alpha/stw.c new file mode 100644 index 0000000..655fdd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stw.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -mno-safe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void +stw (short *p, short v) +{ + *p = v; +} + +/* Expect assembly such as: + + inswl $17,$16,$17 + ldq_u $1,0($16) + mskwl $1,$16,$1 + bis $17,$1,$17 + stq_u $17,0($16) + + without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldq_u\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_u\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sinswl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskwl\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwa-bwa.c b/gcc/testsuite/gcc.target/alpha/stwa-bwa.c new file mode 100644 index 0000000..9ee226e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwa-bwa.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + short c; + } +short_a; + +void +stwa (short_a *p, short v) +{ + p->c = v; +} + +/* Expect assembly such as: + + zapnot $17,3,$17 +$L2: + ldl_l $1,0($16) + zapnot $1,252,$1 + bis $17,$1,$1 + stl_c $1,0($16) + beq $1,$L2 + + without any INSWL or MSKWL instructions and without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldl_l\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl_c\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\szapnot\\s\\\$\[0-9\]+,3,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\szapnot\\s\\\$\[0-9\]+,252,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:inswl|mskwl)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwa-bwx.c b/gcc/testsuite/gcc.target/alpha/stwa-bwx.c new file mode 100644 index 0000000..6331d62 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwa-bwx.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + short c; + } +short_a; + +void +stwa (short_a *p, short v) +{ + p->c = v; +} + +/* Expect assembly such as: + + stw $17,0($16) + */ + +/* { dg-final { scan-assembler-times "\\sstw\\s\\\$17,0\\\(\\\$16\\\)\\s" 1 } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwa.c b/gcc/testsuite/gcc.target/alpha/stwa.c new file mode 100644 index 0000000..6b273cf --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwa.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -mno-safe-bwa" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +typedef union + { + int i; + short c; + } +short_a; + +void +stwa (short_a *p, short v) +{ + p->c = v; +} + +/* Expect assembly such as: + + zapnot $17,3,$17 + ldl $1,0($16) + zapnot $1,252,$1 + bis $17,$1,$17 + stl $17,0($16) + + without any INSWL or MSKWL instructions and without address masking. */ + +/* { dg-final { scan-assembler-times "\\sldl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\szapnot\\s\\\$\[0-9\]+,3,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\szapnot\\s\\\$\[0-9\]+,252,\\\$\[0-9\]+\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbic\\s\\\$\[0-9\]+,7,\\\$\[0-9\]+\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:inswl|mskwl)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwx0-bwx.c b/gcc/testsuite/gcc.target/alpha/stwx0-bwx.c index bba31df..6256f82 100644 --- a/gcc/testsuite/gcc.target/alpha/stwx0-bwx.c +++ b/gcc/testsuite/gcc.target/alpha/stwx0-bwx.c @@ -1,19 +1,15 @@ /* { dg-do compile } */ -/* { dg-options "-mbwx" } */ +/* { dg-options "-mbwx -mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ -typedef struct { short v __attribute__ ((packed)); } shortx; - -void -stwx0 (shortx *p) -{ - p->v = 0; -} +#include "stwx0.c" /* Expect assembly such as: stb $31,0($16) stb $31,1($16) - */ + + without any LDQ_U or STQ_U instructions. */ /* { dg-final { scan-assembler-times "\\sstb\\s\\\$31," 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial-bwx.c b/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial-bwx.c new file mode 100644 index 0000000..031d4c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial-bwx.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mbwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stwx0.c" + +/* Expect assembly such as: + + stb $31,0($16) + stb $31,1($16) + + without any LDQ_U or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sstb\\s\\\$31," 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial.c b/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial.c new file mode 100644 index 0000000..3d0eedd --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/stwx0-safe-partial.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-bwx -msafe-partial" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#include "stwx0.c" + +/* Expect assembly such as: + + lda $2,1($16) + bic $2,7,$2 +$L2: + ldq_l $1,0($2) + mskwh $1,$16,$1 + stq_c $1,0($2) + beq $1,$L2 + bic $16,7,$2 +$L3: + ldq_l $1,0($2) + mskwl $1,$16,$1 + stq_c $1,0($2) + beq $1,$L3 + + without any INSWH, INSWL, BIS, LDQ_U, or STQ_U instructions. */ + +/* { dg-final { scan-assembler-times "\\sldq_l\\s" 2 } } */ +/* { dg-final { scan-assembler-times "\\smskwh\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\smskwl\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sstq_c\\s" 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:bis|inswh|inswl|ldq_u|stq_u)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/alpha/stwx0.c b/gcc/testsuite/gcc.target/alpha/stwx0.c index d60d33f..ad4e716 100644 --- a/gcc/testsuite/gcc.target/alpha/stwx0.c +++ b/gcc/testsuite/gcc.target/alpha/stwx0.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mno-bwx" } */ +/* { dg-options "-mno-bwx -mno-safe-partial" } */ /* { dg-skip-if "" { *-*-* } { "-O0" } } */ typedef struct { short v __attribute__ ((packed)); } shortx; |