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-rw-r--r--gcc/simplify-rtx.cc21
1 files changed, 21 insertions, 0 deletions
diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
index 7bcbe11..cbe61b4 100644
--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
@@ -4063,6 +4063,20 @@ simplify_context::simplify_binary_operation_1 (rtx_code code,
&& rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1))
return simplify_gen_binary (IOR, mode, XEXP (op0, 1), op1);
+ /* Convert (xor (and (rotate (~1) A) B) (ashift 1 A))
+ into B | (1 << A). */
+ if (SHIFT_COUNT_TRUNCATED
+ && GET_CODE (op0) == AND
+ && GET_CODE (XEXP (op0, 0)) == ROTATE
+ && CONST_INT_P (XEXP (XEXP (op0, 0), 0))
+ && INTVAL (XEXP (XEXP (op0, 0), 0)) == -2
+ && GET_CODE (op1) == ASHIFT
+ && CONST_INT_P (XEXP (op1, 0))
+ && INTVAL (XEXP (op1, 0)) == 1
+ && rtx_equal_p (XEXP (XEXP (op0, 0), 1), XEXP (op1, 1))
+ && !side_effects_p (XEXP (op1, 1)))
+ return simplify_gen_binary (IOR, mode, XEXP (op0, 1), op1);
+
tem = simplify_with_subreg_not (code, mode, op0, op1);
if (tem)
return tem;
@@ -7387,6 +7401,13 @@ simplify_context::simplify_ternary_operation (rtx_code code, machine_mode mode,
return gen_rtx_CONST_VECTOR (mode, v);
}
+ if (swap_commutative_operands_p (op0, op1)
+ /* Two operands have same precedence, then first bit of mask
+ select first operand. */
+ || (!swap_commutative_operands_p (op1, op0) && !(sel & 1)))
+ return simplify_gen_ternary (code, mode, mode, op1, op0,
+ GEN_INT (~sel & mask));
+
/* Replace (vec_merge (vec_merge a b m) c n) with (vec_merge b c n)
if no element from a appears in the result. */
if (GET_CODE (op0) == VEC_MERGE)