diff options
Diffstat (limited to 'gcc/lra-constraints.cc')
| -rw-r--r-- | gcc/lra-constraints.cc | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc index 1f63113..61bbb93 100644 --- a/gcc/lra-constraints.cc +++ b/gcc/lra-constraints.cc @@ -240,7 +240,7 @@ enough_allocatable_hard_regs_p (enum reg_class reg_class, enum machine_mode reg_mode) { int i, j, hard_regno, class_size, nregs; - + if (hard_reg_set_subset_p (reg_class_contents[reg_class], lra_no_alloc_regs)) return false; class_size = ira_class_hard_regs_num[reg_class]; @@ -518,7 +518,7 @@ static void update_equiv (int regno) { rtx x; - + if ((x = ira_reg_equiv[regno].memory) != NULL_RTX) ira_reg_equiv[regno].memory = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, @@ -1046,7 +1046,7 @@ match_reload (signed char out, signed char *ins, signed char *outs, bool asm_p = asm_noperands (PATTERN (curr_insn)) >= 0; int hr; HARD_REG_SET temp_hard_reg_set; - + if (asm_p && (hr = get_hard_regno (out_rtx)) >= 0 && hard_regno_nregs (hr, inmode) > 1) { @@ -1105,7 +1105,7 @@ match_reload (signed char out, signed char *ins, signed char *outs, if (GET_CODE (in_rtx) == SUBREG) { rtx subreg_reg = SUBREG_REG (in_rtx); - + /* If SUBREG_REG is dying here and sub-registers IN_RTX and NEW_IN_REG are similar, we can use the same hard register for REG and SUBREG_REG. */ @@ -2045,7 +2045,7 @@ prohibited_class_reg_set_mode_p (enum reg_class rclass, machine_mode mode) { HARD_REG_SET temp; - + lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set)); temp = set & ~lra_no_alloc_regs; return (hard_reg_set_subset_p @@ -2067,7 +2067,7 @@ update_and_check_small_class_inputs (int nop, int nalt, { static unsigned int small_class_check[LIM_REG_CLASSES]; static int small_class_input_nums[LIM_REG_CLASSES]; - + if (SMALL_REGISTER_CLASS_P (op_class) /* We are interesting in classes became small because of fixing some hard regs, e.g. by an user through GCC options. */ @@ -2220,7 +2220,7 @@ process_alt_operands (int only_alternative) print_curr_insn_alt (nalt); fprintf (lra_dump_file, "\n"); } - + bool matching_early_clobber[MAX_RECOG_OPERANDS]; curr_small_class_check++; overall = losers = addr_losers = 0; @@ -2367,7 +2367,7 @@ process_alt_operands (int only_alternative) || curr_operand_mode[nop] == BLKmode) && curr_operand_mode[m] != curr_operand_mode[nop]) break; - + m_hregno = get_hard_regno (*curr_id->operand_loc[m]); /* We are supposed to match a previous operand. If we do, we win if that one did. If we do @@ -2438,7 +2438,7 @@ process_alt_operands (int only_alternative) && REG_USERVAR_P (m_reg)) { int i; - + for (i = 0; i < early_clobbered_regs_num; i++) if (m == early_clobbered_nops[i]) break; @@ -3115,7 +3115,7 @@ process_alt_operands (int only_alternative) nop); reject += 3; } - + /* If reload requires moving value through secondary memory, it will need one more insn at least. */ if (this_alternative != NO_REGS @@ -3992,7 +3992,7 @@ process_address_1 (int nop, bool check_only_p, SCRATCH, SCRATCH, curr_insn); rtx addr = *ad.inner; - + new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, NULL, "addr"); /* addr => new_base. */ lra_emit_move (new_reg, addr); @@ -4185,7 +4185,7 @@ curr_insn_transform (bool check_only_p) if (curr_static_id->operand[i].is_operator) continue; - + old = op = *curr_id->operand_loc[i]; if (GET_CODE (old) == SUBREG) old = SUBREG_REG (old); @@ -4234,7 +4234,7 @@ curr_insn_transform (bool check_only_p) change_p = true; lra_update_dup (curr_id, i); } - + if (change_p) /* If we've changed the instruction then any alternative that we chose previously may no longer be valid. */ @@ -4587,7 +4587,7 @@ curr_insn_transform (bool check_only_p) for (j = 0; goal_alt_matched[i][j] != -1; j++) { rtx op2 = *curr_id->operand_loc[goal_alt_matched[i][j]]; - + if (REG_P (op2) && REGNO (op) != REGNO (op2)) break; } @@ -4606,7 +4606,7 @@ curr_insn_transform (bool check_only_p) else { enum reg_class rclass, common_class; - + if (REG_P (op) && goal_alt[i] != NO_REGS && (regno = REGNO (op)) >= new_regno_start && (rclass = get_reg_class (regno)) == ALL_REGS @@ -5161,7 +5161,7 @@ combine_reload_insn (rtx_insn *from, rtx_insn *to) enum reg_class to_class, from_class; int n, nop; signed char changed_nops[MAX_RECOG_OPERANDS + 1]; - + /* Check conditions for second memory reload and original insn: */ if ((targetm.secondary_memory_needed == hook_bool_mode_reg_class_t_reg_class_t_false) @@ -5172,7 +5172,7 @@ combine_reload_insn (rtx_insn *from, rtx_insn *to) lra_insn_recog_data_t id = lra_get_insn_recog_data (to); struct lra_static_insn_data *static_id = id->insn_static_data; - + if (id->used_insn_alternative == LRA_UNKNOWN_ALT || (set = single_set (from)) == NULL_RTX) return false; @@ -5444,7 +5444,7 @@ lra_constraints (bool first_p) cannot be changed. Such insns might be not in init_insns because we don't update equiv data during insn transformations. - + As an example, let suppose that a pseudo got hard register and on the 1st pass was not changed to equivalent constant. We generate an @@ -6159,7 +6159,7 @@ split_reg (bool before_p, int original_regno, rtx_insn *insn, if (lra_dump_file != NULL) fprintf (lra_dump_file, " ((((((((((((((((((((((((((((((((((((((((((((((((\n"); - + if (call_save_p) { mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno, @@ -6323,7 +6323,7 @@ spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_i unsigned int uid; bitmap_iterator bi; HARD_REG_SET ignore; - + lra_assert (from != NULL && to != NULL); ignore = lra_no_alloc_regs; EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) @@ -6331,7 +6331,7 @@ spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_i lra_insn_recog_data_t id = lra_insn_recog_data[uid]; struct lra_static_insn_data *static_id = id->insn_static_data; struct lra_insn_reg *reg; - + for (reg = id->regs; reg != NULL; reg = reg->next) if (reg->regno < FIRST_PSEUDO_REGISTER) SET_HARD_REG_BIT (ignore, reg->regno); |