5 files changed, 296 insertions, 0 deletions
diff --git a/gcc/doc/contrib.texi b/gcc/doc/contrib.texi
index 37e24f0..face894 100644
--- a/gcc/doc/contrib.texi
+++ b/gcc/doc/contrib.texi
@@ -395,6 +395,9 @@ of testing and bug fixing, particularly of GCC configury code.
 Steve Holmgren for MachTen patches.
 
 @item
+Mat Hostetter for work on the TILE-Gx and TILEPro ports.
+
+@item
 Jan Hubicka for his x86 port improvements.
 
 @item
@@ -506,6 +509,9 @@ handling merges from GCC2, reviewing tons of patches that might have
 fallen through the cracks else, and random but extensive hacking.
 
 @item
+Walter Lee for work on the TILE-Gx and TILEPro ports.
+
+@item
 Marc Lehmann for his direction via the steering committee and helping
 with analysis and improvements of x86 performance.
 
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index ae50ae0..4c71960 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -8531,6 +8531,8 @@ instructions, but allow the compiler to schedule those calls.
 * SPARC VIS Built-in Functions::
 * SPU Built-in Functions::
 * TI C6X Built-in Functions::
+* TILE-Gx Built-in Functions::
+* TILEPro Built-in Functions::
 @end menu
 
 @node Alpha Built-in Functions
@@ -13718,6 +13720,78 @@ int _abs2 (int)
 
 @end smallexample
 
+@node TILE-Gx Built-in Functions
+@subsection TILE-Gx Built-in Functions
+
+GCC provides intrinsics to access every instruction of the TILE-Gx
+processor.  The intrinsics are of the form:
+
+@smallexample
+
+unsigned long long __insn_@var{op} (...)
+
+@end smallexample
+
+Where @var{op} is the name of the instruction.  Refer to the ISA manual
+for the complete list of instructions.
+
+GCC also provides intrinsics to directly access the network registers.
+The intrinsics are:
+
+@smallexample
+
+unsigned long long __tile_idn0_receive (void)
+unsigned long long __tile_idn1_receive (void)
+unsigned long long __tile_udn0_receive (void)
+unsigned long long __tile_udn1_receive (void)
+unsigned long long __tile_udn2_receive (void)
+unsigned long long __tile_udn3_receive (void)
+void __tile_idn_send (unsigned long long)
+void __tile_udn_send (unsigned long long)
+
+@end smallexample
+
+The intrinsic @code{void __tile_network_barrier (void)} is used to
+guarantee that no network operatons before it will be reordered with
+those after it.
+
+@node TILEPro Built-in Functions
+@subsection TILEPro Built-in Functions
+
+GCC provides intrinsics to access every instruction of the TILEPro
+processor.  The intrinsics are of the form:
+
+@smallexample
+
+unsigned __insn_@var{op} (...)
+
+@end smallexample
+
+Where @var{op} is the name of the instruction.  Refer to the ISA manual
+for the complete list of instructions.
+
+GCC also provides intrinsics to directly access the network registers.
+The intrinsics are:
+
+@smallexample
+
+unsigned __tile_idn0_receive (void)
+unsigned __tile_idn1_receive (void)
+unsigned __tile_sn_receive (void)
+unsigned __tile_udn0_receive (void)
+unsigned __tile_udn1_receive (void)
+unsigned __tile_udn2_receive (void)
+unsigned __tile_udn3_receive (void)
+void __tile_idn_send (unsigned)
+void __tile_sn_send (unsigned)
+void __tile_udn_send (unsigned)
+
+@end smallexample
+
+The intrinsic @code{void __tile_network_barrier (void)} is used to
+guarantee that no network operatons before it will be reordered with
+those after it.
+
 @node Target Format Checks
 @section Format Checks Specific to Particular Target Machines
 
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 4a85397..f1f2a6c 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -3096,6 +3096,10 @@ information are.
 @item
 @uref{#c6x-x-x,,c6x-*-*}
 @item
+@uref{#tilegx-x-linux,,tilegx-*-linux*}
+@item
+@uref{#tilepro-x-linux,,tilepro-*-linux*}
+@item
 @uref{#x-x-vxworks,,*-*-vxworks*}
 @item
 @uref{#x86-64-x-x,,x86_64-*-*, amd64-*-*}
@@ -4460,6 +4464,22 @@ The C6X family of processors. This port requires binutils-2.22 or newer.
 @html
 <hr />
 @end html
+@heading @anchor{tilegx-*-linux}tilegx-*-linux*
+
+The TILE-Gx processor running GNU/Linux.  This port requires
+binutils-2.22 or newer.
+
+@html
+<hr />
+@end html
+@heading @anchor{tilepro-*-linux}tilepro-*-linux*
+
+The TILEPro processor running GNU/Linux.  This port requires
+binutils-2.22 or newer.
+
+@html
+<hr />
+@end html
 @heading @anchor{x-x-vxworks}*-*-vxworks*
 Support for VxWorks is in flux.  At present GCC supports @emph{only} the
 very recent VxWorks 5.5 (aka Tornado 2.2) release, and only on PowerPC@.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6c61e53..9f3af4c 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -923,6 +923,12 @@ See RS/6000 and PowerPC Options.
 @emph{System V Options}
 @gccoptlist{-Qy  -Qn  -YP,@var{paths}  -Ym,@var{dir}}
 
+@emph{TILE-Gx Options}
+@gccoptlist{-mcpu=CPU -m32 -m64}
+
+@emph{TILEPro Options}
+@gccoptlist{-mcpu=CPU -m32}
+
 @emph{V850 Options}
 @gccoptlist{-mlong-calls  -mno-long-calls  -mep  -mno-ep @gol
 -mprolog-function  -mno-prolog-function  -mspace @gol
@@ -10349,6 +10355,8 @@ platform.
 * SPARC Options::
 * SPU Options::
 * System V Options::
+* TILE-Gx Options::
+* TILEPro Options::
 * V850 Options::
 * VAX Options::
 * VxWorks Options::
@@ -18479,6 +18487,46 @@ The assembler uses this option.
 @c the generic assembler that comes with Solaris takes just -Ym.
 @end table
 
+@node TILE-Gx Options
+@subsection TILE-Gx Options
+@cindex TILE-Gx options
+
+These @samp{-m} options are supported on the TILE-Gx:
+
+@table @gcctabopt
+@item -mcpu=@var{name}
+@opindex mcpu
+Selects the type of CPU to be targeted.  Currently the only supported
+type is @samp{tilegx}.
+
+@item -m32
+@itemx -m64
+@opindex m32
+@opindex m64
+Generate code for a 32-bit or 64-bit environment.  The 32-bit
+environment sets int, long, and pointer to 32 bits.  The 64-bit
+environment sets int to 32 bits and long and pointer to 64 bits.
+@end table
+
+@node TILEPro Options
+@subsection TILEPro Options
+@cindex TILEPro options
+
+These @samp{-m} options are supported on the TILEPro:
+
+@table @gcctabopt
+@item -mcpu=@var{name}
+@opindex mcpu
+Selects the type of CPU to be targeted.  Currently the only supported
+type is @samp{tilepro}.
+
+@item -m32
+@opindex m32
+Generate code for a 32-bit environment, which sets int, long, and
+pointer to 32 bits.  This is the only supported behavior so the flag
+is essentially ignored.
+@end table
+
 @node V850 Options
 @subsection V850 Options
 @cindex V850 Options
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 92c1b28..c4eb355 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3576,6 +3576,154 @@ Register B14 (aka DP).
 
 @end table
 
+@item TILE-Gx---@file{config/tilegx/constraints.md}
+@table @code
+@item R00
+@itemx R01
+@itemx R02
+@itemx R03
+@itemx R04
+@itemx R05
+@itemx R06
+@itemx R07
+@itemx R08
+@itemx R09
+@itemx R010
+Each of these represents a register constraint for an individual
+register, from r0 to r10.
+
+@item I
+Signed 8-bit integer constant.
+
+@item J
+Signed 16-bit integer constant.
+
+@item K
+Unsigned 16-bit integer constant.
+
+@item L
+Integer constant that fits in one signed byte when incremented by one
+(@minus{}129 @dots{} 126).
+
+@item m
+Memory operand.  If used together with @samp{<} or @samp{>}, the
+operand can have postincrement which requires printing with @samp{%In}
+and @samp{%in} on TILE-Gx.  For example:
+
+@smallexample
+asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
+@end smallexample
+
+@item M
+A bit mask suitable for the BFINS instruction.
+
+@item N
+Integer constant that is a byte tiled out eight times.
+
+@item O
+The integer zero constant.
+
+@item P
+Integer constant that is a sign-extended byte tiled out as four shorts.
+
+@item Q
+Integer constant that fits in one signed byte when incremented
+(@minus{}129 @dots{} 126), but excluding -1.
+
+@item S
+Integer constant that has all 1 bits consecutive and starting at bit 0.
+
+@item T
+A 16-bit fragment of a got, tls, or pc-relative reference.
+
+@item U
+Memory operand except postincrement.  This is roughly the same as
+@samp{m} when not used together with @samp{<} or @samp{>}.
+
+@item W
+An 8-element vector constant with identical elements.
+
+@item Y
+A 4-element vector constant with identical elements.
+
+@item Z0
+The integer constant 0xffffffff.
+
+@item Z1
+The integer constant 0xffffffff00000000.
+
+@end table
+
+@item TILEPro---@file{config/tilepro/constraints.md}
+@table @code
+@item R00
+@itemx R01
+@itemx R02
+@itemx R03
+@itemx R04
+@itemx R05
+@itemx R06
+@itemx R07
+@itemx R08
+@itemx R09
+@itemx R010
+Each of these represents a register constraint for an individual
+register, from r0 to r10.
+
+@item I
+Signed 8-bit integer constant.
+
+@item J
+Signed 16-bit integer constant.
+
+@item K
+Nonzero integer constant with low 16 bits zero.
+
+@item L
+Integer constant that fits in one signed byte when incremented by one
+(@minus{}129 @dots{} 126).
+
+@item m
+Memory operand.  If used together with @samp{<} or @samp{>}, the
+operand can have postincrement which requires printing with @samp{%In}
+and @samp{%in} on TILEPro.  For example:
+
+@smallexample
+asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
+@end smallexample
+
+@item M
+A bit mask suitable for the MM instruction.
+
+@item N
+Integer constant that is a byte tiled out four times.
+
+@item O
+The integer zero constant.
+
+@item P
+Integer constant that is a sign-extended byte tiled out as two shorts.
+
+@item Q
+Integer constant that fits in one signed byte when incremented
+(@minus{}129 @dots{} 126), but excluding -1.
+
+@item T
+A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
+reference.
+
+@item U
+Memory operand except postincrement.  This is roughly the same as
+@samp{m} when not used together with @samp{<} or @samp{>}.
+
+@item W
+A 4-element vector constant with identical elements.
+
+@item Y
+A 2-element vector constant with identical elements.
+
+@end table
+
 @item Xtensa---@file{config/xtensa/constraints.md}
 @table @code
 @item a