diff options
Diffstat (limited to 'gcc/doc')
-rw-r--r-- | gcc/doc/contrib.texi | 10 | ||||
-rw-r--r-- | gcc/doc/install.texi | 30 | ||||
-rw-r--r-- | gcc/doc/invoke.texi | 79 | ||||
-rw-r--r-- | gcc/doc/md.texi | 20 |
4 files changed, 139 insertions, 0 deletions
diff --git a/gcc/doc/contrib.texi b/gcc/doc/contrib.texi index cb1ac95..85cd1d3 100644 --- a/gcc/doc/contrib.texi +++ b/gcc/doc/contrib.texi @@ -173,6 +173,10 @@ Denis Chertykov for contributing and maintaining the AVR port, the first GCC por for an 8-bit architecture. @item +Kito Cheng for his work on the RISC-V port, including bringing up the test +suite and maintenance. + +@item Scott Christley for his Objective-C contributions. @item @@ -217,6 +221,9 @@ Paul Dale for his work to add uClinux platform support to the m68k backend. @item +Palmer Dabbelt for his work maintaining the RISC-V port. + +@item Dario Dariol contributed the four varieties of sample programs that print a copy of their source. @@ -1035,6 +1042,9 @@ associated configure steps. Todd Vierling for contributions for NetBSD ports. @item +Andrew Waterman for contributing the RISC-V port, as well as maintaining it. + +@item Jonathan Wakely for contributing libstdc++ Doxygen notes and XHTML guidance. diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index bc4edfd..0c82fe9 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -4297,6 +4297,36 @@ This configuration is intended for embedded systems. @html <hr /> @end html +@anchor{riscv32-x-elf} +@heading riscv32-*-elf +The RISC-V RV32 instruction set. +This configuration is intended for embedded systems. + +@html +<hr /> +@end html +@anchor{riscv64-x-elf} +@heading riscv64-*-elf +The RISC-V RV64 instruction set. +This configuration is intended for embedded systems. + +@html +<hr /> +@end html +@anchor{riscv32-x-linux} +@heading riscv32-*-linux +The RISC-V RV32 instruction set running GNU/Linux. + +@html +<hr /> +@end html +@anchor{riscv64-x-linux} +@heading riscv64-*-linux +The RISC-V RV64 instruction set running GNU/Linux. + +@html +<hr /> +@end html @anchor{rx-x-elf} @heading rx-*-elf The Renesas RX processor. See diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 08d26a1..ce3c704 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1026,6 +1026,20 @@ See RS/6000 and PowerPC Options. -mstack-protector-guard-offset=@var{offset} @gol -mlra -mno-lra} +@emph{RISC-V Options} +@gccoptlist{-mbranch-cost=@var{N-instruction} @gol +-mmemcpy -mno-memcpy @gol +-mplt -mno-plt @gol +-mabi=@var{ABI-string} @gol +-mfdiv -mno-fdiv @gol +-mdiv -mno-div @gol +-march=@var{ISA-string} @gol +-mtune=@var{processor-string} @gol +-msmall-data-limit=@var{N-bytes} @gol +-msave-restore -mno-save-restore @gol +-mcmodel=@var{code-model} @gol +-mexplicit-relocs -mno-explicit-relocs @gol} + @emph{RX Options} @gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol -mcpu=@gol @@ -13744,6 +13758,7 @@ platform. * PowerPC Options:: * RL78 Options:: * RS/6000 and PowerPC Options:: +* RISC-V Options:: * RX Options:: * S/390 and zSeries Options:: * Score Options:: @@ -22137,6 +22152,70 @@ offset from that base register. The default for those is as specified in the relevant ABI. @end table +@node RISC-V Options +@subsection RISC-V Options +@cindex RISC-V Options + +These command-line options are defined for RISC-V targets: + +@table @gcctabopt +@item -mbranch-cost=@var{n} +@opindex mbranch-cost +Set the cost of branches to roughly @var{n} instructions. + +@item -mmemcpy +@itemx -mno-memcpy +@opindex mmemcpy +Don't optimize block moves. + +@item -mplt +@itemx -mno-plt +@opindex plt +When generating PIC code, allow the use of PLTs. Ignored for non-PIC. + +@item -mabi=@var{ABI-string} +@opindex mabi +Specify integer and floating-point calling convention. This defaults to the +natural calling convention: e.g.@ LP64 for RV64I, ILP32 for RV32I, LP64D for +RV64G. + +@item -mfdiv +@itemx -mno-fdiv +@opindex mfdiv +Use hardware floating-point divide and square root instructions. This requires +the F or D extensions for floating-point registers. + +@item -mdiv +@itemx -mno-div +@opindex mdiv +Use hardware instructions for integer division. This requires the M extension. + +@item -march=@var{ISA-string} +@opindex march +Generate code for given RISC-V ISA (e.g.@ @samp{rv64im}). ISA strings must be +lower-case. Examples include @samp{rv64i}, @samp{rv32g}, and @samp{rv32imaf}. + +@item -mtune=@var{processor-string} +@opindex mtune +Optimize the output for the given processor, specified by microarchitecture +name. + +@item -msmall-data-limit=@var{n} +@opindex msmall-data-limit +Put global and static data smaller than @var{n} bytes into a special section +(on some targets). + +@item -msave-restore +@itemx -mno-save-restore +@opindex msave-restore +Use smaller but slower prologue and epilogue code. + +@item -mcmodel=@var{code-model} +@opindex mcmodel +Specify the code model. + +@end table + @node RX Options @subsection RX Options @cindex RX Options diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 11266d7..3f71074 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3362,6 +3362,26 @@ The @code{X} register. @end table +@item RISC-V---@file{config/riscv/constraints.md} +@table @code + +@item f +A floating-point register (if availiable). + +@item I +An I-type 12-bit signed immediate. + +@item J +Integer zero. + +@item K +A 5-bit unsigned immediate for CSR access instructions. + +@item A +An address that is held in a general-purpose register. + +@end table + @item RX---@file{config/rx/constraints.md} @table @code @item Q |