diff options
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/extend.texi | 155 | ||||
| -rw-r--r-- | gcc/doc/gm2.texi | 2 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 516 | ||||
| -rw-r--r-- | gcc/doc/md.texi | 9 | ||||
| -rw-r--r-- | gcc/doc/riscv-ext.texi | 665 | ||||
| -rw-r--r-- | gcc/doc/sourcebuild.texi | 4 |
6 files changed, 681 insertions, 670 deletions
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 212d248..40ccf22 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -17905,7 +17905,6 @@ instructions, but allow the compiler to schedule those calls. * Alpha Built-in Functions:: * ARC Built-in Functions:: * ARC SIMD Built-in Functions:: -* ARM iWMMXt Built-in Functions:: * ARM C Language Extensions (ACLE):: * ARM Floating Point Status and Control Intrinsics:: * ARM ARMv8-M Security Extensions:: @@ -18521,160 +18520,6 @@ _v4hi __builtin_arc_vaddsub4h (__v4hi, __v4hi); _v4hi __builtin_arc_vsubadd4h (__v4hi, __v4hi); @end example -@node ARM iWMMXt Built-in Functions -@subsection ARM iWMMXt Built-in Functions - -These built-in functions are available for the ARM family of -processors when the @option{-mcpu=iwmmxt} switch is used: - -@smallexample -typedef int v2si __attribute__ ((vector_size (8))); -typedef short v4hi __attribute__ ((vector_size (8))); -typedef char v8qi __attribute__ ((vector_size (8))); - -int __builtin_arm_getwcgr0 (void); -void __builtin_arm_setwcgr0 (int); -int __builtin_arm_getwcgr1 (void); -void __builtin_arm_setwcgr1 (int); -int __builtin_arm_getwcgr2 (void); -void __builtin_arm_setwcgr2 (int); -int __builtin_arm_getwcgr3 (void); -void __builtin_arm_setwcgr3 (int); -int __builtin_arm_textrmsb (v8qi, int); -int __builtin_arm_textrmsh (v4hi, int); -int __builtin_arm_textrmsw (v2si, int); -int __builtin_arm_textrmub (v8qi, int); -int __builtin_arm_textrmuh (v4hi, int); -int __builtin_arm_textrmuw (v2si, int); -v8qi __builtin_arm_tinsrb (v8qi, int, int); -v4hi __builtin_arm_tinsrh (v4hi, int, int); -v2si __builtin_arm_tinsrw (v2si, int, int); -long long __builtin_arm_tmia (long long, int, int); -long long __builtin_arm_tmiabb (long long, int, int); -long long __builtin_arm_tmiabt (long long, int, int); -long long __builtin_arm_tmiaph (long long, int, int); -long long __builtin_arm_tmiatb (long long, int, int); -long long __builtin_arm_tmiatt (long long, int, int); -int __builtin_arm_tmovmskb (v8qi); -int __builtin_arm_tmovmskh (v4hi); -int __builtin_arm_tmovmskw (v2si); -long long __builtin_arm_waccb (v8qi); -long long __builtin_arm_wacch (v4hi); -long long __builtin_arm_waccw (v2si); -v8qi __builtin_arm_waddb (v8qi, v8qi); -v8qi __builtin_arm_waddbss (v8qi, v8qi); -v8qi __builtin_arm_waddbus (v8qi, v8qi); -v4hi __builtin_arm_waddh (v4hi, v4hi); -v4hi __builtin_arm_waddhss (v4hi, v4hi); -v4hi __builtin_arm_waddhus (v4hi, v4hi); -v2si __builtin_arm_waddw (v2si, v2si); -v2si __builtin_arm_waddwss (v2si, v2si); -v2si __builtin_arm_waddwus (v2si, v2si); -v8qi __builtin_arm_walign (v8qi, v8qi, int); -long long __builtin_arm_wand(long long, long long); -long long __builtin_arm_wandn (long long, long long); -v8qi __builtin_arm_wavg2b (v8qi, v8qi); -v8qi __builtin_arm_wavg2br (v8qi, v8qi); -v4hi __builtin_arm_wavg2h (v4hi, v4hi); -v4hi __builtin_arm_wavg2hr (v4hi, v4hi); -v8qi __builtin_arm_wcmpeqb (v8qi, v8qi); -v4hi __builtin_arm_wcmpeqh (v4hi, v4hi); -v2si __builtin_arm_wcmpeqw (v2si, v2si); -v8qi __builtin_arm_wcmpgtsb (v8qi, v8qi); -v4hi __builtin_arm_wcmpgtsh (v4hi, v4hi); -v2si __builtin_arm_wcmpgtsw (v2si, v2si); -v8qi __builtin_arm_wcmpgtub (v8qi, v8qi); -v4hi __builtin_arm_wcmpgtuh (v4hi, v4hi); -v2si __builtin_arm_wcmpgtuw (v2si, v2si); -long long __builtin_arm_wmacs (long long, v4hi, v4hi); -long long __builtin_arm_wmacsz (v4hi, v4hi); -long long __builtin_arm_wmacu (long long, v4hi, v4hi); -long long __builtin_arm_wmacuz (v4hi, v4hi); -v4hi __builtin_arm_wmadds (v4hi, v4hi); -v4hi __builtin_arm_wmaddu (v4hi, v4hi); -v8qi __builtin_arm_wmaxsb (v8qi, v8qi); -v4hi __builtin_arm_wmaxsh (v4hi, v4hi); -v2si __builtin_arm_wmaxsw (v2si, v2si); -v8qi __builtin_arm_wmaxub (v8qi, v8qi); -v4hi __builtin_arm_wmaxuh (v4hi, v4hi); -v2si __builtin_arm_wmaxuw (v2si, v2si); -v8qi __builtin_arm_wminsb (v8qi, v8qi); -v4hi __builtin_arm_wminsh (v4hi, v4hi); -v2si __builtin_arm_wminsw (v2si, v2si); -v8qi __builtin_arm_wminub (v8qi, v8qi); -v4hi __builtin_arm_wminuh (v4hi, v4hi); -v2si __builtin_arm_wminuw (v2si, v2si); -v4hi __builtin_arm_wmulsm (v4hi, v4hi); -v4hi __builtin_arm_wmulul (v4hi, v4hi); -v4hi __builtin_arm_wmulum (v4hi, v4hi); -long long __builtin_arm_wor (long long, long long); -v2si __builtin_arm_wpackdss (long long, long long); -v2si __builtin_arm_wpackdus (long long, long long); -v8qi __builtin_arm_wpackhss (v4hi, v4hi); -v8qi __builtin_arm_wpackhus (v4hi, v4hi); -v4hi __builtin_arm_wpackwss (v2si, v2si); -v4hi __builtin_arm_wpackwus (v2si, v2si); -long long __builtin_arm_wrord (long long, long long); -long long __builtin_arm_wrordi (long long, int); -v4hi __builtin_arm_wrorh (v4hi, long long); -v4hi __builtin_arm_wrorhi (v4hi, int); -v2si __builtin_arm_wrorw (v2si, long long); -v2si __builtin_arm_wrorwi (v2si, int); -v2si __builtin_arm_wsadb (v2si, v8qi, v8qi); -v2si __builtin_arm_wsadbz (v8qi, v8qi); -v2si __builtin_arm_wsadh (v2si, v4hi, v4hi); -v2si __builtin_arm_wsadhz (v4hi, v4hi); -v4hi __builtin_arm_wshufh (v4hi, int); -long long __builtin_arm_wslld (long long, long long); -long long __builtin_arm_wslldi (long long, int); -v4hi __builtin_arm_wsllh (v4hi, long long); -v4hi __builtin_arm_wsllhi (v4hi, int); -v2si __builtin_arm_wsllw (v2si, long long); -v2si __builtin_arm_wsllwi (v2si, int); -long long __builtin_arm_wsrad (long long, long long); -long long __builtin_arm_wsradi (long long, int); -v4hi __builtin_arm_wsrah (v4hi, long long); -v4hi __builtin_arm_wsrahi (v4hi, int); -v2si __builtin_arm_wsraw (v2si, long long); -v2si __builtin_arm_wsrawi (v2si, int); -long long __builtin_arm_wsrld (long long, long long); -long long __builtin_arm_wsrldi (long long, int); -v4hi __builtin_arm_wsrlh (v4hi, long long); -v4hi __builtin_arm_wsrlhi (v4hi, int); -v2si __builtin_arm_wsrlw (v2si, long long); -v2si __builtin_arm_wsrlwi (v2si, int); -v8qi __builtin_arm_wsubb (v8qi, v8qi); -v8qi __builtin_arm_wsubbss (v8qi, v8qi); -v8qi __builtin_arm_wsubbus (v8qi, v8qi); -v4hi __builtin_arm_wsubh (v4hi, v4hi); -v4hi __builtin_arm_wsubhss (v4hi, v4hi); -v4hi __builtin_arm_wsubhus (v4hi, v4hi); -v2si __builtin_arm_wsubw (v2si, v2si); -v2si __builtin_arm_wsubwss (v2si, v2si); -v2si __builtin_arm_wsubwus (v2si, v2si); -v4hi __builtin_arm_wunpckehsb (v8qi); -v2si __builtin_arm_wunpckehsh (v4hi); -long long __builtin_arm_wunpckehsw (v2si); -v4hi __builtin_arm_wunpckehub (v8qi); -v2si __builtin_arm_wunpckehuh (v4hi); -long long __builtin_arm_wunpckehuw (v2si); -v4hi __builtin_arm_wunpckelsb (v8qi); -v2si __builtin_arm_wunpckelsh (v4hi); -long long __builtin_arm_wunpckelsw (v2si); -v4hi __builtin_arm_wunpckelub (v8qi); -v2si __builtin_arm_wunpckeluh (v4hi); -long long __builtin_arm_wunpckeluw (v2si); -v8qi __builtin_arm_wunpckihb (v8qi, v8qi); -v4hi __builtin_arm_wunpckihh (v4hi, v4hi); -v2si __builtin_arm_wunpckihw (v2si, v2si); -v8qi __builtin_arm_wunpckilb (v8qi, v8qi); -v4hi __builtin_arm_wunpckilh (v4hi, v4hi); -v2si __builtin_arm_wunpckilw (v2si, v2si); -long long __builtin_arm_wxor (long long, long long); -long long __builtin_arm_wzero (); -@end smallexample - - @node ARM C Language Extensions (ACLE) @subsection ARM C Language Extensions (ACLE) diff --git a/gcc/doc/gm2.texi b/gcc/doc/gm2.texi index cb52e8c..8293da4 100644 --- a/gcc/doc/gm2.texi +++ b/gcc/doc/gm2.texi @@ -1495,7 +1495,7 @@ from @samp{bad} will cause an overflow to @samp{foo}. If we compile the code with the following options: @example -$ gm2 -g -fsoft-check-all -O2 -c assignvalue.mod +$ gm2 -g -fsoft-check-all -O2 -fm2-plugin -c assignvalue.mod assignvalue.mod:16:0:inevitable that this error will occur at run time, assignment will result in an overflow @end example diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f31d504..ee71801 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1268,7 +1268,7 @@ See RS/6000 and PowerPC Options. -mfence-tso -mno-fence-tso -mdiv -mno-div -misa-spec=@var{ISA-spec-string} --march=@var{ISA-string} +-march=@var{ISA-string|Profiles|Profiles_ISA-string} -mtune=@var{processor-string} -mpreferred-stack-boundary=@var{num} -msmall-data-limit=@var{N-bytes} @@ -23520,7 +23520,7 @@ These @samp{-m} options are defined for the ARM port: @opindex mabi @item -mabi=@var{name} Generate code for the specified ABI@. Permissible values are: @samp{apcs-gnu}, -@samp{atpcs}, @samp{aapcs}, @samp{aapcs-linux} and @samp{iwmmxt}. +@samp{atpcs}, @samp{aapcs} and @samp{aapcs-linux}. @opindex mapcs-frame @item -mapcs-frame @@ -30698,6 +30698,7 @@ Generate code for the specified PTX ISA target architecture. Valid architecture strings are @samp{sm_30}, @samp{sm_35}, @samp{sm_37}, @samp{sm_52}, @samp{sm_53}, +@samp{sm_61}, @samp{sm_70}, @samp{sm_75}, @samp{sm_80}, and @samp{sm_89}. The default depends on how the compiler has been configured, see @@ -30724,6 +30725,7 @@ Generate code for the specified PTX ISA version. Valid version strings are @samp{3.1}, @samp{4.1}, @samp{4.2}, +@samp{5.0}, @samp{6.0}, @samp{6.3}, @samp{7.0}, @samp{7.3}, and @samp{7.8}. The default PTX ISA version is the one that added support for the @@ -31115,11 +31117,16 @@ The default is @option{-misa-spec=20191213} unless GCC has been configured with @option{--with-isa-spec=} specifying a different default version. @opindex march -@item -march=@var{ISA-string} -Generate code for given RISC-V ISA (e.g.@: @samp{rv64im}). ISA strings must be -lower-case. Examples include @samp{rv64i}, @samp{rv32g}, @samp{rv32e}, and -@samp{rv32imaf}. Additionally, a special value @option{help} -(@option{-march=help}) is accepted to list all supported extensions. +@item -march=@var{ISA-string|Profiles|Profile_ISA-string} +Generate code for given RISC-V ISA or Profiles or a combination of them +(e.g.@: @samp{rv64im} @samp{rvi20u64} @samp{rvi20u64_zbb}). ISA strings and +Profiles must be lower-case. Examples include @samp{rv64i}, @samp{rv32g}, +@samp{rv32e}, @samp{rv32imaf}, @samp{rva22u64} and @samp{rva23u64}. +To combine Profiles and optional RISC-V ISA extention, the profile should start +at the beginning of the option, then use underline connect ISA-string (e.g.@: +@samp{rvi20u64_zca_zcb} @samp{rva23u64_zacas}). Additionally, a special value +@option{help} (@option{-march=help}) is accepted to list all supported +extensions. The syntax of the ISA string is defined as follows: @@ -31138,501 +31145,8 @@ syntax @samp{<major>p<minor>} or @samp{<major>}, (e.g.@: @samp{m2p1} or @end table Supported extension are listed below: -@multitable @columnfractions .10 .10 .80 -@headitem Extension Name @tab Supported Version @tab Description -@item i -@tab 2.0, 2.1 -@tab Base integer extension. - -@item e -@tab 2.0 -@tab Reduced base integer extension. - -@item g -@tab - -@tab General-purpose computing base extension, @samp{g} will expand to -@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and -@samp{zifencei}. - -@item m -@tab 2.0 -@tab Integer multiplication and division extension. - -@item a -@tab 2.0, 2.1 -@tab Atomic extension. - -@item f -@tab 2.0, 2.2 -@tab Single-precision floating-point extension. - -@item d -@tab 2.0, 2.2 -@tab Double-precision floating-point extension. - -@item c -@tab 2.0 -@tab Compressed extension. - -@item h -@tab 1.0 -@tab Hypervisor extension. - -@item v -@tab 1.0 -@tab Vector extension. - -@item zicsr -@tab 2.0 -@tab Control and status register access extension. - -@item zifencei -@tab 2.0 -@tab Instruction-fetch fence extension. - -@item zicond -@tab 1.0 -@tab Integer conditional operations extension. - -@item za64rs -@tab 1.0 -@tab Reservation set size of 64 bytes. - -@item za128rs -@tab 1.0 -@tab Reservation set size of 128 bytes. - -@item zawrs -@tab 1.0 -@tab Wait-on-reservation-set extension. - -@item zba -@tab 1.0 -@tab Address calculation extension. - -@item zbb -@tab 1.0 -@tab Basic bit manipulation extension. - -@item zbc -@tab 1.0 -@tab Carry-less multiplication extension. - -@item zbs -@tab 1.0 -@tab Single-bit operation extension. - -@item zfinx -@tab 1.0 -@tab Single-precision floating-point in integer registers extension. - -@item zdinx -@tab 1.0 -@tab Double-precision floating-point in integer registers extension. - -@item zhinx -@tab 1.0 -@tab Half-precision floating-point in integer registers extension. - -@item zhinxmin -@tab 1.0 -@tab Minimal half-precision floating-point in integer registers extension. - -@item zbkb -@tab 1.0 -@tab Cryptography bit-manipulation extension. - -@item zbkc -@tab 1.0 -@tab Cryptography carry-less multiply extension. - -@item zbkx -@tab 1.0 -@tab Cryptography crossbar permutation extension. - -@item zkne -@tab 1.0 -@tab AES Encryption extension. - -@item zknd -@tab 1.0 -@tab AES Decryption extension. - -@item zknh -@tab 1.0 -@tab Hash function extension. - -@item zkr -@tab 1.0 -@tab Entropy source extension. - -@item zksed -@tab 1.0 -@tab SM4 block cipher extension. - -@item zksh -@tab 1.0 -@tab SM3 hash function extension. - -@item zkt -@tab 1.0 -@tab Data independent execution latency extension. - -@item zk -@tab 1.0 -@tab Standard scalar cryptography extension. - -@item zkn -@tab 1.0 -@tab NIST algorithm suite extension. - -@item zks -@tab 1.0 -@tab ShangMi algorithm suite extension. -@item zihintntl -@tab 1.0 -@tab Non-temporal locality hints extension. - -@item zihintpause -@tab 1.0 -@tab Pause hint extension. - -@item zicboz -@tab 1.0 -@tab Cache-block zero extension. - -@item zicbom -@tab 1.0 -@tab Cache-block management extension. - -@item zicbop -@tab 1.0 -@tab Cache-block prefetch extension. - -@item zic64b -@tab 1.0 -@tab Cache block size isf 64 bytes. - -@item ziccamoa -@tab 1.0 -@tab Main memory supports all atomics in A. - -@item ziccif -@tab 1.0 -@tab Main memory supports instruction fetch with atomicity requirement. - -@item zicclsm -@tab 1.0 -@tab Main memory supports misaligned loads/stores. - -@item ziccrse -@tab 1.0 -@tab Main memory supports forward progress on LR/SC sequences. - -@item zicntr -@tab 2.0 -@tab Standard extension for base counters and timers. - -@item zihpm -@tab 2.0 -@tab Standard extension for hardware performance counters. - -@item ztso -@tab 1.0 -@tab Total store ordering extension. - -@item zve32x -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve32f -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve64x -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve64f -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve64d -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zvl32b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl64b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl128b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl256b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl512b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl1024b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl2048b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl4096b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvbb -@tab 1.0 -@tab Vector basic bit-manipulation extension. - -@item zvbc -@tab 1.0 -@tab Vector carryless multiplication extension. - -@item zvkb -@tab 1.0 -@tab Vector cryptography bit-manipulation extension. - -@item zvkg -@tab 1.0 -@tab Vector GCM/GMAC extension. - -@item zvkned -@tab 1.0 -@tab Vector AES block cipher extension. - -@item zvknha -@tab 1.0 -@tab Vector SHA-2 secure hash extension. - -@item zvknhb -@tab 1.0 -@tab Vector SHA-2 secure hash extension. - -@item zvksed -@tab 1.0 -@tab Vector SM4 Block Cipher extension. - -@item zvksh -@tab 1.0 -@tab Vector SM3 Secure Hash extension. - -@item zvkn -@tab 1.0 -@tab Vector NIST Algorithm Suite extension, @samp{zvkn} will expand to -@samp{zvkned}, @samp{zvknhb}, @samp{zvkb} and @samp{zvkt}. - -@item zvknc -@tab 1.0 -@tab Vector NIST Algorithm Suite with carryless multiply extension, @samp{zvknc} -will expand to @samp{zvkn} and @samp{zvbc}. - -@item zvkng -@tab 1.0 -@tab Vector NIST Algorithm Suite with GCM extension, @samp{zvkng} will expand -to @samp{zvkn} and @samp{zvkg}. - -@item zvks -@tab 1.0 -@tab Vector ShangMi algorithm suite extension, @samp{zvks} will expand -to @samp{zvksed}, @samp{zvksh}, @samp{zvkb} and @samp{zvkt}. - -@item zvksc -@tab 1.0 -@tab Vector ShangMi algorithm suite with carryless multiplication extension, -@samp{zvksc} will expand to @samp{zvks} and @samp{zvbc}. - -@item zvksg -@tab 1.0 -@tab Vector ShangMi algorithm suite with GCM extension, @samp{zvksg} will expand -to @samp{zvks} and @samp{zvkg}. - -@item zvkt -@tab 1.0 -@tab Vector data independent execution latency extension. - -@item zfh -@tab 1.0 -@tab Half-precision floating-point extension. - -@item zfhmin -@tab 1.0 -@tab Minimal half-precision floating-point extension. - -@item zvfh -@tab 1.0 -@tab Vector half-precision floating-point extension. - -@item zvfhmin -@tab 1.0 -@tab Vector minimal half-precision floating-point extension. - -@item zvfbfmin -@tab 1.0 -@tab Vector BF16 converts extension. - -@item zfa -@tab 1.0 -@tab Additional floating-point extension. - -@item zmmul -@tab 1.0 -@tab Integer multiplication extension. - -@item zca -@tab 1.0 -@tab Integer compressed instruction extension. - -@item zcf -@tab 1.0 -@tab Compressed single-precision floating point loads and stores extension. - -@item zcd -@tab 1.0 -@tab Compressed double-precision floating point loads and stores extension. - -@item zcb -@tab 1.0 -@tab Simple compressed instruction extension. - -@item zce -@tab 1.0 -@tab Compressed instruction extensions for embedded processors. - -@item zcmp -@tab 1.0 -@tab Compressed push pop extension. - -@item zcmt -@tab 1.0 -@tab Table jump instruction extension. - -@item smaia -@tab 1.0 -@tab Advanced interrupt architecture extension. - -@item smepmp -@tab 1.0 -@tab PMP Enhancements for memory access and execution prevention on Machine mode. - -@item smstateen -@tab 1.0 -@tab State enable extension. - -@item ssaia -@tab 1.0 -@tab Advanced interrupt architecture extension for supervisor-mode. - -@item sscofpmf -@tab 1.0 -@tab Count overflow & filtering extension. - -@item ssstateen -@tab 1.0 -@tab State-enable extension for supervisor-mode. - -@item sstc -@tab 1.0 -@tab Supervisor-mode timer interrupts extension. - -@item svade -@tab 1.0 -@tab Cause exception when hardware updating of A/D bits is disabled - -@item svadu -@tab 1.0 -@tab Hardware Updating of A/D Bits extension. - -@item svinval -@tab 1.0 -@tab Fine-grained address-translation cache invalidation extension. - -@item svnapot -@tab 1.0 -@tab NAPOT translation contiguity extension. - -@item svpbmt -@tab 1.0 -@tab Page-based memory types extension. - -@item xcvmac -@tab 1.0 -@tab Core-V multiply-accumulate extension. - -@item xcvalu -@tab 1.0 -@tab Core-V miscellaneous ALU extension. - -@item xcvelw -@tab 1.0 -@tab Core-V event load word extension. - -@item xtheadba -@tab 1.0 -@tab T-head address calculation extension. - -@item xtheadbb -@tab 1.0 -@tab T-head basic bit-manipulation extension. - -@item xtheadbs -@tab 1.0 -@tab T-head single-bit instructions extension. - -@item xtheadcmo -@tab 1.0 -@tab T-head cache management operations extension. - -@item xtheadcondmov -@tab 1.0 -@tab T-head conditional move extension. - -@item xtheadfmemidx -@tab 1.0 -@tab T-head indexed memory operations for floating-point registers extension. - -@item xtheadfmv -@tab 1.0 -@tab T-head double floating-point high-bit data transmission extension. - -@item xtheadint -@tab 1.0 -@tab T-head acceleration interruption extension. - -@item xtheadmac -@tab 1.0 -@tab T-head multiply-accumulate extension. - -@item xtheadmemidx -@tab 1.0 -@tab T-head indexed memory operation extension. - -@item xtheadmempair -@tab 1.0 -@tab T-head two-GPR memory operation extension. - -@item xtheadsync -@tab 1.0 -@tab T-head multi-core synchronization extension. - -@item xventanacondops -@tab 1.0 -@tab Ventana integer conditional operations extension. - -@end multitable +@include riscv-ext.texi When @option{-march=} is not specified, use the setting from @option{-mcpu}. diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index ae7a601..f6314af 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -2171,12 +2171,6 @@ VFP floating-point registers @code{d0}-@code{d31} and the appropriate subset @code{d0}-@code{d15} based on command line options. Used for 64 bit values only. Not valid for Thumb1. -@item y -The iWMMX co-processor registers. - -@item z -The iWMMX GR registers. - @item G The floating-point constant 0.0 @@ -2210,9 +2204,6 @@ A symbol in the text segment of the current file @item Uv A memory reference suitable for VFP load/store insns (reg+constant offset) -@item Uy -A memory reference suitable for iWMMXt load/store instructions. - @item Uq A memory reference suitable for the ARMv4 ldrsb instruction. @end table diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi new file mode 100644 index 0000000..bd3d29c --- /dev/null +++ b/gcc/doc/riscv-ext.texi @@ -0,0 +1,665 @@ +@c Copyright (C) 2025 Free Software Foundation, Inc. +@c This is part of the GCC manual. +@c For copying conditions, see the file gcc/doc/include/fdl.texi. + +@c This file is generated automatically using +@c gcc/config/riscv/gen-riscv-ext-texi.cc from: +@c gcc/config/riscv/riscv-ext.def +@c gcc/config/riscv/riscv-opts.h + +@c Please *DO NOT* edit manually. + +@multitable @columnfractions .10 .10 .80 +@headitem Extension Name @tab Supported Version @tab Description + +@item g +@tab - +@tab General-purpose computing base extension, @samp{g} will expand to +@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and +@samp{zifencei}. + +@item e +@tab 2.0 +@tab Reduced base integer extension + +@item i +@tab 2.0 2.1 +@tab Base integer extension + +@item m +@tab 2.0 +@tab Integer multiplication and division extension + +@item a +@tab 2.0 2.1 +@tab Atomic extension + +@item f +@tab 2.0 2.2 +@tab Single-precision floating-point extension + +@item d +@tab 2.0 2.2 +@tab Double-precision floating-point extension + +@item c +@tab 2.0 +@tab Compressed extension + +@item b +@tab 1.0 +@tab b extension + +@item v +@tab 1.0 +@tab Vector extension + +@item h +@tab 1.0 +@tab Hypervisor extension + +@item zic64b +@tab 1.0 +@tab Cache block size isf 64 bytes + +@item zicbom +@tab 1.0 +@tab Cache-block management extension + +@item zicbop +@tab 1.0 +@tab Cache-block prefetch extension + +@item zicboz +@tab 1.0 +@tab Cache-block zero extension + +@item ziccamoa +@tab 1.0 +@tab Main memory supports all atomics in A + +@item ziccif +@tab 1.0 +@tab Main memory supports instruction fetch with atomicity requirement + +@item zicclsm +@tab 1.0 +@tab Main memory supports misaligned loads/stores + +@item ziccrse +@tab 1.0 +@tab Main memory supports forward progress on LR/SC sequences + +@item zicfilp +@tab 1.0 +@tab zicfilp extension + +@item zicfiss +@tab 1.0 +@tab zicfiss extension + +@item zicntr +@tab 2.0 +@tab Standard extension for base counters and timers + +@item zicond +@tab 1.0 +@tab Integer conditional operations extension + +@item zicsr +@tab 2.0 +@tab Control and status register access extension + +@item zifencei +@tab 2.0 +@tab Instruction-fetch fence extension + +@item zihintntl +@tab 1.0 +@tab Non-temporal locality hints extension + +@item zihintpause +@tab 2.0 +@tab Pause hint extension + +@item zihpm +@tab 2.0 +@tab Standard extension for hardware performance counters + +@item zimop +@tab 1.0 +@tab zimop extension + +@item zilsd +@tab 1.0 +@tab Load/Store pair instructions extension + +@item zmmul +@tab 1.0 +@tab Integer multiplication extension + +@item za128rs +@tab 1.0 +@tab Reservation set size of 128 bytes + +@item za64rs +@tab 1.0 +@tab Reservation set size of 64 bytes + +@item zaamo +@tab 1.0 +@tab zaamo extension + +@item zabha +@tab 1.0 +@tab zabha extension + +@item zacas +@tab 1.0 +@tab zacas extension + +@item zalrsc +@tab 1.0 +@tab zalrsc extension + +@item zawrs +@tab 1.0 +@tab Wait-on-reservation-set extension + +@item zama16b +@tab 1.0 +@tab Zama16b extension, Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic. + +@item zfa +@tab 1.0 +@tab Additional floating-point extension + +@item zfbfmin +@tab 1.0 +@tab zfbfmin extension + +@item zfh +@tab 1.0 +@tab Half-precision floating-point extension + +@item zfhmin +@tab 1.0 +@tab Minimal half-precision floating-point extension + +@item zfinx +@tab 1.0 +@tab Single-precision floating-point in integer registers extension + +@item zdinx +@tab 1.0 +@tab Double-precision floating-point in integer registers extension + +@item zca +@tab 1.0 +@tab Integer compressed instruction extension + +@item zcb +@tab 1.0 +@tab Simple compressed instruction extension + +@item zcd +@tab 1.0 +@tab Compressed double-precision floating point loads and stores extension + +@item zce +@tab 1.0 +@tab Compressed instruction extensions for embedded processors + +@item zcf +@tab 1.0 +@tab Compressed single-precision floating point loads and stores extension + +@item zcmop +@tab 1.0 +@tab zcmop extension + +@item zcmp +@tab 1.0 +@tab Compressed push pop extension + +@item zcmt +@tab 1.0 +@tab Table jump instruction extension + +@item zclsd +@tab 1.0 +@tab Compressed load/store pair instructions extension + +@item zba +@tab 1.0 +@tab Address calculation extension + +@item zbb +@tab 1.0 +@tab Basic bit manipulation extension + +@item zbc +@tab 1.0 +@tab Carry-less multiplication extension + +@item zbkb +@tab 1.0 +@tab Cryptography bit-manipulation extension + +@item zbkc +@tab 1.0 +@tab Cryptography carry-less multiply extension + +@item zbkx +@tab 1.0 +@tab Cryptography crossbar permutation extension + +@item zbs +@tab 1.0 +@tab Single-bit operation extension + +@item zk +@tab 1.0 +@tab Standard scalar cryptography extension + +@item zkn +@tab 1.0 +@tab NIST algorithm suite extension + +@item zknd +@tab 1.0 +@tab AES Decryption extension + +@item zkne +@tab 1.0 +@tab AES Encryption extension + +@item zknh +@tab 1.0 +@tab Hash function extension + +@item zkr +@tab 1.0 +@tab Entropy source extension + +@item zks +@tab 1.0 +@tab ShangMi algorithm suite extension + +@item zksed +@tab 1.0 +@tab SM4 block cipher extension + +@item zksh +@tab 1.0 +@tab SM3 hash function extension + +@item zkt +@tab 1.0 +@tab Data independent execution latency extension + +@item ztso +@tab 1.0 +@tab Total store ordering extension + +@item zvbb +@tab 1.0 +@tab Vector basic bit-manipulation extension + +@item zvbc +@tab 1.0 +@tab Vector carryless multiplication extension + +@item zve32f +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zve32x +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zve64d +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zve64f +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zve64x +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zvfbfmin +@tab 1.0 +@tab Vector BF16 converts extension + +@item zvfbfwma +@tab 1.0 +@tab zvfbfwma extension + +@item zvfh +@tab 1.0 +@tab Vector half-precision floating-point extension + +@item zvfhmin +@tab 1.0 +@tab Vector minimal half-precision floating-point extension + +@item zvkb +@tab 1.0 +@tab Vector cryptography bit-manipulation extension + +@item zvkg +@tab 1.0 +@tab Vector GCM/GMAC extension + +@item zvkn +@tab 1.0 +@tab Vector NIST Algorithm Suite extension, @samp{zvkn} will expand to + +@item zvknc +@tab 1.0 +@tab Vector NIST Algorithm Suite with carryless multiply extension, @samp{zvknc} + +@item zvkned +@tab 1.0 +@tab Vector AES block cipher extension + +@item zvkng +@tab 1.0 +@tab Vector NIST Algorithm Suite with GCM extension, @samp{zvkng} will expand + +@item zvknha +@tab 1.0 +@tab Vector SHA-2 secure hash extension + +@item zvknhb +@tab 1.0 +@tab Vector SHA-2 secure hash extension + +@item zvks +@tab 1.0 +@tab Vector ShangMi algorithm suite extension, @samp{zvks} will expand + +@item zvksc +@tab 1.0 +@tab Vector ShangMi algorithm suite with carryless multiplication extension, + +@item zvksed +@tab 1.0 +@tab Vector SM4 Block Cipher extension + +@item zvksg +@tab 1.0 +@tab Vector ShangMi algorithm suite with GCM extension, @samp{zvksg} will expand + +@item zvksh +@tab 1.0 +@tab Vector SM3 Secure Hash extension + +@item zvkt +@tab 1.0 +@tab Vector data independent execution latency extension + +@item zvl1024b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl128b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl16384b +@tab 1.0 +@tab zvl16384b extension + +@item zvl2048b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl256b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl32768b +@tab 1.0 +@tab zvl32768b extension + +@item zvl32b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl4096b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl512b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl64b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl65536b +@tab 1.0 +@tab zvl65536b extension + +@item zvl8192b +@tab 1.0 +@tab zvl8192b extension + +@item zhinx +@tab 1.0 +@tab Half-precision floating-point in integer registers extension + +@item zhinxmin +@tab 1.0 +@tab Minimal half-precision floating-point in integer registers extension + +@item sdtrig +@tab 1.0 +@tab sdtrig extension + +@item sha +@tab 1.0 +@tab The augmented hypervisor extension + +@item shcounterenw +@tab 1.0 +@tab Support writeable enables for any supported counter + +@item shgatpa +@tab 1.0 +@tab SvNNx4 mode supported for all modes supported by satp + +@item shtvala +@tab 1.0 +@tab The htval register provides all needed values + +@item shvstvala +@tab 1.0 +@tab The vstval register provides all needed values + +@item shvstvecd +@tab 1.0 +@tab The vstvec register supports Direct mode + +@item shvsatpa +@tab 1.0 +@tab The vsatp register supports all modes supported by satp + +@item smaia +@tab 1.0 +@tab Advanced interrupt architecture extension + +@item smepmp +@tab 1.0 +@tab PMP Enhancements for memory access and execution prevention on Machine mode + +@item smmpm +@tab 1.0 +@tab smmpm extension + +@item smnpm +@tab 1.0 +@tab smnpm extension + +@item smstateen +@tab 1.0 +@tab State enable extension + +@item ssaia +@tab 1.0 +@tab Advanced interrupt architecture extension for supervisor-mode + +@item sscofpmf +@tab 1.0 +@tab Count overflow & filtering extension + +@item ssnpm +@tab 1.0 +@tab ssnpm extension + +@item sspm +@tab 1.0 +@tab sspm extension + +@item ssstateen +@tab 1.0 +@tab State-enable extension for supervisor-mode + +@item sstc +@tab 1.0 +@tab Supervisor-mode timer interrupts extension + +@item ssstrict +@tab 1.0 +@tab ssstrict extension + +@item supm +@tab 1.0 +@tab supm extension + +@item svinval +@tab 1.0 +@tab Fine-grained address-translation cache invalidation extension + +@item svnapot +@tab 1.0 +@tab NAPOT translation contiguity extension + +@item svpbmt +@tab 1.0 +@tab Page-based memory types extension + +@item svvptc +@tab 1.0 +@tab svvptc extension + +@item svadu +@tab 1.0 +@tab Hardware Updating of A/D Bits extension + +@item svade +@tab 1.0 +@tab Cause exception when hardware updating of A/D bits is disabled + +@item xcvalu +@tab 1.0 +@tab Core-V miscellaneous ALU extension + +@item xcvbi +@tab 1.0 +@tab xcvbi extension + +@item xcvelw +@tab 1.0 +@tab Core-V event load word extension + +@item xcvmac +@tab 1.0 +@tab Core-V multiply-accumulate extension + +@item xcvsimd +@tab 1.0 +@tab xcvsimd extension + +@item xsfcease +@tab 1.0 +@tab xsfcease extension + +@item xsfvcp +@tab 1.0 +@tab xsfvcp extension + +@item xsfvfnrclipxfqf +@tab 1.0 +@tab xsfvfnrclipxfqf extension + +@item xsfvqmaccdod +@tab 1.0 +@tab xsfvqmaccdod extension + +@item xsfvqmaccqoq +@tab 1.0 +@tab xsfvqmaccqoq extension + +@item xtheadba +@tab 1.0 +@tab T-head address calculation extension + +@item xtheadbb +@tab 1.0 +@tab T-head basic bit-manipulation extension + +@item xtheadbs +@tab 1.0 +@tab T-head single-bit instructions extension + +@item xtheadcmo +@tab 1.0 +@tab T-head cache management operations extension + +@item xtheadcondmov +@tab 1.0 +@tab T-head conditional move extension + +@item xtheadfmemidx +@tab 1.0 +@tab T-head indexed memory operations for floating-point registers extension + +@item xtheadfmv +@tab 1.0 +@tab T-head double floating-point high-bit data transmission extension + +@item xtheadint +@tab 1.0 +@tab T-head acceleration interruption extension + +@item xtheadmac +@tab 1.0 +@tab T-head multiply-accumulate extension + +@item xtheadmemidx +@tab 1.0 +@tab T-head indexed memory operation extension + +@item xtheadmempair +@tab 1.0 +@tab T-head two-GPR memory operation extension + +@item xtheadsync +@tab 1.0 +@tab T-head multi-core synchronization extension + +@item xtheadvector +@tab 1.0 +@tab xtheadvector extension + +@item xventanacondops +@tab 1.0 +@tab Ventana integer conditional operations extension + +@end multitable diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 65eeecc..1c718c4 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2042,10 +2042,6 @@ ARM target uses emulated floating point operations. ARM target supports @code{-mfpu=vfp -mfloat-abi=hard}. Some multilibs may be incompatible with these options. -@item arm_iwmmxt_ok -ARM target supports @code{-mcpu=iwmmxt}. -Some multilibs may be incompatible with this option. - @item arm_neon ARM target supports generating NEON instructions. |