diff options
Diffstat (limited to 'gcc/doc/riscv-ext.texi')
| -rw-r--r-- | gcc/doc/riscv-ext.texi | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi index bd3d29c..c3ed1bf 100644 --- a/gcc/doc/riscv-ext.texi +++ b/gcc/doc/riscv-ext.texi @@ -474,6 +474,10 @@ @tab 1.0 @tab SvNNx4 mode supported for all modes supported by satp +@item shlcofideleg +@tab 1.0 +@tab Delegating LCOFI interrupts to VS-mode + @item shtvala @tab 1.0 @tab The htval register provides all needed values @@ -494,6 +498,14 @@ @tab 1.0 @tab Advanced interrupt architecture extension +@item smcntrpmf +@tab 1.0 +@tab Cycle and instret privilege mode filtering + +@item smcsrind +@tab 1.0 +@tab Machine-Level Indirect CSR Access + @item smepmp @tab 1.0 @tab PMP Enhancements for memory access and execution prevention on Machine mode @@ -506,18 +518,38 @@ @tab 1.0 @tab smnpm extension +@item smrnmi +@tab 1.0 +@tab Resumable non-maskable interrupts + @item smstateen @tab 1.0 @tab State enable extension +@item smdbltrp +@tab 1.0 +@tab Double Trap Extensions + @item ssaia @tab 1.0 @tab Advanced interrupt architecture extension for supervisor-mode +@item ssccptr +@tab 1.0 +@tab Main memory supports page table reads + @item sscofpmf @tab 1.0 @tab Count overflow & filtering extension +@item sscounterenw +@tab 1.0 +@tab Support writeable enables for any supported counter + +@item sscsrind +@tab 1.0 +@tab Supervisor-Level Indirect CSR Access + @item ssnpm @tab 1.0 @tab ssnpm extension @@ -534,10 +566,26 @@ @tab 1.0 @tab Supervisor-mode timer interrupts extension +@item sstvala +@tab 1.0 +@tab Stval provides all needed values + +@item sstvecd +@tab 1.0 +@tab Stvec supports Direct mode + @item ssstrict @tab 1.0 @tab ssstrict extension +@item ssdbltrp +@tab 1.0 +@tab Double Trap Extensions + +@item ssu64xl +@tab 1.0 +@tab UXLEN=64 must be supported + @item supm @tab 1.0 @tab supm extension @@ -566,6 +614,10 @@ @tab 1.0 @tab Cause exception when hardware updating of A/D bits is disabled +@item svbare +@tab 1.0 +@tab Satp mode bare is supported + @item xcvalu @tab 1.0 @tab Core-V miscellaneous ALU extension |