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diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d6c1faf..780d5c8 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -458,6 +458,14 @@ Objective-C and Objective-C++ Dialects}. @c Try and put the significant identifier (CPU or system) first, @c so users have a clue at guessing where the ones they want will be. +@emph{Adapteva Epiphany Options} +@gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol +-mbranch-cost=@var{num} -mcmove -mnops=@var{num} -msoft-cmpsf @gol +-msplit-lohi -mpost-inc -mpost-modify -mstack-offset=@var{num} @gol +-mround-nearest -mlong-calls -mshort-calls -msmall16 @gol +-mfp-mode=@var{mode} -mvect-double -max-vect-align=@var{num} @gol +-msplit-vecmove-early -m1reg-@var{reg}} + @emph{ARM Options} @gccoptlist{-mapcs-frame -mno-apcs-frame @gol -mabi=@var{name} @gol @@ -10226,6 +10234,7 @@ platform. @c in Machine Dependent Options @menu +* Adapteva Epiphany Options:: * ARM Options:: * AVR Options:: * Blackfin Options:: @@ -10274,6 +10283,161 @@ platform. * zSeries Options:: @end menu +@node Adapteva Epiphany Options +@subsection Adapteva Epiphany Options + +These @samp{-m} options are defined for Adapteva Epiphany: + +@table @gcctabopt +@item -mhalf-reg-file +@opindex mhalf-reg-file +Don't allocate any register in the range @code{r32}@dots{}@code{r63}. +That allows code to run on hardware variants that lack these registers. + +@item -mprefer-short-insn-regs +@opindex mprefer-short-insn-regs +Preferrentially allocate registers that allow short instruction generation. +This can result in increasesd instruction count, so if this reduces or +increases code size might vary from case to case. + +@item -mbranch-cost=@var{num} +@opindex mbranch-cost +Set the cost of branches to roughly @var{num} ``simple'' instructions. +This cost is only a heuristic and is not guaranteed to produce +consistent results across releases. + +@item -mcmove +@opindex mcmove +Enable the generation of conditional moves. + +@item -mnops=@var{num} +@opindex mnops +Emit @var{num} nops before every other generated instruction. + +@item -mno-soft-cmpsf +@opindex mno-soft-cmpsf +For single-precision floating point comparisons, emit an fsub instruction +and test the flags. This is faster than a software comparison, but can +get incorrect results in the presence of NaNs, or when two different small +numbers are compared such that their difference is calculated as zero. +The default is @option{-msoft-cmpsf}, which uses slower, but IEEE-compliant, +software comparisons. + +@item -mstack-offset=@var{num} +@opindex mstack-offset +Set the offset between the top of the stack and the stack pointer. +E.g., a value of 8 means that the eight bytes in the range sp+0@dots{}sp+7 +can be used by leaf functions without stack allocation. +Values other than @samp{8} or @samp{16} are untested and unlikely to work. +Note also that this option changes the ABI, compiling a program with a +different stack offset than the libraries have been compiled with +will generally not work. +This option can be useful if you want to evaluate if a different stack +offset would give you better code, but to actually use a different stack +offset to build working programs, it is recommended to configure the +toolchain with the appropriate @samp{--with-stack-offset=@var{num}} option. + +@item -mno-round-nearest +@opindex mno-round-nearest +Make the scheduler assume that the rounding mode has been set to +truncating. The default is @option{-mround-nearest}. + +@item -mlong-calls +@opindex mlong-calls +If not otherwise specified by an attribute, assume all calls might be beyond +the offset range of the b / bl instructions, and therefore load the +function address into a register before performing a (otherwise direct) call. +This is the default. + +@item -mshort-calls +@opindex short-calls +If not otherwise specified by an attribute, assume all direct calls are +in the range of the b / bl instructions, so use these instructions +for direct calls. The default is @option{-mlong-calls}. + +@item -msmall16 +@opindex msmall16 +Assume addresses can be loaded as 16 bit unsigned values. This does not +apply to function addresses for which @option{-mlong-calls} semantics +are in effect. + +@item -mfp-mode=@var{mode} +@opindex mfp-mode +Set the prevailing mode of the floating point unit. +This determines the floating point mode that is provided and expected +at function call and return time. Making this mode match the mode you +predominantly need at function start can make your programs smaller and +faster by avoiding unnecessary mode switches. + +@var{mode} can be set to one the following values: + +@table @samp +@item caller +Any mode at function entry is valid, and retained or restored when +the function returns, and when it calls other functions. +This mode is useful for compiling libraries or other compilation units +you might want to incorporate into different programs with different +prevailing FPU modes, and the convenience of being able to use a single +object file outweighs the size and speed overhead for any extra +mode switching that might be needed, compared with what would be needed +with a more specific choice of prevailing FPU mode. + +@item truncate +This is the mode used for floating point calculations with +truncating (i.e.@: round towards zero) rounding mode. That includes +conversion from floating point to integer. + +@item round-nearest +This is the mode used for floating point calculations with +round-to-nearest-or-even rounding mode. + +@item int +This is the mode used to perform integer calculations in the FPU, e.g.@: +integer multiply, or integer multiply-and-accumulate. +@end table + +The default is @option{-mfp-mode=caller} + +@item -mnosplit-lohi +@opindex mnosplit-lohi +@item -mno-postinc +@opindex mno-postinc +@item -mno-postmodify +@opindex mno-postmodify +Code generation tweaks that disable, respectively, splitting of 32 +bit loads, generation of post-increment addresses, and generation of +post-modify addresses. The defaults are @option{msplit-lohi}, +@option{-mpost-inc}, and @option{-mpost-modify}. + +@item -mnovect-double +@opindex mno-vect-double +Change the preferred SIMD mode to SImode. The default is +@option{-mvect-double}, which uses DImode as preferred SIMD mode. + +@item -max-vect-align=@var{num} +@opindex max-vect-align +The maximum alignment for SIMD vector mode types. +@var{num} may be 4 or 8. The default is 8. +Note that this is an ABI change, even though many library function +interfaces will be unaffected, if they don't use SIMD vector modes +in places where they affect size and/or alignment of relevant types. + +@item -msplit-vecmove-early +@opindex msplit-vecmove-early +Split vector moves into single word moves before reload. In theory this +could give better register allocation, but so far the reverse seems to be +generally the case. + +@item -m1reg-@var{reg} +@opindex m1reg- +Specify a register to hold the constant @minus{}1, which makes loading small negative +constants and certain bitmasks faster. +Allowable values for reg are r43 and r63, which specify to use that register +as a fixed register, and none, which means that no register is used for this +purpose. The default is @option{-m1reg-none}. + +@end table + @node ARM Options @subsection ARM Options @cindex ARM options |