diff options
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 1081 |
1 files changed, 446 insertions, 635 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 67155ee..7640e7d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -266,7 +266,7 @@ in the following sections. -Wnoexcept -Wnoexcept-type -Wnon-virtual-dtor -Wpessimizing-move -Wno-placement-new -Wplacement-new=@var{n} -Wrange-loop-construct -Wredundant-move -Wredundant-tags --Wreorder -Wregister +-Wreorder -Wregister -Wno-sfinae-incomplete -Wstrict-null-sentinel -Wno-subobject-linkage -Wtemplates -Wno-non-template-friend -Wold-style-cast -Woverloaded-virtual -Wno-pmf-conversions -Wself-move -Wsign-promo @@ -312,7 +312,7 @@ Objective-C and Objective-C++ Dialects}. -fdiagnostics-show-location=@r{[}once@r{|}every-line@r{]} -fdiagnostics-color=@r{[}auto@r{|}never@r{|}always@r{]} -fdiagnostics-urls=@r{[}auto@r{|}never@r{|}always@r{]} --fdiagnostics-format=@r{[}text@r{|}sarif-stderr@r{|}sarif-file@r{|}json@r{|}json-stderr@r{|}json-file@r{]} +-fdiagnostics-format=@r{[}text@r{|}sarif-stderr@r{|}sarif-file@r{]} -fdiagnostics-add-output=@var{DIAGNOSTICS-OUTPUT-SPEC} -fdiagnostics-set-output=@var{DIAGNOSTICS-OUTPUT-SPEC} -fno-diagnostics-json-formatting @@ -340,7 +340,7 @@ Objective-C and Objective-C++ Dialects}. -w -Wextra -Wall -Wabi=@var{n} -Waddress -Wno-address-of-packed-member -Waggregate-return -Walloc-size -Walloc-size-larger-than=@var{byte-size} -Walloc-zero --Walloca -Walloca-larger-than=@var{byte-size} +-Walloca -Walloca-larger-than=@var{byte-size} -Wauto-profile -Wno-aggressive-loop-optimizations -Warith-conversion -Warray-bounds -Warray-bounds=@var{n} -Warray-compare @@ -513,6 +513,7 @@ Objective-C and Objective-C++ Dialects}. -Wno-analyzer-tainted-divisor -Wno-analyzer-tainted-offset -Wno-analyzer-tainted-size +-Wno-analyzer-throw-of-unexpected-type -Wanalyzer-symbol-too-complex -Wanalyzer-too-complex -Wno-analyzer-undefined-behavior-ptrdiff @@ -572,13 +573,13 @@ Objective-C and Objective-C++ Dialects}. -fmin-function-alignment=[@var{n}] -fno-allocation-dce -fallow-store-data-races -fassociative-math -fauto-profile -fauto-profile[=@var{path}] --fauto-inc-dec -fbranch-probabilities +-fauto-profile-inlining -fauto-inc-dec -fbranch-probabilities -fcaller-saves -fcombine-stack-adjustments -fconserve-stack -ffold-mem-offsets -fcompare-elim -fcprop-registers -fcrossjumping -fcse-follow-jumps -fcse-skip-blocks -fcx-fortran-rules --fcx-limited-range +-fcx-limited-range -fcx-method -fdata-sections -fdce -fdelayed-branch -fdelete-null-pointer-checks -fdevirtualize -fdevirtualize-speculatively -fdevirtualize-at-ltrans -fdse @@ -593,7 +594,7 @@ Objective-C and Objective-C++ Dialects}. -finline-functions -finline-functions-called-once -finline-limit=@var{n} -finline-small-functions -fipa-modref -fipa-cp -fipa-cp-clone -fipa-bit-cp -fipa-vrp -fipa-pta -fipa-profile -fipa-pure-const --fipa-reference -fipa-reference-addressable +-fipa-reference -fipa-reference-addressable -fipa-reorder-for-locality -fipa-stack-alignment -fipa-icf -fira-algorithm=@var{algorithm} -flate-combine-instructions -flifetime-dse -flive-patching=@var{level} -fira-region=@var{region} -fira-hoist-pressure @@ -1267,7 +1268,7 @@ See RS/6000 and PowerPC Options. -mfence-tso -mno-fence-tso -mdiv -mno-div -misa-spec=@var{ISA-spec-string} --march=@var{ISA-string} +-march=@var{ISA-string|Profiles|Profiles_ISA-string|CPU/processor string} -mtune=@var{processor-string} -mpreferred-stack-boundary=@var{num} -msmall-data-limit=@var{N-bytes} @@ -1495,8 +1496,8 @@ See RS/6000 and PowerPC Options. -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni -mamx-fp8 -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf --musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512 -mavx10.2 --mamx-avx512 -mamx-tf32 -mamx-transpose -mmovrs -mamx-movrs +-musermsr -mavx10.1 -mavx10.2 -mamx-avx512 -mamx-tf32 -mamx-transpose -mmovrs +-mamx-movrs -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops -minline-stringops-dynamically -mstringop-strategy=@var{alg} -mkl -mwidekl @@ -2199,6 +2200,7 @@ those that have already been displayed. If @option{--help} is also specified anywhere on the command line then this takes precedence over any @option{--help=} option. +@opindex Q If the @option{-Q} option appears on the command line before the @option{--help=} option, then the descriptive text displayed by @option{--help=} is changed. Instead of describing the displayed @@ -2438,8 +2440,8 @@ ISO C99. This standard is substantially completely supported, modulo bugs and floating-point issues (mainly but not entirely relating to optional C99 features from Annexes F and G). See -@w{@uref{https://gcc.gnu.org/c99status.html}} for more information. The -names @samp{c9x} and @samp{iso9899:199x} are deprecated. +@w{@uref{https://gcc.gnu.org/projects/c-status.html}} for more information. +The names @samp{c9x} and @samp{iso9899:199x} are deprecated. @item c11 @itemx c1x @@ -3004,12 +3006,18 @@ in C++14 and up. Version 18, which first appeared in G++ 13, fixes manglings of lambdas that have additional context. -Version 19, which first appeared in G++ 14, fixes manglings of structured -bindings to include ABI tags. +Version 19, which first appeared in G++ 14, fixes manglings of +structured bindings to include ABI tags, handling of cv-qualified +[[no_unique_address]] members, and adds mangling of C++20 constraints +on function templates. Version 20, which first appeared in G++ 15, fixes manglings of lambdas in static data member initializers. +Version 21, which first appeared in G++ 16, fixes unnecessary captures +in noexcept lambdas (c++/119764) and layout of a base class +with all explicitly defaulted constructors (c++/120012). + See also @option{-Wabi}. @opindex fabi-compat-version @@ -3289,6 +3297,50 @@ Enable support for the C++ coroutines extension (experimental). Permit the C++ front end to note all candidates during overload resolution failure, including when a deleted function is selected. +@item -fdump-lang- +@itemx -fdump-lang-@var{switch} +@itemx -fdump-lang-@var{switch}-@var{options} +@itemx -fdump-lang-@var{switch}-@var{options}=@var{filename} +Control the dumping of C++-specific information. The @var{options} +and @var{filename} portions behave as described in the +@option{-fdump-tree} option. The following @var{switch} values are +accepted: + +@table @samp +@item all +Enable all of the below. + +@opindex fdump-lang-class +@item class +Dump class hierarchy information. Virtual table information is emitted +unless '@option{slim}' is specified. + +@opindex fdump-lang-module +@item module +Dump module information. Options @option{lineno} (locations), +@option{graph} (reachability), @option{blocks} (clusters), +@option{uid} (serialization), @option{alias} (mergeable), +@option{asmname} (Elrond), @option{eh} (mapper) & @option{vops} +(macros) may provide additional information. + +@opindex fdump-lang-raw +@item raw +Dump the raw internal tree data. + +@opindex fdump-lang-tinst +@item tinst +Dump the sequence of template instantiations, indented to show the +depth of recursion. The @option{lineno} option adds the source +location where the instantiation was triggered, and the +@option{details} option also dumps pre-instantiation substitutions +such as those performed during template argument deduction. + +Lines in the .tinst dump start with @samp{I} for an instantiation, +@samp{S} for another substitution, and @samp{R[IS]} for the reopened +context of a deferred instantiation. + +@end table + @opindex fno-elide-constructors @opindex felide-constructors @item -fno-elide-constructors @@ -3340,7 +3392,8 @@ aliases, the default is @option{-fno-extern-tls-init}. @item -ffold-simple-inlines @itemx -fno-fold-simple-inlines Permit the C++ frontend to fold calls to @code{std::move}, @code{std::forward}, -@code{std::addressof} and @code{std::as_const}. In contrast to inlining, this +@code{std::addressof}, @code{std::to_underlying} +and @code{std::as_const}. In contrast to inlining, this means no debug information will be generated for such calls. Since these functions are rarely interesting to debug, this flag is enabled by default unless @option{-fno-inline} is active. @@ -4395,6 +4448,20 @@ to filter out those warnings. Disable the warning about the case when an exception handler is shadowed by another handler, which can point out a wrong ordering of exception handlers. +@opindex Wsfinae-incomplete +@opindex Wno-sfinae-incomplete +Warn about a class that is found to be incomplete, or a function with +auto return type that has not yet been deduced, in a context where +that causes substitution failure rather than an error, and then the +class or function is defined later in the translation unit. This is +problematic because template instantiations or concept checks could +have different results if they first occur either before or after the +definition. + +This warning is enabled by default. @option{-Wsfinae-incomplete=2} +adds a warning at the point of substitution failure, to make it easier +to track down problems flagged by the default mode. + @opindex Wstrict-null-sentinel @opindex Wno-strict-null-sentinel @item -Wstrict-null-sentinel @r{(C++ and Objective-C++ only)} @@ -5891,8 +5958,7 @@ column numbers, such as @command{dejagnu}. @opindex fdiagnostics-column-unit @item -fdiagnostics-column-unit=@var{UNIT} Select the units for the column number. This affects traditional diagnostics -(in the absence of @option{-fno-show-column}), as well as JSON format -diagnostics if requested. +(in the absence of @option{-fno-show-column}). The default @var{UNIT}, @samp{display}, considers the number of display columns occupied by each character. This may be larger than the number @@ -5968,8 +6034,7 @@ is set to @samp{C}, in which case the default is @samp{ascii}. @opindex fdiagnostics-format @item -fdiagnostics-format=@var{FORMAT} Select a different format for printing diagnostics. -@var{FORMAT} is @samp{text}, @samp{sarif-stderr}, @samp{sarif-file}, -@samp{json}, @samp{json-stderr}, or @samp{json-file}. +@var{FORMAT} is @samp{text}, @samp{sarif-stderr} or @samp{sarif-file}. Using this option replaces any additional ``output sinks'' added by @option{-fdiagnostics-add-output=}, or that set by @@ -5981,14 +6046,6 @@ The @samp{sarif-stderr} and @samp{sarif-file} formats both emit diagnostics in SARIF Version 2.1.0 format, either to stderr, or to a file named @file{@var{source}.sarif}, respectively. -The various @samp{json}, @samp{json-stderr}, and @samp{json-file} values -are deprecated and refer to a legacy JSON-based output format. -The @samp{json} format is a synonym for @samp{json-stderr}. -The @samp{json-stderr} and @samp{json-file} formats are identical, apart from -where the JSON is emitted to. With @samp{json-stderr}, the JSON is emitted -to stderr, whereas with @samp{json-file} it is written to -@file{@var{source}.gcc.json}. - @opindex fdiagnostics-add-output @item -fdiagnostics-add-output=@var{DIAGNOSTICS-OUTPUT-SPEC} Add an additional ``output sink'' for emitting diagnostics. @@ -6051,6 +6108,11 @@ Specify the filename to write the SARIF output to, potentially with a leading absolute or relative path. If not specified, it defaults to @file{@var{source}.sarif}. +@item serialization=@r{[}json@r{]} +Specify the serialization format to use when writing out the SARIF. +Currently this can only be @code{json}, but is present as an +extension point for experimenting with other serializations. + @item version=@r{[}2.1@r{|}2.2-prerelease@r{]} Specify the version of SARIF to use for the output. If not specified, defaults to 2.1. @code{2.2-prerelease} uses an unofficial draft of the @@ -6059,6 +6121,70 @@ in this release. @end table +There is also this key intended for use by GCC developers, rather than +end-users, and subject to change or removal without notice: + +@table @gcctabopt + +@item xml-state=@r{[}yes@r{|}no@r{]} +This is a debugging feature and defaults to @code{no}. +If @code{xml-state=yes}, then attempt to capture detailed state information +from @option{-fanalyzer} in the generated SARIF. + +@end table + +@item experimental-html +Emit diagnostics to a file in HTML format. This scheme is experimental, +and may go away in future GCC releases. The keys and details of the output +are also subject to change. + +Supported keys are: + +@table @gcctabopt + +@item css=@r{[}yes@r{|}no@r{]} +Add an embedded <style> to the generated HTML. Defaults to yes. + +@item file=@var{FILENAME} +Specify the filename to write the HTML output to, potentially with a +leading absolute or relative path. If not specified, it defaults to +@file{@var{source}.html}. + +@item javascript=@r{[}yes@r{|}no@r{]} +Add an embedded <script> to the generated HTML providing a barebones UI +for viewing results. Defaults to yes. + +@end table + +There are also these keys intended for use by GCC developers, rather than +end-users, and subject to change or removal without notice: + +@table @gcctabopt + +@item show-state-diagrams=@r{[}yes@r{|}no@r{]} +This is a debugging feature and defaults to @code{no}. +If @code{show-state-diagrams=yes}, then attempt to use @command{dot} to +generate SVG diagrams in the generated HTML, visualizing the state at each +event in a diagnostic path. +These are visible by pressing ``j'' and ``k'' to single-step forward and +backward through events. Enabling this option will slow down +HTML generation. + +@item show-state-diagrams-dot-src=@r{[}yes@r{|}no@r{]} +This is a debugging feature and defaults to @code{no}. +If @code{show-state-diagrams-dot-src=yes} +then if @code{show-state-diagrams=yes}, +the generated state diagrams will also show the .dot source input to +GraphViz used for the diagram. + +@item show-state-diagrams-xml=@r{[}yes@r{|}no@r{]} +This is a debugging feature and defaults to @code{no}. +If @code{show-state-diagrams-xml=yes} +then if @code{show-state-diagrams=yes}, the generated state diagrams will +also show an XML representation of the state. + +@end table + @end table For example, @@ -6078,7 +6204,7 @@ In EBNF: @var{diagnostics-output-specifier} = @var{diagnostics-output-name} | @var{diagnostics-output-name}, ":", @var{key-value-pairs}; -@var{diagnostics-output-name} = "text" | "sarif"; +@var{diagnostics-output-name} = "text" | "sarif" | "experimental-html"; @var{key-value-pairs} = @var{key-value-pair} | @var{key-value-pair} "," @var{key-value-pairs}; @@ -6102,11 +6228,8 @@ replaces all existing output sinks, such as from @option{-fdiagnostics-format=}, @opindex fdiagnostics-json-formatting @item -fno-diagnostics-json-formatting By default, when JSON is emitted for diagnostics (via -@option{-fdiagnostics-format=sarif-stderr}, -@option{-fdiagnostics-format=sarif-file}, -@option{-fdiagnostics-format=json}, -@option{-fdiagnostics-format=json-stderr}, -@option{-fdiagnostics-format=json-file}), +@option{-fdiagnostics-format=sarif-stderr} or +@option{-fdiagnostics-format=sarif-file}), GCC will add newlines and indentation to visually emphasize the hierarchical structure of the JSON. @@ -6979,14 +7102,14 @@ which is enabled by optimizations in most targets. The precision of the warnings depends on the optimization options used. @opindex Wno-musttail-local-addr -@opindex -Wmusttail-local-addr +@opindex Wmusttail-local-addr @item -Wno-musttail-local-addr Do not warn about passing a pointer (or in C++, a reference) to a local variable or label to argument of a @code{musttail} call. Those variables go out of scope before the tail call instruction. @opindex Wmaybe-musttail-local-addr -@opindex -Wno-maybe-musttail-local-addr +@opindex Wno-maybe-musttail-local-addr @item -Wmaybe-musttail-local-addr Warn when address of a local variable can escape to a @code{musttail} call, unless it goes out of scope already before the @code{musttail} @@ -8592,6 +8715,11 @@ larger. @item -Walloca This option warns on all uses of @code{alloca} in the source. +@opindex Wno-auto-profile +@opindex Wauto-profile +@item -Wauto-profile +Output warnings about auto-profile inconsistencies. + @opindex Walloca-larger-than= @opindex Wno-alloca-larger-than @item -Walloca-larger-than=@var{byte-size} @@ -11007,6 +11135,7 @@ Enabling this option effectively enables the following warnings: -Wanalyzer-tainted-divisor -Wanalyzer-tainted-offset -Wanalyzer-tainted-size +-Wanalyzer-throw-of-unexpected-type -Wanalyzer-undefined-behavior-ptrdiff -Wanalyzer-undefined-behavior-strtok -Wanalyzer-unsafe-call-within-signal-handler @@ -11658,6 +11787,17 @@ attacker could inject an out-of-bounds access. See @uref{https://cwe.mitre.org/data/definitions/129.html, CWE-129: Improper Validation of Array Index}. +@opindex Wanalyzer-throw-of-unexpected-type +@opindex Wno-analyzer-throw-of-unexpected-type +@item -Wno-analyzer-throw-of-unexpected-type +This warning requires @option{-fanalyzer} which enables it; +use @option{-Wno-analyzer-throw-of-unexpected-type} to disable it. +Dynamic exception specifications are only available in C++14 and earlier. + +This diagnostic warns for paths through the code in which a an exception +is thrown from a function with a dynamic exception specification where +the exception does not comply with the specification. + @opindex Wanalyzer-undefined-behavior-ptrdiff @opindex Wno-analyzer-undefined-behavior-ptrdiff @item -Wno-analyzer-undefined-behavior-ptrdiff @@ -12746,6 +12886,7 @@ complexity than at @option{-O}. -fipa-pure-const -fipa-reference -fipa-reference-addressable +-fivopts -fmerge-constants -fmove-loop-invariants -fmove-loop-stores @@ -12854,6 +12995,13 @@ by @option{-O2} and also turns on the following optimization flags: Reduce compilation time and make debugging produce the expected results. This is the default. +At @option{-O0}, GCC completely disables most optimization passes; +they are not run even if you explicitly enable them on the command +line, or are listed by @option{-Q --help=optimizers} as being enabled by +default. Many optimizations performed by GCC depend on code analysis +or canonicalization passes that are enabled by @option{-O}, and it would +not be useful to run individual optimization passes in isolation. + @opindex Os @item -Os Optimize for size. @option{-Os} enables all @option{-O2} optimizations @@ -12879,17 +13027,19 @@ It turns off @option{-fsemantic-interposition}. @opindex Og @item -Og -Optimize debugging experience. @option{-Og} should be the optimization +Optimize while keeping in mind debugging experience. +@option{-Og} should be the optimization level of choice for the standard edit-compile-debug cycle, offering -a reasonable level of optimization while maintaining fast compilation -and a good debugging experience. It is a better choice than @option{-O0} -for producing debuggable code because some compiler passes -that collect debug information are disabled at @option{-O0}. +a reasonable blend of optimization, fast compilation and debugging experience +especially for code with a high abstraction penalty. In contrast to +@option{-O0}, this enables @option{-fvar-tracking-assignments} and +@option{-fvar-tracking} which handle debug information in the prologue +and epilogue of functions better than @option{-O0}. -Like @option{-O0}, @option{-Og} completely disables a number of +Like @option{-O0}, @option{-Og} completely skips a number of optimization passes so that individual options controlling them have no effect. Otherwise @option{-Og} enables all @option{-O1} -optimization flags except for those that may interfere with debugging: +optimization flags except for those known to greatly interfere with debugging: @gccoptlist{-fbranch-count-reg -fdelayed-branch -fdse -fif-conversion -fif-conversion2 @@ -13871,6 +14021,21 @@ Enabled by default at @option{-O1} and higher. Discover read-only, write-only and non-addressable static variables. Enabled by default at @option{-O1} and higher. +@opindex fipa-reorder-for-locality +@item -fipa-reorder-for-locality +Group call chains close together in the binary layout to improve code +locality and minimize jump distances between frequently called functions. +Unlike @option{-freorder-functions} this pass considers the call +chains between functions and groups them together, rather than grouping all +hot/normal/cold/never-executed functions into separate sections. +Unlike @option{-fprofile-reorder-functions} it aims to improve code locality +throughout the runtime of the program rather than focusing on program startup. +This option is incompatible with an explicit +@option{-flto-partition=} option since it enforces a custom partitioning +scheme. +If using this option it is recommended to also use profile feedback, but this +option is not enabled by default otherwise. + @opindex fipa-stack-alignment @item -fipa-stack-alignment Reduce stack alignment on call sites if possible. @@ -14291,6 +14456,7 @@ Enabled by default at @option{-O1} and higher. @item -fivopts Perform induction variable optimizations (strength reduction, induction variable merging and induction variable elimination) on trees. +Enabled by default at @option{-O1} and higher. @opindex ftree-parallelize-loops @item -ftree-parallelize-loops=n @@ -14606,11 +14772,13 @@ Enabled for x86 at levels @option{-O2}, @option{-O3}, @option{-Os}. @opindex freorder-functions @item -freorder-functions Reorder functions in the object file in order to -improve code locality. This is implemented by using special -subsections @code{.text.hot} for most frequently executed functions and -@code{.text.unlikely} for unlikely executed functions. Reordering is done by -the linker so object file format must support named sections and linker must -place them in a reasonable way. +improve code locality. Unlike @option{-fipa-reorder-for-locality} this option +prioritises grouping all functions within a category +(hot/normal/cold/never-executed) together. +This is implemented by using special subsections @code{.text.hot} for most +frequently executed functions and @code{.text.unlikely} for unlikely executed +functions. Reordering is done by the linker so object file format must support +named sections and linker must place them in a reasonable way. This option isn't effective unless you either provide profile feedback (see @option{-fprofile-arcs} for details) or manually annotate functions with @@ -14622,12 +14790,14 @@ Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}. @item -fstrict-aliasing Allow the compiler to assume the strictest aliasing rules applicable to the language being compiled. For C (and C++), this activates -optimizations based on the type of expressions. In particular, an -object of one type is assumed never to reside at the same address as an -object of a different type, unless the types are almost the same. For -example, an @code{unsigned int} can alias an @code{int}, but not a -@code{void*} or a @code{double}. A character type may alias any other -type. +optimizations based on the type of expressions. In particular, accessing +an object of one type via an expression of a different type is not allowed, +unless the types are @dfn{compatible types}, differ only in signedness or +qualifiers, or the expression has a character type. Accessing scalar +objects via a corresponding vector type is also allowed. + +For example, an @code{unsigned int} can alias an @code{int}, but not a +@code{void*} or a @code{double}. A character type may alias any other type. @anchor{Type-punning}Pay special attention to code like this: @smallexample @@ -15324,6 +15494,12 @@ E.g. create_gcov --binary=your_program.unstripped --profile=perf.data \ --gcov=profile.afdo @end smallexample + +@opindex fauto-profile-inlining +@item -fauto-profile-inlining +When auto-profile is available inline all relevant functions which was +inlined in the tran run before reading the profile feedback. This improves +context sensitivity of the profile. Enabled by default. @end table The following options control compiler behavior regarding floating-point @@ -15574,8 +15750,7 @@ When enabled, this option states that a range reduction step is not needed when performing complex division. Also, there is no checking whether the result of a complex multiplication or division is @code{NaN + I*NaN}, with an attempt to rescue the situation in that case. The -default is @option{-fno-cx-limited-range}, but is enabled by -@option{-ffast-math}. +option is enabled by @option{-ffast-math}. This option controls the default setting of the ISO C99 @code{CX_LIMITED_RANGE} pragma. Nevertheless, the option applies to @@ -15588,7 +15763,14 @@ reduction is done as part of complex division, but there is no checking whether the result of a complex multiplication or division is @code{NaN + I*NaN}, with an attempt to rescue the situation in that case. -The default is @option{-fno-cx-fortran-rules}. +@opindex fcx-method +@item -fcx-method=@var{method} +Complex multiplication and division follow the stated @var{method}. The +@var{method} argument should be one of @samp{limited-range}, @samp{fortran} +or @samp{stdc}. + +The default is to honor language specific constraints which means +@samp{fortran} for Fortran and @samp{stdc} otherwise. @end table @@ -15635,7 +15817,8 @@ Enabled by @option{-fprofile-generate}, @option{-fprofile-use}, and @item -fprofile-reorder-functions Function reordering based on profile instrumentation collects first time of execution of a function and orders these functions -in ascending order. +in ascending order, aiming to optimize program startup through more +efficient loading of text segments. Enabled with @option{-fprofile-use}. @@ -16867,11 +17050,6 @@ Maximum depth of recursive cloning for self-recursive function. Recursive cloning only when the probability of call being executed exceeds the parameter. -@item ipa-cp-profile-count-base -When using @option{-fprofile-use} option, IPA-CP will consider the measured -execution count of a call graph edge at this percentage position in their -histogram as the basis for its heuristics calculation. - @item ipa-cp-recursive-freq-factor The number of times interprocedural copy propagation expects recursive functions to call themselves. @@ -16933,6 +17111,19 @@ Size of max partition for WHOPR (in estimated instructions). to provide an upper bound for individual size of partition. Meant to be used only with balanced partitioning. +@item lto-partition-locality-frequency-cutoff +The denominator n of fraction 1/n of the execution frequency of callee to be +cloned for a particular caller. Special value of 0 dictates to always clone +without a cut-off. + +@item lto-partition-locality-size-cutoff +Size cut-off for callee including inlined calls to be cloned for a particular +caller. + +@item lto-max-locality-partition +Maximal size of a locality partition for LTO (in estimated instructions). +Value of 0 results in default value being used. + @item lto-max-streaming-parallelism Maximal number of parallel processes used for LTO streaming. @@ -17187,8 +17378,9 @@ this parameter. The default value of this parameter is 50. @item vect-induction-float Enable loop vectorization of floating point inductions. -@item vect-force-slp -Force the use of SLP when vectorizing, fail if not possible. +@item vect-scalar-cost-multiplier +Apply the given multiplier % to scalar loop costing during vectorization. +Increasing the cost multiplier will make vector loops more profitable. @item vrp-block-limit Maximum number of basic blocks before VRP switches to a lower memory algorithm. @@ -17267,6 +17459,9 @@ predicate chain. @item uninit-max-num-chains Maximum number of predicates ored in the normalized predicate chain. +@item uninit-max-prune-work +Maximum amount of work done to prune paths where the variable is always initialized. + @item sched-autopref-queue-depth Hardware autoprefetcher scheduler model control flag. Number of lookahead cycles the model looks into; at ' @@ -17430,20 +17625,9 @@ The precision of division is proportional to this param when division approximation is enabled. The default value is 2. @item aarch64-autovec-preference -Force an ISA selection strategy for auto-vectorization. -@table @samp -@item default -Use the default heuristics. -@item asimd-only -Use only Advanced SIMD for auto-vectorization. -@item sve-only -Use only SVE for auto-vectorization. -@item prefer-asimd -Use both Advanced SIMD and SVE. Prefer Advanced SIMD when the costs are -deemed equal. -@item prefer-sve -Use both Advanced SIMD and SVE. Prefer SVE when the costs are deemed equal. -@end table +An old alias for @option{-mautovec-preference}. If both +@option{-mautovec-preference} and @option{--param=aarch64-autovec-preference} +are passed, the @option{--param} value will be used. @item aarch64-ldp-policy Fine-grained policy for load pairs. @@ -20707,6 +20891,93 @@ By default, the dump will contain messages about successful optimizations (equivalent to @option{-optimized}) together with low-level details about the analysis. +@opindex fdump-ipa-clones +@item -fdump-ipa-clones + +Create a dump file containing information about creation of call graph +node clones and removals of call graph nodes during inter-procedural +optimizations and transformations. Its main intended use is that tools +that create live-patches can determine the set of functions that need to +be live-patched to completely replace a particular function (see +@option{-flive-patching}). The file name is generated by appending +suffix @code{ipa-clones} to the source file name, and the file is +created in the same directory as the output file. Each entry in the +file is on a separate line containing semicolon separated fields. + +In the case of call graph clone creation, the individual fields are: + +@enumerate +@item +String @code{Callgraph clone}. + +@item +Name of the function being cloned as it is presented to the assembler. + +@item +A number that uniquely represents the function being cloned in the call +graph. Note that the number is unique only within a compilation unit or +within whole-program analysis but is likely to be different in the two +phases. + +@item +The file name of the source file where the function is defined. + +@item +The line on which the function definition is located. + +@item +The column where the function definition is located. + +@item +Name of the new function clone as it is presented to the assembler. + +@item +A number that uniquely represents the new function clone in the call +graph. Note that the number is unique only within a compilation unit or +within whole-program analysis but is likely to be different in the two +phases. + +@item +The file name of the source file where the source code location of the +new clone points to. + +@item +The line to which the source code location of the new clone points to. + +@item +The column to which the source code location of the new clone points to. + +@item +A string that determines the reason for cloning. + +@end enumerate + +In the case of call graph clone removal, the individual fields are: + +@enumerate +@item +String @code{Callgraph removal}. + +@item +Name of the function being removed as it would be presented to the assembler. + +@item +A number that uniquely represents the function being cloned in the call +graph. Note that the number is unique only within a compilation unit or +within whole-program analysis but is likely to be different in the two +phases. + +@item +The file name of the source file where the function is defined. + +@item +The line on which the function definition is located. + +@item +The column where the function definition is located. + +@end enumerate + @opindex fdump-lang @item -fdump-lang Dump language-specific information. The file name is made by appending @@ -20720,30 +20991,10 @@ Dump language-specific information. The file name is made by appending @itemx -fdump-lang-@var{switch}-@var{options}=@var{filename} Control the dumping of language-specific information. The @var{options} and @var{filename} portions behave as described in the -@option{-fdump-tree} option. The following @var{switch} values are -accepted: - -@table @samp -@item all - -Enable all language-specific dumps. - -@item class -Dump class hierarchy information. Virtual table information is emitted -unless '@option{slim}' is specified. This option is applicable to C++ only. - -@item module -Dump module information. Options @option{lineno} (locations), -@option{graph} (reachability), @option{blocks} (clusters), -@option{uid} (serialization), @option{alias} (mergeable), -@option{asmname} (Elrond), @option{eh} (mapper) & @option{vops} -(macros) may provide additional information. This option is -applicable to C++ only. - -@item raw -Dump the raw internal tree data. This option is applicable to C++ only. - -@end table +@option{-fdump-tree} option. @option{-fdump-tree-all} enables all +language-specific dumps; other options vary with the language. For +instance, see @xref{C++ Dialect Options} for the @option{-fdump-lang} +flags supported by the C++ front-end. @opindex fdump-passes @item -fdump-passes @@ -21284,8 +21535,13 @@ Toggle @option{-fvar-tracking-assignments}, in the same way that @opindex Q @item -Q -Makes the compiler print out each function name as it is compiled, and -print some statistics about each pass when it finishes. +When used on the command line prior to @option{--help=}, @option{-Q} +acts as a modifier to the help output. @xref{Overall Options}, +for details about @option{--help=}. + +Otherwise, this option makes the compiler print out each function name +as it is compiled, and print some statistics about each pass when it +finishes. @opindex ftime-report @item -ftime-report @@ -21805,6 +22061,36 @@ used directly. The same applies when using @option{-mcpu=} when the selected cpu supports the @samp{lse} feature. This option is on by default. +@item -mmax-vectorization +@itemx -mno-max-vectorization +Enable or disable an override to vectorizer cost model making vectorization +always appear profitable. This option can be combined with +@option{-mautovec-preference} allowing precise control over which ISA will be +used for auto-vectorization. Unlike @option{-fno-vect-cost-model} or +@option{-fvect-cost-model=unlimited} this option does not turn off cost +comparison between different vector modes. + +@item -mautovec-preference=@var{name} +Force an ISA selection strategy for auto-vectorization. The possible +values of @var{name} are: +@table @samp +@item default +Use the default heuristics. +@item asimd-only +Use only Advanced SIMD for auto-vectorization. +@item sve-only +Use only SVE for auto-vectorization. +@item prefer-asimd +Use both Advanced SIMD and SVE. Prefer Advanced SIMD when the costs are +deemed equal. +@item prefer-sve +Use both Advanced SIMD and SVE. Prefer SVE when the costs are deemed equal. +@end table + +For best performance it is highly recommended to use @option{-mcpu} or +@option{-mtune} instead. This parameter should only be used for code +exploration. + @opindex march @item -march=@var{name} Specify the name of the target architecture and, optionally, one or @@ -21891,7 +22177,7 @@ performance of the code. Permissible values for this option are: The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53}, @samp{cortex-a75.cortex-a55}, @samp{cortex-a76.cortex-a55}, -@samp{apple-m1}, @samp{apple-m2}, @samp{apple-m3} specify that GCC +@samp{apple-m1}, @samp{apple-m2}, @samp{apple-m3}, @samp{gb10} specify that GCC should tune for a big.LITTLE system. The value @samp{neoverse-512tvb} specifies that GCC should tune @@ -22180,6 +22466,9 @@ Enable the FlagM2 flag conversion instructions. Enable the Pointer Authentication Extension. @item cssc Enable the Common Short Sequence Compression instructions. +@item cmpbr +Enable the shorter compare and branch instructions, @code{cbb}, @code{cbh} and +@code{cb}. @item sme Enable the Scalable Matrix Extension. This is only supported when SVE2 is also enabled. @@ -22462,10 +22751,20 @@ Compile for CDNA2 Instinct MI200 series devices (gfx90a). @item gfx90c Compile for GCN5 Vega 7 devices (gfx90c). +@item gfx942 +Compile for CDNA3 Instinct MI300 series devices (gfx942). (Experimental) + +@item gfx950 +Compile for the CDNA3 gfx950 devices. (Experimental) + @item gfx9-generic Compile generic code for Vega devices, executable on the following subset of GFX9 devices: gfx900, gfx902, gfx904, gfx906, gfx909 and gfx90c. (Experimental) +@item gfx9-4-generic +Compile generic code for CDNA3 devices, executable on the following subset of +GFX9 devices: gfx942 and gfx950. (Experimental) + @item gfx1030 Compile for RDNA2 gfx1030 devices (GFX10 series). @@ -23345,7 +23644,7 @@ These @samp{-m} options are defined for the ARM port: @opindex mabi @item -mabi=@var{name} Generate code for the specified ABI@. Permissible values are: @samp{apcs-gnu}, -@samp{atpcs}, @samp{aapcs}, @samp{aapcs-linux} and @samp{iwmmxt}. +@samp{atpcs}, @samp{aapcs} and @samp{aapcs-linux}. @opindex mapcs-frame @item -mapcs-frame @@ -30523,6 +30822,7 @@ Generate code for the specified PTX ISA target architecture. Valid architecture strings are @samp{sm_30}, @samp{sm_35}, @samp{sm_37}, @samp{sm_52}, @samp{sm_53}, +@samp{sm_61}, @samp{sm_70}, @samp{sm_75}, @samp{sm_80}, and @samp{sm_89}. The default depends on how the compiler has been configured, see @@ -30549,6 +30849,7 @@ Generate code for the specified PTX ISA version. Valid version strings are @samp{3.1}, @samp{4.1}, @samp{4.2}, +@samp{5.0}, @samp{6.0}, @samp{6.3}, @samp{7.0}, @samp{7.3}, and @samp{7.8}. The default PTX ISA version is the one that added support for the @@ -30702,12 +31003,13 @@ to store the immediate to a register first. @opindex mcmodel= @opindex mcmodel=small @item -mcmodel=small -Generate OpenRISC code for the small model: The GOT is limited to 64k. This is -the default model. +Generate OpenRISC code for the small model: The GOT is limited to 64k and +function call jumps are limited to 64M offsets. This is the default model. @opindex mcmodel=large @item -mcmodel=large -Generate OpenRISC code for the large model: The GOT may grow up to 4G in size. +Generate OpenRISC code for the large model: The GOT may grow up to 4G in size +and function call jumps can target the full 4G address space. @end table @@ -30940,11 +31242,16 @@ The default is @option{-misa-spec=20191213} unless GCC has been configured with @option{--with-isa-spec=} specifying a different default version. @opindex march -@item -march=@var{ISA-string} -Generate code for given RISC-V ISA (e.g.@: @samp{rv64im}). ISA strings must be -lower-case. Examples include @samp{rv64i}, @samp{rv32g}, @samp{rv32e}, and -@samp{rv32imaf}. Additionally, a special value @option{help} -(@option{-march=help}) is accepted to list all supported extensions. +@item -march=@var{ISA-string|Profiles|Profile_ISA-string} +Generate code for given RISC-V ISA or Profiles or a combination of them +(e.g.@: @samp{rv64im} @samp{rvi20u64} @samp{rvi20u64_zbb}). ISA strings and +Profiles must be lower-case. Examples include @samp{rv64i}, @samp{rv32g}, +@samp{rv32e}, @samp{rv32imaf}, @samp{rva22u64} and @samp{rva23u64}. +To combine Profiles and optional RISC-V ISA extention, the profile should start +at the beginning of the option, then use underline connect ISA-string (e.g.@: +@samp{rvi20u64_zca_zcb} @samp{rva23u64_zacas}). Additionally, a special value +@option{help} (@option{-march=help}) is accepted to list all supported +extensions. The syntax of the ISA string is defined as follows: @@ -30963,493 +31270,8 @@ syntax @samp{<major>p<minor>} or @samp{<major>}, (e.g.@: @samp{m2p1} or @end table Supported extension are listed below: -@multitable @columnfractions .10 .10 .80 -@headitem Extension Name @tab Supported Version @tab Description -@item i -@tab 2.0, 2.1 -@tab Base integer extension. - -@item e -@tab 2.0 -@tab Reduced base integer extension. - -@item g -@tab - -@tab General-purpose computing base extension, @samp{g} will expand to -@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and -@samp{zifencei}. - -@item m -@tab 2.0 -@tab Integer multiplication and division extension. - -@item a -@tab 2.0, 2.1 -@tab Atomic extension. - -@item f -@tab 2.0, 2.2 -@tab Single-precision floating-point extension. - -@item d -@tab 2.0, 2.2 -@tab Double-precision floating-point extension. - -@item c -@tab 2.0 -@tab Compressed extension. - -@item h -@tab 1.0 -@tab Hypervisor extension. - -@item v -@tab 1.0 -@tab Vector extension. - -@item zicsr -@tab 2.0 -@tab Control and status register access extension. - -@item zifencei -@tab 2.0 -@tab Instruction-fetch fence extension. - -@item zicond -@tab 1.0 -@tab Integer conditional operations extension. - -@item za64rs -@tab 1.0 -@tab Reservation set size of 64 bytes. - -@item za128rs -@tab 1.0 -@tab Reservation set size of 128 bytes. - -@item zawrs -@tab 1.0 -@tab Wait-on-reservation-set extension. - -@item zba -@tab 1.0 -@tab Address calculation extension. - -@item zbb -@tab 1.0 -@tab Basic bit manipulation extension. - -@item zbc -@tab 1.0 -@tab Carry-less multiplication extension. - -@item zbs -@tab 1.0 -@tab Single-bit operation extension. - -@item zfinx -@tab 1.0 -@tab Single-precision floating-point in integer registers extension. -@item zdinx -@tab 1.0 -@tab Double-precision floating-point in integer registers extension. - -@item zhinx -@tab 1.0 -@tab Half-precision floating-point in integer registers extension. - -@item zhinxmin -@tab 1.0 -@tab Minimal half-precision floating-point in integer registers extension. - -@item zbkb -@tab 1.0 -@tab Cryptography bit-manipulation extension. - -@item zbkc -@tab 1.0 -@tab Cryptography carry-less multiply extension. - -@item zbkx -@tab 1.0 -@tab Cryptography crossbar permutation extension. - -@item zkne -@tab 1.0 -@tab AES Encryption extension. - -@item zknd -@tab 1.0 -@tab AES Decryption extension. - -@item zknh -@tab 1.0 -@tab Hash function extension. - -@item zkr -@tab 1.0 -@tab Entropy source extension. - -@item zksed -@tab 1.0 -@tab SM4 block cipher extension. - -@item zksh -@tab 1.0 -@tab SM3 hash function extension. - -@item zkt -@tab 1.0 -@tab Data independent execution latency extension. - -@item zk -@tab 1.0 -@tab Standard scalar cryptography extension. - -@item zkn -@tab 1.0 -@tab NIST algorithm suite extension. - -@item zks -@tab 1.0 -@tab ShangMi algorithm suite extension. - -@item zihintntl -@tab 1.0 -@tab Non-temporal locality hints extension. - -@item zihintpause -@tab 1.0 -@tab Pause hint extension. - -@item zicboz -@tab 1.0 -@tab Cache-block zero extension. - -@item zicbom -@tab 1.0 -@tab Cache-block management extension. - -@item zicbop -@tab 1.0 -@tab Cache-block prefetch extension. - -@item zic64b -@tab 1.0 -@tab Cache block size isf 64 bytes. - -@item ziccamoa -@tab 1.0 -@tab Main memory supports all atomics in A. - -@item ziccif -@tab 1.0 -@tab Main memory supports instruction fetch with atomicity requirement. - -@item zicclsm -@tab 1.0 -@tab Main memory supports misaligned loads/stores. - -@item ziccrse -@tab 1.0 -@tab Main memory supports forward progress on LR/SC sequences. - -@item zicntr -@tab 2.0 -@tab Standard extension for base counters and timers. - -@item zihpm -@tab 2.0 -@tab Standard extension for hardware performance counters. - -@item ztso -@tab 1.0 -@tab Total store ordering extension. - -@item zve32x -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve32f -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve64x -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve64f -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve64d -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zvl32b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl64b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl128b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl256b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl512b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl1024b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl2048b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl4096b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvbb -@tab 1.0 -@tab Vector basic bit-manipulation extension. - -@item zvbc -@tab 1.0 -@tab Vector carryless multiplication extension. - -@item zvkb -@tab 1.0 -@tab Vector cryptography bit-manipulation extension. - -@item zvkg -@tab 1.0 -@tab Vector GCM/GMAC extension. - -@item zvkned -@tab 1.0 -@tab Vector AES block cipher extension. - -@item zvknha -@tab 1.0 -@tab Vector SHA-2 secure hash extension. - -@item zvknhb -@tab 1.0 -@tab Vector SHA-2 secure hash extension. - -@item zvksed -@tab 1.0 -@tab Vector SM4 Block Cipher extension. - -@item zvksh -@tab 1.0 -@tab Vector SM3 Secure Hash extension. - -@item zvkn -@tab 1.0 -@tab Vector NIST Algorithm Suite extension, @samp{zvkn} will expand to -@samp{zvkned}, @samp{zvknhb}, @samp{zvkb} and @samp{zvkt}. - -@item zvknc -@tab 1.0 -@tab Vector NIST Algorithm Suite with carryless multiply extension, @samp{zvknc} -will expand to @samp{zvkn} and @samp{zvbc}. - -@item zvkng -@tab 1.0 -@tab Vector NIST Algorithm Suite with GCM extension, @samp{zvkng} will expand -to @samp{zvkn} and @samp{zvkg}. - -@item zvks -@tab 1.0 -@tab Vector ShangMi algorithm suite extension, @samp{zvks} will expand -to @samp{zvksed}, @samp{zvksh}, @samp{zvkb} and @samp{zvkt}. - -@item zvksc -@tab 1.0 -@tab Vector ShangMi algorithm suite with carryless multiplication extension, -@samp{zvksc} will expand to @samp{zvks} and @samp{zvbc}. - -@item zvksg -@tab 1.0 -@tab Vector ShangMi algorithm suite with GCM extension, @samp{zvksg} will expand -to @samp{zvks} and @samp{zvkg}. - -@item zvkt -@tab 1.0 -@tab Vector data independent execution latency extension. - -@item zfh -@tab 1.0 -@tab Half-precision floating-point extension. - -@item zfhmin -@tab 1.0 -@tab Minimal half-precision floating-point extension. - -@item zvfh -@tab 1.0 -@tab Vector half-precision floating-point extension. - -@item zvfhmin -@tab 1.0 -@tab Vector minimal half-precision floating-point extension. - -@item zvfbfmin -@tab 1.0 -@tab Vector BF16 converts extension. - -@item zfa -@tab 1.0 -@tab Additional floating-point extension. - -@item zmmul -@tab 1.0 -@tab Integer multiplication extension. - -@item zca -@tab 1.0 -@tab Integer compressed instruction extension. - -@item zcf -@tab 1.0 -@tab Compressed single-precision floating point loads and stores extension. - -@item zcd -@tab 1.0 -@tab Compressed double-precision floating point loads and stores extension. - -@item zcb -@tab 1.0 -@tab Simple compressed instruction extension. - -@item zce -@tab 1.0 -@tab Compressed instruction extensions for embedded processors. - -@item zcmp -@tab 1.0 -@tab Compressed push pop extension. - -@item zcmt -@tab 1.0 -@tab Table jump instruction extension. - -@item smaia -@tab 1.0 -@tab Advanced interrupt architecture extension. - -@item smepmp -@tab 1.0 -@tab PMP Enhancements for memory access and execution prevention on Machine mode. - -@item smstateen -@tab 1.0 -@tab State enable extension. - -@item ssaia -@tab 1.0 -@tab Advanced interrupt architecture extension for supervisor-mode. - -@item sscofpmf -@tab 1.0 -@tab Count overflow & filtering extension. - -@item ssstateen -@tab 1.0 -@tab State-enable extension for supervisor-mode. - -@item sstc -@tab 1.0 -@tab Supervisor-mode timer interrupts extension. - -@item svinval -@tab 1.0 -@tab Fine-grained address-translation cache invalidation extension. - -@item svnapot -@tab 1.0 -@tab NAPOT translation contiguity extension. - -@item svpbmt -@tab 1.0 -@tab Page-based memory types extension. - -@item xcvmac -@tab 1.0 -@tab Core-V multiply-accumulate extension. - -@item xcvalu -@tab 1.0 -@tab Core-V miscellaneous ALU extension. - -@item xcvelw -@tab 1.0 -@tab Core-V event load word extension. - -@item xtheadba -@tab 1.0 -@tab T-head address calculation extension. - -@item xtheadbb -@tab 1.0 -@tab T-head basic bit-manipulation extension. - -@item xtheadbs -@tab 1.0 -@tab T-head single-bit instructions extension. - -@item xtheadcmo -@tab 1.0 -@tab T-head cache management operations extension. - -@item xtheadcondmov -@tab 1.0 -@tab T-head conditional move extension. - -@item xtheadfmemidx -@tab 1.0 -@tab T-head indexed memory operations for floating-point registers extension. - -@item xtheadfmv -@tab 1.0 -@tab T-head double floating-point high-bit data transmission extension. - -@item xtheadint -@tab 1.0 -@tab T-head acceleration interruption extension. - -@item xtheadmac -@tab 1.0 -@tab T-head multiply-accumulate extension. - -@item xtheadmemidx -@tab 1.0 -@tab T-head indexed memory operation extension. - -@item xtheadmempair -@tab 1.0 -@tab T-head two-GPR memory operation extension. - -@item xtheadsync -@tab 1.0 -@tab T-head multi-core synchronization extension. - -@item xventanacondops -@tab 1.0 -@tab Ventana integer conditional operations extension. - -@end multitable +@include riscv-ext.texi When @option{-march=} is not specified, use the setting from @option{-mcpu}. @@ -31465,12 +31287,13 @@ extension set if they weren't added explicitly. @item -mcpu=@var{processor-string} Use architecture of and optimize the output for the given processor, specified by particular CPU name. -Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21}, -@samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, @samp{sifive-e76}, -@samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76}, -@samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, @samp{sifive-xp450}, -@samp{sifive-x670}, @samp{thead-c906}, @samp{tt-ascalon-d8}, -@samp{xiangshan-nanhu}. +Permissible values for this option are: @samp{mips-p8700}, @samp{sifive-e20}, +@samp{sifive-e21}, @samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, +@samp{sifive-e76}, @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, +@samp{sifive-s76}, @samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, +@samp{sifive-xp450}, @samp{sifive-x670}, @samp{thead-c906}, @samp{tt-ascalon-d8}, +@samp{xiangshan-nanhu}, @samp{xiangshan-kunminghu}, @samp{xt-c908}, @samp{xt-c908v}, +@samp{xt-c910}, @samp{xt-c910v2}, @samp{xt-c920}, @samp{xt-c920v2}. Note that @option{-mcpu} does not override @option{-march} or @option{-mtune}. @@ -31478,7 +31301,7 @@ Note that @option{-mcpu} does not override @option{-march} or @option{-mtune}. @item -mtune=@var{processor-string} Optimize the output for the given processor, specified by microarchitecture or particular CPU name. Permissible values for this option are: -@samp{generic-ooo}, @samp{rocket}, @samp{sifive-3-series}, +@samp{generic-ooo}, @samp{mips-p8700}, @samp{rocket}, @samp{sifive-3-series}, @samp{sifive-5-series}, @samp{sifive-7-series}, @samp{size}, @samp{sifive-p400-series}, @samp{sifive-p600-series}, and all valid options for @option{-mcpu=}. @@ -34872,7 +34695,7 @@ Intel Lakemont MCU, based on Intel Pentium CPU. Intel Pentium MMX CPU, based on Pentium core with MMX instruction set support. @item pentiumpro -Intel Pentium Pro CPU@. +Intel Pentium Pro CPU with no MMX support. @item i686 When used with @option{-march}, the Pentium Pro @@ -35018,37 +34841,36 @@ VPCLMULQDQ, AVX512BITALG, RDPID and AVX512VPOPCNTDQ instruction set support. Intel Alder Lake/Raptor Lake/Meteor Lake/Gracemont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, -GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, -BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, -WIDEKL and AVX-VNNI instruction set support. +GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, +FMA, LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL and +AVX-VNNI instruction set support. @item arrowlake Intel Arrow Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, -MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, -PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, -UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set -support. +MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, +VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, UINTR, AVXIFMA, +AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set support. @item arrowlake-s @itemx lunarlake Intel Arrow Lake S/Lunar Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, -MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, -LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, -UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, -SM3 and SM4 instruction set support. +MOVDIRI, MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, +PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, UINTR, +AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3 and +SM4 instruction set support. @item pantherlake Intel Panther Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, -MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, -PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, -UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, -SM3, SM4 and PREFETCHI instruction set support. +MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, +VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, UINTR, AVXIFMA, +AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 and +PREFETCHI instruction set support. @item sapphirerapids @itemx emeraldrapids @@ -35400,8 +35222,8 @@ Produce code optimized for the most current Intel processors, which are Haswell and Silvermont for this version of GCC. If you know the CPU on which your code will run, then you should use the corresponding @option{-mtune} or @option{-march} option instead of @option{-mtune=intel}. -But, if you want your application performs better on both Haswell and -Silvermont, then you should use this option. +But, if you want your application performs better on both Diamond Rapids +and Clearwater Forest, then you should use this option. As new Intel processors are deployed in the marketplace, the behavior of this option will change. Therefore, if you upgrade to a newer version of @@ -36043,12 +35865,6 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @opindex mavx10.1 @itemx -mavx10.1 @need 200 -@opindex mavx10.1-256 -@itemx -mavx10.1-256 -@need 200 -@opindex mavx10.1-512 -@itemx -mavx10.1-512 -@need 200 @opindex mavx10.2 @itemx -mavx10.2 @need 200 @@ -36837,11 +36653,6 @@ To invoke egpr usage in inline asm, use new compiler option -mapx-inline-asm-use-gpr32 and user should ensure the instruction supports EGPR. -@opindex mevex512 -@item -mevex512 -@itemx -mno-evex512 -Enables/disables 512-bit vector. It will be default on if AVX512F is enabled. - @end table These @samp{-m} switches are supported in addition to the above |