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Diffstat (limited to 'gcc/config/sparc/sparc.h')
| -rw-r--r-- | gcc/config/sparc/sparc.h | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index a9672e3..af350d7 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -907,23 +907,6 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] -/* Defines invalid mode changes. Borrowed from the PA port. - - SImode loads to floating-point registers are not zero-extended. - The definition for LOAD_EXTEND_OP specifies that integer loads - narrower than BITS_PER_WORD will be zero-extended. As a result, - we inhibit changes from SImode unless they are to a mode that is - identical in size. - - Likewise for SFmode, since word-mode paradoxical subregs are - problematic on big-endian architectures. */ - -#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ - (TARGET_ARCH64 \ - && GET_MODE_SIZE (FROM) == 4 \ - && GET_MODE_SIZE (TO) != 4 \ - ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) - /* This is the order in which to allocate registers normally. We put %f0-%f7 last among the float registers, so as to make it more |