diff options
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
-rw-r--r-- | gcc/config/rs6000/rs6000.md | 92 |
1 files changed, 59 insertions, 33 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index e8a6205..12f5d6f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -184,12 +184,12 @@ vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm, vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto, veclogical,veccmpfx,vecexts,vecmove, - htm" + htm,htmsimple,dfp" (const_string "integer")) ;; What data size does this instruction work on? -;; This is used for insert, mul. -(define_attr "size" "8,16,32,64" (const_string "32")) +;; This is used for insert, mul and others as necessary. +(define_attr "size" "8,16,32,64,128" (const_string "32")) ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)? ;; This is used for add, logical, shift, exts, mul. @@ -299,6 +299,7 @@ (include "power6.md") (include "power7.md") (include "power8.md") +(include "power9.md") (include "cell.md") (include "xfpu.md") (include "a2.md") @@ -6792,6 +6793,7 @@ # #" [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,two,store,load,two") + (set_attr "size" "64") (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8,8,8")]) (define_insn "*mov<mode>_softfloat32" @@ -6837,6 +6839,7 @@ mfvsrd %0,%x1 mtvsrd %x0,%1" [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr") + (set_attr "size" "64") (set_attr "length" "4")]) (define_insn "*mov<mode>_softfloat64" @@ -7885,10 +7888,11 @@ # #" [(set_attr "type" - "store, load, *, fpstore, fpload, fpsimple, - *, fpstore, fpstore, fpload, fpload, veclogical, - vecsimple, vecsimple, vecsimple, veclogical, veclogical, vecsimple, - vecsimple")]) + "store, load, *, fpstore, fpload, fpsimple, + *, fpstore, fpstore, fpload, fpload, veclogical, + vecsimple, vecsimple, vecsimple, veclogical, veclogical, vecsimple, + vecsimple") + (set_attr "size" "64")]) (define_split [(set (match_operand:DI 0 "gpc_reg_operand" "") @@ -7971,12 +7975,13 @@ mfvsrd %0,%x1 mtvsrd %x0,%1" [(set_attr "type" - "store, load, *, *, *, *, - fpstore, fpload, fpsimple, fpstore, fpstore, fpload, - fpload, veclogical, vecsimple, vecsimple, vecsimple, veclogical, - veclogical, vecsimple, vecsimple, mfjmpr, mtjmpr, *, - mftgpr, mffgpr, mftgpr, mffgpr") + "store, load, *, *, *, *, + fpstore, fpload, fpsimple, fpstore, fpstore, fpload, + fpload, veclogical, vecsimple, vecsimple, vecsimple, veclogical, + veclogical, vecsimple, vecsimple, mfjmpr, mtjmpr, *, + mftgpr, mffgpr, mftgpr, mffgpr") + (set_attr "size" "64") (set_attr "length" "4, 4, 4, 4, 4, 20, 4, 4, 4, 4, 4, 4, @@ -9026,7 +9031,8 @@ lfdu %3,%2(%0)" [(set_attr "type" "fpload") (set_attr "update" "yes") - (set_attr "indexed" "yes,no")]) + (set_attr "indexed" "yes,no") + (set_attr "size" "64")]) (define_insn "*movdf_update2" [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") @@ -13431,7 +13437,8 @@ (match_operand:IEEE128 2 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsaddqp %0,%1,%2" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "sub<mode>3" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13440,7 +13447,8 @@ (match_operand:IEEE128 2 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xssubqp %0,%1,%2" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "mul<mode>3" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13449,7 +13457,8 @@ (match_operand:IEEE128 2 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsmulqp %0,%1,%2" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "div<mode>3" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13458,7 +13467,8 @@ (match_operand:IEEE128 2 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsdivqp %0,%1,%2" - [(set_attr "type" "vecdiv")]) + [(set_attr "type" "vecdiv") + (set_attr "size" "128")]) (define_insn "sqrt<mode>2" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13466,7 +13476,8 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xssqrtqp %0,%1" - [(set_attr "type" "vecdiv")]) + [(set_attr "type" "vecdiv") + (set_attr "size" "128")]) (define_expand "copysign<mode>3" [(use (match_operand:IEEE128 0 "altivec_register_operand")) @@ -13494,7 +13505,8 @@ UNSPEC_COPYSIGN))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscpsgnqp %0,%2,%1" - [(set_attr "type" "vecmove")]) + [(set_attr "type" "vecmove") + (set_attr "size" "128")]) (define_insn "copysign<mode>3_soft" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13514,7 +13526,8 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsnegqp %0,%1" - [(set_attr "type" "vecmove")]) + [(set_attr "type" "vecmove") + (set_attr "size" "128")]) (define_insn "abs<mode>2_hw" @@ -13523,7 +13536,8 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsabsqp %0,%1" - [(set_attr "type" "vecmove")]) + [(set_attr "type" "vecmove") + (set_attr "size" "128")]) (define_insn "*nabs<mode>2_hw" @@ -13533,7 +13547,8 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v"))))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsnabsqp %0,%1" - [(set_attr "type" "vecmove")]) + [(set_attr "type" "vecmove") + (set_attr "size" "128")]) ;; Initially don't worry about doing fusion (define_insn "*fma<mode>4_hw" @@ -13544,7 +13559,8 @@ (match_operand:IEEE128 3 "altivec_register_operand" "0")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsmaddqp %0,%1,%2" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "*fms<mode>4_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13555,7 +13571,8 @@ (match_operand:IEEE128 3 "altivec_register_operand" "0"))))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsmsubqp %0,%1,%2" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "*nfma<mode>4_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13566,7 +13583,8 @@ (match_operand:IEEE128 3 "altivec_register_operand" "0"))))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsnmaddqp %0,%1,%2" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "*nfms<mode>4_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13578,7 +13596,8 @@ (match_operand:IEEE128 3 "altivec_register_operand" "0")))))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsnmsubqp %0,%1,%2" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "extend<SFDF:mode><IEEE128:mode>2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13586,7 +13605,8 @@ (match_operand:SFDF 1 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)" "xscvdpqp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) ;; Conversion between KFmode and TFmode if TFmode is ieee 128-bit floating ;; point is a simple copy. @@ -13628,7 +13648,8 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscvqpdp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) ;; There is no KFmode -> SFmode instruction. Preserve the accuracy by doing ;; the KFmode -> DFmode conversion using round to odd rather than the normal @@ -13725,7 +13746,8 @@ UNSPEC_IEEE128_CONVERT))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscvqp<su>wz %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "*xscvqp<su>dz_<mode>" [(set (match_operand:V2DI 0 "altivec_register_operand" "=v") @@ -13735,7 +13757,8 @@ UNSPEC_IEEE128_CONVERT))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscvqp<su>dz %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "*xscv<su>dqp_<mode>" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13744,7 +13767,8 @@ UNSPEC_IEEE128_CONVERT)))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscv<su>dqp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "*ieee128_mfvsrd_64bit" [(set (match_operand:DI 0 "reg_or_indexed_operand" "=wr,Z,wi") @@ -13821,7 +13845,8 @@ UNSPEC_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscvqpdpo %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) ;; IEEE 128-bit comparisons (define_insn "*cmp<mode>_hw" @@ -13830,7 +13855,8 @@ (match_operand:IEEE128 2 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscmpuqp %0,%1,%2" - [(set_attr "type" "fpcompare")]) + [(set_attr "type" "veccmp") + (set_attr "size" "128")]) |