diff options
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 61 |
1 files changed, 40 insertions, 21 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 408d20a..5993537 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -160,13 +160,12 @@ (define_attr "type" "integer,two,three, shift,var_shift_rotate,insert_word,insert_dword, - imul,imul2,imul3,lmul,halfmul,idiv,ldiv, + mul,halfmul,idiv,ldiv, exts,cntlz,popcnt,isel, load,store,fpload,fpstore,vecload,vecstore, cmp, branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c, compare,fast_compare,delayed_compare,var_delayed_compare, - imul_compare,lmul_compare, cr_logical,delayed_cr,mfcr,mfcrf,mtcr, fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt, brinc, @@ -175,6 +174,14 @@ htm" (const_string "integer")) +;; What data size does this instruction work on? +;; This is used for mul. +(define_attr "size" "8,16,32,64" (const_string "32")) + +;; Is this instruction record form ("dot", signed compare to 0, writing CR0)? +;; This is used for mul. +(define_attr "dot" "no,yes" (const_string "no")) + ;; Does this instruction sign-extend its result? ;; This is used for load insns. (define_attr "sign_extend" "no,yes" (const_string "no")) @@ -229,7 +236,9 @@ ;; If this instruction is microcoded on the CELL processor ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded (define_attr "cell_micro" "not,conditional,always" - (if_then_else (ior (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,var_shift_rotate,var_delayed_compare") + (if_then_else (ior (eq_attr "type" "compare,delayed_compare,var_shift_rotate,var_delayed_compare") + (and (eq_attr "type" "mul") + (eq_attr "dot" "yes")) (and (eq_attr "type" "load") (eq_attr "sign_extend" "yes"))) (const_string "always") @@ -2665,12 +2674,13 @@ "@ mullw %0,%1,%2 mulli %0,%1,%2" - [(set (attr "type") + [(set_attr "type" "mul") + (set (attr "size") (cond [(match_operand:SI 2 "s8bit_cint_operand" "") - (const_string "imul3") + (const_string "8") (match_operand:SI 2 "short_cint_operand" "") - (const_string "imul2")] - (const_string "imul")))]) + (const_string "16")] + (const_string "32")))]) (define_insn "*mulsi3_internal1" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -2682,7 +2692,8 @@ "@ mullw. %3,%1,%2 #" - [(set_attr "type" "imul_compare") + [(set_attr "type" "mul") + (set_attr "dot" "yes") (set_attr "length" "4,8")]) (define_split @@ -2710,7 +2721,8 @@ "@ mullw. %0,%1,%2 #" - [(set_attr "type" "imul_compare") + [(set_attr "type" "mul") + (set_attr "dot" "yes") (set_attr "length" "4,8")]) (define_split @@ -6600,7 +6612,7 @@ ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; } - [(set_attr "type" "imul") + [(set_attr "type" "mul") (set_attr "length" "8")]) (define_split @@ -6634,7 +6646,7 @@ ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; }" - [(set_attr "type" "imul") + [(set_attr "type" "mul") (set_attr "length" "8")]) (define_split @@ -6667,7 +6679,7 @@ (const_int 32))))] "" "mulhw %0,%1,%2" - [(set_attr "type" "imul")]) + [(set_attr "type" "mul")]) (define_insn "umulsi3_highpart" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -6679,7 +6691,7 @@ (const_int 32))))] "" "mulhwu %0,%1,%2" - [(set_attr "type" "imul")]) + [(set_attr "type" "mul")]) ;; Shift by a variable amount is too complex to be worth open-coding. We ;; just handle shifts by constants. @@ -6734,12 +6746,13 @@ "@ mulld %0,%1,%2 mulli %0,%1,%2" - [(set (attr "type") + [(set_attr "type" "mul") + (set (attr "size") (cond [(match_operand:SI 2 "s8bit_cint_operand" "") - (const_string "imul3") + (const_string "8") (match_operand:SI 2 "short_cint_operand" "") - (const_string "imul2")] - (const_string "lmul")))]) + (const_string "16")] + (const_string "64")))]) (define_insn "*muldi3_internal1" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -6751,7 +6764,9 @@ "@ mulld. %3,%1,%2 #" - [(set_attr "type" "lmul_compare") + [(set_attr "type" "mul") + (set_attr "size" "64") + (set_attr "dot" "yes") (set_attr "length" "4,8")]) (define_split @@ -6779,7 +6794,9 @@ "@ mulld. %0,%1,%2 #" - [(set_attr "type" "lmul_compare") + [(set_attr "type" "mul") + (set_attr "size" "64") + (set_attr "dot" "yes") (set_attr "length" "4,8")]) (define_split @@ -6807,7 +6824,8 @@ (const_int 64))))] "TARGET_POWERPC64" "mulhd %0,%1,%2" - [(set_attr "type" "lmul")]) + [(set_attr "type" "mul") + (set_attr "size" "64")]) (define_insn "umuldi3_highpart" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -6819,7 +6837,8 @@ (const_int 64))))] "TARGET_POWERPC64" "mulhdu %0,%1,%2" - [(set_attr "type" "lmul")]) + [(set_attr "type" "mul") + (set_attr "size" "64")]) (define_expand "mulditi3" [(set (match_operand:TI 0 "gpc_reg_operand") |