diff options
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 780 |
1 files changed, 390 insertions, 390 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 999aa37..0976d50 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1576,12 +1576,12 @@ "dlmzb. %0,%1,%2") (define_expand "strlensi" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (unspec:SI [(match_operand:BLK 1 "general_operand" "") - (match_operand:QI 2 "const_int_operand" "") - (match_operand 3 "const_int_operand" "")] + [(set (match_operand:SI 0 "gpc_reg_operand") + (unspec:SI [(match_operand:BLK 1 "general_operand") + (match_operand:QI 2 "const_int_operand") + (match_operand 3 "const_int_operand")] UNSPEC_DLMZB_STRLEN)) - (clobber (match_scratch:CC 4 "=x"))] + (clobber (match_scratch:CC 4))] "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size" { rtx result = operands[0]; @@ -1630,9 +1630,9 @@ ;; Fixed-point arithmetic insns. (define_expand "add<mode>3" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "") - (match_operand:SDI 2 "reg_or_add_cint_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (plus:SDI (match_operand:SDI 1 "gpc_reg_operand") + (match_operand:SDI 2 "reg_or_add_cint_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -1805,9 +1805,9 @@ ;; add should be last in case the result gets used in an address. (define_split - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "non_add_cint_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (plus:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "non_add_cint_operand")))] "" [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3))) (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))] @@ -1950,8 +1950,8 @@ (define_expand "one_cmpl<mode>2" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (not:SDI (match_operand:SDI 1 "gpc_reg_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -2010,9 +2010,9 @@ (define_expand "sub<mode>3" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "") - (match_operand:SDI 2 "gpc_reg_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (minus:SDI (match_operand:SDI 1 "reg_or_short_operand") + (match_operand:SDI 2 "gpc_reg_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -2338,8 +2338,8 @@ (define_expand "popcount<mode>2" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand")))] "TARGET_POPCNTB || TARGET_POPCNTD" { rs6000_emit_popcount (operands[0], operands[1]); @@ -2363,8 +2363,8 @@ (define_expand "parity<mode>2" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (parity:GPR (match_operand:GPR 1 "gpc_reg_operand")))] "TARGET_POPCNTB" { rs6000_emit_parity (operands[0], operands[1]); @@ -2508,11 +2508,11 @@ ;; complex code. (define_expand "bswapdi2" - [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "") + [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand") (bswap:DI - (match_operand:DI 1 "reg_or_mem_operand" ""))) - (clobber (match_scratch:DI 2 "")) - (clobber (match_scratch:DI 3 ""))])] + (match_operand:DI 1 "reg_or_mem_operand"))) + (clobber (match_scratch:DI 2)) + (clobber (match_scratch:DI 3))])] "" { rtx dest = operands[0]; @@ -2589,10 +2589,10 @@ [(set_attr "length" "16,12,36")]) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" ""))) - (clobber (match_operand:DI 2 "gpc_reg_operand" "")) - (clobber (match_operand:DI 3 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand"))) + (clobber (match_operand:DI 2 "gpc_reg_operand")) + (clobber (match_operand:DI 3 "gpc_reg_operand"))] "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed" [(const_int 0)] { @@ -2652,10 +2652,10 @@ }) (define_split - [(set (match_operand:DI 0 "indexed_or_indirect_operand" "") - (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) - (clobber (match_operand:DI 2 "gpc_reg_operand" "")) - (clobber (match_operand:DI 3 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "indexed_or_indirect_operand") + (bswap:DI (match_operand:DI 1 "gpc_reg_operand"))) + (clobber (match_operand:DI 2 "gpc_reg_operand")) + (clobber (match_operand:DI 3 "gpc_reg_operand"))] "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed" [(const_int 0)] { @@ -2714,10 +2714,10 @@ }) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) - (clobber (match_operand:DI 2 "gpc_reg_operand" "")) - (clobber (match_operand:DI 3 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (bswap:DI (match_operand:DI 1 "gpc_reg_operand"))) + (clobber (match_operand:DI 2 "gpc_reg_operand")) + (clobber (match_operand:DI 3 "gpc_reg_operand"))] "TARGET_POWERPC64 && !TARGET_P9_VECTOR && reload_completed" [(const_int 0)] { @@ -2748,9 +2748,9 @@ [(set_attr "length" "16,12,36")]) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" ""))) - (clobber (match_operand:SI 2 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand"))) + (clobber (match_operand:SI 2 "gpc_reg_operand"))] "!TARGET_POWERPC64 && reload_completed" [(const_int 0)] { @@ -2800,9 +2800,9 @@ }) (define_split - [(set (match_operand:DI 0 "indexed_or_indirect_operand" "") - (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) - (clobber (match_operand:SI 2 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "indexed_or_indirect_operand") + (bswap:DI (match_operand:DI 1 "gpc_reg_operand"))) + (clobber (match_operand:SI 2 "gpc_reg_operand"))] "!TARGET_POWERPC64 && reload_completed" [(const_int 0)] { @@ -2848,9 +2848,9 @@ }) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) - (clobber (match_operand:SI 2 "" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (bswap:DI (match_operand:DI 1 "gpc_reg_operand"))) + (clobber (match_operand:SI 2 ""))] "!TARGET_POWERPC64 && reload_completed" [(const_int 0)] { @@ -2877,9 +2877,9 @@ mulli %0,%1,%2" [(set_attr "type" "mul") (set (attr "size") - (cond [(match_operand:GPR 2 "s8bit_cint_operand" "") + (cond [(match_operand:GPR 2 "s8bit_cint_operand") (const_string "8") - (match_operand:GPR 2 "short_cint_operand" "") + (match_operand:GPR 2 "short_cint_operand") (const_string "16")] (const_string "<bits>")))]) @@ -3048,9 +3048,9 @@ ;; modulus. If it isn't a power of two, force operands into register and do ;; a normal divide. (define_expand "div<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "reg_or_cint_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (div:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "reg_or_cint_operand")))] "" { if (CONST_INT_P (operands[2]) @@ -3190,10 +3190,10 @@ ;; after a divide. (define_peephole2 - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "gpc_reg_operand" ""))) - (set (match_operand:GPR 3 "gpc_reg_operand" "") + [(set (match_operand:GPR 0 "gpc_reg_operand") + (div:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "gpc_reg_operand"))) + (set (match_operand:GPR 3 "gpc_reg_operand") (mod:GPR (match_dup 1) (match_dup 2)))] "TARGET_MODULO @@ -3212,10 +3212,10 @@ (match_dup 3)))]) (define_peephole2 - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "gpc_reg_operand" ""))) - (set (match_operand:GPR 3 "gpc_reg_operand" "") + [(set (match_operand:GPR 0 "gpc_reg_operand") + (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "gpc_reg_operand"))) + (set (match_operand:GPR 3 "gpc_reg_operand") (umod:GPR (match_dup 1) (match_dup 2)))] "TARGET_MODULO @@ -3241,9 +3241,9 @@ ;; those rotate-and-mask operations. Thus, the AND insns come first. (define_expand "and<mode>3" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "") - (match_operand:SDI 2 "reg_or_cint_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (and:SDI (match_operand:SDI 1 "gpc_reg_operand") + (match_operand:SDI 2 "reg_or_cint_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -3539,9 +3539,9 @@ (define_expand "<code><mode>3" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "") - (match_operand:SDI 2 "reg_or_cint_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand") + (match_operand:SDI 2 "reg_or_cint_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -3570,9 +3570,9 @@ }) (define_split - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "non_logical_cint_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "non_logical_cint_operand")))] "" [(set (match_dup 3) (iorxor:GPR (match_dup 1) @@ -4473,9 +4473,9 @@ ;; Builtins to replace a division to generate FRE reciprocal estimate ;; instructions and the necessary fixup instructions (define_expand "recip<mode>3" - [(match_operand:RECIPF 0 "gpc_reg_operand" "") - (match_operand:RECIPF 1 "gpc_reg_operand" "") - (match_operand:RECIPF 2 "gpc_reg_operand" "")] + [(match_operand:RECIPF 0 "gpc_reg_operand") + (match_operand:RECIPF 1 "gpc_reg_operand") + (match_operand:RECIPF 2 "gpc_reg_operand")] "RS6000_RECIP_HAVE_RE_P (<MODE>mode)" { rs6000_emit_swdiv (operands[0], operands[1], operands[2], false); @@ -4488,9 +4488,9 @@ ;; We used to also check optimize_insn_for_speed_p () but problems with guessed ;; frequencies (pr68212/pr77536) yields that unreliable so it was removed. (define_split - [(set (match_operand:RECIPF 0 "gpc_reg_operand" "") - (div:RECIPF (match_operand 1 "gpc_reg_operand" "") - (match_operand 2 "gpc_reg_operand" "")))] + [(set (match_operand:RECIPF 0 "gpc_reg_operand") + (div:RECIPF (match_operand 1 "gpc_reg_operand") + (match_operand 2 "gpc_reg_operand")))] "RS6000_RECIP_AUTO_RE_P (<MODE>mode) && can_create_pseudo_p () && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math" @@ -4503,8 +4503,8 @@ ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the ;; appropriate fixup. (define_expand "rsqrt<mode>2" - [(match_operand:RECIPF 0 "gpc_reg_operand" "") - (match_operand:RECIPF 1 "gpc_reg_operand" "")] + [(match_operand:RECIPF 0 "gpc_reg_operand") + (match_operand:RECIPF 1 "gpc_reg_operand")] "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)" { rs6000_emit_swsqrt (operands[0], operands[1], 1); @@ -4517,8 +4517,8 @@ ;; -mupper-regs-{df,sf} option is enabled. (define_expand "abs<mode>2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4545,8 +4545,8 @@ (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "neg<mode>2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4561,9 +4561,9 @@ (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "add<mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4579,9 +4579,9 @@ (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "sub<mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4597,9 +4597,9 @@ (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "mul<mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4615,9 +4615,9 @@ (set_attr "fp_type" "fp_mul_<Fs>")]) (define_expand "div<mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU" { if (RS6000_RECIP_AUTO_RE_P (<MODE>mode) @@ -4652,8 +4652,8 @@ (set_attr "fp_type" "fp_sqrt_<Fs>")]) (define_expand "sqrt<mode>2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))" { @@ -4741,8 +4741,8 @@ [(set_attr "type" "fp")]) (define_expand "truncdfsf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "") @@ -4760,12 +4760,12 @@ ;; when little-endian. (define_expand "signbit<mode>2" [(set (match_dup 2) - (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" ""))) + (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand"))) (set (match_dup 3) (subreg:DI (match_dup 2) 0)) (set (match_dup 4) (match_dup 5)) - (set (match_operand:SI 0 "gpc_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand") (match_dup 6))] "TARGET_HARD_FLOAT && (!FLOAT128_IEEE_P (<MODE>mode) @@ -4868,11 +4868,11 @@ (define_expand "copysign<mode>3" [(set (match_dup 3) - (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ""))) + (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand"))) (set (match_dup 4) (neg:SFDF (abs:SFDF (match_dup 1)))) - (set (match_operand:SFDF 0 "gpc_reg_operand" "") - (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "") + (set (match_operand:SFDF 0 "gpc_reg_operand") + (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand") (match_dup 5)) (match_dup 3) (match_dup 4)))] @@ -4922,9 +4922,9 @@ ;; to allow either DF/SF to use only traditional registers. (define_expand "s<minmax><mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_MINMAX_<MODE>" { rs6000_emit_minmax (operands[0], <SMINMAX>, operands[1], operands[2]); @@ -4948,9 +4948,9 @@ ;; instruction. (define_insn_and_split "*s<minmax><mode>3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "!TARGET_VSX && TARGET_MINMAX_<MODE>" "#" "&& 1" @@ -4961,10 +4961,10 @@ }) (define_expand "mov<mode>cc" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (if_then_else:GPR (match_operand 1 "comparison_operator" "") - (match_operand:GPR 2 "gpc_reg_operand" "") - (match_operand:GPR 3 "gpc_reg_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (if_then_else:GPR (match_operand 1 "comparison_operator") + (match_operand:GPR 2 "gpc_reg_operand") + (match_operand:GPR 3 "gpc_reg_operand")))] "TARGET_ISEL" { if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) @@ -5041,10 +5041,10 @@ ;; Floating point conditional move (define_expand "mov<mode>cc" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (if_then_else:SFDF (match_operand 1 "comparison_operator" "") - (match_operand:SFDF 2 "gpc_reg_operand" "") - (match_operand:SFDF 3 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (if_then_else:SFDF (match_operand 1 "comparison_operator") + (match_operand:SFDF 2 "gpc_reg_operand") + (match_operand:SFDF 3 "gpc_reg_operand")))] "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT" { if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) @@ -5321,8 +5321,8 @@ ; then to have the insns split later (between sched1 and final). (define_expand "floatsidf2" - [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") - (float:DF (match_operand:SI 1 "nonimmediate_operand" ""))) + [(parallel [(set (match_operand:DF 0 "gpc_reg_operand") + (float:DF (match_operand:SI 1 "nonimmediate_operand"))) (use (match_dup 2)) (use (match_dup 3)) (clobber (match_dup 4)) @@ -5389,8 +5389,8 @@ ;; conversion for 32-bit without fast math, because we don't have the insn to ;; generate the fixup swizzle to avoid double rounding problems. (define_expand "floatunssisf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand")))] "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && ((TARGET_FCFIDUS && TARGET_LFIWZX) || (TARGET_DOUBLE_FLOAT && TARGET_FCFID @@ -5413,8 +5413,8 @@ }) (define_expand "floatunssidf2" - [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") - (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" ""))) + [(parallel [(set (match_operand:DF 0 "gpc_reg_operand") + (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand"))) (use (match_dup 2)) (use (match_dup 3)) (clobber (match_dup 4)) @@ -5534,9 +5534,9 @@ (define_expand "floatuns<QHI:mode><FP_ISA3:mode>2" [(parallel [(set (match_operand:FP_ISA3 0 "vsx_register_operand") (unsigned_float:FP_ISA3 - (match_operand:QHI 1 "input_operand" ""))) - (clobber (match_scratch:DI 2 "")) - (clobber (match_scratch:DI 3 ""))])] + (match_operand:QHI 1 "input_operand"))) + (clobber (match_scratch:DI 2)) + (clobber (match_scratch:DI 3))])] "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64" { if (MEM_P (operands[1])) @@ -5577,8 +5577,8 @@ }) (define_expand "fix_trunc<mode>si2" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand") + (fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && <TARGET_FLOAT>" { if (!TARGET_P8_VECTOR) @@ -5667,8 +5667,8 @@ (set_attr "type" "fp")]) (define_expand "fix_trunc<mode>di2" - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (fix:DI (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFID" "") @@ -5737,8 +5737,8 @@ }) (define_expand "fixuns_trunc<mode>si2" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand") + (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX" { if (!TARGET_P8_VECTOR) @@ -5981,9 +5981,9 @@ (define_expand "lround<mode>di2" [(set (match_dup 2) - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand")] UNSPEC_XSRDPI)) - (set (match_operand:DI 0 "gpc_reg_operand" "") + (set (match_operand:DI 0 "gpc_reg_operand") (unspec:DI [(match_dup 2)] UNSPEC_FCTID))] "TARGET_<MODE>_FPR && TARGET_VSX" @@ -6008,8 +6008,8 @@ ;; conversion for 32-bit without fast math, because we don't have the insn to ;; generate the fixup swizzle to avoid double rounding problems. (define_expand "floatsisf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (float:SF (match_operand:SI 1 "nonimmediate_operand")))] "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && ((TARGET_FCFIDS && TARGET_LFIWAX) || (TARGET_DOUBLE_FLOAT && TARGET_FCFID @@ -6066,9 +6066,9 @@ (set_attr "type" "fpload")]) (define_expand "floatunsdidf2" - [(set (match_operand:DF 0 "gpc_reg_operand" "") + [(set (match_operand:DF 0 "gpc_reg_operand") (unsigned_float:DF - (match_operand:DI 1 "gpc_reg_operand" "")))] + (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_FCFIDU" "") @@ -6096,8 +6096,8 @@ (set_attr "type" "fpload")]) (define_expand "floatdisf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (float:SF (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)" { @@ -6166,11 +6166,11 @@ ;; by a bit that won't be lost at that stage, but is below the SFmode ;; rounding position. (define_expand "floatdisf2_internal2" - [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "") + [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "") (const_int 53))) (clobber (reg:DI CA_REGNO))]) - (set (match_operand:DI 0 "" "") (and:DI (match_dup 1) - (const_int 2047))) + (set (match_operand:DI 0 "") (and:DI (match_dup 1) + (const_int 2047))) (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1))) (set (match_dup 0) (plus:DI (match_dup 0) @@ -6182,7 +6182,7 @@ (set (match_dup 0) (and:DI (match_dup 0) (const_int -2048))) (set (pc) (if_then_else (geu (match_dup 4) (const_int 0)) - (label_ref (match_operand:DI 2 "" "")) + (label_ref (match_operand:DI 2 "")) (pc))) (set (match_dup 0) (match_dup 1))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT @@ -6193,8 +6193,8 @@ }) (define_expand "floatunsdisf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS" "") @@ -6233,9 +6233,9 @@ ;; also allow for the output being the same as one of the inputs. (define_expand "addti3" - [(set (match_operand:TI 0 "gpc_reg_operand" "") - (plus:TI (match_operand:TI 1 "gpc_reg_operand" "") - (match_operand:TI 2 "reg_or_short_operand" "")))] + [(set (match_operand:TI 0 "gpc_reg_operand") + (plus:TI (match_operand:TI 1 "gpc_reg_operand") + (match_operand:TI 2 "reg_or_short_operand")))] "TARGET_64BIT" { rtx lo0 = gen_lowpart (DImode, operands[0]); @@ -6256,9 +6256,9 @@ }) (define_expand "subti3" - [(set (match_operand:TI 0 "gpc_reg_operand" "") - (minus:TI (match_operand:TI 1 "reg_or_short_operand" "") - (match_operand:TI 2 "gpc_reg_operand" "")))] + [(set (match_operand:TI 0 "gpc_reg_operand") + (minus:TI (match_operand:TI 1 "reg_or_short_operand") + (match_operand:TI 2 "gpc_reg_operand")))] "TARGET_64BIT" { rtx lo0 = gen_lowpart (DImode, operands[0]); @@ -6281,73 +6281,73 @@ ;; 128-bit logical operations expanders (define_expand "and<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") - (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") - (match_operand:BOOL_128 2 "vlogical_operand" "")))] + [(set (match_operand:BOOL_128 0 "vlogical_operand") + (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand") + (match_operand:BOOL_128 2 "vlogical_operand")))] "" "") (define_expand "ior<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") - (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") - (match_operand:BOOL_128 2 "vlogical_operand" "")))] + [(set (match_operand:BOOL_128 0 "vlogical_operand") + (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand") + (match_operand:BOOL_128 2 "vlogical_operand")))] "" "") (define_expand "xor<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") - (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") - (match_operand:BOOL_128 2 "vlogical_operand" "")))] + [(set (match_operand:BOOL_128 0 "vlogical_operand") + (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand") + (match_operand:BOOL_128 2 "vlogical_operand")))] "" "") (define_expand "one_cmpl<mode>2" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") - (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))] + [(set (match_operand:BOOL_128 0 "vlogical_operand") + (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")))] "" "") (define_expand "nor<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (and:BOOL_128 - (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")) - (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))] + (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")) + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))))] "" "") (define_expand "andc<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (and:BOOL_128 - (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" "")) - (match_operand:BOOL_128 1 "vlogical_operand" "")))] + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand")) + (match_operand:BOOL_128 1 "vlogical_operand")))] "" "") ;; Power8 vector logical instructions. (define_expand "eqv<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (not:BOOL_128 - (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") - (match_operand:BOOL_128 2 "vlogical_operand" ""))))] + (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand") + (match_operand:BOOL_128 2 "vlogical_operand"))))] "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR" "") ;; Rewrite nand into canonical form (define_expand "nand<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (ior:BOOL_128 - (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")) - (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))] + (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")) + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))))] "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR" "") ;; The canonical form is to have the negated element first, so we need to ;; reverse arguments. (define_expand "orc<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (ior:BOOL_128 - (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" "")) - (match_operand:BOOL_128 1 "vlogical_operand" "")))] + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand")) + (match_operand:BOOL_128 1 "vlogical_operand")))] "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR" "") @@ -6641,8 +6641,8 @@ ;; Set up a register with a value from the GOT table (define_expand "movsi_got" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (unspec:SI [(match_operand:SI 1 "got_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand") + (unspec:SI [(match_operand:SI 1 "got_operand") (match_dup 2)] UNSPEC_MOVSI_GOT))] "DEFAULT_ABI == ABI_V4 && flag_pic == 1" { @@ -6679,9 +6679,9 @@ ;; Used by sched, shorten_branches and final when the GOT pseudo reg ;; didn't get allocated to a hard register. (define_split - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") - (match_operand:SI 2 "memory_operand" "")] + [(set (match_operand:SI 0 "gpc_reg_operand") + (unspec:SI [(match_operand:SI 1 "got_no_const_operand") + (match_operand:SI 2 "memory_operand")] UNSPEC_MOVSI_GOT))] "DEFAULT_ABI == ABI_V4 && flag_pic == 1 @@ -6940,8 +6940,8 @@ ;; sequence. (define_split - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (match_operand:SI 1 "const_int_operand" ""))] + [(set (match_operand:SI 0 "gpc_reg_operand") + (match_operand:SI 1 "const_int_operand"))] "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 && (INTVAL (operands[1]) & 0xffff) != 0" [(set (match_dup 0) @@ -7000,8 +7000,8 @@ "") (define_expand "mov<mode>" - [(set (match_operand:INT 0 "general_operand" "") - (match_operand:INT 1 "any_operand" ""))] + [(set (match_operand:INT 0 "general_operand") + (match_operand:INT 1 "any_operand"))] "" { rs6000_emit_move (operands[0], operands[1], <MODE>mode); @@ -7056,8 +7056,8 @@ ;; an integer register or memory, we store just the high-order 4 bits. ;; This lets us not shift in the most common case of CR0. (define_expand "movcc" - [(set (match_operand:CC 0 "nonimmediate_operand" "") - (match_operand:CC 1 "nonimmediate_operand" ""))] + [(set (match_operand:CC 0 "nonimmediate_operand") + (match_operand:CC 1 "nonimmediate_operand"))] "" "") @@ -7110,8 +7110,8 @@ ;; Move 32-bit binary/decimal floating point (define_expand "mov<mode>" - [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "") - (match_operand:FMOVE32 1 "any_operand" ""))] + [(set (match_operand:FMOVE32 0 "nonimmediate_operand") + (match_operand:FMOVE32 1 "any_operand"))] "<fmove_ok>" { rs6000_emit_move (operands[0], operands[1], <MODE>mode); @@ -7119,8 +7119,8 @@ }) (define_split - [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "") - (match_operand:FMOVE32 1 "const_double_operand" ""))] + [(set (match_operand:FMOVE32 0 "gpc_reg_operand") + (match_operand:FMOVE32 1 "const_double_operand"))] "reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG @@ -7309,8 +7309,8 @@ ;; Move 64-bit binary/decimal floating point (define_expand "mov<mode>" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "") - (match_operand:FMOVE64 1 "any_operand" ""))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand") + (match_operand:FMOVE64 1 "any_operand"))] "" { rs6000_emit_move (operands[0], operands[1], <MODE>mode); @@ -7318,8 +7318,8 @@ }) (define_split - [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") - (match_operand:FMOVE64 1 "const_int_operand" ""))] + [(set (match_operand:FMOVE64 0 "gpc_reg_operand") + (match_operand:FMOVE64 1 "const_int_operand"))] "! TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG @@ -7338,8 +7338,8 @@ }) (define_split - [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") - (match_operand:FMOVE64 1 "const_double_operand" ""))] + [(set (match_operand:FMOVE64 0 "gpc_reg_operand") + (match_operand:FMOVE64 1 "const_double_operand"))] "! TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG @@ -7360,8 +7360,8 @@ }) (define_split - [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") - (match_operand:FMOVE64 1 "const_double_operand" ""))] + [(set (match_operand:FMOVE64 0 "gpc_reg_operand") + (match_operand:FMOVE64 1 "const_double_operand"))] "TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG @@ -7486,8 +7486,8 @@ (set_attr "length" "4,4,4,4,4,8,12,16,4")]) (define_expand "mov<mode>" - [(set (match_operand:FMOVE128 0 "general_operand" "") - (match_operand:FMOVE128 1 "any_operand" ""))] + [(set (match_operand:FMOVE128 0 "general_operand") + (match_operand:FMOVE128 1 "any_operand"))] "" { rs6000_emit_move (operands[0], operands[1], <MODE>mode); @@ -7555,8 +7555,8 @@ [(set_attr "length" "20,20,16")]) (define_expand "extenddf<mode>2" - [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "") - (float_extend:FLOAT128 (match_operand:DF 1 "gpc_reg_operand" "")))] + [(set (match_operand:FLOAT128 0 "gpc_reg_operand") + (float_extend:FLOAT128 (match_operand:DF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { if (FLOAT128_IEEE_P (<MODE>mode)) @@ -7624,8 +7624,8 @@ }) (define_expand "extendsf<mode>2" - [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "") - (float_extend:FLOAT128 (match_operand:SF 1 "gpc_reg_operand" "")))] + [(set (match_operand:FLOAT128 0 "gpc_reg_operand") + (float_extend:FLOAT128 (match_operand:SF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { if (FLOAT128_IEEE_P (<MODE>mode)) @@ -7640,8 +7640,8 @@ }) (define_expand "trunc<mode>df2" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:DF 0 "gpc_reg_operand") + (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { if (FLOAT128_IEEE_P (<MODE>mode)) @@ -7678,8 +7678,8 @@ (set_attr "fp_type" "fp_addsub_d")]) (define_expand "trunc<mode>sf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (float_truncate:SF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (float_truncate:SF (match_operand:FLOAT128 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { if (FLOAT128_IEEE_P (<MODE>mode)) @@ -7750,8 +7750,8 @@ (set_attr "length" "20")]) (define_expand "fix_trunc<mode>si2" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (fix:SI (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand") + (fix:SI (match_operand:FLOAT128 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { rtx op0 = operands[0]; @@ -7774,8 +7774,8 @@ }) (define_expand "fix_trunc<mode>si2_fprs" - [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") - (fix:SI (match_operand:IBM128 1 "gpc_reg_operand" ""))) + [(parallel [(set (match_operand:SI 0 "gpc_reg_operand") + (fix:SI (match_operand:IBM128 1 "gpc_reg_operand"))) (clobber (match_dup 2)) (clobber (match_dup 3)) (clobber (match_dup 4)) @@ -7814,8 +7814,8 @@ }) (define_expand "fix_trunc<mode>di2" - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (fix:DI (match_operand:IEEE128 1 "gpc_reg_operand" "")))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (fix:DI (match_operand:IEEE128 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { if (!TARGET_FLOAT128_HW) @@ -7826,8 +7826,8 @@ }) (define_expand "fixuns_trunc<IEEE128:mode><SDI:mode>2" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (unsigned_fix:SDI (match_operand:IEEE128 1 "gpc_reg_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (unsigned_fix:SDI (match_operand:IEEE128 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], true); @@ -7835,8 +7835,8 @@ }) (define_expand "floatdi<mode>2" - [(set (match_operand:IEEE128 0 "gpc_reg_operand" "") - (float:IEEE128 (match_operand:DI 1 "gpc_reg_operand" "")))] + [(set (match_operand:IEEE128 0 "gpc_reg_operand") + (float:IEEE128 (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { if (!TARGET_FLOAT128_HW) @@ -7847,8 +7847,8 @@ }) (define_expand "floatunsdi<IEEE128:mode>2" - [(set (match_operand:IEEE128 0 "gpc_reg_operand" "") - (unsigned_float:IEEE128 (match_operand:DI 1 "gpc_reg_operand" "")))] + [(set (match_operand:IEEE128 0 "gpc_reg_operand") + (unsigned_float:IEEE128 (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { if (!TARGET_FLOAT128_HW) @@ -7859,8 +7859,8 @@ }) (define_expand "floatuns<IEEE128:mode>2" - [(set (match_operand:IEEE128 0 "gpc_reg_operand" "") - (unsigned_float:IEEE128 (match_operand:SI 1 "gpc_reg_operand" "")))] + [(set (match_operand:IEEE128 0 "gpc_reg_operand") + (unsigned_float:IEEE128 (match_operand:SI 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rtx op0 = operands[0]; @@ -7874,8 +7874,8 @@ }) (define_expand "neg<mode>2" - [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "") - (neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:FLOAT128 0 "gpc_reg_operand") + (neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand")))] "FLOAT128_IEEE_P (<MODE>mode) || (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)" { @@ -7927,8 +7927,8 @@ (set_attr "length" "8")]) (define_expand "abs<mode>2" - [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "") - (abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:FLOAT128 0 "gpc_reg_operand") + (abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand")))] "FLOAT128_IEEE_P (<MODE>mode) || (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)" { @@ -7972,13 +7972,13 @@ }) (define_expand "abs<mode>2_internal" - [(set (match_operand:IBM128 0 "gpc_reg_operand" "") - (match_operand:IBM128 1 "gpc_reg_operand" "")) + [(set (match_operand:IBM128 0 "gpc_reg_operand") + (match_operand:IBM128 1 "gpc_reg_operand")) (set (match_dup 3) (match_dup 5)) (set (match_dup 5) (abs:DF (match_dup 5))) (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5))) (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) - (label_ref (match_operand 2 "" "")) + (label_ref (match_operand 2 "")) (pc))) (set (match_dup 6) (neg:DF (match_dup 6)))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" @@ -7996,7 +7996,7 @@ ;; register (define_expand "ieee_128bit_negative_zero" - [(set (match_operand:V16QI 0 "register_operand" "") (match_dup 1))] + [(set (match_operand:V16QI 0 "register_operand") (match_dup 1))] "TARGET_FLOAT128_TYPE" { rtvec v = rtvec_alloc (16); @@ -8115,8 +8115,8 @@ ;; We use expand to convert from IBM double double to IEEE 128-bit ;; and trunc for the opposite. (define_expand "extendiftf2" - [(set (match_operand:TF 0 "gpc_reg_operand" "") - (float_extend:TF (match_operand:IF 1 "gpc_reg_operand" "")))] + [(set (match_operand:TF 0 "gpc_reg_operand") + (float_extend:TF (match_operand:IF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8124,8 +8124,8 @@ }) (define_expand "extendifkf2" - [(set (match_operand:KF 0 "gpc_reg_operand" "") - (float_extend:KF (match_operand:IF 1 "gpc_reg_operand" "")))] + [(set (match_operand:KF 0 "gpc_reg_operand") + (float_extend:KF (match_operand:IF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8133,8 +8133,8 @@ }) (define_expand "extendtfkf2" - [(set (match_operand:KF 0 "gpc_reg_operand" "") - (float_extend:KF (match_operand:TF 1 "gpc_reg_operand" "")))] + [(set (match_operand:KF 0 "gpc_reg_operand") + (float_extend:KF (match_operand:TF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8142,8 +8142,8 @@ }) (define_expand "trunciftf2" - [(set (match_operand:IF 0 "gpc_reg_operand" "") - (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand" "")))] + [(set (match_operand:IF 0 "gpc_reg_operand") + (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8151,8 +8151,8 @@ }) (define_expand "truncifkf2" - [(set (match_operand:IF 0 "gpc_reg_operand" "") - (float_truncate:IF (match_operand:KF 1 "gpc_reg_operand" "")))] + [(set (match_operand:IF 0 "gpc_reg_operand") + (float_truncate:IF (match_operand:KF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8160,8 +8160,8 @@ }) (define_expand "trunckftf2" - [(set (match_operand:TF 0 "gpc_reg_operand" "") - (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand" "")))] + [(set (match_operand:TF 0 "gpc_reg_operand") + (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8169,8 +8169,8 @@ }) (define_expand "trunctfif2" - [(set (match_operand:IF 0 "gpc_reg_operand" "") - (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand" "")))] + [(set (match_operand:IF 0 "gpc_reg_operand") + (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8349,8 +8349,8 @@ (set_attr "type" "three")]) (define_split - [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "") - (match_operand:FMOVE128_GPR 1 "input_operand" ""))] + [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand") + (match_operand:FMOVE128_GPR 1 "input_operand"))] "reload_completed && (int_reg_operand (operands[0], <MODE>mode) || int_reg_operand (operands[1], <MODE>mode)) @@ -8516,8 +8516,8 @@ (set_attr "size" "64")]) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (match_operand:DI 1 "const_int_operand" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (match_operand:DI 1 "const_int_operand"))] "! TARGET_POWERPC64 && reload_completed && gpr_or_gpr_p (operands[0], operands[1]) && !direct_move_p (operands[0], operands[1])" @@ -8534,8 +8534,8 @@ }) (define_split - [(set (match_operand:DIFD 0 "nonimmediate_operand" "") - (match_operand:DIFD 1 "input_operand" ""))] + [(set (match_operand:DIFD 0 "nonimmediate_operand") + (match_operand:DIFD 1 "input_operand"))] "reload_completed && !TARGET_POWERPC64 && gpr_or_gpr_p (operands[0], operands[1]) && !direct_move_p (operands[0], operands[1])" @@ -8630,8 +8630,8 @@ ;; When non-easy constants can go in the TOC, this should use ;; easy_fp_constant predicate. (define_split - [(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "") - (match_operand:DI 1 "const_int_operand" ""))] + [(set (match_operand:DI 0 "int_reg_operand_not_pseudo") + (match_operand:DI 1 "const_int_operand"))] "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] @@ -8643,8 +8643,8 @@ }) (define_split - [(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "") - (match_operand:DI 1 "const_scalar_int_operand" ""))] + [(set (match_operand:DI 0 "int_reg_operand_not_pseudo") + (match_operand:DI 1 "const_scalar_int_operand"))] "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] @@ -8656,8 +8656,8 @@ }) (define_split - [(set (match_operand:DI 0 "altivec_register_operand" "") - (match_operand:DI 1 "s5bit_cint_operand" ""))] + [(set (match_operand:DI 0 "altivec_register_operand") + (match_operand:DI 1 "s5bit_cint_operand"))] "TARGET_VSX && reload_completed" [(const_int 0)] { @@ -8678,8 +8678,8 @@ ;; Split integer constants that can be loaded with XXSPLTIB and a ;; sign extend operation. (define_split - [(set (match_operand:INT_ISA3 0 "altivec_register_operand" "") - (match_operand:INT_ISA3 1 "xxspltib_constant_split" ""))] + [(set (match_operand:INT_ISA3 0 "altivec_register_operand") + (match_operand:INT_ISA3 1 "xxspltib_constant_split"))] "TARGET_P9_VECTOR && reload_completed" [(const_int 0)] { @@ -8731,8 +8731,8 @@ (set_attr "length" "8")]) (define_split - [(set (match_operand:TI2 0 "int_reg_operand" "") - (match_operand:TI2 1 "const_scalar_int_operand" ""))] + [(set (match_operand:TI2 0 "int_reg_operand") + (match_operand:TI2 1 "const_scalar_int_operand"))] "TARGET_POWERPC64 && (VECTOR_MEM_NONE_P (<MODE>mode) || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))" @@ -8758,8 +8758,8 @@ }) (define_split - [(set (match_operand:TI2 0 "nonimmediate_operand" "") - (match_operand:TI2 1 "input_operand" ""))] + [(set (match_operand:TI2 0 "nonimmediate_operand") + (match_operand:TI2 1 "input_operand"))] "reload_completed && gpr_or_gpr_p (operands[0], operands[1]) && !direct_move_p (operands[0], operands[1]) @@ -8768,10 +8768,10 @@ { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) (define_expand "setmemsi" - [(parallel [(set (match_operand:BLK 0 "" "") - (match_operand 2 "const_int_operand" "")) - (use (match_operand:SI 1 "" "")) - (use (match_operand:SI 3 "" ""))])] + [(parallel [(set (match_operand:BLK 0 "") + (match_operand 2 "const_int_operand")) + (use (match_operand:SI 1 "")) + (use (match_operand:SI 3 ""))])] "" { /* If value to set is not zero, use the library routine. */ @@ -8858,10 +8858,10 @@ ;; Argument 3 is the alignment (define_expand "movmemsi" - [(parallel [(set (match_operand:BLK 0 "" "") - (match_operand:BLK 1 "" "")) - (use (match_operand:SI 2 "" "")) - (use (match_operand:SI 3 "" ""))])] + [(parallel [(set (match_operand:BLK 0 "") + (match_operand:BLK 1 "")) + (use (match_operand:SI 2 "")) + (use (match_operand:SI 3 ""))])] "" { if (expand_block_move (operands)) @@ -9216,18 +9216,18 @@ ;; Also this optimization interferes with scalars going into ;; altivec registers (the code does reloading through the FPRs). (define_peephole2 - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (match_operand:DF 1 "any_operand" "")) - (set (match_operand:DF 2 "gpc_reg_operand" "") + [(set (match_operand:DF 0 "gpc_reg_operand") + (match_operand:DF 1 "any_operand")) + (set (match_operand:DF 2 "gpc_reg_operand") (match_dup 0))] "!TARGET_VSX && peep2_reg_dead_p (2, operands[0])" [(set (match_dup 2) (match_dup 1))]) (define_peephole2 - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (match_operand:SF 1 "any_operand" "")) - (set (match_operand:SF 2 "gpc_reg_operand" "") + [(set (match_operand:SF 0 "gpc_reg_operand") + (match_operand:SF 1 "any_operand")) + (set (match_operand:SF 2 "gpc_reg_operand") (match_dup 0))] "!TARGET_P8_VECTOR && peep2_reg_dead_p (2, operands[0])" @@ -9662,7 +9662,7 @@ "add %0,%1,%2@tls") (define_expand "tls_get_tpointer" - [(set (match_operand:SI 0 "gpc_reg_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand") (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))] "TARGET_XCOFF && HAVE_AS_TLS" { @@ -9679,9 +9679,9 @@ "bla __get_tpointer") (define_expand "tls_get_addr<mode>" - [(set (match_operand:P 0 "gpc_reg_operand" "") - (unspec:P [(match_operand:P 1 "gpc_reg_operand" "") - (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))] + [(set (match_operand:P 0 "gpc_reg_operand") + (unspec:P [(match_operand:P 1 "gpc_reg_operand") + (match_operand:P 2 "gpc_reg_operand")] UNSPEC_TLSTLS))] "TARGET_XCOFF && HAVE_AS_TLS" { emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]); @@ -9719,8 +9719,8 @@ ;; the constant size. The value is forced into a register if necessary. ;; (define_expand "allocate_stack" - [(set (match_operand 0 "gpc_reg_operand" "") - (minus (reg 1) (match_operand 1 "reg_or_cint_operand" ""))) + [(set (match_operand 0 "gpc_reg_operand") + (minus (reg 1) (match_operand 1 "reg_or_cint_operand"))) (set (reg 1) (minus (reg 1) (match_dup 1)))] "" @@ -9841,14 +9841,14 @@ ;; save area is a memory location. (define_expand "save_stack_function" - [(match_operand 0 "any_operand" "") - (match_operand 1 "any_operand" "")] + [(match_operand 0 "any_operand") + (match_operand 1 "any_operand")] "" "DONE;") (define_expand "restore_stack_function" - [(match_operand 0 "any_operand" "") - (match_operand 1 "any_operand" "")] + [(match_operand 0 "any_operand") + (match_operand 1 "any_operand")] "" "DONE;") @@ -9859,8 +9859,8 @@ [(set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 2)) (match_dup 5) - (set (match_operand 0 "register_operand" "") - (match_operand 1 "register_operand" ""))] + (set (match_operand 0 "register_operand") + (match_operand 1 "register_operand"))] "" { rtvec p; @@ -9877,8 +9877,8 @@ (define_expand "save_stack_nonlocal" [(set (match_dup 3) (match_dup 4)) - (set (match_operand 0 "memory_operand" "") (match_dup 3)) - (set (match_dup 2) (match_operand 1 "register_operand" ""))] + (set (match_operand 0 "memory_operand") (match_dup 3)) + (set (match_dup 2) (match_operand 1 "register_operand"))] "" { int units_per_word = (TARGET_32BIT) ? 4 : 8; @@ -9891,11 +9891,11 @@ }) (define_expand "restore_stack_nonlocal" - [(set (match_dup 2) (match_operand 1 "memory_operand" "")) + [(set (match_dup 2) (match_operand 1 "memory_operand")) (set (match_dup 3) (match_dup 4)) (set (match_dup 5) (match_dup 2)) (match_dup 6) - (set (match_operand 0 "register_operand" "") (match_dup 3))] + (set (match_operand 0 "register_operand") (match_dup 3))] "" { int units_per_word = (TARGET_32BIT) ? 4 : 8; @@ -10004,7 +10004,7 @@ (define_expand "load_toc_v4_PIC_1b" [(parallel [(set (reg:SI LR_REGNO) (unspec:SI [(match_operand:SI 0 "immediate_operand" "s") - (label_ref (match_operand 1 "" ""))] + (label_ref (match_operand 1 ""))] UNSPEC_TOCPTR)) (match_dup 1)])] "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2" @@ -10077,7 +10077,7 @@ ;; On Darwin, we need to reload the picbase. (define_expand "builtin_setjmp_receiver" - [(use (label_ref (match_operand 0 "" "")))] + [(use (label_ref (match_operand 0 "")))] "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) || (TARGET_TOC && TARGET_MINIMAL_TOC) || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" @@ -10188,9 +10188,9 @@ ;; Call and call_value insns (define_expand "call" - [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) + [(parallel [(call (mem:SI (match_operand 0 "address_operand")) + (match_operand 1 "")) + (use (match_operand 2 "")) (clobber (reg:SI LR_REGNO))])] "" { @@ -10230,10 +10230,10 @@ }) (define_expand "call_value" - [(parallel [(set (match_operand 0 "" "") - (call (mem:SI (match_operand 1 "address_operand" "")) - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) + [(parallel [(set (match_operand 0 "") + (call (mem:SI (match_operand 1 "address_operand")) + (match_operand 2 ""))) + (use (match_operand 3 "")) (clobber (reg:SI LR_REGNO))])] "" { @@ -10718,10 +10718,10 @@ ;; Call subroutine returning any type. (define_expand "untyped_call" - [(parallel [(call (match_operand 0 "" "") + [(parallel [(call (match_operand 0 "") (const_int 0)) - (match_operand 1 "" "") - (match_operand 2 "" "")])] + (match_operand 1 "") + (match_operand 2 "")])] "" { int i; @@ -10745,9 +10745,9 @@ ;; sibling call patterns (define_expand "sibcall" - [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) + [(parallel [(call (mem:SI (match_operand 0 "address_operand")) + (match_operand 1 "")) + (use (match_operand 2 "")) (simple_return)])] "" { @@ -10769,10 +10769,10 @@ }) (define_expand "sibcall_value" - [(parallel [(set (match_operand 0 "register_operand" "") - (call (mem:SI (match_operand 1 "address_operand" "")) - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) + [(parallel [(set (match_operand 0 "register_operand") + (call (mem:SI (match_operand 1 "address_operand")) + (match_operand 2 ""))) + (use (match_operand 3 "")) (simple_return)])] "" { @@ -11061,9 +11061,9 @@ (define_expand "cbranch<mode>4" [(use (match_operator 0 "comparison_operator" - [(match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "reg_or_short_operand" "")])) - (use (match_operand 3 ""))] + [(match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "reg_or_short_operand")])) + (use (match_operand 3))] "" { /* Take care of the possibility that operands[2] might be negative but @@ -11083,9 +11083,9 @@ (define_expand "cbranch<mode>4" [(use (match_operator 0 "comparison_operator" - [(match_operand:FP 1 "gpc_reg_operand" "") - (match_operand:FP 2 "gpc_reg_operand" "")])) - (use (match_operand 3 ""))] + [(match_operand:FP 1 "gpc_reg_operand") + (match_operand:FP 2 "gpc_reg_operand")])) + (use (match_operand 3))] "" { rs6000_emit_cbranch (<MODE>mode, operands); @@ -11502,18 +11502,18 @@ (define_peephole2 [(set (match_operand:SI 0 "register_operand") - (match_operand:SI 1 "logical_const_operand" "")) + (match_operand:SI 1 "logical_const_operand")) (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator" [(match_dup 0) - (match_operand:SI 2 "logical_const_operand" "")])) - (set (match_operand:CC 4 "cc_reg_operand" "") - (compare:CC (match_operand:SI 5 "gpc_reg_operand" "") + (match_operand:SI 2 "logical_const_operand")])) + (set (match_operand:CC 4 "cc_reg_operand") + (compare:CC (match_operand:SI 5 "gpc_reg_operand") (match_dup 0))) (set (pc) (if_then_else (match_operator 6 "equality_operator" [(match_dup 4) (const_int 0)]) - (match_operand 7 "" "") - (match_operand 8 "" "")))] + (match_operand 7 "") + (match_operand 8 "")))] "peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (4, operands[4]) && REGNO (operands[0]) != REGNO (operands[5])" @@ -11562,21 +11562,21 @@ [(set_attr "length" "8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_operand" "") - (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "short_cint_operand" ""))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] + [(set (match_operand:CC 3 "cc_reg_operand") + (compare:CC (match_operand:SI 1 "gpc_reg_operand") + (match_operand:SI 2 "short_cint_operand"))) + (set (match_operand:SI 0 "gpc_reg_operand") + (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand")))] "" [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) (define_split - [(set (match_operand:CCUNS 3 "cc_reg_operand" "") - (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "u_short_cint_operand" ""))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] + [(set (match_operand:CCUNS 3 "cc_reg_operand") + (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand") + (match_operand:SI 2 "u_short_cint_operand"))) + (set (match_operand:SI 0 "gpc_reg_operand") + (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand")))] "" [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) @@ -11715,12 +11715,12 @@ (set_attr "length" "8,16")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand") (compare:CC (match_operator:SI 1 "scc_comparison_operator" - [(match_operand 2 "cc_reg_operand" "") + [(match_operand 2 "cc_reg_operand") (const_int 0)]) (const_int 0))) - (set (match_operand:SI 3 "gpc_reg_operand" "") + (set (match_operand:SI 3 "gpc_reg_operand") (match_op_dup 1 [(match_dup 2) (const_int 0)]))] "TARGET_32BIT && reload_completed" [(set (match_dup 3) @@ -13002,8 +13002,8 @@ ; faster; for instance, on the 601 and 750. (define_expand "movsi_to_cr_one" - [(set (match_operand:CC 0 "cc_reg_operand" "") - (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "") + [(set (match_operand:CC 0 "cc_reg_operand") + (unspec:CC [(match_operand:SI 1 "gpc_reg_operand") (match_dup 2)] UNSPEC_MOVESI_TO_CR))] "" "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") @@ -13210,7 +13210,7 @@ ; This is used in compiling the unwind routines. (define_expand "eh_return" - [(use (match_operand 0 "general_operand" ""))] + [(use (match_operand 0 "general_operand"))] "" { if (TARGET_32BIT) @@ -13229,8 +13229,8 @@ "#") (define_split - [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) - (clobber (match_scratch 1 ""))] + [(unspec_volatile [(match_operand 0 "register_operand")] UNSPECV_EH_RR) + (clobber (match_scratch 1))] "reload_completed" [(const_int 0)] { @@ -13331,11 +13331,11 @@ ;; Note that the conditions for expansion are in the FMA_F iterator. (define_expand "fma<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (match_operand:FMA_F 3 "gpc_reg_operand" "")))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (match_operand:FMA_F 3 "gpc_reg_operand")))] "" "") @@ -13355,11 +13355,11 @@ ; Altivec only has fma and nfms. (define_expand "fms<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" ""))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand"))))] "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "") @@ -13379,34 +13379,34 @@ ;; If signed zeros are ignored, -(a * b - c) = -a * b + c. (define_expand "fnma<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (neg:FMA_F (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" "")))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand")))))] "!HONOR_SIGNED_ZEROS (<MODE>mode)" "") ;; If signed zeros are ignored, -(a * b + c) = -a * b - c. (define_expand "fnms<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (neg:FMA_F (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (match_operand:FMA_F 3 "gpc_reg_operand" ""))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (match_operand:FMA_F 3 "gpc_reg_operand"))))] "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "") ; Not an official optab name, but used from builtins. (define_expand "nfma<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (neg:FMA_F (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (match_operand:FMA_F 3 "gpc_reg_operand" ""))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (match_operand:FMA_F 3 "gpc_reg_operand"))))] "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "") @@ -13427,12 +13427,12 @@ ; Not an official optab name, but used from builtins. (define_expand "nfms<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (neg:FMA_F (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" "")))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand")))))] "" "") @@ -13454,7 +13454,7 @@ (define_expand "rs6000_get_timebase" - [(use (match_operand:DI 0 "gpc_reg_operand" ""))] + [(use (match_operand:DI 0 "gpc_reg_operand"))] "" { if (TARGET_POWERPC64) @@ -13552,8 +13552,8 @@ ;; (addis followed by load) even on power8. (define_split - [(set (match_operand:INT1 0 "toc_fusion_or_p9_reg_operand" "") - (match_operand:INT1 1 "toc_fusion_mem_raw" ""))] + [(set (match_operand:INT1 0 "toc_fusion_or_p9_reg_operand") + (match_operand:INT1 1 "toc_fusion_mem_raw"))] "TARGET_TOC_FUSION_INT && can_create_pseudo_p ()" [(parallel [(set (match_dup 0) (match_dup 2)) (unspec [(const_int 0)] UNSPEC_FUSION_ADDIS) @@ -13603,10 +13603,10 @@ ;; insn (define_peephole2 - [(set (match_operand:P 0 "base_reg_operand" "") - (match_operand:P 1 "fusion_gpr_addis" "")) - (set (match_operand:INT1 2 "base_reg_operand" "") - (match_operand:INT1 3 "fusion_gpr_mem_load" ""))] + [(set (match_operand:P 0 "base_reg_operand") + (match_operand:P 1 "fusion_gpr_addis")) + (set (match_operand:INT1 2 "base_reg_operand") + (match_operand:INT1 3 "fusion_gpr_mem_load"))] "TARGET_P8_FUSION && fusion_gpr_load_p (operands[0], operands[1], operands[2], operands[3])" @@ -13634,10 +13634,10 @@ ;; ISA 3.0 (power9) fusion support ;; Merge addis with floating load/store to FPRs (or GPRs). (define_peephole2 - [(set (match_operand:P 0 "base_reg_operand" "") - (match_operand:P 1 "fusion_gpr_addis" "")) - (set (match_operand:SFDF 2 "toc_fusion_or_p9_reg_operand" "") - (match_operand:SFDF 3 "fusion_offsettable_mem_operand" ""))] + [(set (match_operand:P 0 "base_reg_operand") + (match_operand:P 1 "fusion_gpr_addis")) + (set (match_operand:SFDF 2 "toc_fusion_or_p9_reg_operand") + (match_operand:SFDF 3 "fusion_offsettable_mem_operand"))] "TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0]) && fusion_p9_p (operands[0], operands[1], operands[2], operands[3])" [(const_int 0)] @@ -13647,10 +13647,10 @@ }) (define_peephole2 - [(set (match_operand:P 0 "base_reg_operand" "") - (match_operand:P 1 "fusion_gpr_addis" "")) - (set (match_operand:SFDF 2 "offsettable_mem_operand" "") - (match_operand:SFDF 3 "toc_fusion_or_p9_reg_operand" ""))] + [(set (match_operand:P 0 "base_reg_operand") + (match_operand:P 1 "fusion_gpr_addis")) + (set (match_operand:SFDF 2 "offsettable_mem_operand") + (match_operand:SFDF 3 "toc_fusion_or_p9_reg_operand"))] "TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0]) && fusion_p9_p (operands[0], operands[1], operands[2], operands[3]) && !rtx_equal_p (operands[0], operands[3])" @@ -13661,22 +13661,22 @@ }) (define_peephole2 - [(set (match_operand:SDI 0 "int_reg_operand" "") - (match_operand:SDI 1 "upper16_cint_operand" "")) + [(set (match_operand:SDI 0 "int_reg_operand") + (match_operand:SDI 1 "upper16_cint_operand")) (set (match_dup 0) (ior:SDI (match_dup 0) - (match_operand:SDI 2 "u_short_cint_operand" "")))] + (match_operand:SDI 2 "u_short_cint_operand")))] "TARGET_P9_FUSION" [(set (match_dup 0) (unspec:SDI [(match_dup 1) (match_dup 2)] UNSPEC_FUSION_P9))]) (define_peephole2 - [(set (match_operand:SDI 0 "int_reg_operand" "") - (match_operand:SDI 1 "upper16_cint_operand" "")) - (set (match_operand:SDI 2 "int_reg_operand" "") + [(set (match_operand:SDI 0 "int_reg_operand") + (match_operand:SDI 1 "upper16_cint_operand")) + (set (match_operand:SDI 2 "int_reg_operand") (ior:SDI (match_dup 0) - (match_operand:SDI 3 "u_short_cint_operand" "")))] + (match_operand:SDI 3 "u_short_cint_operand")))] "TARGET_P9_FUSION && !rtx_equal_p (operands[0], operands[2]) && peep2_reg_dead_p (2, operands[0])" @@ -13892,10 +13892,10 @@ (KF "DI")]) (define_expand "unpack<mode>" - [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "") + [(set (match_operand:<FP128_64> 0 "nonimmediate_operand") (unspec:<FP128_64> - [(match_operand:FMOVE128 1 "register_operand" "") - (match_operand:QI 2 "const_0_to_1_operand" "")] + [(match_operand:FMOVE128 1 "register_operand") + (match_operand:QI 2 "const_0_to_1_operand")] UNSPEC_UNPACK_128BIT))] "FLOAT128_2REG_P (<MODE>mode)" "") |