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-rw-r--r--gcc/config/rs6000/rs6000.md24
1 files changed, 20 insertions, 4 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9019ba8..f22dbce 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -986,8 +986,11 @@
(define_insn "extendsi<mode>2"
- [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wl,wu,wj,wK,wH")
- (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "Y,r,Z,Z,r,wK,wH")))]
+ [(set (match_operand:EXTSI 0 "gpc_reg_operand"
+ "=r, r, wl, wu, wj, wK, wH, wr")
+
+ (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand"
+ "Y, r, Z, Z, r, wK, wH, ?wIwH")))]
""
"@
lwa%U1%X1 %0,%1
@@ -996,10 +999,23 @@
lxsiwax %x0,%y1
mtvsrwa %x0,%1
vextsw2d %0,%1
+ #
#"
- [(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm")
+ [(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm,mftgpr")
(set_attr "sign_extend" "yes")
- (set_attr "length" "4,4,4,4,4,4,8")])
+ (set_attr "length" "4,4,4,4,4,4,8,8")])
+
+(define_split
+ [(set (match_operand:EXTSI 0 "int_reg_operand")
+ (sign_extend:EXTSI (match_operand:SI 1 "vsx_register_operand")))]
+ "TARGET_DIRECT_MOVE_64BIT && reload_completed"
+ [(set (match_dup 2)
+ (match_dup 1))
+ (set (match_dup 0)
+ (sign_extend:DI (match_dup 2)))]
+{
+ operands[2] = gen_rtx_REG (SImode, reg_or_subregno (operands[0]));
+})
(define_split
[(set (match_operand:DI 0 "altivec_register_operand")