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-rw-r--r--gcc/config/riscv/riscv-v.cc9
1 files changed, 0 insertions, 9 deletions
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 417c36a..b0de4c5 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -4011,15 +4011,6 @@ expand_vec_perm_const (machine_mode vmode, machine_mode op_mode, rtx target,
mask to do the iteration loop control. Just disable it directly. */
if (GET_MODE_CLASS (vmode) == MODE_VECTOR_BOOL)
return false;
- /* FIXME: Explicitly disable VLA interleave SLP vectorization when we
- may encounter ICE for poly size (1, 1) vectors in loop vectorizer.
- Ideally, middle-end loop vectorizer should be able to disable it
- itself, We can remove the codes here when middle-end code is able
- to disable VLA SLP vectorization for poly size (1, 1) VF. */
- if (!BYTES_PER_RISCV_VECTOR.is_constant ()
- && maybe_lt (BYTES_PER_RISCV_VECTOR * TARGET_MAX_LMUL,
- poly_int64 (16, 16)))
- return false;
struct expand_vec_perm_d d;