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-rw-r--r--gcc/config/riscv/constraints.md8
1 files changed, 8 insertions, 0 deletions
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 18556a5..ccab1a2 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -43,6 +43,10 @@
(define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : (TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
"RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use zfinx.")
+(define_register_constraint "cR" "RVC_GR_REGS"
+ "Even-odd RVC general purpose register (x8-x15)."
+ "regno % 2 == 0")
+
;; General constraints
(define_constraint "I"
@@ -321,3 +325,7 @@
"A 2-bit unsigned immediate."
(and (match_code "const_int")
(match_test "IN_RANGE (ival, 0, 3)")))
+
+(define_constraint "Q"
+ "An address operand that is valid for a prefetch instruction"
+ (match_operand 0 "prefetch_operand"))