1 files changed, 33 insertions, 18 deletions

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 8537b9d..c6175a3 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2096,7 +2096,8 @@
   "&& 1"
   [(const_int 0)]
 {
-  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands, CONST0_RTX (<VEL>mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, riscv_vector::REDUCE_OP,
+                                  operands, CONST0_RTX (<VEL>mode));
   DONE;
 }
 [(set_attr "type" "vector")])
@@ -2108,7 +2109,8 @@
 {
   int prec = GET_MODE_PRECISION (<VEL>mode);
   rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED), <VEL>mode);
-  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, min);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, riscv_vector::REDUCE_OP,
+                                  operands, min);
   DONE;
 })
 
@@ -2117,7 +2119,8 @@
    (match_operand:VI 1 "register_operand")]
   "TARGET_VECTOR"
 {
-  riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, operands, CONST0_RTX (<VEL>mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, riscv_vector::REDUCE_OP,
+                                  operands, CONST0_RTX (<VEL>mode));
   DONE;
 })
 
@@ -2128,7 +2131,8 @@
 {
   int prec = GET_MODE_PRECISION (<VEL>mode);
   rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED), <VEL>mode);
-  riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, max);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, riscv_vector::REDUCE_OP,
+                                  operands, max);
   DONE;
 })
 
@@ -2139,7 +2143,8 @@
 {
   int prec = GET_MODE_PRECISION (<VEL>mode);
   rtx max = immed_wide_int_const (wi::max_value (prec, UNSIGNED), <VEL>mode);
-  riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, operands, max);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, riscv_vector::REDUCE_OP,
+                                  operands, max);
   DONE;
 })
 
@@ -2148,7 +2153,8 @@
    (match_operand:VI 1 "register_operand")]
   "TARGET_VECTOR"
 {
-  riscv_vector::expand_reduction (UNSPEC_REDUC_AND, operands, CONSTM1_RTX (<VEL>mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_AND, riscv_vector::REDUCE_OP,
+                                  operands, CONSTM1_RTX (<VEL>mode));
   DONE;
 })
 
@@ -2157,7 +2163,8 @@
    (match_operand:VI 1 "register_operand")]
   "TARGET_VECTOR"
 {
-  riscv_vector::expand_reduction (UNSPEC_REDUC_OR, operands, CONST0_RTX (<VEL>mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_OR, riscv_vector::REDUCE_OP,
+                                  operands, CONST0_RTX (<VEL>mode));
   DONE;
 })
 
@@ -2166,7 +2173,8 @@
    (match_operand:VI 1 "register_operand")]
   "TARGET_VECTOR"
 {
-  riscv_vector::expand_reduction (UNSPEC_REDUC_XOR, operands, CONST0_RTX (<VEL>mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_XOR, riscv_vector::REDUCE_OP,
+                                  operands, CONST0_RTX (<VEL>mode));
   DONE;
 })
 
@@ -2189,8 +2197,9 @@
   "&& 1"
   [(const_int 0)]
 {
-  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_UNORDERED, operands,
-                                  CONST0_RTX (<VEL>mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_UNORDERED,
+                                  riscv_vector::REDUCE_OP_FRM_DYN,
+                                  operands, CONST0_RTX (<VEL>mode));
   DONE;
 }
 [(set_attr "type" "vector")])
@@ -2203,7 +2212,8 @@
   REAL_VALUE_TYPE rv;
   real_inf (&rv, true);
   rtx f = const_double_from_real_value (rv, <VEL>mode);
-  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, f);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, riscv_vector::REDUCE_OP,
+                                  operands, f);
   DONE;
 })
 
@@ -2215,7 +2225,8 @@
   REAL_VALUE_TYPE rv;
   real_inf (&rv, false);
   rtx f = const_double_from_real_value (rv, <VEL>mode);
-  riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, f);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, riscv_vector::REDUCE_OP,
+                                  operands, f);
   DONE;
 })
 
@@ -2238,9 +2249,10 @@
   "&& 1"
   [(const_int 0)]
 {
-  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED, operands,
-				  operands[1],
-				  riscv_vector::reduction_type::FOLD_LEFT);
+  rtx ops[] = {operands[0], operands[2]};
+  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED,
+                                  riscv_vector::REDUCE_OP_FRM_DYN,
+                                  ops, operands[1]);
   DONE;
 }
 [(set_attr "type" "vector")])
@@ -2263,9 +2275,12 @@
   if (rtx_equal_p (operands[4], const0_rtx))
     emit_move_insn (operands[0], operands[1]);
   else
-    riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED, operands,
-				    operands[1],
-				    riscv_vector::reduction_type::MASK_LEN_FOLD_LEFT);
+    {
+      rtx ops[] = {operands[0], operands[2], operands[3], operands[4]};
+      riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED,
+                                      riscv_vector::REDUCE_OP_M_FRM_DYN,
+                                      ops, operands[1]);
+    }
   DONE;
 }
 [(set_attr "type" "vector")])