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Diffstat (limited to 'gcc/config/riscv/autovec.md')
-rw-r--r--gcc/config/riscv/autovec.md98
1 files changed, 65 insertions, 33 deletions
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 48de5ef..c694684 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -55,8 +55,8 @@
[(match_operand:RATIO64 0 "register_operand")
(match_operand 1 "pmode_reg_or_0_operand")
(match_operand:RATIO64I 2 "register_operand")
- (match_operand 3 "<RATIO64:gs_extension>")
- (match_operand 4 "<RATIO64:gs_scale>")
+ (match_operand 3 "const_1_operand")
+ (match_operand 4 "const_1_operand")
(match_operand:<RATIO64:VM> 5 "vector_mask_operand")
(match_operand 6 "maskload_else_operand")
(match_operand 7 "autovec_length_operand")
@@ -71,8 +71,8 @@
[(match_operand:RATIO32 0 "register_operand")
(match_operand 1 "pmode_reg_or_0_operand")
(match_operand:RATIO32I 2 "register_operand")
- (match_operand 3 "<RATIO32:gs_extension>")
- (match_operand 4 "<RATIO32:gs_scale>")
+ (match_operand 3 "const_1_operand")
+ (match_operand 4 "const_1_operand")
(match_operand:<RATIO32:VM> 5 "vector_mask_operand")
(match_operand 6 "maskload_else_operand")
(match_operand 7 "autovec_length_operand")
@@ -87,8 +87,8 @@
[(match_operand:RATIO16 0 "register_operand")
(match_operand 1 "pmode_reg_or_0_operand")
(match_operand:RATIO16I 2 "register_operand")
- (match_operand 3 "<RATIO16:gs_extension>")
- (match_operand 4 "<RATIO16:gs_scale>")
+ (match_operand 3 "const_1_operand")
+ (match_operand 4 "const_1_operand")
(match_operand:<RATIO16:VM> 5 "vector_mask_operand")
(match_operand 6 "maskload_else_operand")
(match_operand 7 "autovec_length_operand")
@@ -103,8 +103,8 @@
[(match_operand:RATIO8 0 "register_operand")
(match_operand 1 "pmode_reg_or_0_operand")
(match_operand:RATIO8I 2 "register_operand")
- (match_operand 3 "<RATIO8:gs_extension>")
- (match_operand 4 "<RATIO8:gs_scale>")
+ (match_operand 3 "const_1_operand")
+ (match_operand 4 "const_1_operand")
(match_operand:<RATIO8:VM> 5 "vector_mask_operand")
(match_operand 6 "maskload_else_operand")
(match_operand 7 "autovec_length_operand")
@@ -119,8 +119,8 @@
[(match_operand:RATIO4 0 "register_operand")
(match_operand 1 "pmode_reg_or_0_operand")
(match_operand:RATIO4I 2 "register_operand")
- (match_operand 3 "<RATIO4:gs_extension>")
- (match_operand 4 "<RATIO4:gs_scale>")
+ (match_operand 3 "const_1_operand")
+ (match_operand 4 "const_1_operand")
(match_operand:<RATIO4:VM> 5 "vector_mask_operand")
(match_operand 6 "maskload_else_operand")
(match_operand 7 "autovec_length_operand")
@@ -135,8 +135,8 @@
[(match_operand:RATIO2 0 "register_operand")
(match_operand 1 "pmode_reg_or_0_operand")
(match_operand:RATIO2I 2 "register_operand")
- (match_operand 3 "<RATIO2:gs_extension>")
- (match_operand 4 "<RATIO2:gs_scale>")
+ (match_operand 3 "const_1_operand")
+ (match_operand 4 "const_1_operand")
(match_operand:<RATIO2:VM> 5 "vector_mask_operand")
(match_operand 6 "maskload_else_operand")
(match_operand 7 "autovec_length_operand")
@@ -155,8 +155,8 @@
[(match_operand:RATIO1 0 "register_operand")
(match_operand 1 "pmode_reg_or_0_operand")
(match_operand:RATIO1 2 "register_operand")
- (match_operand 3 "<gs_extension>")
- (match_operand 4 "<gs_scale>")
+ (match_operand 3 "const_1_operand")
+ (match_operand 4 "const_1_operand")
(match_operand:<VM> 5 "vector_mask_operand")
(match_operand 6 "maskload_else_operand")
(match_operand 7 "autovec_length_operand")
@@ -174,8 +174,8 @@
(define_expand "mask_len_scatter_store<RATIO64:mode><RATIO64I:mode>"
[(match_operand 0 "pmode_reg_or_0_operand")
(match_operand:RATIO64I 1 "register_operand")
- (match_operand 2 "<RATIO64:gs_extension>")
- (match_operand 3 "<RATIO64:gs_scale>")
+ (match_operand 2 "const_1_operand")
+ (match_operand 3 "const_1_operand")
(match_operand:RATIO64 4 "register_operand")
(match_operand:<RATIO64:VM> 5 "vector_mask_operand")
(match_operand 6 "autovec_length_operand")
@@ -189,8 +189,8 @@
(define_expand "mask_len_scatter_store<RATIO32:mode><RATIO32I:mode>"
[(match_operand 0 "pmode_reg_or_0_operand")
(match_operand:RATIO32I 1 "register_operand")
- (match_operand 2 "<RATIO32:gs_extension>")
- (match_operand 3 "<RATIO32:gs_scale>")
+ (match_operand 2 "const_1_operand")
+ (match_operand 3 "const_1_operand")
(match_operand:RATIO32 4 "register_operand")
(match_operand:<RATIO32:VM> 5 "vector_mask_operand")
(match_operand 6 "autovec_length_operand")
@@ -204,8 +204,8 @@
(define_expand "mask_len_scatter_store<RATIO16:mode><RATIO16I:mode>"
[(match_operand 0 "pmode_reg_or_0_operand")
(match_operand:RATIO16I 1 "register_operand")
- (match_operand 2 "<RATIO16:gs_extension>")
- (match_operand 3 "<RATIO16:gs_scale>")
+ (match_operand 2 "const_1_operand")
+ (match_operand 3 "const_1_operand")
(match_operand:RATIO16 4 "register_operand")
(match_operand:<RATIO16:VM> 5 "vector_mask_operand")
(match_operand 6 "autovec_length_operand")
@@ -219,8 +219,8 @@
(define_expand "mask_len_scatter_store<RATIO8:mode><RATIO8I:mode>"
[(match_operand 0 "pmode_reg_or_0_operand")
(match_operand:RATIO8I 1 "register_operand")
- (match_operand 2 "<RATIO8:gs_extension>")
- (match_operand 3 "<RATIO8:gs_scale>")
+ (match_operand 2 "const_1_operand")
+ (match_operand 3 "const_1_operand")
(match_operand:RATIO8 4 "register_operand")
(match_operand:<RATIO8:VM> 5 "vector_mask_operand")
(match_operand 6 "autovec_length_operand")
@@ -234,8 +234,8 @@
(define_expand "mask_len_scatter_store<RATIO4:mode><RATIO4I:mode>"
[(match_operand 0 "pmode_reg_or_0_operand")
(match_operand:RATIO4I 1 "register_operand")
- (match_operand 2 "<RATIO4:gs_extension>")
- (match_operand 3 "<RATIO4:gs_scale>")
+ (match_operand 2 "const_1_operand")
+ (match_operand 3 "const_1_operand")
(match_operand:RATIO4 4 "register_operand")
(match_operand:<RATIO4:VM> 5 "vector_mask_operand")
(match_operand 6 "autovec_length_operand")
@@ -249,8 +249,8 @@
(define_expand "mask_len_scatter_store<RATIO2:mode><RATIO2I:mode>"
[(match_operand 0 "pmode_reg_or_0_operand")
(match_operand:RATIO2I 1 "register_operand")
- (match_operand 2 "<RATIO2:gs_extension>")
- (match_operand 3 "<RATIO2:gs_scale>")
+ (match_operand 2 "const_1_operand")
+ (match_operand 3 "const_1_operand")
(match_operand:RATIO2 4 "register_operand")
(match_operand:<RATIO2:VM> 5 "vector_mask_operand")
(match_operand 6 "autovec_length_operand")
@@ -268,8 +268,8 @@
(define_expand "mask_len_scatter_store<mode><mode>"
[(match_operand 0 "pmode_reg_or_0_operand")
(match_operand:RATIO1 1 "register_operand")
- (match_operand 2 "<gs_extension>")
- (match_operand 3 "<gs_scale>")
+ (match_operand 2 "const_1_operand")
+ (match_operand 3 "const_1_operand")
(match_operand:RATIO1 4 "register_operand")
(match_operand:<VM> 5 "vector_mask_operand")
(match_operand 6 "autovec_length_operand")
@@ -1335,10 +1335,11 @@
;; == SELECT_VL
;; =========================================================================
-(define_expand "select_vl<mode>"
+(define_expand "select_vl<V:mode><P:mode>"
[(match_operand:P 0 "register_operand")
(match_operand:P 1 "vector_length_operand")
- (match_operand:P 2 "immediate_operand")]
+ (match_operand:P 2 "immediate_operand")
+ (match_operand:V 3)]
"TARGET_VECTOR"
{
riscv_vector::expand_select_vl (operands);
@@ -1350,9 +1351,9 @@
;; -------------------------------------------------------------------------
(define_expand "vec_set<mode>"
- [(match_operand:V_VLS 0 "register_operand")
- (match_operand:<VEL> 1 "register_operand")
- (match_operand 2 "nonmemory_operand")]
+ [(match_operand:V_VLS_ZVFH 0 "register_operand")
+ (match_operand:<VEL> 1 "register_operand")
+ (match_operand 2 "nonmemory_operand")]
"TARGET_VECTOR"
{
/* If we set the first element, emit an v(f)mv.s.[xf]. */
@@ -2301,6 +2302,37 @@
})
;; -------------------------------------------------------------------------
+;; ---- [INT] Mask reductions
+;; -------------------------------------------------------------------------
+
+(define_expand "reduc_sbool_and_scal_<mode>"
+ [(match_operand:QI 0 "register_operand")
+ (match_operand:VB_VLS 1 "register_operand")]
+ "TARGET_VECTOR"
+{
+ riscv_vector::expand_mask_reduction (operands, AND);
+ DONE;
+})
+
+(define_expand "reduc_sbool_ior_scal_<mode>"
+ [(match_operand:QI 0 "register_operand")
+ (match_operand:VB_VLS 1 "register_operand")]
+ "TARGET_VECTOR"
+{
+ riscv_vector::expand_mask_reduction (operands, IOR);
+ DONE;
+})
+
+(define_expand "reduc_sbool_xor_scal_<mode>"
+ [(match_operand:QI 0 "register_operand")
+ (match_operand:VB_VLS 1 "register_operand")]
+ "TARGET_VECTOR"
+{
+ riscv_vector::expand_mask_reduction (operands, XOR);
+ DONE;
+})
+
+;; -------------------------------------------------------------------------
;; ---- [FP] Tree reductions
;; -------------------------------------------------------------------------
;; Includes:
generated by cgit v1.1 at 2026-01-07 13:54:58 +0000